drivers/net/wireless/ti/wl18xx/main.c

   1 /*
   2  * This file is part of wl18xx
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/ip.h>
  25
  26 #include "../wlcore/wlcore.h"
  27 #include "../wlcore/debug.h"
  28 #include "../wlcore/io.h"
  29 #include "../wlcore/acx.h"
  30 #include "../wlcore/tx.h"
  31 #include "../wlcore/rx.h"
  32 #include "../wlcore/io.h"
  33 #include "../wlcore/boot.h"
  34
  35 #include "reg.h"
  36 #include "conf.h"
  37 #include "acx.h"
  38 #include "tx.h"
  39 #include "wl18xx.h"
  40
  41
  42 #define WL18XX_RX_CHECKSUM_MASK      0x40
  43
  44 static const u8 wl18xx_rate_to_idx_2ghz[] = {
  45         /* MCS rates are used only with 11n */
  46         15,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
  47         14,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
  48         13,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
  49         12,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
  50         11,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
  51         10,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
  52         9,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
  53         8,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
  54         7,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
  55         6,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
  56         5,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
  57         4,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
  58         3,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
  59         2,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
  60         1,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
  61         0,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
  62
  63         11,                            /* WL18XX_CONF_HW_RXTX_RATE_54   */
  64         10,                            /* WL18XX_CONF_HW_RXTX_RATE_48   */
  65         9,                             /* WL18XX_CONF_HW_RXTX_RATE_36   */
  66         8,                             /* WL18XX_CONF_HW_RXTX_RATE_24   */
  67
  68         /* TI-specific rate */
  69         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22   */
  70
  71         7,                             /* WL18XX_CONF_HW_RXTX_RATE_18   */
  72         6,                             /* WL18XX_CONF_HW_RXTX_RATE_12   */
  73         3,                             /* WL18XX_CONF_HW_RXTX_RATE_11   */
  74         5,                             /* WL18XX_CONF_HW_RXTX_RATE_9    */
  75         4,                             /* WL18XX_CONF_HW_RXTX_RATE_6    */
  76         2,                             /* WL18XX_CONF_HW_RXTX_RATE_5_5  */
  77         1,                             /* WL18XX_CONF_HW_RXTX_RATE_2    */
  78         0                              /* WL18XX_CONF_HW_RXTX_RATE_1    */
  79 };
  80
  81 static const u8 wl18xx_rate_to_idx_5ghz[] = {
  82         /* MCS rates are used only with 11n */
  83         15,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
  84         14,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
  85         13,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
  86         12,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
  87         11,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
  88         10,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
  89         9,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
  90         8,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
  91         7,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
  92         6,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
  93         5,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
  94         4,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
  95         3,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
  96         2,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
  97         1,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
  98         0,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
  99
 100         7,                             /* WL18XX_CONF_HW_RXTX_RATE_54   */
 101         6,                             /* WL18XX_CONF_HW_RXTX_RATE_48   */
 102         5,                             /* WL18XX_CONF_HW_RXTX_RATE_36   */
 103         4,                             /* WL18XX_CONF_HW_RXTX_RATE_24   */
 104
 105         /* TI-specific rate */
 106         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22   */
 107
 108         3,                             /* WL18XX_CONF_HW_RXTX_RATE_18   */
 109         2,                             /* WL18XX_CONF_HW_RXTX_RATE_12   */
 110         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11   */
 111         1,                             /* WL18XX_CONF_HW_RXTX_RATE_9    */
 112         0,                             /* WL18XX_CONF_HW_RXTX_RATE_6    */
 113         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5  */
 114         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2    */
 115         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1    */
 116 };
 117
 118 static const u8 *wl18xx_band_rate_to_idx[] = {
 119         [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
 120         [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
 121 };
 122
 123 enum wl18xx_hw_rates {
 124         WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
 125         WL18XX_CONF_HW_RXTX_RATE_MCS14,
 126         WL18XX_CONF_HW_RXTX_RATE_MCS13,
 127         WL18XX_CONF_HW_RXTX_RATE_MCS12,
 128         WL18XX_CONF_HW_RXTX_RATE_MCS11,
 129         WL18XX_CONF_HW_RXTX_RATE_MCS10,
 130         WL18XX_CONF_HW_RXTX_RATE_MCS9,
 131         WL18XX_CONF_HW_RXTX_RATE_MCS8,
 132         WL18XX_CONF_HW_RXTX_RATE_MCS7,
 133         WL18XX_CONF_HW_RXTX_RATE_MCS6,
 134         WL18XX_CONF_HW_RXTX_RATE_MCS5,
 135         WL18XX_CONF_HW_RXTX_RATE_MCS4,
 136         WL18XX_CONF_HW_RXTX_RATE_MCS3,
 137         WL18XX_CONF_HW_RXTX_RATE_MCS2,
 138         WL18XX_CONF_HW_RXTX_RATE_MCS1,
 139         WL18XX_CONF_HW_RXTX_RATE_MCS0,
 140         WL18XX_CONF_HW_RXTX_RATE_54,
 141         WL18XX_CONF_HW_RXTX_RATE_48,
 142         WL18XX_CONF_HW_RXTX_RATE_36,
 143         WL18XX_CONF_HW_RXTX_RATE_24,
 144         WL18XX_CONF_HW_RXTX_RATE_22,
 145         WL18XX_CONF_HW_RXTX_RATE_18,
 146         WL18XX_CONF_HW_RXTX_RATE_12,
 147         WL18XX_CONF_HW_RXTX_RATE_11,
 148         WL18XX_CONF_HW_RXTX_RATE_9,
 149         WL18XX_CONF_HW_RXTX_RATE_6,
 150         WL18XX_CONF_HW_RXTX_RATE_5_5,
 151         WL18XX_CONF_HW_RXTX_RATE_2,
 152         WL18XX_CONF_HW_RXTX_RATE_1,
 153         WL18XX_CONF_HW_RXTX_RATE_MAX,
 154 };
 155
 156 static struct wlcore_conf wl18xx_conf = {
 157         .sg = {
 158                 .params = {
 159                         [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
 160                         [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
 161                         [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
 162                         [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
 163                         [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
 164                         [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
 165                         [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
 166                         [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
 167                         [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
 168                         [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
 169                         [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
 170                         [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
 171                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
 172                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
 173                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
 174                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
 175                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
 176                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
 177                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
 178                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
 179                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
 180                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
 181                         [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
 182                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
 183                         [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
 184                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
 185                         /* active scan params */
 186                         [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
 187                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
 188                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
 189                         /* passive scan params */
 190                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
 191                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
 192                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
 193                         /* passive scan in dual antenna params */
 194                         [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
 195                         [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
 196                         [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
 197                         /* general params */
 198                         [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
 199                         [CONF_SG_ANTENNA_CONFIGURATION] = 0,
 200                         [CONF_SG_BEACON_MISS_PERCENT] = 60,
 201                         [CONF_SG_DHCP_TIME] = 5000,
 202                         [CONF_SG_RXT] = 1200,
 203                         [CONF_SG_TXT] = 1000,
 204                         [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
 205                         [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
 206                         [CONF_SG_HV3_MAX_SERVED] = 6,
 207                         [CONF_SG_PS_POLL_TIMEOUT] = 10,
 208                         [CONF_SG_UPSD_TIMEOUT] = 10,
 209                         [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
 210                         [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
 211                         [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
 212                         /* AP params */
 213                         [CONF_AP_BEACON_MISS_TX] = 3,
 214                         [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
 215                         [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
 216                         [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
 217                         [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
 218                         [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
 219                         /* CTS Diluting params */
 220                         [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
 221                         [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
 222                 },
 223                 .state = CONF_SG_PROTECTIVE,
 224         },
 225         .rx = {
 226                 .rx_msdu_life_time           = 512000,
 227                 .packet_detection_threshold  = 0,
 228                 .ps_poll_timeout             = 15,
 229                 .upsd_timeout                = 15,
 230                 .rts_threshold               = IEEE80211_MAX_RTS_THRESHOLD,
 231                 .rx_cca_threshold            = 0,
 232                 .irq_blk_threshold           = 0xFFFF,
 233                 .irq_pkt_threshold           = 0,
 234                 .irq_timeout                 = 600,
 235                 .queue_type                  = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
 236         },
 237         .tx = {
 238                 .tx_energy_detection         = 0,
 239                 .sta_rc_conf                 = {
 240                         .enabled_rates       = 0,
 241                         .short_retry_limit   = 10,
 242                         .long_retry_limit    = 10,
 243                         .aflags              = 0,
 244                 },
 245                 .ac_conf_count               = 4,
 246                 .ac_conf                     = {
 247                         [CONF_TX_AC_BE] = {
 248                                 .ac          = CONF_TX_AC_BE,
 249                                 .cw_min      = 15,
 250                                 .cw_max      = 63,
 251                                 .aifsn       = 3,
 252                                 .tx_op_limit = 0,
 253                         },
 254                         [CONF_TX_AC_BK] = {
 255                                 .ac          = CONF_TX_AC_BK,
 256                                 .cw_min      = 15,
 257                                 .cw_max      = 63,
 258                                 .aifsn       = 7,
 259                                 .tx_op_limit = 0,
 260                         },
 261                         [CONF_TX_AC_VI] = {
 262                                 .ac          = CONF_TX_AC_VI,
 263                                 .cw_min      = 15,
 264                                 .cw_max      = 63,
 265                                 .aifsn       = CONF_TX_AIFS_PIFS,
 266                                 .tx_op_limit = 3008,
 267                         },
 268                         [CONF_TX_AC_VO] = {
 269                                 .ac          = CONF_TX_AC_VO,
 270                                 .cw_min      = 15,
 271                                 .cw_max      = 63,
 272                                 .aifsn       = CONF_TX_AIFS_PIFS,
 273                                 .tx_op_limit = 1504,
 274                         },
 275                 },
 276                 .max_tx_retries = 100,
 277                 .ap_aging_period = 300,
 278                 .tid_conf_count = 4,
 279                 .tid_conf = {
 280                         [CONF_TX_AC_BE] = {
 281                                 .queue_id    = CONF_TX_AC_BE,
 282                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 283                                 .tsid        = CONF_TX_AC_BE,
 284                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 285                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 286                                 .apsd_conf   = {0, 0},
 287                         },
 288                         [CONF_TX_AC_BK] = {
 289                                 .queue_id    = CONF_TX_AC_BK,
 290                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 291                                 .tsid        = CONF_TX_AC_BK,
 292                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 293                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 294                                 .apsd_conf   = {0, 0},
 295                         },
 296                         [CONF_TX_AC_VI] = {
 297                                 .queue_id    = CONF_TX_AC_VI,
 298                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 299                                 .tsid        = CONF_TX_AC_VI,
 300                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 301                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 302                                 .apsd_conf   = {0, 0},
 303                         },
 304                         [CONF_TX_AC_VO] = {
 305                                 .queue_id    = CONF_TX_AC_VO,
 306                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 307                                 .tsid        = CONF_TX_AC_VO,
 308                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 309                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 310                                 .apsd_conf   = {0, 0},
 311                         },
 312                 },
 313                 .frag_threshold              = IEEE80211_MAX_FRAG_THRESHOLD,
 314                 .tx_compl_timeout            = 350,
 315                 .tx_compl_threshold          = 10,
 316                 .basic_rate                  = CONF_HW_BIT_RATE_1MBPS,
 317                 .basic_rate_5                = CONF_HW_BIT_RATE_6MBPS,
 318                 .tmpl_short_retry_limit      = 10,
 319                 .tmpl_long_retry_limit       = 10,
 320                 .tx_watchdog_timeout         = 5000,
 321         },
 322         .conn = {
 323                 .wake_up_event               = CONF_WAKE_UP_EVENT_DTIM,
 324                 .listen_interval             = 1,
 325                 .suspend_wake_up_event       = CONF_WAKE_UP_EVENT_N_DTIM,
 326                 .suspend_listen_interval     = 3,
 327                 .bcn_filt_mode               = CONF_BCN_FILT_MODE_ENABLED,
 328                 .bcn_filt_ie_count           = 2,
 329                 .bcn_filt_ie = {
 330                         [0] = {
 331                                 .ie          = WLAN_EID_CHANNEL_SWITCH,
 332                                 .rule        = CONF_BCN_RULE_PASS_ON_APPEARANCE,
 333                         },
 334                         [1] = {
 335                                 .ie          = WLAN_EID_HT_OPERATION,
 336                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 337                         },
 338                 },
 339                 .synch_fail_thold            = 10,
 340                 .bss_lose_timeout            = 100,
 341                 .beacon_rx_timeout           = 10000,
 342                 .broadcast_timeout           = 20000,
 343                 .rx_broadcast_in_ps          = 1,
 344                 .ps_poll_threshold           = 10,
 345                 .bet_enable                  = CONF_BET_MODE_ENABLE,
 346                 .bet_max_consecutive         = 50,
 347                 .psm_entry_retries           = 8,
 348                 .psm_exit_retries            = 16,
 349                 .psm_entry_nullfunc_retries  = 3,
 350                 .dynamic_ps_timeout          = 40,
 351                 .forced_ps                   = false,
 352                 .keep_alive_interval         = 55000,
 353                 .max_listen_interval         = 20,
 354         },
 355         .itrim = {
 356                 .enable = false,
 357                 .timeout = 50000,
 358         },
 359         .pm_config = {
 360                 .host_clk_settling_time = 5000,
 361                 .host_fast_wakeup_support = false
 362         },
 363         .roam_trigger = {
 364                 .trigger_pacing               = 1,
 365                 .avg_weight_rssi_beacon       = 20,
 366                 .avg_weight_rssi_data         = 10,
 367                 .avg_weight_snr_beacon        = 20,
 368                 .avg_weight_snr_data          = 10,
 369         },
 370         .scan = {
 371                 .min_dwell_time_active        = 7500,
 372                 .max_dwell_time_active        = 30000,
 373                 .min_dwell_time_passive       = 100000,
 374                 .max_dwell_time_passive       = 100000,
 375                 .num_probe_reqs               = 2,
 376                 .split_scan_timeout           = 50000,
 377         },
 378         .sched_scan = {
 379                 /*
 380                  * Values are in TU/1000 but since sched scan FW command
 381                  * params are in TUs rounding up may occur.
 382                  */
 383                 .base_dwell_time                = 7500,
 384                 .max_dwell_time_delta           = 22500,
 385                 /* based on 250bits per probe @1Mbps */
 386                 .dwell_time_delta_per_probe     = 2000,
 387                 /* based on 250bits per probe @6Mbps (plus a bit more) */
 388                 .dwell_time_delta_per_probe_5   = 350,
 389                 .dwell_time_passive             = 100000,
 390                 .dwell_time_dfs                 = 150000,
 391                 .num_probe_reqs                 = 2,
 392                 .rssi_threshold                 = -90,
 393                 .snr_threshold                  = 0,
 394         },
 395         .ht = {
 396                 .rx_ba_win_size = 10,
 397                 .tx_ba_win_size = 10,
 398                 .inactivity_timeout = 10000,
 399                 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
 400         },
 401         .mem = {
 402                 .num_stations                 = 1,
 403                 .ssid_profiles                = 1,
 404                 .rx_block_num                 = 40,
 405                 .tx_min_block_num             = 40,
 406                 .dynamic_memory               = 1,
 407                 .min_req_tx_blocks            = 45,
 408                 .min_req_rx_blocks            = 22,
 409                 .tx_min                       = 27,
 410         },
 411         .fm_coex = {
 412                 .enable                       = true,
 413                 .swallow_period               = 5,
 414                 .n_divider_fref_set_1         = 0xff,       /* default */
 415                 .n_divider_fref_set_2         = 12,
 416                 .m_divider_fref_set_1         = 148,
 417                 .m_divider_fref_set_2         = 0xffff,     /* default */
 418                 .coex_pll_stabilization_time  = 0xffffffff, /* default */
 419                 .ldo_stabilization_time       = 0xffff,     /* default */
 420                 .fm_disturbed_band_margin     = 0xff,       /* default */
 421                 .swallow_clk_diff             = 0xff,       /* default */
 422         },
 423         .rx_streaming = {
 424                 .duration                      = 150,
 425                 .queues                        = 0x1,
 426                 .interval                      = 20,
 427                 .always                        = 0,
 428         },
 429         .fwlog = {
 430                 .mode                         = WL12XX_FWLOG_ON_DEMAND,
 431                 .mem_blocks                   = 2,
 432                 .severity                     = 0,
 433                 .timestamp                    = WL12XX_FWLOG_TIMESTAMP_DISABLED,
 434                 .output                       = WL12XX_FWLOG_OUTPUT_HOST,
 435                 .threshold                    = 0,
 436         },
 437         .rate = {
 438                 .rate_retry_score = 32000,
 439                 .per_add = 8192,
 440                 .per_th1 = 2048,
 441                 .per_th2 = 4096,
 442                 .max_per = 8100,
 443                 .inverse_curiosity_factor = 5,
 444                 .tx_fail_low_th = 4,
 445                 .tx_fail_high_th = 10,
 446                 .per_alpha_shift = 4,
 447                 .per_add_shift = 13,
 448                 .per_beta1_shift = 10,
 449                 .per_beta2_shift = 8,
 450                 .rate_check_up = 2,
 451                 .rate_check_down = 12,
 452                 .rate_retry_policy = {
 453                         0x00, 0x00, 0x00, 0x00, 0x00,
 454                         0x00, 0x00, 0x00, 0x00, 0x00,
 455                         0x00, 0x00, 0x00,
 456                 },
 457         },
 458         .hangover = {
 459                 .recover_time               = 0,
 460                 .hangover_period            = 20,
 461                 .dynamic_mode               = 1,
 462                 .early_termination_mode     = 1,
 463                 .max_period                 = 20,
 464                 .min_period                 = 1,
 465                 .increase_delta             = 1,
 466                 .decrease_delta             = 2,
 467                 .quiet_time                 = 4,
 468                 .increase_time              = 1,
 469                 .window_size                = 16,
 470         },
 471 };
 472
 473 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
 474         .phy = {
 475                 .phy_standalone                 = 0x00,
 476                 .primary_clock_setting_time     = 0x05,
 477                 .clock_valid_on_wake_up         = 0x00,
 478                 .secondary_clock_setting_time   = 0x05,
 479                 .rdl                            = 0x01,
 480                 .auto_detect                    = 0x00,
 481                 .dedicated_fem                  = FEM_NONE,
 482                 .low_band_component             = COMPONENT_2_WAY_SWITCH,
 483                 .low_band_component_type        = 0x05,
 484                 .high_band_component            = COMPONENT_2_WAY_SWITCH,
 485                 .high_band_component_type       = 0x09,
 486                 .number_of_assembled_ant2_4     = 0x01,
 487                 .number_of_assembled_ant5       = 0x01,
 488                 .external_pa_dc2dc              = 0x00,
 489                 .tcxo_ldo_voltage               = 0x00,
 490                 .xtal_itrim_val                 = 0x04,
 491                 .srf_state                      = 0x00,
 492                 .io_configuration               = 0x01,
 493                 .sdio_configuration             = 0x00,
 494                 .settings                       = 0x00,
 495                 .enable_clpc                    = 0x00,
 496                 .enable_tx_low_pwr_on_siso_rdl  = 0x00,
 497                 .rx_profile                     = 0x00,
 498         },
 499 };
 500
 501 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
 502         [PART_TOP_PRCM_ELP_SOC] = {
 503                 .mem  = { .start = 0x00A02000, .size  = 0x00010000 },
 504                 .reg  = { .start = 0x00807000, .size  = 0x00005000 },
 505                 .mem2 = { .start = 0x00800000, .size  = 0x0000B000 },
 506                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 507         },
 508         [PART_DOWN] = {
 509                 .mem  = { .start = 0x00000000, .size  = 0x00014000 },
 510                 .reg  = { .start = 0x00810000, .size  = 0x0000BFFF },
 511                 .mem2 = { .start = 0x00000000, .size  = 0x00000000 },
 512                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 513         },
 514         [PART_BOOT] = {
 515                 .mem  = { .start = 0x00700000, .size = 0x0000030c },
 516                 .reg  = { .start = 0x00802000, .size = 0x00014578 },
 517                 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
 518                 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
 519         },
 520         [PART_WORK] = {
 521                 .mem  = { .start = 0x00800000, .size  = 0x000050FC },
 522                 .reg  = { .start = 0x00B00404, .size  = 0x00001000 },
 523                 .mem2 = { .start = 0x00C00000, .size  = 0x00000400 },
 524                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 525         },
 526         [PART_PHY_INIT] = {
 527                 /* TODO: use the phy_conf struct size here */
 528                 .mem  = { .start = 0x80926000, .size = 252 },
 529                 .reg  = { .start = 0x00000000, .size = 0x00000000 },
 530                 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
 531                 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
 532         },
 533 };
 534
 535 static const int wl18xx_rtable[REG_TABLE_LEN] = {
 536         [REG_ECPU_CONTROL]              = WL18XX_REG_ECPU_CONTROL,
 537         [REG_INTERRUPT_NO_CLEAR]        = WL18XX_REG_INTERRUPT_NO_CLEAR,
 538         [REG_INTERRUPT_ACK]             = WL18XX_REG_INTERRUPT_ACK,
 539         [REG_COMMAND_MAILBOX_PTR]       = WL18XX_REG_COMMAND_MAILBOX_PTR,
 540         [REG_EVENT_MAILBOX_PTR]         = WL18XX_REG_EVENT_MAILBOX_PTR,
 541         [REG_INTERRUPT_TRIG]            = WL18XX_REG_INTERRUPT_TRIG_H,
 542         [REG_INTERRUPT_MASK]            = WL18XX_REG_INTERRUPT_MASK,
 543         [REG_PC_ON_RECOVERY]            = 0, /* TODO: where is the PC? */
 544         [REG_CHIP_ID_B]                 = WL18XX_REG_CHIP_ID_B,
 545         [REG_CMD_MBOX_ADDRESS]          = WL18XX_CMD_MBOX_ADDRESS,
 546
 547         /* data access memory addresses, used with partition translation */
 548         [REG_SLV_MEM_DATA]              = WL18XX_SLV_MEM_DATA,
 549         [REG_SLV_REG_DATA]              = WL18XX_SLV_REG_DATA,
 550
 551         /* raw data access memory addresses */
 552         [REG_RAW_FW_STATUS_ADDR]        = WL18XX_FW_STATUS_ADDR,
 553 };
 554
 555 /* TODO: maybe move to a new header file? */
 556 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw.bin"
 557
 558 static int wl18xx_identify_chip(struct wl1271 *wl)
 559 {
 560         int ret = 0;
 561
 562         switch (wl->chip.id) {
 563         case CHIP_ID_185x_PG10:
 564                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG10)",
 565                              wl->chip.id);
 566                 wl->sr_fw_name = WL18XX_FW_NAME;
 567                 wl->quirks |= WLCORE_QUIRK_NO_ELP |
 568                               WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN;
 569
 570                 /* TODO: need to blocksize alignment for RX/TX separately? */
 571                 break;
 572         default:
 573                 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
 574                 ret = -ENODEV;
 575                 goto out;
 576         }
 577
 578 out:
 579         return ret;
 580 }
 581
 582 static void wl18xx_set_clk(struct wl1271 *wl)
 583 {
 584         /*
 585          * TODO: this is hardcoded just for DVP/EVB, fix according to
 586          * new unified_drv.
 587          */
 588         wl1271_write32(wl, WL18XX_SCR_PAD2, 0xB3);
 589
 590         wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
 591         wl1271_write32(wl, 0x00A02360, 0xD0078);
 592         wl1271_write32(wl, 0x00A0236c, 0x12);
 593         wl1271_write32(wl, 0x00A02390, 0x20118);
 594 }
 595
 596 static void wl18xx_boot_soft_reset(struct wl1271 *wl)
 597 {
 598         /* disable Rx/Tx */
 599         wl1271_write32(wl, WL18XX_ENABLE, 0x0);
 600
 601         /* disable auto calibration on start*/
 602         wl1271_write32(wl, WL18XX_SPARE_A2, 0xffff);
 603 }
 604
 605 static int wl18xx_pre_boot(struct wl1271 *wl)
 606 {
 607         /* TODO: add hw_pg_ver reading */
 608
 609         wl18xx_set_clk(wl);
 610
 611         /* Continue the ELP wake up sequence */
 612         wl1271_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
 613         udelay(500);
 614
 615         wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 616
 617         /* Disable interrupts */
 618         wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
 619
 620         wl18xx_boot_soft_reset(wl);
 621
 622         return 0;
 623 }
 624
 625 static void wl18xx_pre_upload(struct wl1271 *wl)
 626 {
 627         u32 tmp;
 628
 629         wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 630
 631         /* TODO: check if this is all needed */
 632         wl1271_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
 633
 634         tmp = wlcore_read_reg(wl, REG_CHIP_ID_B);
 635
 636         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
 637
 638         tmp = wl1271_read32(wl, WL18XX_SCR_PAD2);
 639 }
 640
 641 static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
 642 {
 643         struct wl18xx_priv *priv = wl->priv;
 644         struct wl18xx_conf_phy *phy = &priv->conf.phy;
 645         struct wl18xx_mac_and_phy_params params;
 646
 647         memset(&params, 0, sizeof(params));
 648
 649         params.phy_standalone = phy->phy_standalone;
 650         params.rdl = phy->rdl;
 651         params.enable_clpc = phy->enable_clpc;
 652         params.enable_tx_low_pwr_on_siso_rdl =
 653                 phy->enable_tx_low_pwr_on_siso_rdl;
 654         params.auto_detect = phy->auto_detect;
 655         params.dedicated_fem = phy->dedicated_fem;
 656         params.low_band_component = phy->low_band_component;
 657         params.low_band_component_type =
 658                 phy->low_band_component_type;
 659         params.high_band_component = phy->high_band_component;
 660         params.high_band_component_type =
 661                 phy->high_band_component_type;
 662         params.number_of_assembled_ant2_4 =
 663                 phy->number_of_assembled_ant2_4;
 664         params.number_of_assembled_ant5 =
 665                 phy->number_of_assembled_ant5;
 666         params.external_pa_dc2dc = phy->external_pa_dc2dc;
 667         params.tcxo_ldo_voltage = phy->tcxo_ldo_voltage;
 668         params.xtal_itrim_val = phy->xtal_itrim_val;
 669         params.srf_state = phy->srf_state;
 670         params.io_configuration = phy->io_configuration;
 671         params.sdio_configuration = phy->sdio_configuration;
 672         params.settings = phy->settings;
 673         params.rx_profile = phy->rx_profile;
 674         params.primary_clock_setting_time =
 675                 phy->primary_clock_setting_time;
 676         params.clock_valid_on_wake_up =
 677                 phy->clock_valid_on_wake_up;
 678         params.secondary_clock_setting_time =
 679                 phy->secondary_clock_setting_time;
 680
 681         /* TODO: hardcoded for now */
 682         params.board_type = BOARD_TYPE_DVP_EVB_18XX;
 683
 684         wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
 685         wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)&params,
 686                      sizeof(params), false);
 687 }
 688
 689 static void wl18xx_enable_interrupts(struct wl1271 *wl)
 690 {
 691         wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_ALL_EVENTS_VECTOR);
 692
 693         wlcore_enable_interrupts(wl);
 694         wlcore_write_reg(wl, REG_INTERRUPT_MASK,
 695                          WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
 696 }
 697
 698 static int wl18xx_boot(struct wl1271 *wl)
 699 {
 700         int ret;
 701
 702         ret = wl18xx_pre_boot(wl);
 703         if (ret < 0)
 704                 goto out;
 705
 706         ret = wlcore_boot_upload_nvs(wl);
 707         if (ret < 0)
 708                 goto out;
 709
 710         wl18xx_pre_upload(wl);
 711
 712         ret = wlcore_boot_upload_firmware(wl);
 713         if (ret < 0)
 714                 goto out;
 715
 716         wl18xx_set_mac_and_phy(wl);
 717
 718         ret = wlcore_boot_run_firmware(wl);
 719         if (ret < 0)
 720                 goto out;
 721
 722         wl18xx_enable_interrupts(wl);
 723
 724 out:
 725         return ret;
 726 }
 727
 728 static void wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
 729                                void *buf, size_t len)
 730 {
 731         struct wl18xx_priv *priv = wl->priv;
 732
 733         memcpy(priv->cmd_buf, buf, len);
 734         memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
 735
 736         wl1271_write(wl, cmd_box_addr, priv->cmd_buf, WL18XX_CMD_MAX_SIZE,
 737                      false);
 738 }
 739
 740 static void wl18xx_ack_event(struct wl1271 *wl)
 741 {
 742         wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL18XX_INTR_TRIG_EVENT_ACK);
 743 }
 744
 745 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
 746 {
 747         u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
 748         return (len + blk_size - 1) / blk_size + spare_blks;
 749 }
 750
 751 static void
 752 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
 753                           u32 blks, u32 spare_blks)
 754 {
 755         desc->wl18xx_mem.total_mem_blocks = blks;
 756         desc->wl18xx_mem.reserved = 0;
 757 }
 758
 759 static void
 760 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
 761                             struct sk_buff *skb)
 762 {
 763         desc->length = cpu_to_le16(skb->len);
 764
 765         wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
 766                      "len: %d life: %d mem: %d", desc->hlid,
 767                      le16_to_cpu(desc->length),
 768                      le16_to_cpu(desc->life_time),
 769                      desc->wl18xx_mem.total_mem_blocks);
 770 }
 771
 772 static enum wl_rx_buf_align
 773 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
 774 {
 775         if (rx_desc & RX_BUF_PADDED_PAYLOAD)
 776                 return WLCORE_RX_BUF_PADDED;
 777
 778         return WLCORE_RX_BUF_ALIGNED;
 779 }
 780
 781 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
 782                                     u32 data_len)
 783 {
 784         struct wl1271_rx_descriptor *desc = rx_data;
 785
 786         /* invalid packet */
 787         if (data_len < sizeof(*desc))
 788                 return 0;
 789
 790         return data_len - sizeof(*desc);
 791 }
 792
 793 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
 794 {
 795         wl18xx_tx_immediate_complete(wl);
 796 }
 797
 798 static int wl18xx_hw_init(struct wl1271 *wl)
 799 {
 800         int ret;
 801         u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
 802                 HOST_IF_CFG_ADD_RX_ALIGNMENT;
 803
 804         u32 sdio_align_size = 0;
 805
 806         /* Enable Tx SDIO padding */
 807         if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
 808                 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
 809                 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
 810         }
 811
 812         /* Enable Rx SDIO padding */
 813         if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
 814                 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
 815                 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
 816         }
 817
 818         ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
 819                                             sdio_align_size,
 820                                             WL18XX_TX_HW_BLOCK_SPARE,
 821                                             WL18XX_HOST_IF_LEN_SIZE_FIELD);
 822         if (ret < 0)
 823                 return ret;
 824
 825         ret = wl18xx_acx_set_checksum_state(wl);
 826         if (ret != 0)
 827                 return ret;
 828
 829         return ret;
 830 }
 831
 832 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
 833                                     struct wl1271_tx_hw_descr *desc,
 834                                     struct sk_buff *skb)
 835 {
 836         u32 ip_hdr_offset;
 837         struct iphdr *ip_hdr;
 838
 839         if (skb->ip_summed != CHECKSUM_PARTIAL) {
 840                 desc->wl18xx_checksum_data = 0;
 841                 return;
 842         }
 843
 844         ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
 845         if (WARN_ON(ip_hdr_offset >= (1<<7))) {
 846                 desc->wl18xx_checksum_data = 0;
 847                 return;
 848         }
 849
 850         desc->wl18xx_checksum_data = ip_hdr_offset << 1;
 851
 852         /* FW is interested only in the LSB of the protocol  TCP=0 UDP=1 */
 853         ip_hdr = (void *)skb_network_header(skb);
 854         desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
 855 }
 856
 857 static void wl18xx_set_rx_csum(struct wl1271 *wl,
 858                                struct wl1271_rx_descriptor *desc,
 859                                struct sk_buff *skb)
 860 {
 861         if (desc->status & WL18XX_RX_CHECKSUM_MASK)
 862                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 863 }
 864
 865 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
 866                                        struct wl12xx_vif *wlvif)
 867 {
 868         u32 hw_rate_set = wlvif->rate_set;
 869
 870         if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
 871             wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
 872                 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
 873                 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
 874
 875                 /* we don't support MIMO in wide-channel mode */
 876                 hw_rate_set &= ~CONF_TX_MIMO_RATES;
 877         }
 878
 879         return hw_rate_set;
 880 }
 881
 882 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
 883                                              struct wl12xx_vif *wlvif)
 884 {
 885         if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
 886             wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
 887                 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
 888                 return CONF_TX_RATE_USE_WIDE_CHAN;
 889         } else {
 890                 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
 891                 return CONF_TX_MIMO_RATES;
 892         }
 893 }
 894
 895 static void wl18xx_conf_init(struct wl1271 *wl)
 896 {
 897         struct wl18xx_priv *priv = wl->priv;
 898
 899         /* apply driver default configuration */
 900         memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf));
 901
 902         /* apply default private configuration */
 903         memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf));
 904 }
 905
 906 static struct wlcore_ops wl18xx_ops = {
 907         .identify_chip  = wl18xx_identify_chip,
 908         .boot           = wl18xx_boot,
 909         .trigger_cmd    = wl18xx_trigger_cmd,
 910         .ack_event      = wl18xx_ack_event,
 911         .calc_tx_blocks = wl18xx_calc_tx_blocks,
 912         .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
 913         .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
 914         .get_rx_buf_align = wl18xx_get_rx_buf_align,
 915         .get_rx_packet_len = wl18xx_get_rx_packet_len,
 916         .tx_immediate_compl = wl18xx_tx_immediate_completion,
 917         .tx_delayed_compl = NULL,
 918         .hw_init        = wl18xx_hw_init,
 919         .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
 920         .set_rx_csum = wl18xx_set_rx_csum,
 921         .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
 922         .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
 923 };
 924
 925 /* HT cap appropriate for wide channels */
 926 static struct ieee80211_sta_ht_cap wl18xx_ht_cap = {
 927         .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
 928                IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40,
 929         .ht_supported = true,
 930         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
 931         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
 932         .mcs = {
 933                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
 934                 .rx_highest = cpu_to_le16(150),
 935                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
 936                 },
 937 };
 938
 939 int __devinit wl18xx_probe(struct platform_device *pdev)
 940 {
 941         struct wl1271 *wl;
 942         struct ieee80211_hw *hw;
 943         struct wl18xx_priv *priv;
 944
 945         hw = wlcore_alloc_hw(sizeof(*priv));
 946         if (IS_ERR(hw)) {
 947                 wl1271_error("can't allocate hw");
 948                 return PTR_ERR(hw);
 949         }
 950
 951         wl = hw->priv;
 952         wl->ops = &wl18xx_ops;
 953         wl->ptable = wl18xx_ptable;
 954         wl->rtable = wl18xx_rtable;
 955         wl->num_tx_desc = 32;
 956         wl->normal_tx_spare = WL18XX_TX_HW_BLOCK_SPARE;
 957         wl->gem_tx_spare = WL18XX_TX_HW_GEM_BLOCK_SPARE;
 958         wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
 959         wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
 960         wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
 961         wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
 962         memcpy(&wl->ht_cap, &wl18xx_ht_cap, sizeof(wl18xx_ht_cap));
 963         wl18xx_conf_init(wl);
 964
 965         return wlcore_probe(wl, pdev);
 966 }
 967
 968 static const struct platform_device_id wl18xx_id_table[] __devinitconst = {
 969         { "wl18xx", 0 },
 970         {  } /* Terminating Entry */
 971 };
 972 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
 973
 974 static struct platform_driver wl18xx_driver = {
 975         .probe          = wl18xx_probe,
 976         .remove         = __devexit_p(wlcore_remove),
 977         .id_table       = wl18xx_id_table,
 978         .driver = {
 979                 .name   = "wl18xx_driver",
 980                 .owner  = THIS_MODULE,
 981         }
 982 };
 983
 984 static int __init wl18xx_init(void)
 985 {
 986         return platform_driver_register(&wl18xx_driver);
 987 }
 988 module_init(wl18xx_init);
 989
 990 static void __exit wl18xx_exit(void)
 991 {
 992         platform_driver_unregister(&wl18xx_driver);
 993 }
 994 module_exit(wl18xx_exit);
 995
 996 MODULE_LICENSE("GPL v2");
 997 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
 998 MODULE_FIRMWARE(WL18XX_FW_NAME);