2 * This file is part of wl1271
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
25 #include <linux/err.h>
27 #include <linux/wl12xx.h>
29 #include "../wlcore/wlcore.h"
30 #include "../wlcore/debug.h"
31 #include "../wlcore/io.h"
32 #include "../wlcore/acx.h"
33 #include "../wlcore/tx.h"
34 #include "../wlcore/rx.h"
35 #include "../wlcore/boot.h"
43 static char *fref_param;
44 static char *tcxo_param;
46 static struct wlcore_conf wl12xx_conf = {
49 [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
50 [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
51 [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
52 [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
53 [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
54 [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
55 [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
56 [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
57 [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
58 [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
59 [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
60 [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
61 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
62 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
63 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
64 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
65 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
66 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
67 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
68 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
69 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
70 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
71 [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
72 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
73 [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
74 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
75 /* active scan params */
76 [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
77 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
78 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
79 /* passive scan params */
80 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
81 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
82 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
83 /* passive scan in dual antenna params */
84 [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
85 [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
86 [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
88 [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
89 [CONF_SG_ANTENNA_CONFIGURATION] = 0,
90 [CONF_SG_BEACON_MISS_PERCENT] = 60,
91 [CONF_SG_DHCP_TIME] = 5000,
94 [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
95 [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
96 [CONF_SG_HV3_MAX_SERVED] = 6,
97 [CONF_SG_PS_POLL_TIMEOUT] = 10,
98 [CONF_SG_UPSD_TIMEOUT] = 10,
99 [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
100 [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
101 [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
103 [CONF_AP_BEACON_MISS_TX] = 3,
104 [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
105 [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
106 [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
107 [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
108 [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
109 /* CTS Diluting params */
110 [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
111 [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
113 .state = CONF_SG_PROTECTIVE,
116 .rx_msdu_life_time = 512000,
117 .packet_detection_threshold = 0,
118 .ps_poll_timeout = 15,
120 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
121 .rx_cca_threshold = 0,
122 .irq_blk_threshold = 0xFFFF,
123 .irq_pkt_threshold = 0,
125 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
128 .tx_energy_detection = 0,
131 .short_retry_limit = 10,
132 .long_retry_limit = 10,
155 .aifsn = CONF_TX_AIFS_PIFS,
162 .aifsn = CONF_TX_AIFS_PIFS,
166 .max_tx_retries = 100,
167 .ap_aging_period = 300,
171 .queue_id = CONF_TX_AC_BE,
172 .channel_type = CONF_CHANNEL_TYPE_EDCF,
173 .tsid = CONF_TX_AC_BE,
174 .ps_scheme = CONF_PS_SCHEME_LEGACY,
175 .ack_policy = CONF_ACK_POLICY_LEGACY,
179 .queue_id = CONF_TX_AC_BK,
180 .channel_type = CONF_CHANNEL_TYPE_EDCF,
181 .tsid = CONF_TX_AC_BK,
182 .ps_scheme = CONF_PS_SCHEME_LEGACY,
183 .ack_policy = CONF_ACK_POLICY_LEGACY,
187 .queue_id = CONF_TX_AC_VI,
188 .channel_type = CONF_CHANNEL_TYPE_EDCF,
189 .tsid = CONF_TX_AC_VI,
190 .ps_scheme = CONF_PS_SCHEME_LEGACY,
191 .ack_policy = CONF_ACK_POLICY_LEGACY,
195 .queue_id = CONF_TX_AC_VO,
196 .channel_type = CONF_CHANNEL_TYPE_EDCF,
197 .tsid = CONF_TX_AC_VO,
198 .ps_scheme = CONF_PS_SCHEME_LEGACY,
199 .ack_policy = CONF_ACK_POLICY_LEGACY,
203 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
204 .tx_compl_timeout = 700,
205 .tx_compl_threshold = 4,
206 .basic_rate = CONF_HW_BIT_RATE_1MBPS,
207 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
208 .tmpl_short_retry_limit = 10,
209 .tmpl_long_retry_limit = 10,
210 .tx_watchdog_timeout = 5000,
213 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
214 .listen_interval = 1,
215 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
216 .suspend_listen_interval = 3,
217 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
218 .bcn_filt_ie_count = 3,
221 .ie = WLAN_EID_CHANNEL_SWITCH,
222 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
225 .ie = WLAN_EID_HT_OPERATION,
226 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
229 .ie = WLAN_EID_ERP_INFO,
230 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
233 .synch_fail_thold = 12,
234 .bss_lose_timeout = 400,
235 .beacon_rx_timeout = 10000,
236 .broadcast_timeout = 20000,
237 .rx_broadcast_in_ps = 1,
238 .ps_poll_threshold = 10,
239 .bet_enable = CONF_BET_MODE_ENABLE,
240 .bet_max_consecutive = 50,
241 .psm_entry_retries = 8,
242 .psm_exit_retries = 16,
243 .psm_entry_nullfunc_retries = 3,
244 .dynamic_ps_timeout = 1500,
246 .keep_alive_interval = 55000,
247 .max_listen_interval = 20,
248 .sta_sleep_auth = WL1271_PSM_ILLEGAL,
255 .host_clk_settling_time = 5000,
256 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
260 .avg_weight_rssi_beacon = 20,
261 .avg_weight_rssi_data = 10,
262 .avg_weight_snr_beacon = 20,
263 .avg_weight_snr_data = 10,
266 .min_dwell_time_active = 7500,
267 .max_dwell_time_active = 30000,
268 .min_dwell_time_passive = 100000,
269 .max_dwell_time_passive = 100000,
271 .split_scan_timeout = 50000,
275 * Values are in TU/1000 but since sched scan FW command
276 * params are in TUs rounding up may occur.
278 .base_dwell_time = 7500,
279 .max_dwell_time_delta = 22500,
280 /* based on 250bits per probe @1Mbps */
281 .dwell_time_delta_per_probe = 2000,
282 /* based on 250bits per probe @6Mbps (plus a bit more) */
283 .dwell_time_delta_per_probe_5 = 350,
284 .dwell_time_passive = 100000,
285 .dwell_time_dfs = 150000,
287 .rssi_threshold = -90,
292 .tx_ba_win_size = 64,
293 .inactivity_timeout = 10000,
294 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
297 * Memory config for wl127x chips is given in the
298 * wl12xx_default_priv_conf struct. The below configuration is
305 .tx_min_block_num = 40,
307 .min_req_tx_blocks = 45,
308 .min_req_rx_blocks = 22,
314 .n_divider_fref_set_1 = 0xff, /* default */
315 .n_divider_fref_set_2 = 12,
316 .m_divider_fref_set_1 = 0xffff,
317 .m_divider_fref_set_2 = 148, /* default */
318 .coex_pll_stabilization_time = 0xffffffff, /* default */
319 .ldo_stabilization_time = 0xffff, /* default */
320 .fm_disturbed_band_margin = 0xff, /* default */
321 .swallow_clk_diff = 0xff, /* default */
330 .mode = WL12XX_FWLOG_ON_DEMAND,
333 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
334 .output = WL12XX_FWLOG_OUTPUT_HOST,
338 .rate_retry_score = 32000,
343 .inverse_curiosity_factor = 5,
345 .tx_fail_high_th = 10,
346 .per_alpha_shift = 4,
348 .per_beta1_shift = 10,
349 .per_beta2_shift = 8,
351 .rate_check_down = 12,
352 .rate_retry_policy = {
353 0x00, 0x00, 0x00, 0x00, 0x00,
354 0x00, 0x00, 0x00, 0x00, 0x00,
360 .hangover_period = 20,
362 .early_termination_mode = 1,
373 static struct wl12xx_priv_conf wl12xx_default_priv_conf = {
375 .tx_per_channel_power_compensation_2 = {
376 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
378 .tx_per_channel_power_compensation_5 = {
379 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
380 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
381 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
388 .tx_min_block_num = 40,
390 .min_req_tx_blocks = 100,
391 .min_req_rx_blocks = 22,
397 #define WL12XX_TX_HW_BLOCK_SPARE_DEFAULT 1
398 #define WL12XX_TX_HW_BLOCK_GEM_SPARE 2
399 #define WL12XX_TX_HW_BLOCK_SIZE 252
401 static const u8 wl12xx_rate_to_idx_2ghz[] = {
402 /* MCS rates are used only with 11n */
403 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
404 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
405 6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
406 5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
407 4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
408 3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
409 2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
410 1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
411 0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
413 11, /* WL12XX_CONF_HW_RXTX_RATE_54 */
414 10, /* WL12XX_CONF_HW_RXTX_RATE_48 */
415 9, /* WL12XX_CONF_HW_RXTX_RATE_36 */
416 8, /* WL12XX_CONF_HW_RXTX_RATE_24 */
418 /* TI-specific rate */
419 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
421 7, /* WL12XX_CONF_HW_RXTX_RATE_18 */
422 6, /* WL12XX_CONF_HW_RXTX_RATE_12 */
423 3, /* WL12XX_CONF_HW_RXTX_RATE_11 */
424 5, /* WL12XX_CONF_HW_RXTX_RATE_9 */
425 4, /* WL12XX_CONF_HW_RXTX_RATE_6 */
426 2, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
427 1, /* WL12XX_CONF_HW_RXTX_RATE_2 */
428 0 /* WL12XX_CONF_HW_RXTX_RATE_1 */
431 static const u8 wl12xx_rate_to_idx_5ghz[] = {
432 /* MCS rates are used only with 11n */
433 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
434 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
435 6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
436 5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
437 4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
438 3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
439 2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
440 1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
441 0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
443 7, /* WL12XX_CONF_HW_RXTX_RATE_54 */
444 6, /* WL12XX_CONF_HW_RXTX_RATE_48 */
445 5, /* WL12XX_CONF_HW_RXTX_RATE_36 */
446 4, /* WL12XX_CONF_HW_RXTX_RATE_24 */
448 /* TI-specific rate */
449 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
451 3, /* WL12XX_CONF_HW_RXTX_RATE_18 */
452 2, /* WL12XX_CONF_HW_RXTX_RATE_12 */
453 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_11 */
454 1, /* WL12XX_CONF_HW_RXTX_RATE_9 */
455 0, /* WL12XX_CONF_HW_RXTX_RATE_6 */
456 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
457 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_2 */
458 CONF_HW_RXTX_RATE_UNSUPPORTED /* WL12XX_CONF_HW_RXTX_RATE_1 */
461 static const u8 *wl12xx_band_rate_to_idx[] = {
462 [IEEE80211_BAND_2GHZ] = wl12xx_rate_to_idx_2ghz,
463 [IEEE80211_BAND_5GHZ] = wl12xx_rate_to_idx_5ghz
466 enum wl12xx_hw_rates {
467 WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI = 0,
468 WL12XX_CONF_HW_RXTX_RATE_MCS7,
469 WL12XX_CONF_HW_RXTX_RATE_MCS6,
470 WL12XX_CONF_HW_RXTX_RATE_MCS5,
471 WL12XX_CONF_HW_RXTX_RATE_MCS4,
472 WL12XX_CONF_HW_RXTX_RATE_MCS3,
473 WL12XX_CONF_HW_RXTX_RATE_MCS2,
474 WL12XX_CONF_HW_RXTX_RATE_MCS1,
475 WL12XX_CONF_HW_RXTX_RATE_MCS0,
476 WL12XX_CONF_HW_RXTX_RATE_54,
477 WL12XX_CONF_HW_RXTX_RATE_48,
478 WL12XX_CONF_HW_RXTX_RATE_36,
479 WL12XX_CONF_HW_RXTX_RATE_24,
480 WL12XX_CONF_HW_RXTX_RATE_22,
481 WL12XX_CONF_HW_RXTX_RATE_18,
482 WL12XX_CONF_HW_RXTX_RATE_12,
483 WL12XX_CONF_HW_RXTX_RATE_11,
484 WL12XX_CONF_HW_RXTX_RATE_9,
485 WL12XX_CONF_HW_RXTX_RATE_6,
486 WL12XX_CONF_HW_RXTX_RATE_5_5,
487 WL12XX_CONF_HW_RXTX_RATE_2,
488 WL12XX_CONF_HW_RXTX_RATE_1,
489 WL12XX_CONF_HW_RXTX_RATE_MAX,
492 static struct wlcore_partition_set wl12xx_ptable[PART_TABLE_LEN] = {
499 .start = REGISTERS_BASE,
512 [PART_BOOT] = { /* in wl12xx we can use a mix of work and down
519 .start = REGISTERS_BASE,
538 .start = REGISTERS_BASE,
571 static const int wl12xx_rtable[REG_TABLE_LEN] = {
572 [REG_ECPU_CONTROL] = WL12XX_REG_ECPU_CONTROL,
573 [REG_INTERRUPT_NO_CLEAR] = WL12XX_REG_INTERRUPT_NO_CLEAR,
574 [REG_INTERRUPT_ACK] = WL12XX_REG_INTERRUPT_ACK,
575 [REG_COMMAND_MAILBOX_PTR] = WL12XX_REG_COMMAND_MAILBOX_PTR,
576 [REG_EVENT_MAILBOX_PTR] = WL12XX_REG_EVENT_MAILBOX_PTR,
577 [REG_INTERRUPT_TRIG] = WL12XX_REG_INTERRUPT_TRIG,
578 [REG_INTERRUPT_MASK] = WL12XX_REG_INTERRUPT_MASK,
579 [REG_PC_ON_RECOVERY] = WL12XX_SCR_PAD4,
580 [REG_CHIP_ID_B] = WL12XX_CHIP_ID_B,
581 [REG_CMD_MBOX_ADDRESS] = WL12XX_CMD_MBOX_ADDRESS,
583 /* data access memory addresses, used with partition translation */
584 [REG_SLV_MEM_DATA] = WL1271_SLV_MEM_DATA,
585 [REG_SLV_REG_DATA] = WL1271_SLV_REG_DATA,
587 /* raw data access memory addresses */
588 [REG_RAW_FW_STATUS_ADDR] = FW_STATUS_ADDR,
591 /* TODO: maybe move to a new header file? */
592 #define WL127X_FW_NAME_MULTI "ti-connectivity/wl127x-fw-5-mr.bin"
593 #define WL127X_FW_NAME_SINGLE "ti-connectivity/wl127x-fw-5-sr.bin"
594 #define WL127X_PLT_FW_NAME "ti-connectivity/wl127x-fw-5-plt.bin"
596 #define WL128X_FW_NAME_MULTI "ti-connectivity/wl128x-fw-5-mr.bin"
597 #define WL128X_FW_NAME_SINGLE "ti-connectivity/wl128x-fw-5-sr.bin"
598 #define WL128X_PLT_FW_NAME "ti-connectivity/wl128x-fw-5-plt.bin"
600 static int wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
604 if (wl->chip.id != CHIP_ID_1283_PG20) {
605 struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
606 struct wl127x_rx_mem_pool_addr rx_mem_addr;
609 * Choose the block we want to read
610 * For aggregated packets, only the first memory block
611 * should be retrieved. The FW takes care of the rest.
613 u32 mem_block = rx_desc & RX_MEM_BLOCK_MASK;
615 rx_mem_addr.addr = (mem_block << 8) +
616 le32_to_cpu(wl_mem_map->packet_memory_pool_start);
618 rx_mem_addr.addr_extra = rx_mem_addr.addr + 4;
620 ret = wlcore_write(wl, WL1271_SLV_REG_DATA, &rx_mem_addr,
621 sizeof(rx_mem_addr), false);
629 static int wl12xx_identify_chip(struct wl1271 *wl)
633 switch (wl->chip.id) {
634 case CHIP_ID_1271_PG10:
635 wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
638 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
639 WLCORE_QUIRK_DUAL_PROBE_TMPL |
640 WLCORE_QUIRK_TKIP_HEADER_SPACE;
641 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
642 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
643 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
644 sizeof(wl->conf.mem));
646 /* read data preparation is only needed by wl127x */
647 wl->ops->prepare_read = wl127x_prepare_read;
649 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER, WL127X_IFTYPE_VER,
650 WL127X_MAJOR_VER, WL127X_SUBTYPE_VER,
654 case CHIP_ID_1271_PG20:
655 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
658 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
659 WLCORE_QUIRK_DUAL_PROBE_TMPL |
660 WLCORE_QUIRK_TKIP_HEADER_SPACE;
661 wl->plt_fw_name = WL127X_PLT_FW_NAME;
662 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
663 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
664 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
665 sizeof(wl->conf.mem));
667 /* read data preparation is only needed by wl127x */
668 wl->ops->prepare_read = wl127x_prepare_read;
670 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER, WL127X_IFTYPE_VER,
671 WL127X_MAJOR_VER, WL127X_SUBTYPE_VER,
675 case CHIP_ID_1283_PG20:
676 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1283 PG20)",
678 wl->plt_fw_name = WL128X_PLT_FW_NAME;
679 wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
680 wl->mr_fw_name = WL128X_FW_NAME_MULTI;
682 /* wl128x requires TX blocksize alignment */
683 wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
684 WLCORE_QUIRK_DUAL_PROBE_TMPL |
685 WLCORE_QUIRK_TKIP_HEADER_SPACE;
687 wlcore_set_min_fw_ver(wl, WL128X_CHIP_VER, WL128X_IFTYPE_VER,
688 WL128X_MAJOR_VER, WL128X_SUBTYPE_VER,
691 case CHIP_ID_1283_PG10:
693 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
702 static int __must_check wl12xx_top_reg_write(struct wl1271 *wl, int addr,
707 /* write address >> 1 + 0x30000 to OCP_POR_CTR */
708 addr = (addr >> 1) + 0x30000;
709 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
713 /* write value to OCP_POR_WDATA */
714 ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val);
718 /* write 1 to OCP_CMD */
719 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
727 static int __must_check wl12xx_top_reg_read(struct wl1271 *wl, int addr,
731 int timeout = OCP_CMD_LOOP;
734 /* write address >> 1 + 0x30000 to OCP_POR_CTR */
735 addr = (addr >> 1) + 0x30000;
736 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
740 /* write 2 to OCP_CMD */
741 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
745 /* poll for data ready */
747 ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val);
750 } while (!(val & OCP_READY_MASK) && --timeout);
753 wl1271_warning("Top register access timed out.");
757 /* check data status and return if OK */
758 if ((val & OCP_STATUS_MASK) != OCP_STATUS_OK) {
759 wl1271_warning("Top register access returned error.");
769 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
774 /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
775 ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
779 if (spare_reg == 0xFFFF)
781 spare_reg |= (BIT(3) | BIT(5) | BIT(6));
782 ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
786 /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
787 ret = wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
788 WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
792 /* Delay execution for 15msec, to let the HW settle */
798 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
803 ret = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG, &tcxo_detection);
807 if (tcxo_detection & TCXO_DET_FAILED)
813 static bool wl128x_is_fref_valid(struct wl1271 *wl)
818 ret = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG, &fref_detection);
822 if (fref_detection & FREF_CLK_DETECT_FAIL)
828 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
832 ret = wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
836 ret = wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
840 ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG,
841 MCS_PLL_CONFIG_REG_VAL);
847 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
852 struct wl12xx_priv *priv = wl->priv;
855 /* Mask bits [3:1] in the sys_clk_cfg register */
856 ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
860 if (spare_reg == 0xFFFF)
863 ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
867 /* Handle special cases of the TCXO clock */
868 if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
869 priv->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
870 return wl128x_manually_configure_mcs_pll(wl);
872 /* Set the input frequency according to the selected clock source */
873 input_freq = (clk & 1) + 1;
875 ret = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG, &pll_config);
879 if (pll_config == 0xFFFF)
881 pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
882 pll_config |= MCS_PLL_ENABLE_HP;
883 ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
889 * WL128x has two clocks input - TCXO and FREF.
890 * TCXO is the main clock of the device, while FREF is used to sync
891 * between the GPS and the cellular modem.
892 * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
893 * as the WLAN/BT main clock.
895 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
897 struct wl12xx_priv *priv = wl->priv;
901 /* For XTAL-only modes, FREF will be used after switching from TCXO */
902 if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
903 priv->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
904 if (!wl128x_switch_tcxo_to_fref(wl))
909 /* Query the HW, to determine which clock source we should use */
910 ret = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG, &sys_clk_cfg);
914 if (sys_clk_cfg == 0xFFFF)
916 if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
919 /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
920 if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
921 priv->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
922 if (!wl128x_switch_tcxo_to_fref(wl))
927 /* TCXO clock is selected */
928 if (!wl128x_is_tcxo_valid(wl))
930 *selected_clock = priv->tcxo_clock;
934 /* FREF clock is selected */
935 if (!wl128x_is_fref_valid(wl))
937 *selected_clock = priv->ref_clock;
940 return wl128x_configure_mcs_pll(wl, *selected_clock);
943 static int wl127x_boot_clk(struct wl1271 *wl)
945 struct wl12xx_priv *priv = wl->priv;
950 if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
951 wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
953 if (priv->ref_clock == CONF_REF_CLK_19_2_E ||
954 priv->ref_clock == CONF_REF_CLK_38_4_E ||
955 priv->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
956 /* ref clk: 19.2/38.4/38.4-XTAL */
958 else if (priv->ref_clock == CONF_REF_CLK_26_E ||
959 priv->ref_clock == CONF_REF_CLK_26_M_XTAL ||
960 priv->ref_clock == CONF_REF_CLK_52_E)
966 if (priv->ref_clock != CONF_REF_CLK_19_2_E) {
968 /* Set clock type (open drain) */
969 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE, &val);
973 val &= FREF_CLK_TYPE_BITS;
974 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
978 /* Set clock pull mode (no pull) */
979 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL, &val);
984 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
989 /* Set clock polarity */
990 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY, &val);
994 val &= FREF_CLK_POLARITY_BITS;
995 val |= CLK_REQ_OUTN_SEL;
996 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
1001 ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk);
1005 ret = wlcore_read32(wl, WL12XX_PLL_PARAMETERS, &pause);
1009 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
1011 pause &= ~(WU_COUNTER_PAUSE_VAL);
1012 pause |= WU_COUNTER_PAUSE_VAL;
1013 ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
1019 static int wl1271_boot_soft_reset(struct wl1271 *wl)
1021 unsigned long timeout;
1025 /* perform soft reset */
1026 ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
1030 /* SOFT_RESET is self clearing */
1031 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
1033 ret = wlcore_read32(wl, WL12XX_SLV_SOFT_RESET, &boot_data);
1037 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
1038 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
1041 if (time_after(jiffies, timeout)) {
1042 /* 1.2 check pWhalBus->uSelfClearTime if the
1043 * timeout was reached */
1044 wl1271_error("soft reset timeout");
1048 udelay(SOFT_RESET_STALL_TIME);
1052 ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0);
1056 /* disable auto calibration on start*/
1057 ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff);
1063 static int wl12xx_pre_boot(struct wl1271 *wl)
1065 struct wl12xx_priv *priv = wl->priv;
1068 int selected_clock = -1;
1070 if (wl->chip.id == CHIP_ID_1283_PG20) {
1071 ret = wl128x_boot_clk(wl, &selected_clock);
1075 ret = wl127x_boot_clk(wl);
1080 /* Continue the ELP wake up sequence */
1081 ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1087 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1091 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
1092 to be used by DRPw FW. The RTRIM value will be added by the FW
1093 before taking DRPw out of reset */
1095 ret = wlcore_read32(wl, WL12XX_DRPW_SCRATCH_START, &clk);
1099 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
1101 if (wl->chip.id == CHIP_ID_1283_PG20)
1102 clk |= ((selected_clock & 0x3) << 1) << 4;
1104 clk |= (priv->ref_clock << 1) << 4;
1106 ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
1110 ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
1114 /* Disable interrupts */
1115 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
1119 ret = wl1271_boot_soft_reset(wl);
1127 static int wl12xx_pre_upload(struct wl1271 *wl)
1133 /* write firmware's last address (ie. it's length) to
1134 * ACX_EEPROMLESS_IND_REG */
1135 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
1137 ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
1141 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
1145 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
1147 /* 6. read the EEPROM parameters */
1148 ret = wlcore_read32(wl, WL12XX_SCR_PAD2, &tmp);
1152 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
1155 if (wl->chip.id == CHIP_ID_1283_PG20) {
1156 ret = wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
1161 /* polarity must be set before the firmware is loaded */
1162 ret = wl12xx_top_reg_read(wl, OCP_REG_POLARITY, &polarity);
1166 /* We use HIGH polarity, so unset the LOW bit */
1167 polarity &= ~POLARITY_LOW;
1168 ret = wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
1174 static int wl12xx_enable_interrupts(struct wl1271 *wl)
1178 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1179 WL12XX_ACX_ALL_EVENTS_VECTOR);
1183 wlcore_enable_interrupts(wl);
1184 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1185 WL1271_ACX_INTR_ALL & ~(WL12XX_INTR_MASK));
1189 ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
1195 static int wl12xx_boot(struct wl1271 *wl)
1199 ret = wl12xx_pre_boot(wl);
1203 ret = wlcore_boot_upload_nvs(wl);
1207 ret = wl12xx_pre_upload(wl);
1211 ret = wlcore_boot_upload_firmware(wl);
1215 ret = wlcore_boot_run_firmware(wl);
1219 ret = wl12xx_enable_interrupts(wl);
1225 static int wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1226 void *buf, size_t len)
1230 ret = wlcore_write(wl, cmd_box_addr, buf, len, false);
1234 ret = wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
1239 static int wl12xx_ack_event(struct wl1271 *wl)
1241 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1242 WL12XX_INTR_TRIG_EVENT_ACK);
1245 static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1247 u32 blk_size = WL12XX_TX_HW_BLOCK_SIZE;
1248 u32 align_len = wlcore_calc_packet_alignment(wl, len);
1250 return (align_len + blk_size - 1) / blk_size + spare_blks;
1254 wl12xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1255 u32 blks, u32 spare_blks)
1257 if (wl->chip.id == CHIP_ID_1283_PG20) {
1258 desc->wl128x_mem.total_mem_blocks = blks;
1260 desc->wl127x_mem.extra_blocks = spare_blks;
1261 desc->wl127x_mem.total_mem_blocks = blks;
1266 wl12xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1267 struct sk_buff *skb)
1269 u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len);
1271 if (wl->chip.id == CHIP_ID_1283_PG20) {
1272 desc->wl128x_mem.extra_bytes = aligned_len - skb->len;
1273 desc->length = cpu_to_le16(aligned_len >> 2);
1275 wl1271_debug(DEBUG_TX,
1276 "tx_fill_hdr: hlid: %d len: %d life: %d mem: %d extra: %d",
1278 le16_to_cpu(desc->length),
1279 le16_to_cpu(desc->life_time),
1280 desc->wl128x_mem.total_mem_blocks,
1281 desc->wl128x_mem.extra_bytes);
1283 /* calculate number of padding bytes */
1284 int pad = aligned_len - skb->len;
1286 cpu_to_le16(pad << TX_HW_ATTR_OFST_LAST_WORD_PAD);
1288 /* Store the aligned length in terms of words */
1289 desc->length = cpu_to_le16(aligned_len >> 2);
1291 wl1271_debug(DEBUG_TX,
1292 "tx_fill_hdr: pad: %d hlid: %d len: %d life: %d mem: %d",
1294 le16_to_cpu(desc->length),
1295 le16_to_cpu(desc->life_time),
1296 desc->wl127x_mem.total_mem_blocks);
1300 static enum wl_rx_buf_align
1301 wl12xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1303 if (rx_desc & RX_BUF_UNALIGNED_PAYLOAD)
1304 return WLCORE_RX_BUF_UNALIGNED;
1306 return WLCORE_RX_BUF_ALIGNED;
1309 static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1312 struct wl1271_rx_descriptor *desc = rx_data;
1314 /* invalid packet */
1315 if (data_len < sizeof(*desc) ||
1316 data_len < sizeof(*desc) + desc->pad_len)
1319 return data_len - sizeof(*desc) - desc->pad_len;
1322 static int wl12xx_tx_delayed_compl(struct wl1271 *wl)
1324 if (wl->fw_status_1->tx_results_counter ==
1325 (wl->tx_results_count & 0xff))
1328 return wlcore_tx_complete(wl);
1331 static int wl12xx_hw_init(struct wl1271 *wl)
1335 if (wl->chip.id == CHIP_ID_1283_PG20) {
1336 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
1338 ret = wl128x_cmd_general_parms(wl);
1343 * If we are in calibrator based auto detect then we got the FEM nr
1344 * in wl->fem_manuf. No need to continue further
1346 if (wl->plt_mode == PLT_FEM_DETECT)
1349 ret = wl128x_cmd_radio_parms(wl);
1353 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
1354 /* Enable SDIO padding */
1355 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1357 /* Must be before wl1271_acx_init_mem_config() */
1358 ret = wl1271_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap);
1362 ret = wl1271_cmd_general_parms(wl);
1367 * If we are in calibrator based auto detect then we got the FEM nr
1368 * in wl->fem_manuf. No need to continue further
1370 if (wl->plt_mode == PLT_FEM_DETECT)
1373 ret = wl1271_cmd_radio_parms(wl);
1376 ret = wl1271_cmd_ext_radio_parms(wl);
1384 static u32 wl12xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1385 struct wl12xx_vif *wlvif)
1387 return wlvif->rate_set;
1390 static int wl12xx_identify_fw(struct wl1271 *wl)
1392 unsigned int *fw_ver = wl->chip.fw_ver;
1394 /* Only new station firmwares support routing fw logs to the host */
1395 if ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) &&
1396 (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_FWLOG_STA_MIN))
1397 wl->quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
1399 /* This feature is not yet supported for AP mode */
1400 if (fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP)
1401 wl->quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
1406 static void wl12xx_conf_init(struct wl1271 *wl)
1408 struct wl12xx_priv *priv = wl->priv;
1410 /* apply driver default configuration */
1411 memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf));
1413 /* apply default private configuration */
1414 memcpy(&priv->conf, &wl12xx_default_priv_conf, sizeof(priv->conf));
1417 static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
1419 bool supported = false;
1422 if (wl->chip.id == CHIP_ID_1283_PG20) {
1423 major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver);
1424 minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver);
1426 /* in wl128x we have the MAC address if the PG is >= (2, 1) */
1427 if (major > 2 || (major == 2 && minor >= 1))
1430 major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver);
1431 minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver);
1433 /* in wl127x we have the MAC address if the PG is >= (3, 1) */
1434 if (major == 3 && minor >= 1)
1438 wl1271_debug(DEBUG_PROBE,
1439 "PG Ver major = %d minor = %d, MAC %s present",
1440 major, minor, supported ? "is" : "is not");
1445 static int wl12xx_get_fuse_mac(struct wl1271 *wl)
1450 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1454 ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1, &mac1);
1458 ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2, &mac2);
1462 /* these are the two parts of the BD_ADDR */
1463 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1464 ((mac1 & 0xff000000) >> 24);
1465 wl->fuse_nic_addr = mac1 & 0xffffff;
1467 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1473 static int wl12xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1478 if (wl->chip.id == CHIP_ID_1283_PG20)
1479 ret = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1,
1482 ret = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1,
1485 if (ret >= 0 && ver)
1486 *ver = (s8)((die_info & PG_VER_MASK) >> PG_VER_OFFSET);
1491 static int wl12xx_get_mac(struct wl1271 *wl)
1493 if (wl12xx_mac_in_fuse(wl))
1494 return wl12xx_get_fuse_mac(wl);
1499 static void wl12xx_set_tx_desc_csum(struct wl1271 *wl,
1500 struct wl1271_tx_hw_descr *desc,
1501 struct sk_buff *skb)
1503 desc->wl12xx_reserved = 0;
1506 static int wl12xx_plt_init(struct wl1271 *wl)
1510 ret = wl->ops->boot(wl);
1514 ret = wl->ops->hw_init(wl);
1516 goto out_irq_disable;
1519 * If we are in calibrator based auto detect then we got the FEM nr
1520 * in wl->fem_manuf. No need to continue further
1522 if (wl->plt_mode == PLT_FEM_DETECT)
1525 ret = wl1271_acx_init_mem_config(wl);
1527 goto out_irq_disable;
1529 ret = wl12xx_acx_mem_cfg(wl);
1531 goto out_free_memmap;
1533 /* Enable data path */
1534 ret = wl1271_cmd_data_path(wl, 1);
1536 goto out_free_memmap;
1538 /* Configure for CAM power saving (ie. always active) */
1539 ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
1541 goto out_free_memmap;
1544 ret = wl1271_acx_pm_config(wl);
1546 goto out_free_memmap;
1551 kfree(wl->target_mem_map);
1552 wl->target_mem_map = NULL;
1555 mutex_unlock(&wl->mutex);
1556 /* Unlocking the mutex in the middle of handling is
1557 inherently unsafe. In this case we deem it safe to do,
1558 because we need to let any possibly pending IRQ out of
1559 the system (and while we are WL1271_STATE_OFF the IRQ
1560 work function will not do anything.) Also, any other
1561 possible concurrent operations will fail due to the
1562 current state, hence the wl1271 struct should be safe. */
1563 wlcore_disable_interrupts(wl);
1564 mutex_lock(&wl->mutex);
1569 static int wl12xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1572 return WL12XX_TX_HW_BLOCK_GEM_SPARE;
1574 return WL12XX_TX_HW_BLOCK_SPARE_DEFAULT;
1577 static int wl12xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1578 struct ieee80211_vif *vif,
1579 struct ieee80211_sta *sta,
1580 struct ieee80211_key_conf *key_conf)
1582 return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1585 static struct wlcore_ops wl12xx_ops = {
1586 .identify_chip = wl12xx_identify_chip,
1587 .identify_fw = wl12xx_identify_fw,
1588 .boot = wl12xx_boot,
1589 .plt_init = wl12xx_plt_init,
1590 .trigger_cmd = wl12xx_trigger_cmd,
1591 .ack_event = wl12xx_ack_event,
1592 .calc_tx_blocks = wl12xx_calc_tx_blocks,
1593 .set_tx_desc_blocks = wl12xx_set_tx_desc_blocks,
1594 .set_tx_desc_data_len = wl12xx_set_tx_desc_data_len,
1595 .get_rx_buf_align = wl12xx_get_rx_buf_align,
1596 .get_rx_packet_len = wl12xx_get_rx_packet_len,
1597 .tx_immediate_compl = NULL,
1598 .tx_delayed_compl = wl12xx_tx_delayed_compl,
1599 .hw_init = wl12xx_hw_init,
1601 .sta_get_ap_rate_mask = wl12xx_sta_get_ap_rate_mask,
1602 .get_pg_ver = wl12xx_get_pg_ver,
1603 .get_mac = wl12xx_get_mac,
1604 .set_tx_desc_csum = wl12xx_set_tx_desc_csum,
1605 .set_rx_csum = NULL,
1606 .ap_get_mimo_wide_rate_mask = NULL,
1607 .debugfs_init = wl12xx_debugfs_add_files,
1608 .get_spare_blocks = wl12xx_get_spare_blocks,
1609 .set_key = wl12xx_set_key,
1610 .pre_pkt_send = NULL,
1613 static struct ieee80211_sta_ht_cap wl12xx_ht_cap = {
1614 .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
1615 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT),
1616 .ht_supported = true,
1617 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
1618 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_8,
1620 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1621 .rx_highest = cpu_to_le16(72),
1622 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1626 static int __devinit wl12xx_probe(struct platform_device *pdev)
1628 struct wl12xx_platform_data *pdata = pdev->dev.platform_data;
1630 struct ieee80211_hw *hw;
1631 struct wl12xx_priv *priv;
1633 hw = wlcore_alloc_hw(sizeof(*priv));
1635 wl1271_error("can't allocate hw");
1641 wl->ops = &wl12xx_ops;
1642 wl->ptable = wl12xx_ptable;
1643 wl->rtable = wl12xx_rtable;
1644 wl->num_tx_desc = 16;
1645 wl->num_rx_desc = 8;
1646 wl->band_rate_to_idx = wl12xx_band_rate_to_idx;
1647 wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX;
1648 wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
1649 wl->fw_status_priv_len = 0;
1650 wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics);
1651 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, &wl12xx_ht_cap);
1652 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ, &wl12xx_ht_cap);
1653 wl12xx_conf_init(wl);
1656 priv->ref_clock = pdata->board_ref_clock;
1658 if (!strcmp(fref_param, "19.2"))
1659 priv->ref_clock = WL12XX_REFCLOCK_19;
1660 else if (!strcmp(fref_param, "26"))
1661 priv->ref_clock = WL12XX_REFCLOCK_26;
1662 else if (!strcmp(fref_param, "26x"))
1663 priv->ref_clock = WL12XX_REFCLOCK_26_XTAL;
1664 else if (!strcmp(fref_param, "38.4"))
1665 priv->ref_clock = WL12XX_REFCLOCK_38;
1666 else if (!strcmp(fref_param, "38.4x"))
1667 priv->ref_clock = WL12XX_REFCLOCK_38_XTAL;
1668 else if (!strcmp(fref_param, "52"))
1669 priv->ref_clock = WL12XX_REFCLOCK_52;
1671 wl1271_error("Invalid fref parameter %s", fref_param);
1675 priv->tcxo_clock = pdata->board_tcxo_clock;
1677 if (!strcmp(tcxo_param, "19.2"))
1678 priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
1679 else if (!strcmp(tcxo_param, "26"))
1680 priv->tcxo_clock = WL12XX_TCXOCLOCK_26;
1681 else if (!strcmp(tcxo_param, "38.4"))
1682 priv->tcxo_clock = WL12XX_TCXOCLOCK_38_4;
1683 else if (!strcmp(tcxo_param, "52"))
1684 priv->tcxo_clock = WL12XX_TCXOCLOCK_52;
1685 else if (!strcmp(tcxo_param, "16.368"))
1686 priv->tcxo_clock = WL12XX_TCXOCLOCK_16_368;
1687 else if (!strcmp(tcxo_param, "32.736"))
1688 priv->tcxo_clock = WL12XX_TCXOCLOCK_32_736;
1689 else if (!strcmp(tcxo_param, "16.8"))
1690 priv->tcxo_clock = WL12XX_TCXOCLOCK_16_8;
1691 else if (!strcmp(tcxo_param, "33.6"))
1692 priv->tcxo_clock = WL12XX_TCXOCLOCK_33_6;
1694 wl1271_error("Invalid tcxo parameter %s", tcxo_param);
1697 return wlcore_probe(wl, pdev);
1700 static const struct platform_device_id wl12xx_id_table[] __devinitconst = {
1702 { } /* Terminating Entry */
1704 MODULE_DEVICE_TABLE(platform, wl12xx_id_table);
1706 static struct platform_driver wl12xx_driver = {
1707 .probe = wl12xx_probe,
1708 .remove = __devexit_p(wlcore_remove),
1709 .id_table = wl12xx_id_table,
1711 .name = "wl12xx_driver",
1712 .owner = THIS_MODULE,
1716 module_platform_driver(wl12xx_driver);
1718 module_param_named(fref, fref_param, charp, 0);
1719 MODULE_PARM_DESC(fref, "FREF clock: 19.2, 26, 26x, 38.4, 38.4x, 52");
1721 module_param_named(tcxo, tcxo_param, charp, 0);
1722 MODULE_PARM_DESC(tcxo,
1723 "TCXO clock: 19.2, 26, 38.4, 52, 16.368, 32.736, 16.8, 33.6");
1725 MODULE_LICENSE("GPL v2");
1726 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1727 MODULE_FIRMWARE(WL127X_FW_NAME_SINGLE);
1728 MODULE_FIRMWARE(WL127X_FW_NAME_MULTI);
1729 MODULE_FIRMWARE(WL127X_PLT_FW_NAME);
1730 MODULE_FIRMWARE(WL128X_FW_NAME_SINGLE);
1731 MODULE_FIRMWARE(WL128X_FW_NAME_MULTI);
1732 MODULE_FIRMWARE(WL128X_PLT_FW_NAME);