drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 225                         const u8 command, const u8 token,
 226                         const u8 arg0, const u8 arg1)
 227 {
 228         u32 reg;
 229
 230         /*
 231          * SOC devices don't support MCU requests.
 232          */
 233         if (rt2x00_is_soc(rt2x00dev))
 234                 return;
 235
 236         mutex_lock(&rt2x00dev->csr_mutex);
 237
 238         /*
 239          * Wait until the MCU becomes available, afterwards we
 240          * can safely write the new data into the register.
 241          */
 242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 248
 249                 reg = 0;
 250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 252         }
 253
 254         mutex_unlock(&rt2x00dev->csr_mutex);
 255 }
 256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 257
 258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 259 {
 260         unsigned int i = 0;
 261         u32 reg;
 262
 263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 265                 if (reg && reg != ~0)
 266                         return 0;
 267                 msleep(1);
 268         }
 269
 270         ERROR(rt2x00dev, "Unstable hardware.\n");
 271         return -EBUSY;
 272 }
 273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 274
 275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 276 {
 277         unsigned int i;
 278         u32 reg;
 279
 280         /*
 281          * Some devices are really slow to respond here. Wait a whole second
 282          * before timing out.
 283          */
 284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 288                         return 0;
 289
 290                 msleep(10);
 291         }
 292
 293         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 294         return -EACCES;
 295 }
 296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 297
 298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 299 {
 300         u16 fw_crc;
 301         u16 crc;
 302
 303         /*
 304          * The last 2 bytes in the firmware array are the crc checksum itself,
 305          * this means that we should never pass those 2 bytes to the crc
 306          * algorithm.
 307          */
 308         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 309
 310         /*
 311          * Use the crc ccitt algorithm.
 312          * This will return the same value as the legacy driver which
 313          * used bit ordering reversion on the both the firmware bytes
 314          * before input input as well as on the final output.
 315          * Obviously using crc ccitt directly is much more efficient.
 316          */
 317         crc = crc_ccitt(~0, data, len - 2);
 318
 319         /*
 320          * There is a small difference between the crc-itu-t + bitrev and
 321          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 322          * will be swapped, use swab16 to convert the crc to the correct
 323          * value.
 324          */
 325         crc = swab16(crc);
 326
 327         return fw_crc == crc;
 328 }
 329
 330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 331                           const u8 *data, const size_t len)
 332 {
 333         size_t offset = 0;
 334         size_t fw_len;
 335         bool multiple;
 336
 337         /*
 338          * PCI(e) & SOC devices require firmware with a length
 339          * of 8kb. USB devices require firmware files with a length
 340          * of 4kb. Certain USB chipsets however require different firmware,
 341          * which Ralink only provides attached to the original firmware
 342          * file. Thus for USB devices, firmware files have a length
 343          * which is a multiple of 4kb.
 344          */
 345         if (rt2x00_is_usb(rt2x00dev)) {
 346                 fw_len = 4096;
 347                 multiple = true;
 348         } else {
 349                 fw_len = 8192;
 350                 multiple = true;
 351         }
 352
 353         /*
 354          * Validate the firmware length
 355          */
 356         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 357                 return FW_BAD_LENGTH;
 358
 359         /*
 360          * Check if the chipset requires one of the upper parts
 361          * of the firmware.
 362          */
 363         if (rt2x00_is_usb(rt2x00dev) &&
 364             !rt2x00_rt(rt2x00dev, RT2860) &&
 365             !rt2x00_rt(rt2x00dev, RT2872) &&
 366             !rt2x00_rt(rt2x00dev, RT3070) &&
 367             ((len / fw_len) == 1))
 368                 return FW_BAD_VERSION;
 369
 370         /*
 371          * 8kb firmware files must be checked as if it were
 372          * 2 separate firmware files.
 373          */
 374         while (offset < len) {
 375                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 376                         return FW_BAD_CRC;
 377
 378                 offset += fw_len;
 379         }
 380
 381         return FW_OK;
 382 }
 383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 384
 385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 386                          const u8 *data, const size_t len)
 387 {
 388         unsigned int i;
 389         u32 reg;
 390
 391         /*
 392          * If driver doesn't wake up firmware here,
 393          * rt2800_load_firmware will hang forever when interface is up again.
 394          */
 395         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 396
 397         /*
 398          * Wait for stable hardware.
 399          */
 400         if (rt2800_wait_csr_ready(rt2x00dev))
 401                 return -EBUSY;
 402
 403         if (rt2x00_is_pci(rt2x00dev)) {
 404                 if (rt2x00_rt(rt2x00dev, RT3572) ||
 405                     rt2x00_rt(rt2x00dev, RT5390)) {
 406                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 407                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 408                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 409                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 410                 }
 411                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 412         }
 413
 414         /*
 415          * Disable DMA, will be reenabled later when enabling
 416          * the radio.
 417          */
 418         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 419         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 420         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 421         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 422         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 423         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 424         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 425
 426         /*
 427          * Write firmware to the device.
 428          */
 429         rt2800_drv_write_firmware(rt2x00dev, data, len);
 430
 431         /*
 432          * Wait for device to stabilize.
 433          */
 434         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 435                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 436                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 437                         break;
 438                 msleep(1);
 439         }
 440
 441         if (i == REGISTER_BUSY_COUNT) {
 442                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 443                 return -EBUSY;
 444         }
 445
 446         /*
 447          * Initialize firmware.
 448          */
 449         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 450         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 451         msleep(1);
 452
 453         return 0;
 454 }
 455 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 456
 457 void rt2800_write_tx_data(struct queue_entry *entry,
 458                           struct txentry_desc *txdesc)
 459 {
 460         __le32 *txwi = rt2800_drv_get_txwi(entry);
 461         u32 word;
 462
 463         /*
 464          * Initialize TX Info descriptor
 465          */
 466         rt2x00_desc_read(txwi, 0, &word);
 467         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 468                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 469         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 470                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 471         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 472         rt2x00_set_field32(&word, TXWI_W0_TS,
 473                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 474         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 475                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 476         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 477                            txdesc->u.ht.mpdu_density);
 478         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 479         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 480         rt2x00_set_field32(&word, TXWI_W0_BW,
 481                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 482         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 483                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 484         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 485         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 486         rt2x00_desc_write(txwi, 0, word);
 487
 488         rt2x00_desc_read(txwi, 1, &word);
 489         rt2x00_set_field32(&word, TXWI_W1_ACK,
 490                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 491         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 492                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 493         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 494         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 495                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 496                            txdesc->key_idx : txdesc->u.ht.wcid);
 497         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 498                            txdesc->length);
 499         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 500         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 501         rt2x00_desc_write(txwi, 1, word);
 502
 503         /*
 504          * Always write 0 to IV/EIV fields, hardware will insert the IV
 505          * from the IVEIV register when TXD_W3_WIV is set to 0.
 506          * When TXD_W3_WIV is set to 1 it will use the IV data
 507          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 508          * crypto entry in the registers should be used to encrypt the frame.
 509          */
 510         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 511         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 512 }
 513 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 514
 515 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 516 {
 517         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 518         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 519         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 520         u16 eeprom;
 521         u8 offset0;
 522         u8 offset1;
 523         u8 offset2;
 524
 525         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 526                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 527                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 528                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 529                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 530                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 531         } else {
 532                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 533                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 534                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 535                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 536                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 537         }
 538
 539         /*
 540          * Convert the value from the descriptor into the RSSI value
 541          * If the value in the descriptor is 0, it is considered invalid
 542          * and the default (extremely low) rssi value is assumed
 543          */
 544         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 545         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 546         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 547
 548         /*
 549          * mac80211 only accepts a single RSSI value. Calculating the
 550          * average doesn't deliver a fair answer either since -60:-60 would
 551          * be considered equally good as -50:-70 while the second is the one
 552          * which gives less energy...
 553          */
 554         rssi0 = max(rssi0, rssi1);
 555         return max(rssi0, rssi2);
 556 }
 557
 558 void rt2800_process_rxwi(struct queue_entry *entry,
 559                          struct rxdone_entry_desc *rxdesc)
 560 {
 561         __le32 *rxwi = (__le32 *) entry->skb->data;
 562         u32 word;
 563
 564         rt2x00_desc_read(rxwi, 0, &word);
 565
 566         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 567         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 568
 569         rt2x00_desc_read(rxwi, 1, &word);
 570
 571         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 572                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 573
 574         if (rt2x00_get_field32(word, RXWI_W1_BW))
 575                 rxdesc->flags |= RX_FLAG_40MHZ;
 576
 577         /*
 578          * Detect RX rate, always use MCS as signal type.
 579          */
 580         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 581         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 582         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 583
 584         /*
 585          * Mask of 0x8 bit to remove the short preamble flag.
 586          */
 587         if (rxdesc->rate_mode == RATE_MODE_CCK)
 588                 rxdesc->signal &= ~0x8;
 589
 590         rt2x00_desc_read(rxwi, 2, &word);
 591
 592         /*
 593          * Convert descriptor AGC value to RSSI value.
 594          */
 595         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 596
 597         /*
 598          * Remove RXWI descriptor from start of buffer.
 599          */
 600         skb_pull(entry->skb, RXWI_DESC_SIZE);
 601 }
 602 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 603
 604 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 605 {
 606         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 607         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 608         struct txdone_entry_desc txdesc;
 609         u32 word;
 610         u16 mcs, real_mcs;
 611         int aggr, ampdu;
 612
 613         /*
 614          * Obtain the status about this packet.
 615          */
 616         txdesc.flags = 0;
 617         rt2x00_desc_read(txwi, 0, &word);
 618
 619         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 620         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 621
 622         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 623         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 624
 625         /*
 626          * If a frame was meant to be sent as a single non-aggregated MPDU
 627          * but ended up in an aggregate the used tx rate doesn't correlate
 628          * with the one specified in the TXWI as the whole aggregate is sent
 629          * with the same rate.
 630          *
 631          * For example: two frames are sent to rt2x00, the first one sets
 632          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 633          * and requests MCS15. If the hw aggregates both frames into one
 634          * AMDPU the tx status for both frames will contain MCS7 although
 635          * the frame was sent successfully.
 636          *
 637          * Hence, replace the requested rate with the real tx rate to not
 638          * confuse the rate control algortihm by providing clearly wrong
 639          * data.
 640          */
 641         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 642                 skbdesc->tx_rate_idx = real_mcs;
 643                 mcs = real_mcs;
 644         }
 645
 646         if (aggr == 1 || ampdu == 1)
 647                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 648
 649         /*
 650          * Ralink has a retry mechanism using a global fallback
 651          * table. We setup this fallback table to try the immediate
 652          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 653          * always contains the MCS used for the last transmission, be
 654          * it successful or not.
 655          */
 656         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 657                 /*
 658                  * Transmission succeeded. The number of retries is
 659                  * mcs - real_mcs
 660                  */
 661                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 662                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 663         } else {
 664                 /*
 665                  * Transmission failed. The number of retries is
 666                  * always 7 in this case (for a total number of 8
 667                  * frames sent).
 668                  */
 669                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 670                 txdesc.retry = rt2x00dev->long_retry;
 671         }
 672
 673         /*
 674          * the frame was retried at least once
 675          * -> hw used fallback rates
 676          */
 677         if (txdesc.retry)
 678                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 679
 680         rt2x00lib_txdone(entry, &txdesc);
 681 }
 682 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 683
 684 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 685 {
 686         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 687         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 688         unsigned int beacon_base;
 689         unsigned int padding_len;
 690         u32 orig_reg, reg;
 691
 692         /*
 693          * Disable beaconing while we are reloading the beacon data,
 694          * otherwise we might be sending out invalid data.
 695          */
 696         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 697         orig_reg = reg;
 698         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 699         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 700
 701         /*
 702          * Add space for the TXWI in front of the skb.
 703          */
 704         memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
 705
 706         /*
 707          * Register descriptor details in skb frame descriptor.
 708          */
 709         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 710         skbdesc->desc = entry->skb->data;
 711         skbdesc->desc_len = TXWI_DESC_SIZE;
 712
 713         /*
 714          * Add the TXWI for the beacon to the skb.
 715          */
 716         rt2800_write_tx_data(entry, txdesc);
 717
 718         /*
 719          * Dump beacon to userspace through debugfs.
 720          */
 721         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 722
 723         /*
 724          * Write entire beacon with TXWI and padding to register.
 725          */
 726         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 727         if (padding_len && skb_pad(entry->skb, padding_len)) {
 728                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
 729                 /* skb freed by skb_pad() on failure */
 730                 entry->skb = NULL;
 731                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 732                 return;
 733         }
 734
 735         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 736         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 737                                    entry->skb->len + padding_len);
 738
 739         /*
 740          * Enable beaconing again.
 741          */
 742         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 743         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 744
 745         /*
 746          * Clean up beacon skb.
 747          */
 748         dev_kfree_skb_any(entry->skb);
 749         entry->skb = NULL;
 750 }
 751 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 752
 753 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 754                                                 unsigned int beacon_base)
 755 {
 756         int i;
 757
 758         /*
 759          * For the Beacon base registers we only need to clear
 760          * the whole TXWI which (when set to 0) will invalidate
 761          * the entire beacon.
 762          */
 763         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 764                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 765 }
 766
 767 void rt2800_clear_beacon(struct queue_entry *entry)
 768 {
 769         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 770         u32 reg;
 771
 772         /*
 773          * Disable beaconing while we are reloading the beacon data,
 774          * otherwise we might be sending out invalid data.
 775          */
 776         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 777         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 778         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 779
 780         /*
 781          * Clear beacon.
 782          */
 783         rt2800_clear_beacon_register(rt2x00dev,
 784                                      HW_BEACON_OFFSET(entry->entry_idx));
 785
 786         /*
 787          * Enabled beaconing again.
 788          */
 789         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 790         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 791 }
 792 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 793
 794 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 795 const struct rt2x00debug rt2800_rt2x00debug = {
 796         .owner  = THIS_MODULE,
 797         .csr    = {
 798                 .read           = rt2800_register_read,
 799                 .write          = rt2800_register_write,
 800                 .flags          = RT2X00DEBUGFS_OFFSET,
 801                 .word_base      = CSR_REG_BASE,
 802                 .word_size      = sizeof(u32),
 803                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 804         },
 805         .eeprom = {
 806                 .read           = rt2x00_eeprom_read,
 807                 .write          = rt2x00_eeprom_write,
 808                 .word_base      = EEPROM_BASE,
 809                 .word_size      = sizeof(u16),
 810                 .word_count     = EEPROM_SIZE / sizeof(u16),
 811         },
 812         .bbp    = {
 813                 .read           = rt2800_bbp_read,
 814                 .write          = rt2800_bbp_write,
 815                 .word_base      = BBP_BASE,
 816                 .word_size      = sizeof(u8),
 817                 .word_count     = BBP_SIZE / sizeof(u8),
 818         },
 819         .rf     = {
 820                 .read           = rt2x00_rf_read,
 821                 .write          = rt2800_rf_write,
 822                 .word_base      = RF_BASE,
 823                 .word_size      = sizeof(u32),
 824                 .word_count     = RF_SIZE / sizeof(u32),
 825         },
 826 };
 827 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 828 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 829
 830 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 831 {
 832         u32 reg;
 833
 834         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 835         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 836 }
 837 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 838
 839 #ifdef CONFIG_RT2X00_LIB_LEDS
 840 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 841                                   enum led_brightness brightness)
 842 {
 843         struct rt2x00_led *led =
 844             container_of(led_cdev, struct rt2x00_led, led_dev);
 845         unsigned int enabled = brightness != LED_OFF;
 846         unsigned int bg_mode =
 847             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 848         unsigned int polarity =
 849                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 850                                    EEPROM_FREQ_LED_POLARITY);
 851         unsigned int ledmode =
 852                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 853                                    EEPROM_FREQ_LED_MODE);
 854         u32 reg;
 855
 856         /* Check for SoC (SOC devices don't support MCU requests) */
 857         if (rt2x00_is_soc(led->rt2x00dev)) {
 858                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 859
 860                 /* Set LED Polarity */
 861                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
 862
 863                 /* Set LED Mode */
 864                 if (led->type == LED_TYPE_RADIO) {
 865                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
 866                                            enabled ? 3 : 0);
 867                 } else if (led->type == LED_TYPE_ASSOC) {
 868                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
 869                                            enabled ? 3 : 0);
 870                 } else if (led->type == LED_TYPE_QUALITY) {
 871                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
 872                                            enabled ? 3 : 0);
 873                 }
 874
 875                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 876
 877         } else {
 878                 if (led->type == LED_TYPE_RADIO) {
 879                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 880                                               enabled ? 0x20 : 0);
 881                 } else if (led->type == LED_TYPE_ASSOC) {
 882                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 883                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 884                 } else if (led->type == LED_TYPE_QUALITY) {
 885                         /*
 886                          * The brightness is divided into 6 levels (0 - 5),
 887                          * The specs tell us the following levels:
 888                          *      0, 1 ,3, 7, 15, 31
 889                          * to determine the level in a simple way we can simply
 890                          * work with bitshifting:
 891                          *      (1 << level) - 1
 892                          */
 893                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 894                                               (1 << brightness / (LED_FULL / 6)) - 1,
 895                                               polarity);
 896                 }
 897         }
 898 }
 899
 900 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 901                      struct rt2x00_led *led, enum led_type type)
 902 {
 903         led->rt2x00dev = rt2x00dev;
 904         led->type = type;
 905         led->led_dev.brightness_set = rt2800_brightness_set;
 906         led->flags = LED_INITIALIZED;
 907 }
 908 #endif /* CONFIG_RT2X00_LIB_LEDS */
 909
 910 /*
 911  * Configuration handlers.
 912  */
 913 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
 914                                const u8 *address,
 915                                int wcid)
 916 {
 917         struct mac_wcid_entry wcid_entry;
 918         u32 offset;
 919
 920         offset = MAC_WCID_ENTRY(wcid);
 921
 922         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
 923         if (address)
 924                 memcpy(wcid_entry.mac, address, ETH_ALEN);
 925
 926         rt2800_register_multiwrite(rt2x00dev, offset,
 927                                       &wcid_entry, sizeof(wcid_entry));
 928 }
 929
 930 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
 931 {
 932         u32 offset;
 933         offset = MAC_WCID_ATTR_ENTRY(wcid);
 934         rt2800_register_write(rt2x00dev, offset, 0);
 935 }
 936
 937 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
 938                                            int wcid, u32 bssidx)
 939 {
 940         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
 941         u32 reg;
 942
 943         /*
 944          * The BSS Idx numbers is split in a main value of 3 bits,
 945          * and a extended field for adding one additional bit to the value.
 946          */
 947         rt2800_register_read(rt2x00dev, offset, &reg);
 948         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
 949         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
 950                            (bssidx & 0x8) >> 3);
 951         rt2800_register_write(rt2x00dev, offset, reg);
 952 }
 953
 954 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
 955                                            struct rt2x00lib_crypto *crypto,
 956                                            struct ieee80211_key_conf *key)
 957 {
 958         struct mac_iveiv_entry iveiv_entry;
 959         u32 offset;
 960         u32 reg;
 961
 962         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 963
 964         if (crypto->cmd == SET_KEY) {
 965                 rt2800_register_read(rt2x00dev, offset, &reg);
 966                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 967                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 968                 /*
 969                  * Both the cipher as the BSS Idx numbers are split in a main
 970                  * value of 3 bits, and a extended field for adding one additional
 971                  * bit to the value.
 972                  */
 973                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 974                                    (crypto->cipher & 0x7));
 975                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
 976                                    (crypto->cipher & 0x8) >> 3);
 977                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 978                 rt2800_register_write(rt2x00dev, offset, reg);
 979         } else {
 980                 /* Delete the cipher without touching the bssidx */
 981                 rt2800_register_read(rt2x00dev, offset, &reg);
 982                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
 983                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
 984                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
 985                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
 986                 rt2800_register_write(rt2x00dev, offset, reg);
 987         }
 988
 989         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 990
 991         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 992         if ((crypto->cipher == CIPHER_TKIP) ||
 993             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 994             (crypto->cipher == CIPHER_AES))
 995                 iveiv_entry.iv[3] |= 0x20;
 996         iveiv_entry.iv[3] |= key->keyidx << 6;
 997         rt2800_register_multiwrite(rt2x00dev, offset,
 998                                       &iveiv_entry, sizeof(iveiv_entry));
 999 }
1000
1001 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1002                              struct rt2x00lib_crypto *crypto,
1003                              struct ieee80211_key_conf *key)
1004 {
1005         struct hw_key_entry key_entry;
1006         struct rt2x00_field32 field;
1007         u32 offset;
1008         u32 reg;
1009
1010         if (crypto->cmd == SET_KEY) {
1011                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1012
1013                 memcpy(key_entry.key, crypto->key,
1014                        sizeof(key_entry.key));
1015                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1016                        sizeof(key_entry.tx_mic));
1017                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1018                        sizeof(key_entry.rx_mic));
1019
1020                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1021                 rt2800_register_multiwrite(rt2x00dev, offset,
1022                                               &key_entry, sizeof(key_entry));
1023         }
1024
1025         /*
1026          * The cipher types are stored over multiple registers
1027          * starting with SHARED_KEY_MODE_BASE each word will have
1028          * 32 bits and contains the cipher types for 2 bssidx each.
1029          * Using the correct defines correctly will cause overhead,
1030          * so just calculate the correct offset.
1031          */
1032         field.bit_offset = 4 * (key->hw_key_idx % 8);
1033         field.bit_mask = 0x7 << field.bit_offset;
1034
1035         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1036
1037         rt2800_register_read(rt2x00dev, offset, &reg);
1038         rt2x00_set_field32(&reg, field,
1039                            (crypto->cmd == SET_KEY) * crypto->cipher);
1040         rt2800_register_write(rt2x00dev, offset, reg);
1041
1042         /*
1043          * Update WCID information
1044          */
1045         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1046         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1047                                        crypto->bssidx);
1048         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1049
1050         return 0;
1051 }
1052 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1053
1054 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1055 {
1056         struct mac_wcid_entry wcid_entry;
1057         int idx;
1058         u32 offset;
1059
1060         /*
1061          * Search for the first free WCID entry and return the corresponding
1062          * index.
1063          *
1064          * Make sure the WCID starts _after_ the last possible shared key
1065          * entry (>32).
1066          *
1067          * Since parts of the pairwise key table might be shared with
1068          * the beacon frame buffers 6 & 7 we should only write into the
1069          * first 222 entries.
1070          */
1071         for (idx = 33; idx <= 222; idx++) {
1072                 offset = MAC_WCID_ENTRY(idx);
1073                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1074                                           sizeof(wcid_entry));
1075                 if (is_broadcast_ether_addr(wcid_entry.mac))
1076                         return idx;
1077         }
1078
1079         /*
1080          * Use -1 to indicate that we don't have any more space in the WCID
1081          * table.
1082          */
1083         return -1;
1084 }
1085
1086 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1087                                struct rt2x00lib_crypto *crypto,
1088                                struct ieee80211_key_conf *key)
1089 {
1090         struct hw_key_entry key_entry;
1091         u32 offset;
1092
1093         if (crypto->cmd == SET_KEY) {
1094                 /*
1095                  * Allow key configuration only for STAs that are
1096                  * known by the hw.
1097                  */
1098                 if (crypto->wcid < 0)
1099                         return -ENOSPC;
1100                 key->hw_key_idx = crypto->wcid;
1101
1102                 memcpy(key_entry.key, crypto->key,
1103                        sizeof(key_entry.key));
1104                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1105                        sizeof(key_entry.tx_mic));
1106                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1107                        sizeof(key_entry.rx_mic));
1108
1109                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1110                 rt2800_register_multiwrite(rt2x00dev, offset,
1111                                               &key_entry, sizeof(key_entry));
1112         }
1113
1114         /*
1115          * Update WCID information
1116          */
1117         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1118
1119         return 0;
1120 }
1121 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1122
1123 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1124                    struct ieee80211_sta *sta)
1125 {
1126         int wcid;
1127         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1128
1129         /*
1130          * Find next free WCID.
1131          */
1132         wcid = rt2800_find_wcid(rt2x00dev);
1133
1134         /*
1135          * Store selected wcid even if it is invalid so that we can
1136          * later decide if the STA is uploaded into the hw.
1137          */
1138         sta_priv->wcid = wcid;
1139
1140         /*
1141          * No space left in the device, however, we can still communicate
1142          * with the STA -> No error.
1143          */
1144         if (wcid < 0)
1145                 return 0;
1146
1147         /*
1148          * Clean up WCID attributes and write STA address to the device.
1149          */
1150         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1151         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1152         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1153                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1154         return 0;
1155 }
1156 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1157
1158 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1159 {
1160         /*
1161          * Remove WCID entry, no need to clean the attributes as they will
1162          * get renewed when the WCID is reused.
1163          */
1164         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1165
1166         return 0;
1167 }
1168 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1169
1170 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1171                           const unsigned int filter_flags)
1172 {
1173         u32 reg;
1174
1175         /*
1176          * Start configuration steps.
1177          * Note that the version error will always be dropped
1178          * and broadcast frames will always be accepted since
1179          * there is no filter for it at this time.
1180          */
1181         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1182         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1183                            !(filter_flags & FIF_FCSFAIL));
1184         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1185                            !(filter_flags & FIF_PLCPFAIL));
1186         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1187                            !(filter_flags & FIF_PROMISC_IN_BSS));
1188         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1189         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1190         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1191                            !(filter_flags & FIF_ALLMULTI));
1192         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1193         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1194         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1195                            !(filter_flags & FIF_CONTROL));
1196         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1197                            !(filter_flags & FIF_CONTROL));
1198         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1199                            !(filter_flags & FIF_CONTROL));
1200         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1201                            !(filter_flags & FIF_CONTROL));
1202         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1203                            !(filter_flags & FIF_CONTROL));
1204         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1205                            !(filter_flags & FIF_PSPOLL));
1206         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,
1207                            !(filter_flags & FIF_CONTROL));
1208         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1209                            !(filter_flags & FIF_CONTROL));
1210         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1211                            !(filter_flags & FIF_CONTROL));
1212         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1213 }
1214 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1215
1216 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1217                         struct rt2x00intf_conf *conf, const unsigned int flags)
1218 {
1219         u32 reg;
1220         bool update_bssid = false;
1221
1222         if (flags & CONFIG_UPDATE_TYPE) {
1223                 /*
1224                  * Enable synchronisation.
1225                  */
1226                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1227                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1228                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1229
1230                 if (conf->sync == TSF_SYNC_AP_NONE) {
1231                         /*
1232                          * Tune beacon queue transmit parameters for AP mode
1233                          */
1234                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1235                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1236                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1237                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1238                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1239                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1240                 } else {
1241                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1242                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1243                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1244                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1245                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1246                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1247                 }
1248         }
1249
1250         if (flags & CONFIG_UPDATE_MAC) {
1251                 if (flags & CONFIG_UPDATE_TYPE &&
1252                     conf->sync == TSF_SYNC_AP_NONE) {
1253                         /*
1254                          * The BSSID register has to be set to our own mac
1255                          * address in AP mode.
1256                          */
1257                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1258                         update_bssid = true;
1259                 }
1260
1261                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1262                         reg = le32_to_cpu(conf->mac[1]);
1263                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1264                         conf->mac[1] = cpu_to_le32(reg);
1265                 }
1266
1267                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1268                                               conf->mac, sizeof(conf->mac));
1269         }
1270
1271         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1272                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1273                         reg = le32_to_cpu(conf->bssid[1]);
1274                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1275                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1276                         conf->bssid[1] = cpu_to_le32(reg);
1277                 }
1278
1279                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1280                                               conf->bssid, sizeof(conf->bssid));
1281         }
1282 }
1283 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1284
1285 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1286                                     struct rt2x00lib_erp *erp)
1287 {
1288         bool any_sta_nongf = !!(erp->ht_opmode &
1289                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1290         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1291         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1292         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1293         u32 reg;
1294
1295         /* default protection rate for HT20: OFDM 24M */
1296         mm20_rate = gf20_rate = 0x4004;
1297
1298         /* default protection rate for HT40: duplicate OFDM 24M */
1299         mm40_rate = gf40_rate = 0x4084;
1300
1301         switch (protection) {
1302         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1303                 /*
1304                  * All STAs in this BSS are HT20/40 but there might be
1305                  * STAs not supporting greenfield mode.
1306                  * => Disable protection for HT transmissions.
1307                  */
1308                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1309
1310                 break;
1311         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1312                 /*
1313                  * All STAs in this BSS are HT20 or HT20/40 but there
1314                  * might be STAs not supporting greenfield mode.
1315                  * => Protect all HT40 transmissions.
1316                  */
1317                 mm20_mode = gf20_mode = 0;
1318                 mm40_mode = gf40_mode = 2;
1319
1320                 break;
1321         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1322                 /*
1323                  * Nonmember protection:
1324                  * According to 802.11n we _should_ protect all
1325                  * HT transmissions (but we don't have to).
1326                  *
1327                  * But if cts_protection is enabled we _shall_ protect
1328                  * all HT transmissions using a CCK rate.
1329                  *
1330                  * And if any station is non GF we _shall_ protect
1331                  * GF transmissions.
1332                  *
1333                  * We decide to protect everything
1334                  * -> fall through to mixed mode.
1335                  */
1336         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1337                 /*
1338                  * Legacy STAs are present
1339                  * => Protect all HT transmissions.
1340                  */
1341                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1342
1343                 /*
1344                  * If erp protection is needed we have to protect HT
1345                  * transmissions with CCK 11M long preamble.
1346                  */
1347                 if (erp->cts_protection) {
1348                         /* don't duplicate RTS/CTS in CCK mode */
1349                         mm20_rate = mm40_rate = 0x0003;
1350                         gf20_rate = gf40_rate = 0x0003;
1351                 }
1352                 break;
1353         }
1354
1355         /* check for STAs not supporting greenfield mode */
1356         if (any_sta_nongf)
1357                 gf20_mode = gf40_mode = 2;
1358
1359         /* Update HT protection config */
1360         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1361         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1362         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1363         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1364
1365         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1366         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1367         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1368         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1369
1370         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1371         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1372         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1373         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1374
1375         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1376         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1377         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1378         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1379 }
1380
1381 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1382                        u32 changed)
1383 {
1384         u32 reg;
1385
1386         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1387                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1388                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1389                                    !!erp->short_preamble);
1390                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1391                                    !!erp->short_preamble);
1392                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1393         }
1394
1395         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1396                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1397                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1398                                    erp->cts_protection ? 2 : 0);
1399                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1400         }
1401
1402         if (changed & BSS_CHANGED_BASIC_RATES) {
1403                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1404                                          erp->basic_rates);
1405                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1406         }
1407
1408         if (changed & BSS_CHANGED_ERP_SLOT) {
1409                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1410                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1411                                    erp->slot_time);
1412                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1413
1414                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1415                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1416                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1417         }
1418
1419         if (changed & BSS_CHANGED_BEACON_INT) {
1420                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1421                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1422                                    erp->beacon_int * 16);
1423                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1424         }
1425
1426         if (changed & BSS_CHANGED_HT)
1427                 rt2800_config_ht_opmode(rt2x00dev, erp);
1428 }
1429 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1430
1431 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1432 {
1433         u32 reg;
1434         u16 eeprom;
1435         u8 led_ctrl, led_g_mode, led_r_mode;
1436
1437         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1438         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1439                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1440                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1441         } else {
1442                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1443                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1444         }
1445         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1446
1447         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1448         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1449         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1450         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1451             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1452                 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1453                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1454                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1455                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1456                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1457                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1458                 } else {
1459                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1460                                            (led_g_mode << 2) | led_r_mode, 1);
1461                 }
1462         }
1463 }
1464
1465 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1466                                      enum antenna ant)
1467 {
1468         u32 reg;
1469         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1470         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1471
1472         if (rt2x00_is_pci(rt2x00dev)) {
1473                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1474                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1475                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1476         } else if (rt2x00_is_usb(rt2x00dev))
1477                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1478                                    eesk_pin, 0);
1479
1480         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1481         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1482         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1483         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1484 }
1485
1486 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1487 {
1488         u8 r1;
1489         u8 r3;
1490         u16 eeprom;
1491
1492         rt2800_bbp_read(rt2x00dev, 1, &r1);
1493         rt2800_bbp_read(rt2x00dev, 3, &r3);
1494
1495         if (rt2x00_rt(rt2x00dev, RT3572) &&
1496             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1497                 rt2800_config_3572bt_ant(rt2x00dev);
1498
1499         /*
1500          * Configure the TX antenna.
1501          */
1502         switch (ant->tx_chain_num) {
1503         case 1:
1504                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1505                 break;
1506         case 2:
1507                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1508                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1509                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1510                 else
1511                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1512                 break;
1513         case 3:
1514                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1515                 break;
1516         }
1517
1518         /*
1519          * Configure the RX antenna.
1520          */
1521         switch (ant->rx_chain_num) {
1522         case 1:
1523                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1524                     rt2x00_rt(rt2x00dev, RT3090) ||
1525                     rt2x00_rt(rt2x00dev, RT3390)) {
1526                         rt2x00_eeprom_read(rt2x00dev,
1527                                            EEPROM_NIC_CONF1, &eeprom);
1528                         if (rt2x00_get_field16(eeprom,
1529                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1530                                 rt2800_set_ant_diversity(rt2x00dev,
1531                                                 rt2x00dev->default_ant.rx);
1532                 }
1533                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1534                 break;
1535         case 2:
1536                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1537                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1538                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1539                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1540                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1541                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1542                 } else {
1543                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1544                 }
1545                 break;
1546         case 3:
1547                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1548                 break;
1549         }
1550
1551         rt2800_bbp_write(rt2x00dev, 3, r3);
1552         rt2800_bbp_write(rt2x00dev, 1, r1);
1553 }
1554 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1555
1556 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1557                                    struct rt2x00lib_conf *libconf)
1558 {
1559         u16 eeprom;
1560         short lna_gain;
1561
1562         if (libconf->rf.channel <= 14) {
1563                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1564                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1565         } else if (libconf->rf.channel <= 64) {
1566                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1567                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1568         } else if (libconf->rf.channel <= 128) {
1569                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1570                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1571         } else {
1572                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1573                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1574         }
1575
1576         rt2x00dev->lna_gain = lna_gain;
1577 }
1578
1579 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1580                                          struct ieee80211_conf *conf,
1581                                          struct rf_channel *rf,
1582                                          struct channel_info *info)
1583 {
1584         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1585
1586         if (rt2x00dev->default_ant.tx_chain_num == 1)
1587                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1588
1589         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1590                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1591                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1592         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1593                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1594
1595         if (rf->channel > 14) {
1596                 /*
1597                  * When TX power is below 0, we should increase it by 7 to
1598                  * make it a positive value (Minimum value is -7).
1599                  * However this means that values between 0 and 7 have
1600                  * double meaning, and we should set a 7DBm boost flag.
1601                  */
1602                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1603                                    (info->default_power1 >= 0));
1604
1605                 if (info->default_power1 < 0)
1606                         info->default_power1 += 7;
1607
1608                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1609
1610                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1611                                    (info->default_power2 >= 0));
1612
1613                 if (info->default_power2 < 0)
1614                         info->default_power2 += 7;
1615
1616                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1617         } else {
1618                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1619                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1620         }
1621
1622         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1623
1624         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1625         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1626         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1627         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1628
1629         udelay(200);
1630
1631         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1632         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1633         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1634         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1635
1636         udelay(200);
1637
1638         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1639         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1640         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1641         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1642 }
1643
1644 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1645                                          struct ieee80211_conf *conf,
1646                                          struct rf_channel *rf,
1647                                          struct channel_info *info)
1648 {
1649         u8 rfcsr;
1650
1651         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1652         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1653
1654         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1655         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1656         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1657
1658         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1659         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1660         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1661
1662         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1663         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1664         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1665
1666         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1667         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1668         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1669
1670         rt2800_rfcsr_write(rt2x00dev, 24,
1671                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1672
1673         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1674         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1675         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1676 }
1677
1678 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1679                                          struct ieee80211_conf *conf,
1680                                          struct rf_channel *rf,
1681                                          struct channel_info *info)
1682 {
1683         u8 rfcsr;
1684         u32 reg;
1685
1686         if (rf->channel <= 14) {
1687                 rt2800_bbp_write(rt2x00dev, 25, 0x15);
1688                 rt2800_bbp_write(rt2x00dev, 26, 0x85);
1689         } else {
1690                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1691                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1692         }
1693
1694         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1695         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1696
1697         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1698         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1699         if (rf->channel <= 14)
1700                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1701         else
1702                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1703         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1704
1705         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1706         if (rf->channel <= 14)
1707                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1708         else
1709                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1710         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1711
1712         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1713         if (rf->channel <= 14) {
1714                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1715                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1716                                 (info->default_power1 & 0x3) |
1717                                 ((info->default_power1 & 0xC) << 1));
1718         } else {
1719                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1720                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1721                                 (info->default_power1 & 0x3) |
1722                                 ((info->default_power1 & 0xC) << 1));
1723         }
1724         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1725
1726         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1727         if (rf->channel <= 14) {
1728                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1729                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1730                                 (info->default_power2 & 0x3) |
1731                                 ((info->default_power2 & 0xC) << 1));
1732         } else {
1733                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1734                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1735                                 (info->default_power2 & 0x3) |
1736                                 ((info->default_power2 & 0xC) << 1));
1737         }
1738         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1739
1740         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1741         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1742         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1743         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1744         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1745         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1746         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1747                 if (rf->channel <= 14) {
1748                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1749                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1750                 }
1751                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1752                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1753         } else {
1754                 switch (rt2x00dev->default_ant.tx_chain_num) {
1755                 case 1:
1756                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1757                 case 2:
1758                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1759                         break;
1760                 }
1761
1762                 switch (rt2x00dev->default_ant.rx_chain_num) {
1763                 case 1:
1764                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1765                 case 2:
1766                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1767                         break;
1768                 }
1769         }
1770         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1771
1772         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1773         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1774         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1775
1776         rt2800_rfcsr_write(rt2x00dev, 24,
1777                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1778         rt2800_rfcsr_write(rt2x00dev, 31,
1779                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1780
1781         if (rf->channel <= 14) {
1782                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1783                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1784                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1785                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1786                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1787                 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
1788                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1789                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1790                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1791                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1792                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1793                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1794                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1795         } else {
1796                 rt2800_rfcsr_write(rt2x00dev, 7, 0x14);
1797                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1798                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1799                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1800                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1801                 rt2800_rfcsr_write(rt2x00dev, 16, 0x7a);
1802                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1803                 if (rf->channel <= 64) {
1804                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1805                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1806                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1807                 } else if (rf->channel <= 128) {
1808                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1809                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1810                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1811                 } else {
1812                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1813                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1814                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1815                 }
1816                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1817                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1818                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1819         }
1820
1821         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1822         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1823         if (rf->channel <= 14)
1824                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1825         else
1826                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1827         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1828
1829         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1830         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1831         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1832 }
1833
1834 #define RT5390_POWER_BOUND     0x27
1835 #define RT5390_FREQ_OFFSET_BOUND       0x5f
1836
1837 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1838                                          struct ieee80211_conf *conf,
1839                                          struct rf_channel *rf,
1840                                          struct channel_info *info)
1841 {
1842         u8 rfcsr;
1843
1844         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1845         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1846         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1847         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1848         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1849
1850         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1851         if (info->default_power1 > RT5390_POWER_BOUND)
1852                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1853         else
1854                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1855         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1856
1857         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1858         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1859         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1860         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1861         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1862         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1863
1864         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1865         if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1866                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1867                                   RT5390_FREQ_OFFSET_BOUND);
1868         else
1869                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1870         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1871
1872         if (rf->channel <= 14) {
1873                 int idx = rf->channel-1;
1874
1875                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1876                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1877                                 /* r55/r59 value array of channel 1~14 */
1878                                 static const char r55_bt_rev[] = {0x83, 0x83,
1879                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1880                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1881                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
1882                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1883                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1884
1885                                 rt2800_rfcsr_write(rt2x00dev, 55,
1886                                                    r55_bt_rev[idx]);
1887                                 rt2800_rfcsr_write(rt2x00dev, 59,
1888                                                    r59_bt_rev[idx]);
1889                         } else {
1890                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1891                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1892                                         0x88, 0x88, 0x86, 0x85, 0x84};
1893
1894                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1895                         }
1896                 } else {
1897                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1898                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
1899                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1900                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1901                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
1902                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1903                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1904
1905                                 rt2800_rfcsr_write(rt2x00dev, 55,
1906                                                    r55_nonbt_rev[idx]);
1907                                 rt2800_rfcsr_write(rt2x00dev, 59,
1908                                                    r59_nonbt_rev[idx]);
1909                         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1910                                 static const char r59_non_bt[] = {0x8f, 0x8f,
1911                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1912                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1913
1914                                 rt2800_rfcsr_write(rt2x00dev, 59,
1915                                                    r59_non_bt[idx]);
1916                         }
1917                 }
1918         }
1919
1920         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1921         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1922         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1923         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1924
1925         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1926         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1927         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1928 }
1929
1930 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1931                                   struct ieee80211_conf *conf,
1932                                   struct rf_channel *rf,
1933                                   struct channel_info *info)
1934 {
1935         u32 reg;
1936         unsigned int tx_pin;
1937         u8 bbp;
1938
1939         if (rf->channel <= 14) {
1940                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1941                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1942         } else {
1943                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1944                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1945         }
1946
1947         if (rt2x00_rf(rt2x00dev, RF2020) ||
1948             rt2x00_rf(rt2x00dev, RF3020) ||
1949             rt2x00_rf(rt2x00dev, RF3021) ||
1950             rt2x00_rf(rt2x00dev, RF3022) ||
1951             rt2x00_rf(rt2x00dev, RF3320))
1952                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1953         else if (rt2x00_rf(rt2x00dev, RF3052))
1954                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
1955         else if (rt2x00_rf(rt2x00dev, RF5370) ||
1956                  rt2x00_rf(rt2x00dev, RF5390))
1957                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1958         else
1959                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1960
1961         /*
1962          * Change BBP settings
1963          */
1964         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1965         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1966         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1967         rt2800_bbp_write(rt2x00dev, 86, 0);
1968
1969         if (rf->channel <= 14) {
1970                 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1971                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
1972                                      &rt2x00dev->cap_flags)) {
1973                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1974                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1975                         } else {
1976                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1977                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1978                         }
1979                 }
1980         } else {
1981                 if (rt2x00_rt(rt2x00dev, RT3572))
1982                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
1983                 else
1984                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1985
1986                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
1987                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1988                 else
1989                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1990         }
1991
1992         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1993         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1994         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1995         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1996         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1997
1998         if (rt2x00_rt(rt2x00dev, RT3572))
1999                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2000
2001         tx_pin = 0;
2002
2003         /* Turn on unused PA or LNA when not using 1T or 1R */
2004         if (rt2x00dev->default_ant.tx_chain_num == 2) {
2005                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2006                                    rf->channel > 14);
2007                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2008                                    rf->channel <= 14);
2009         }
2010
2011         /* Turn on unused PA or LNA when not using 1T or 1R */
2012         if (rt2x00dev->default_ant.rx_chain_num == 2) {
2013                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2014                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2015         }
2016
2017         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2018         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2019         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2020         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2021         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2022                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2023         else
2024                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2025                                    rf->channel <= 14);
2026         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2027
2028         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2029
2030         if (rt2x00_rt(rt2x00dev, RT3572))
2031                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2032
2033         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2034         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2035         rt2800_bbp_write(rt2x00dev, 4, bbp);
2036
2037         rt2800_bbp_read(rt2x00dev, 3, &bbp);
2038         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2039         rt2800_bbp_write(rt2x00dev, 3, bbp);
2040
2041         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2042                 if (conf_is_ht40(conf)) {
2043                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2044                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2045                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
2046                 } else {
2047                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
2048                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
2049                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
2050                 }
2051         }
2052
2053         msleep(1);
2054
2055         /*
2056          * Clear channel statistic counters
2057          */
2058         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2059         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2060         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2061 }
2062
2063 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2064 {
2065         u8 tssi_bounds[9];
2066         u8 current_tssi;
2067         u16 eeprom;
2068         u8 step;
2069         int i;
2070
2071         /*
2072          * Read TSSI boundaries for temperature compensation from
2073          * the EEPROM.
2074          *
2075          * Array idx               0    1    2    3    4    5    6    7    8
2076          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
2077          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2078          */
2079         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2080                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2081                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2082                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
2083                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2084                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
2085
2086                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2087                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2088                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
2089                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2090                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
2091
2092                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2093                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2094                                         EEPROM_TSSI_BOUND_BG3_REF);
2095                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2096                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
2097
2098                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2099                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2100                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
2101                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2102                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
2103
2104                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2105                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2106                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
2107
2108                 step = rt2x00_get_field16(eeprom,
2109                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2110         } else {
2111                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2112                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2113                                         EEPROM_TSSI_BOUND_A1_MINUS4);
2114                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2115                                         EEPROM_TSSI_BOUND_A1_MINUS3);
2116
2117                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2118                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2119                                         EEPROM_TSSI_BOUND_A2_MINUS2);
2120                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2121                                         EEPROM_TSSI_BOUND_A2_MINUS1);
2122
2123                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2124                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2125                                         EEPROM_TSSI_BOUND_A3_REF);
2126                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2127                                         EEPROM_TSSI_BOUND_A3_PLUS1);
2128
2129                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2130                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2131                                         EEPROM_TSSI_BOUND_A4_PLUS2);
2132                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2133                                         EEPROM_TSSI_BOUND_A4_PLUS3);
2134
2135                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2136                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2137                                         EEPROM_TSSI_BOUND_A5_PLUS4);
2138
2139                 step = rt2x00_get_field16(eeprom,
2140                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
2141         }
2142
2143         /*
2144          * Check if temperature compensation is supported.
2145          */
2146         if (tssi_bounds[4] == 0xff)
2147                 return 0;
2148
2149         /*
2150          * Read current TSSI (BBP 49).
2151          */
2152         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2153
2154         /*
2155          * Compare TSSI value (BBP49) with the compensation boundaries
2156          * from the EEPROM and increase or decrease tx power.
2157          */
2158         for (i = 0; i <= 3; i++) {
2159                 if (current_tssi > tssi_bounds[i])
2160                         break;
2161         }
2162
2163         if (i == 4) {
2164                 for (i = 8; i >= 5; i--) {
2165                         if (current_tssi < tssi_bounds[i])
2166                                 break;
2167                 }
2168         }
2169
2170         return (i - 4) * step;
2171 }
2172
2173 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2174                                       enum ieee80211_band band)
2175 {
2176         u16 eeprom;
2177         u8 comp_en;
2178         u8 comp_type;
2179         int comp_value = 0;
2180
2181         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2182
2183         /*
2184          * HT40 compensation not required.
2185          */
2186         if (eeprom == 0xffff ||
2187             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2188                 return 0;
2189
2190         if (band == IEEE80211_BAND_2GHZ) {
2191                 comp_en = rt2x00_get_field16(eeprom,
2192                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
2193                 if (comp_en) {
2194                         comp_type = rt2x00_get_field16(eeprom,
2195                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
2196                         comp_value = rt2x00_get_field16(eeprom,
2197                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
2198                         if (!comp_type)
2199                                 comp_value = -comp_value;
2200                 }
2201         } else {
2202                 comp_en = rt2x00_get_field16(eeprom,
2203                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
2204                 if (comp_en) {
2205                         comp_type = rt2x00_get_field16(eeprom,
2206                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
2207                         comp_value = rt2x00_get_field16(eeprom,
2208                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
2209                         if (!comp_type)
2210                                 comp_value = -comp_value;
2211                 }
2212         }
2213
2214         return comp_value;
2215 }
2216
2217 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2218                                    enum ieee80211_band band, int power_level,
2219                                    u8 txpower, int delta)
2220 {
2221         u32 reg;
2222         u16 eeprom;
2223         u8 criterion;
2224         u8 eirp_txpower;
2225         u8 eirp_txpower_criterion;
2226         u8 reg_limit;
2227
2228         if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2229                 return txpower;
2230
2231         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2232                 /*
2233                  * Check if eirp txpower exceed txpower_limit.
2234                  * We use OFDM 6M as criterion and its eirp txpower
2235                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
2236                  * .11b data rate need add additional 4dbm
2237                  * when calculating eirp txpower.
2238                  */
2239                 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2240                 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2241
2242                 rt2x00_eeprom_read(rt2x00dev,
2243                                    EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2244
2245                 if (band == IEEE80211_BAND_2GHZ)
2246                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2247                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2248                 else
2249                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2250                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2251
2252                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2253                                (is_rate_b ? 4 : 0) + delta;
2254
2255                 reg_limit = (eirp_txpower > power_level) ?
2256                                         (eirp_txpower - power_level) : 0;
2257         } else
2258                 reg_limit = 0;
2259
2260         return txpower + delta - reg_limit;
2261 }
2262
2263 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2264                                   enum ieee80211_band band,
2265                                   int power_level)
2266 {
2267         u8 txpower;
2268         u16 eeprom;
2269         int i, is_rate_b;
2270         u32 reg;
2271         u8 r1;
2272         u32 offset;
2273         int delta;
2274
2275         /*
2276          * Calculate HT40 compensation delta
2277          */
2278         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2279
2280         /*
2281          * calculate temperature compensation delta
2282          */
2283         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2284
2285         /*
2286          * set to normal bbp tx power control mode: +/- 0dBm
2287          */
2288         rt2800_bbp_read(rt2x00dev, 1, &r1);
2289         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2290         rt2800_bbp_write(rt2x00dev, 1, r1);
2291         offset = TX_PWR_CFG_0;
2292
2293         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2294                 /* just to be safe */
2295                 if (offset > TX_PWR_CFG_4)
2296                         break;
2297
2298                 rt2800_register_read(rt2x00dev, offset, &reg);
2299
2300                 /* read the next four txpower values */
2301                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2302                                    &eeprom);
2303
2304                 is_rate_b = i ? 0 : 1;
2305                 /*
2306                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2307                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2308                  * TX_PWR_CFG_4: unknown
2309                  */
2310                 txpower = rt2x00_get_field16(eeprom,
2311                                              EEPROM_TXPOWER_BYRATE_RATE0);
2312                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2313                                              power_level, txpower, delta);
2314                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2315
2316                 /*
2317                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2318                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2319                  * TX_PWR_CFG_4: unknown
2320                  */
2321                 txpower = rt2x00_get_field16(eeprom,
2322                                              EEPROM_TXPOWER_BYRATE_RATE1);
2323                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2324                                              power_level, txpower, delta);
2325                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2326
2327                 /*
2328                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2329                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
2330                  * TX_PWR_CFG_4: unknown
2331                  */
2332                 txpower = rt2x00_get_field16(eeprom,
2333                                              EEPROM_TXPOWER_BYRATE_RATE2);
2334                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2335                                              power_level, txpower, delta);
2336                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2337
2338                 /*
2339                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2340                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
2341                  * TX_PWR_CFG_4: unknown
2342                  */
2343                 txpower = rt2x00_get_field16(eeprom,
2344                                              EEPROM_TXPOWER_BYRATE_RATE3);
2345                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2346                                              power_level, txpower, delta);
2347                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2348
2349                 /* read the next four txpower values */
2350                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2351                                    &eeprom);
2352
2353                 is_rate_b = 0;
2354                 /*
2355                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2356                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2357                  * TX_PWR_CFG_4: unknown
2358                  */
2359                 txpower = rt2x00_get_field16(eeprom,
2360                                              EEPROM_TXPOWER_BYRATE_RATE0);
2361                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2362                                              power_level, txpower, delta);
2363                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2364
2365                 /*
2366                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2367                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2368                  * TX_PWR_CFG_4: unknown
2369                  */
2370                 txpower = rt2x00_get_field16(eeprom,
2371                                              EEPROM_TXPOWER_BYRATE_RATE1);
2372                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2373                                              power_level, txpower, delta);
2374                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2375
2376                 /*
2377                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2378                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2379                  * TX_PWR_CFG_4: unknown
2380                  */
2381                 txpower = rt2x00_get_field16(eeprom,
2382                                              EEPROM_TXPOWER_BYRATE_RATE2);
2383                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2384                                              power_level, txpower, delta);
2385                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2386
2387                 /*
2388                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2389                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2390                  * TX_PWR_CFG_4: unknown
2391                  */
2392                 txpower = rt2x00_get_field16(eeprom,
2393                                              EEPROM_TXPOWER_BYRATE_RATE3);
2394                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2395                                              power_level, txpower, delta);
2396                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2397
2398                 rt2800_register_write(rt2x00dev, offset, reg);
2399
2400                 /* next TX_PWR_CFG register */
2401                 offset += 4;
2402         }
2403 }
2404
2405 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2406 {
2407         rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2408                               rt2x00dev->tx_power);
2409 }
2410 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2411
2412 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2413                                       struct rt2x00lib_conf *libconf)
2414 {
2415         u32 reg;
2416
2417         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2418         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2419                            libconf->conf->short_frame_max_tx_count);
2420         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2421                            libconf->conf->long_frame_max_tx_count);
2422         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2423 }
2424
2425 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2426                              struct rt2x00lib_conf *libconf)
2427 {
2428         enum dev_state state =
2429             (libconf->conf->flags & IEEE80211_CONF_PS) ?
2430                 STATE_SLEEP : STATE_AWAKE;
2431         u32 reg;
2432
2433         if (state == STATE_SLEEP) {
2434                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2435
2436                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2437                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2438                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2439                                    libconf->conf->listen_interval - 1);
2440                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2441                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2442
2443                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2444         } else {
2445                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2446                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2447                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2448                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2449                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2450
2451                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2452         }
2453 }
2454
2455 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2456                    struct rt2x00lib_conf *libconf,
2457                    const unsigned int flags)
2458 {
2459         /* Always recalculate LNA gain before changing configuration */
2460         rt2800_config_lna_gain(rt2x00dev, libconf);
2461
2462         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2463                 rt2800_config_channel(rt2x00dev, libconf->conf,
2464                                       &libconf->rf, &libconf->channel);
2465                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2466                                       libconf->conf->power_level);
2467         }
2468         if (flags & IEEE80211_CONF_CHANGE_POWER)
2469                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2470                                       libconf->conf->power_level);
2471         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2472                 rt2800_config_retry_limit(rt2x00dev, libconf);
2473         if (flags & IEEE80211_CONF_CHANGE_PS)
2474                 rt2800_config_ps(rt2x00dev, libconf);
2475 }
2476 EXPORT_SYMBOL_GPL(rt2800_config);
2477
2478 /*
2479  * Link tuning
2480  */
2481 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2482 {
2483         u32 reg;
2484
2485         /*
2486          * Update FCS error count from register.
2487          */
2488         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2489         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2490 }
2491 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2492
2493 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2494 {
2495         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2496                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2497                     rt2x00_rt(rt2x00dev, RT3071) ||
2498                     rt2x00_rt(rt2x00dev, RT3090) ||
2499                     rt2x00_rt(rt2x00dev, RT3390) ||
2500                     rt2x00_rt(rt2x00dev, RT5390))
2501                         return 0x1c + (2 * rt2x00dev->lna_gain);
2502                 else
2503                         return 0x2e + rt2x00dev->lna_gain;
2504         }
2505
2506         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2507                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2508         else
2509                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2510 }
2511
2512 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2513                                   struct link_qual *qual, u8 vgc_level)
2514 {
2515         if (qual->vgc_level != vgc_level) {
2516                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2517                 qual->vgc_level = vgc_level;
2518                 qual->vgc_level_reg = vgc_level;
2519         }
2520 }
2521
2522 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2523 {
2524         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2525 }
2526 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2527
2528 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2529                        const u32 count)
2530 {
2531         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2532                 return;
2533
2534         /*
2535          * When RSSI is better then -80 increase VGC level with 0x10
2536          */
2537         rt2800_set_vgc(rt2x00dev, qual,
2538                        rt2800_get_default_vgc(rt2x00dev) +
2539                        ((qual->rssi > -80) * 0x10));
2540 }
2541 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2542
2543 /*
2544  * Initialization functions.
2545  */
2546 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2547 {
2548         u32 reg;
2549         u16 eeprom;
2550         unsigned int i;
2551         int ret;
2552
2553         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2554         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2555         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2556         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2557         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2558         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2559         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2560
2561         ret = rt2800_drv_init_registers(rt2x00dev);
2562         if (ret)
2563                 return ret;
2564
2565         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2566         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2567         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2568         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2569         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2570         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2571
2572         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2573         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2574         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2575         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2576         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2577         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2578
2579         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2580         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2581
2582         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2583
2584         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2585         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2586         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2587         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2588         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2589         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2590         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2591         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2592
2593         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2594
2595         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2596         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2597         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2598         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2599
2600         if (rt2x00_rt(rt2x00dev, RT3071) ||
2601             rt2x00_rt(rt2x00dev, RT3090) ||
2602             rt2x00_rt(rt2x00dev, RT3390)) {
2603                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2604                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2605                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2606                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2607                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2608                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2609                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2610                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2611                                                       0x0000002c);
2612                         else
2613                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2614                                                       0x0000000f);
2615                 } else {
2616                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2617                 }
2618         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2619                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2620
2621                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2622                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2623                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2624                 } else {
2625                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2626                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2627                 }
2628         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2629                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2630                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2631                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
2632         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2633                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2634                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2635         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2636                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2637                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2638                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2639         } else {
2640                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2641                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2642         }
2643
2644         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2645         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2646         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2647         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2648         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2649         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2650         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2651         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2652         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2653         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2654
2655         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2656         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2657         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2658         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2659         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2660
2661         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2662         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2663         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2664             rt2x00_rt(rt2x00dev, RT2883) ||
2665             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2666                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2667         else
2668                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2669         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2670         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2671         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2672
2673         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2674         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2675         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2676         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2677         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2678         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2679         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2680         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2681         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2682
2683         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2684
2685         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2686         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2687         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2688         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2689         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2690         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2691         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2692         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2693
2694         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2695         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2696         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2697         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2698         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2699         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2700         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2701         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2702         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2703
2704         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2705         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2706         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2707         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2708         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2709         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2710         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2711         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2712         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2713         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2714         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2715         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2716
2717         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2718         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2719         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2720         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2721         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2722         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2723         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2724         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2725         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2726         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2727         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2728         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2729
2730         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2731         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2732         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2733         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2734         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2735         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2736         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2737         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2738         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2739         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2740         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2741         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2742
2743         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2744         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2745         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2746         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2747         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2748         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2749         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2750         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2751         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2752         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2753         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2754         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2755
2756         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2757         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2758         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2759         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2760         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2761         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2762         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2763         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2764         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2765         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2766         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2767         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2768
2769         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2770         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2771         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2772         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2773         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2774         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2775         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2776         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2777         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2778         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2779         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2780         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2781
2782         if (rt2x00_is_usb(rt2x00dev)) {
2783                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2784
2785                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2786                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2787                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2788                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2789                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2790                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2791                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2792                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2793                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2794                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2795                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2796         }
2797
2798         /*
2799          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2800          * although it is reserved.
2801          */
2802         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2803         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2804         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2805         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2806         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2807         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2808         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2809         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2810         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2811         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2812         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2813         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2814
2815         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2816
2817         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2818         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2819         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2820                            IEEE80211_MAX_RTS_THRESHOLD);
2821         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2822         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2823
2824         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2825
2826         /*
2827          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2828          * time should be set to 16. However, the original Ralink driver uses
2829          * 16 for both and indeed using a value of 10 for CCK SIFS results in
2830          * connection problems with 11g + CTS protection. Hence, use the same
2831          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2832          */
2833         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
2834         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2835         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2836         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2837         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2838         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2839         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2840
2841         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2842
2843         /*
2844          * ASIC will keep garbage value after boot, clear encryption keys.
2845          */
2846         for (i = 0; i < 4; i++)
2847                 rt2800_register_write(rt2x00dev,
2848                                          SHARED_KEY_MODE_ENTRY(i), 0);
2849
2850         for (i = 0; i < 256; i++) {
2851                 rt2800_config_wcid(rt2x00dev, NULL, i);
2852                 rt2800_delete_wcid_attr(rt2x00dev, i);
2853                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2854         }
2855
2856         /*
2857          * Clear all beacons
2858          */
2859         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2860         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2861         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2862         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2863         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2864         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2865         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2866         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2867
2868         if (rt2x00_is_usb(rt2x00dev)) {
2869                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2870                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2871                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2872         } else if (rt2x00_is_pcie(rt2x00dev)) {
2873                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2874                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2875                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2876         }
2877
2878         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2879         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2880         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2881         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2882         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2883         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2884         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2885         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2886         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2887         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2888
2889         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2890         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2891         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2892         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2893         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2894         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2895         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2896         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2897         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2898         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2899
2900         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2901         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2902         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2903         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2904         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2905         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2906         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2907         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2908         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2909         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2910
2911         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2912         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2913         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2914         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2915         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2916         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2917
2918         /*
2919          * Do not force the BA window size, we use the TXWI to set it
2920          */
2921         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2922         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2923         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2924         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2925
2926         /*
2927          * We must clear the error counters.
2928          * These registers are cleared on read,
2929          * so we may pass a useless variable to store the value.
2930          */
2931         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2932         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2933         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2934         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2935         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2936         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2937
2938         /*
2939          * Setup leadtime for pre tbtt interrupt to 6ms
2940          */
2941         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2942         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2943         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2944
2945         /*
2946          * Set up channel statistics timer
2947          */
2948         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2949         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2950         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2951         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2952         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2953         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2954         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2955
2956         return 0;
2957 }
2958
2959 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2960 {
2961         unsigned int i;
2962         u32 reg;
2963
2964         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2965                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2966                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2967                         return 0;
2968
2969                 udelay(REGISTER_BUSY_DELAY);
2970         }
2971
2972         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2973         return -EACCES;
2974 }
2975
2976 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2977 {
2978         unsigned int i;
2979         u8 value;
2980
2981         /*
2982          * BBP was enabled after firmware was loaded,
2983          * but we need to reactivate it now.
2984          */
2985         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2986         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2987         msleep(1);
2988
2989         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2990                 rt2800_bbp_read(rt2x00dev, 0, &value);
2991                 if ((value != 0xff) && (value != 0x00))
2992                         return 0;
2993                 udelay(REGISTER_BUSY_DELAY);
2994         }
2995
2996         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2997         return -EACCES;
2998 }
2999
3000 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3001 {
3002         unsigned int i;
3003         u16 eeprom;
3004         u8 reg_id;
3005         u8 value;
3006
3007         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3008                      rt2800_wait_bbp_ready(rt2x00dev)))
3009                 return -EACCES;
3010
3011         if (rt2x00_rt(rt2x00dev, RT5390)) {
3012                 rt2800_bbp_read(rt2x00dev, 4, &value);
3013                 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3014                 rt2800_bbp_write(rt2x00dev, 4, value);
3015         }
3016
3017         if (rt2800_is_305x_soc(rt2x00dev) ||
3018             rt2x00_rt(rt2x00dev, RT3572) ||
3019             rt2x00_rt(rt2x00dev, RT5390))
3020                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3021
3022         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3023         rt2800_bbp_write(rt2x00dev, 66, 0x38);
3024
3025         if (rt2x00_rt(rt2x00dev, RT5390))
3026                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3027
3028         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3029                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3030                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3031         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3032                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3033                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3034                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3035                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3036                 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3037         } else {
3038                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3039                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3040         }
3041
3042         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3043
3044         if (rt2x00_rt(rt2x00dev, RT3070) ||
3045             rt2x00_rt(rt2x00dev, RT3071) ||
3046             rt2x00_rt(rt2x00dev, RT3090) ||
3047             rt2x00_rt(rt2x00dev, RT3390) ||
3048             rt2x00_rt(rt2x00dev, RT3572) ||
3049             rt2x00_rt(rt2x00dev, RT5390)) {
3050                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3051                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3052                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3053         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3054                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3055                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3056         } else {
3057                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3058         }
3059
3060         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3061         if (rt2x00_rt(rt2x00dev, RT5390))
3062                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3063         else
3064                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3065
3066         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3067                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3068         else if (rt2x00_rt(rt2x00dev, RT5390))
3069                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3070         else
3071                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3072
3073         if (rt2x00_rt(rt2x00dev, RT5390))
3074                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3075         else
3076                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3077
3078         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3079
3080         if (rt2x00_rt(rt2x00dev, RT5390))
3081                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3082         else
3083                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3084
3085         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
3086             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3087             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3088             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3089             rt2x00_rt(rt2x00dev, RT3572) ||
3090             rt2x00_rt(rt2x00dev, RT5390) ||
3091             rt2800_is_305x_soc(rt2x00dev))
3092                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3093         else
3094                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3095
3096         if (rt2x00_rt(rt2x00dev, RT5390))
3097                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3098
3099         if (rt2800_is_305x_soc(rt2x00dev))
3100                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3101         else if (rt2x00_rt(rt2x00dev, RT5390))
3102                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3103         else
3104                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3105
3106         if (rt2x00_rt(rt2x00dev, RT5390))
3107                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3108         else
3109                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3110
3111         if (rt2x00_rt(rt2x00dev, RT5390))
3112                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3113
3114         if (rt2x00_rt(rt2x00dev, RT3071) ||
3115             rt2x00_rt(rt2x00dev, RT3090) ||
3116             rt2x00_rt(rt2x00dev, RT3390) ||
3117             rt2x00_rt(rt2x00dev, RT3572) ||
3118             rt2x00_rt(rt2x00dev, RT5390)) {
3119                 rt2800_bbp_read(rt2x00dev, 138, &value);
3120
3121                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3122                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3123                         value |= 0x20;
3124                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3125                         value &= ~0x02;
3126
3127                 rt2800_bbp_write(rt2x00dev, 138, value);
3128         }
3129
3130         if (rt2x00_rt(rt2x00dev, RT5390)) {
3131                 int ant, div_mode;
3132
3133                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3134                 div_mode = rt2x00_get_field16(eeprom,
3135                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
3136                 ant = (div_mode == 3) ? 1 : 0;
3137
3138                 /* check if this is a Bluetooth combo card */
3139                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
3140                         u32 reg;
3141
3142                         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3143                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3144                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3145                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3146                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3147                         if (ant == 0)
3148                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3149                         else if (ant == 1)
3150                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3151                         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3152                 }
3153
3154                 rt2800_bbp_read(rt2x00dev, 152, &value);
3155                 if (ant == 0)
3156                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3157                 else
3158                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3159                 rt2800_bbp_write(rt2x00dev, 152, value);
3160
3161                 /* Init frequency calibration */
3162                 rt2800_bbp_write(rt2x00dev, 142, 1);
3163                 rt2800_bbp_write(rt2x00dev, 143, 57);
3164         }
3165
3166         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3167                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3168
3169                 if (eeprom != 0xffff && eeprom != 0x0000) {
3170                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3171                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3172                         rt2800_bbp_write(rt2x00dev, reg_id, value);
3173                 }
3174         }
3175
3176         return 0;
3177 }
3178
3179 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3180                                 bool bw40, u8 rfcsr24, u8 filter_target)
3181 {
3182         unsigned int i;
3183         u8 bbp;
3184         u8 rfcsr;
3185         u8 passband;
3186         u8 stopband;
3187         u8 overtuned = 0;
3188
3189         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3190
3191         rt2800_bbp_read(rt2x00dev, 4, &bbp);
3192         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3193         rt2800_bbp_write(rt2x00dev, 4, bbp);
3194
3195         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3196         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3197         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3198
3199         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3200         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3201         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3202
3203         /*
3204          * Set power & frequency of passband test tone
3205          */
3206         rt2800_bbp_write(rt2x00dev, 24, 0);
3207
3208         for (i = 0; i < 100; i++) {
3209                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3210                 msleep(1);
3211
3212                 rt2800_bbp_read(rt2x00dev, 55, &passband);
3213                 if (passband)
3214                         break;
3215         }
3216
3217         /*
3218          * Set power & frequency of stopband test tone
3219          */
3220         rt2800_bbp_write(rt2x00dev, 24, 0x06);
3221
3222         for (i = 0; i < 100; i++) {
3223                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3224                 msleep(1);
3225
3226                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3227
3228                 if ((passband - stopband) <= filter_target) {
3229                         rfcsr24++;
3230                         overtuned += ((passband - stopband) == filter_target);
3231                 } else
3232                         break;
3233
3234                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3235         }
3236
3237         rfcsr24 -= !!overtuned;
3238
3239         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3240         return rfcsr24;
3241 }
3242
3243 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3244 {
3245         u8 rfcsr;
3246         u8 bbp;
3247         u32 reg;
3248         u16 eeprom;
3249
3250         if (!rt2x00_rt(rt2x00dev, RT3070) &&
3251             !rt2x00_rt(rt2x00dev, RT3071) &&
3252             !rt2x00_rt(rt2x00dev, RT3090) &&
3253             !rt2x00_rt(rt2x00dev, RT3390) &&
3254             !rt2x00_rt(rt2x00dev, RT3572) &&
3255             !rt2x00_rt(rt2x00dev, RT5390) &&
3256             !rt2800_is_305x_soc(rt2x00dev))
3257                 return 0;
3258
3259         /*
3260          * Init RF calibration.
3261          */
3262         if (rt2x00_rt(rt2x00dev, RT5390)) {
3263                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3264                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3265                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3266                 msleep(1);
3267                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3268                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3269         } else {
3270                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3271                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3272                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3273                 msleep(1);
3274                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3275                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3276         }
3277
3278         if (rt2x00_rt(rt2x00dev, RT3070) ||
3279             rt2x00_rt(rt2x00dev, RT3071) ||
3280             rt2x00_rt(rt2x00dev, RT3090)) {
3281                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3282                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3283                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3284                 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3285                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3286                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3287                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3288                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3289                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3290                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3291                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3292                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3293                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3294                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3295                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3296                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3297                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3298                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3299                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3300         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3301                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3302                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3303                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3304                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3305                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3306                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3307                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3308                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3309                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3310                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3311                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3312                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3313                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3314                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3315                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3316                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3317                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3318                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3319                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3320                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3321                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3322                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3323                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3324                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3325                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3326                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3327                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3328                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3329                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3330                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3331                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3332                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3333         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3334                 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3335                 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3336                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3337                 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3338                 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3339                 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3340                 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3341                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3342                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3343                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3344                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3345                 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3346                 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3347                 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3348                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3349                 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3350                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3351                 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3352                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3353                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3354                 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3355                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3356                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3357                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3358                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3359                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3360                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3361                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3362                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3363                 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3364                 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
3365         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3366                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3367                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3368                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3369                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3370                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3371                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3372                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3373                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3374                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3375                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3376                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3377                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3378                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3379                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3380                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3381                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3382                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3383                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3384                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3385                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3386                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3387                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3388                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3389                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3390                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3391                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3392                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3393                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3394                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3395                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3396                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3397                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3398                 return 0;
3399         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3400                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3401                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3402                 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3403                 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3404                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3405                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3406                 else
3407                         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3408                 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3409                 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3410                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3411                 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3412                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3413                 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3414                 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3415                 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3416                 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3417                 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3418
3419                 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3420                 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3421                 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3422                 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3423                 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3424                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3425                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3426                 else
3427                         rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3428                 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3429                 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3430                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3431                 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3432
3433                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3434                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3435                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3436                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3437                 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3438                 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3439                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3440                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3441                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3442                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3443
3444                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3445                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3446                 else
3447                         rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3448                 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3449                 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3450                 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3451                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3452                 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3453                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3454                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3455                 else
3456                         rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3457                 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3458                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3459                 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3460
3461                 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3462                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3463                         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3464                 else
3465                         rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3466                 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3467                 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3468                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3469                 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3470                 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3471                 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3472
3473                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3474                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3475                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3476                 else
3477                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3478                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3479                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3480         }
3481
3482         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3483                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3484                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3485                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3486                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3487         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3488                    rt2x00_rt(rt2x00dev, RT3090)) {
3489                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3490
3491                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3492                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3493                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3494
3495                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3496                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3497                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3498                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3499                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3500                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3501                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3502                         else
3503                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3504                 }
3505                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3506
3507                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3508                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3509                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3510         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3511                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3512                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3513                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3514         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3515                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3516                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3517                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3518
3519                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3520                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3521                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3522                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3523                 msleep(1);
3524                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3525                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3526                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3527         }
3528
3529         /*
3530          * Set RX Filter calibration for 20MHz and 40MHz
3531          */
3532         if (rt2x00_rt(rt2x00dev, RT3070)) {
3533                 rt2x00dev->calibration[0] =
3534                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3535                 rt2x00dev->calibration[1] =
3536                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3537         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3538                    rt2x00_rt(rt2x00dev, RT3090) ||
3539                    rt2x00_rt(rt2x00dev, RT3390) ||
3540                    rt2x00_rt(rt2x00dev, RT3572)) {
3541                 rt2x00dev->calibration[0] =
3542                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3543                 rt2x00dev->calibration[1] =
3544                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3545         }
3546
3547         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3548                 /*
3549                  * Set back to initial state
3550                  */
3551                 rt2800_bbp_write(rt2x00dev, 24, 0);
3552
3553                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3554                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3555                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3556
3557                 /*
3558                  * Set BBP back to BW20
3559                  */
3560                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3561                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3562                 rt2800_bbp_write(rt2x00dev, 4, bbp);
3563         }
3564
3565         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3566             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3567             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3568             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3569                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3570
3571         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3572         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3573         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3574
3575         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3576                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3577                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3578                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3579                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3580                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3581                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3582                         if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3583                                       &rt2x00dev->cap_flags))
3584                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3585                 }
3586                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3587                 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3588                         rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3589                                         rt2x00_get_field16(eeprom,
3590                                                 EEPROM_TXMIXER_GAIN_BG_VAL));
3591                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3592         }
3593
3594         if (rt2x00_rt(rt2x00dev, RT3090)) {
3595                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3596
3597                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
3598                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3599                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3600                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3601                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3602                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3603
3604                 rt2800_bbp_write(rt2x00dev, 138, bbp);
3605         }
3606
3607         if (rt2x00_rt(rt2x00dev, RT3071) ||
3608             rt2x00_rt(rt2x00dev, RT3090) ||
3609             rt2x00_rt(rt2x00dev, RT3390)) {
3610                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3611                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3612                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3613                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3614                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3615                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3616                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3617
3618                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3619                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3620                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3621
3622                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3623                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3624                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3625
3626                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3627                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3628                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3629         }
3630
3631         if (rt2x00_rt(rt2x00dev, RT3070)) {
3632                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3633                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3634                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3635                 else
3636                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3637                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3638                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3639                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3640                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3641         }
3642
3643         if (rt2x00_rt(rt2x00dev, RT5390)) {
3644                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3645                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3646                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3647
3648                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3649                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3650                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3651
3652                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3653                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3654                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3655         }
3656
3657         return 0;
3658 }
3659
3660 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3661 {
3662         u32 reg;
3663         u16 word;
3664
3665         /*
3666          * Initialize all registers.
3667          */
3668         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3669                      rt2800_init_registers(rt2x00dev) ||
3670                      rt2800_init_bbp(rt2x00dev) ||
3671                      rt2800_init_rfcsr(rt2x00dev)))
3672                 return -EIO;
3673
3674         /*
3675          * Send signal to firmware during boot time.
3676          */
3677         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3678
3679         if (rt2x00_is_usb(rt2x00dev) &&
3680             (rt2x00_rt(rt2x00dev, RT3070) ||
3681              rt2x00_rt(rt2x00dev, RT3071) ||
3682              rt2x00_rt(rt2x00dev, RT3572))) {
3683                 udelay(200);
3684                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3685                 udelay(10);
3686         }
3687
3688         /*
3689          * Enable RX.
3690          */
3691         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3692         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3693         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3694         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3695
3696         udelay(50);
3697
3698         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3699         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3700         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3701         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3702         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3703         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3704
3705         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3706         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3707         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3708         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3709
3710         /*
3711          * Initialize LED control
3712          */
3713         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3714         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3715                            word & 0xff, (word >> 8) & 0xff);
3716
3717         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3718         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3719                            word & 0xff, (word >> 8) & 0xff);
3720
3721         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3722         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3723                            word & 0xff, (word >> 8) & 0xff);
3724
3725         return 0;
3726 }
3727 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3728
3729 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3730 {
3731         u32 reg;
3732
3733         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3734         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3735         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3736         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3737
3738         /* Wait for DMA, ignore error */
3739         rt2800_wait_wpdma_ready(rt2x00dev);
3740
3741         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3742         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3743         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3744         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3745 }
3746 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
3747
3748 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3749 {
3750         u32 reg;
3751
3752         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3753
3754         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3755 }
3756 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3757
3758 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3759 {
3760         u32 reg;
3761
3762         mutex_lock(&rt2x00dev->csr_mutex);
3763
3764         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
3765         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3766         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3767         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
3768         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
3769
3770         /* Wait until the EEPROM has been loaded */
3771         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3772
3773         /* Apparently the data is read from end to start */
3774         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, &reg);
3775         /* The returned value is in CPU order, but eeprom is le */
3776         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
3777         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, &reg);
3778         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
3779         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, &reg);
3780         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
3781         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, &reg);
3782         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
3783
3784         mutex_unlock(&rt2x00dev->csr_mutex);
3785 }
3786
3787 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3788 {
3789         unsigned int i;
3790
3791         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3792                 rt2800_efuse_read(rt2x00dev, i);
3793 }
3794 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3795
3796 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3797 {
3798         u16 word;
3799         u8 *mac;
3800         u8 default_lna_gain;
3801
3802         /*
3803          * Start validation of the data that has been read.
3804          */
3805         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3806         if (!is_valid_ether_addr(mac)) {
3807                 random_ether_addr(mac);
3808                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3809         }
3810
3811         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
3812         if (word == 0xffff) {
3813                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3814                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3815                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3816                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3817                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
3818         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
3819                    rt2x00_rt(rt2x00dev, RT2872)) {
3820                 /*
3821                  * There is a max of 2 RX streams for RT28x0 series
3822                  */
3823                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3824                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3825                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3826         }
3827
3828         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
3829         if (word == 0xffff) {
3830                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3831                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3832                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3833                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3834                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3835                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3836                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3837                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3838                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3839                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3840                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3841                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3842                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3843                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3844                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3845                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
3846                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3847         }
3848
3849         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3850         if ((word & 0x00ff) == 0x00ff) {
3851                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3852                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3853                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3854         }
3855         if ((word & 0xff00) == 0xff00) {
3856                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3857                                    LED_MODE_TXRX_ACTIVITY);
3858                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3859                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3860                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3861                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3862                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
3863                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
3864         }
3865
3866         /*
3867          * During the LNA validation we are going to use
3868          * lna0 as correct value. Note that EEPROM_LNA
3869          * is never validated.
3870          */
3871         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3872         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3873
3874         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3875         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3876                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3877         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3878                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3879         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3880
3881         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3882         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3883                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3884         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3885             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3886                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3887                                    default_lna_gain);
3888         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3889
3890         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3891         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3892                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3893         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3894                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3895         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3896
3897         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3898         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3899                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3900         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3901             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3902                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3903                                    default_lna_gain);
3904         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3905
3906         return 0;
3907 }
3908 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3909
3910 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3911 {
3912         u32 reg;
3913         u16 value;
3914         u16 eeprom;
3915
3916         /*
3917          * Read EEPROM word for configuration.
3918          */
3919         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3920
3921         /*
3922          * Identify RF chipset by EEPROM value
3923          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3924          * RT53xx: defined in "EEPROM_CHIP_ID" field
3925          */
3926         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3927         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3928                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3929         else
3930                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3931
3932         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3933                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3934
3935         if (!rt2x00_rt(rt2x00dev, RT2860) &&
3936             !rt2x00_rt(rt2x00dev, RT2872) &&
3937             !rt2x00_rt(rt2x00dev, RT2883) &&
3938             !rt2x00_rt(rt2x00dev, RT3070) &&
3939             !rt2x00_rt(rt2x00dev, RT3071) &&
3940             !rt2x00_rt(rt2x00dev, RT3090) &&
3941             !rt2x00_rt(rt2x00dev, RT3390) &&
3942             !rt2x00_rt(rt2x00dev, RT3572) &&
3943             !rt2x00_rt(rt2x00dev, RT5390)) {
3944                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3945                 return -ENODEV;
3946         }
3947
3948         switch (rt2x00dev->chip.rf) {
3949         case RF2820:
3950         case RF2850:
3951         case RF2720:
3952         case RF2750:
3953         case RF3020:
3954         case RF2020:
3955         case RF3021:
3956         case RF3022:
3957         case RF3052:
3958         case RF3320:
3959         case RF5370:
3960         case RF5390:
3961                 break;
3962         default:
3963                 ERROR(rt2x00dev, "Invalid RF chipset 0x%x detected.\n",
3964                       rt2x00dev->chip.rf);
3965                 return -ENODEV;
3966         }
3967
3968         /*
3969          * Identify default antenna configuration.
3970          */
3971         rt2x00dev->default_ant.tx_chain_num =
3972             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
3973         rt2x00dev->default_ant.rx_chain_num =
3974             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3975
3976         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3977
3978         if (rt2x00_rt(rt2x00dev, RT3070) ||
3979             rt2x00_rt(rt2x00dev, RT3090) ||
3980             rt2x00_rt(rt2x00dev, RT3390)) {
3981                 value = rt2x00_get_field16(eeprom,
3982                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3983                 switch (value) {
3984                 case 0:
3985                 case 1:
3986                 case 2:
3987                         rt2x00dev->default_ant.tx = ANTENNA_A;
3988                         rt2x00dev->default_ant.rx = ANTENNA_A;
3989                         break;
3990                 case 3:
3991                         rt2x00dev->default_ant.tx = ANTENNA_A;
3992                         rt2x00dev->default_ant.rx = ANTENNA_B;
3993                         break;
3994                 }
3995         } else {
3996                 rt2x00dev->default_ant.tx = ANTENNA_A;
3997                 rt2x00dev->default_ant.rx = ANTENNA_A;
3998         }
3999
4000         /*
4001          * Determine external LNA informations.
4002          */
4003         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
4004                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
4005         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
4006                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
4007
4008         /*
4009          * Detect if this device has an hardware controlled radio.
4010          */
4011         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
4012                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
4013
4014         /*
4015          * Detect if this device has Bluetooth co-existence.
4016          */
4017         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4018                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4019
4020         /*
4021          * Read frequency offset and RF programming sequence.
4022          */
4023         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4024         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4025
4026         /*
4027          * Store led settings, for correct led behaviour.
4028          */
4029 #ifdef CONFIG_RT2X00_LIB_LEDS
4030         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4031         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4032         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4033
4034         rt2x00dev->led_mcu_reg = eeprom;
4035 #endif /* CONFIG_RT2X00_LIB_LEDS */
4036
4037         /*
4038          * Check if support EIRP tx power limit feature.
4039          */
4040         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4041
4042         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4043                                         EIRP_MAX_TX_POWER_LIMIT)
4044                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
4045
4046         return 0;
4047 }
4048 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4049
4050 /*
4051  * RF value list for rt28xx
4052  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4053  */
4054 static const struct rf_channel rf_vals[] = {
4055         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4056         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4057         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4058         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4059         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4060         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4061         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4062         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4063         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4064         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4065         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4066         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4067         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4068         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4069
4070         /* 802.11 UNI / HyperLan 2 */
4071         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4072         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4073         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4074         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4075         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4076         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4077         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4078         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4079         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4080         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4081         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4082         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4083
4084         /* 802.11 HyperLan 2 */
4085         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4086         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4087         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4088         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4089         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4090         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4091         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4092         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4093         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4094         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4095         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4096         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4097         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4098         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4099         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4100         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4101
4102         /* 802.11 UNII */
4103         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4104         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4105         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4106         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4107         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4108         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4109         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4110         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4111         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4112         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4113         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4114
4115         /* 802.11 Japan */
4116         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4117         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4118         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4119         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4120         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4121         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4122         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4123 };
4124
4125 /*
4126  * RF value list for rt3xxx
4127  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4128  */
4129 static const struct rf_channel rf_vals_3x[] = {
4130         {1,  241, 2, 2 },
4131         {2,  241, 2, 7 },
4132         {3,  242, 2, 2 },
4133         {4,  242, 2, 7 },
4134         {5,  243, 2, 2 },
4135         {6,  243, 2, 7 },
4136         {7,  244, 2, 2 },
4137         {8,  244, 2, 7 },
4138         {9,  245, 2, 2 },
4139         {10, 245, 2, 7 },
4140         {11, 246, 2, 2 },
4141         {12, 246, 2, 7 },
4142         {13, 247, 2, 2 },
4143         {14, 248, 2, 4 },
4144
4145         /* 802.11 UNI / HyperLan 2 */
4146         {36, 0x56, 0, 4},
4147         {38, 0x56, 0, 6},
4148         {40, 0x56, 0, 8},
4149         {44, 0x57, 0, 0},
4150         {46, 0x57, 0, 2},
4151         {48, 0x57, 0, 4},
4152         {52, 0x57, 0, 8},
4153         {54, 0x57, 0, 10},
4154         {56, 0x58, 0, 0},
4155         {60, 0x58, 0, 4},
4156         {62, 0x58, 0, 6},
4157         {64, 0x58, 0, 8},
4158
4159         /* 802.11 HyperLan 2 */
4160         {100, 0x5b, 0, 8},
4161         {102, 0x5b, 0, 10},
4162         {104, 0x5c, 0, 0},
4163         {108, 0x5c, 0, 4},
4164         {110, 0x5c, 0, 6},
4165         {112, 0x5c, 0, 8},
4166         {116, 0x5d, 0, 0},
4167         {118, 0x5d, 0, 2},
4168         {120, 0x5d, 0, 4},
4169         {124, 0x5d, 0, 8},
4170         {126, 0x5d, 0, 10},
4171         {128, 0x5e, 0, 0},
4172         {132, 0x5e, 0, 4},
4173         {134, 0x5e, 0, 6},
4174         {136, 0x5e, 0, 8},
4175         {140, 0x5f, 0, 0},
4176
4177         /* 802.11 UNII */
4178         {149, 0x5f, 0, 9},
4179         {151, 0x5f, 0, 11},
4180         {153, 0x60, 0, 1},
4181         {157, 0x60, 0, 5},
4182         {159, 0x60, 0, 7},
4183         {161, 0x60, 0, 9},
4184         {165, 0x61, 0, 1},
4185         {167, 0x61, 0, 3},
4186         {169, 0x61, 0, 5},
4187         {171, 0x61, 0, 7},
4188         {173, 0x61, 0, 9},
4189 };
4190
4191 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4192 {
4193         struct hw_mode_spec *spec = &rt2x00dev->spec;
4194         struct channel_info *info;
4195         char *default_power1;
4196         char *default_power2;
4197         unsigned int i;
4198         u16 eeprom;
4199
4200         /*
4201          * Disable powersaving as default on PCI devices.
4202          */
4203         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
4204                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4205
4206         /*
4207          * Initialize all hw fields.
4208          */
4209         rt2x00dev->hw->flags =
4210             IEEE80211_HW_SIGNAL_DBM |
4211             IEEE80211_HW_SUPPORTS_PS |
4212             IEEE80211_HW_PS_NULLFUNC_STACK |
4213             IEEE80211_HW_AMPDU_AGGREGATION;
4214         /*
4215          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4216          * unless we are capable of sending the buffered frames out after the
4217          * DTIM transmission using rt2x00lib_beacondone. This will send out
4218          * multicast and broadcast traffic immediately instead of buffering it
4219          * infinitly and thus dropping it after some time.
4220          */
4221         if (!rt2x00_is_usb(rt2x00dev))
4222                 rt2x00dev->hw->flags |=
4223                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4224
4225         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4226         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4227                                 rt2x00_eeprom_addr(rt2x00dev,
4228                                                    EEPROM_MAC_ADDR_0));
4229
4230         /*
4231          * As rt2800 has a global fallback table we cannot specify
4232          * more then one tx rate per frame but since the hw will
4233          * try several rates (based on the fallback table) we should
4234          * initialize max_report_rates to the maximum number of rates
4235          * we are going to try. Otherwise mac80211 will truncate our
4236          * reported tx rates and the rc algortihm will end up with
4237          * incorrect data.
4238          */
4239         rt2x00dev->hw->max_rates = 1;
4240         rt2x00dev->hw->max_report_rates = 7;
4241         rt2x00dev->hw->max_rate_tries = 1;
4242
4243         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4244
4245         /*
4246          * Initialize hw_mode information.
4247          */
4248         spec->supported_bands = SUPPORT_BAND_2GHZ;
4249         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4250
4251         if (rt2x00_rf(rt2x00dev, RF2820) ||
4252             rt2x00_rf(rt2x00dev, RF2720)) {
4253                 spec->num_channels = 14;
4254                 spec->channels = rf_vals;
4255         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4256                    rt2x00_rf(rt2x00dev, RF2750)) {
4257                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4258                 spec->num_channels = ARRAY_SIZE(rf_vals);
4259                 spec->channels = rf_vals;
4260         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4261                    rt2x00_rf(rt2x00dev, RF2020) ||
4262                    rt2x00_rf(rt2x00dev, RF3021) ||
4263                    rt2x00_rf(rt2x00dev, RF3022) ||
4264                    rt2x00_rf(rt2x00dev, RF3320) ||
4265                    rt2x00_rf(rt2x00dev, RF5370) ||
4266                    rt2x00_rf(rt2x00dev, RF5390)) {
4267                 spec->num_channels = 14;
4268                 spec->channels = rf_vals_3x;
4269         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4270                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4271                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4272                 spec->channels = rf_vals_3x;
4273         }
4274
4275         /*
4276          * Initialize HT information.
4277          */
4278         if (!rt2x00_rf(rt2x00dev, RF2020))
4279                 spec->ht.ht_supported = true;
4280         else
4281                 spec->ht.ht_supported = false;
4282
4283         spec->ht.cap =
4284             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4285             IEEE80211_HT_CAP_GRN_FLD |
4286             IEEE80211_HT_CAP_SGI_20 |
4287             IEEE80211_HT_CAP_SGI_40;
4288
4289         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
4290                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4291
4292         spec->ht.cap |=
4293             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
4294                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4295
4296         spec->ht.ampdu_factor = 3;
4297         spec->ht.ampdu_density = 4;
4298         spec->ht.mcs.tx_params =
4299             IEEE80211_HT_MCS_TX_DEFINED |
4300             IEEE80211_HT_MCS_TX_RX_DIFF |
4301             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4302                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4303
4304         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4305         case 3:
4306                 spec->ht.mcs.rx_mask[2] = 0xff;
4307         case 2:
4308                 spec->ht.mcs.rx_mask[1] = 0xff;
4309         case 1:
4310                 spec->ht.mcs.rx_mask[0] = 0xff;
4311                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4312                 break;
4313         }
4314
4315         /*
4316          * Create channel information array
4317          */
4318         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4319         if (!info)
4320                 return -ENOMEM;
4321
4322         spec->channels_info = info;
4323
4324         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4325         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4326
4327         for (i = 0; i < 14; i++) {
4328                 info[i].default_power1 = default_power1[i];
4329                 info[i].default_power2 = default_power2[i];
4330         }
4331
4332         if (spec->num_channels > 14) {
4333                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4334                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4335
4336                 for (i = 14; i < spec->num_channels; i++) {
4337                         info[i].default_power1 = default_power1[i];
4338                         info[i].default_power2 = default_power2[i];
4339                 }
4340         }
4341
4342         return 0;
4343 }
4344 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4345
4346 /*
4347  * IEEE80211 stack callback functions.
4348  */
4349 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4350                          u16 *iv16)
4351 {
4352         struct rt2x00_dev *rt2x00dev = hw->priv;
4353         struct mac_iveiv_entry iveiv_entry;
4354         u32 offset;
4355
4356         offset = MAC_IVEIV_ENTRY(hw_key_idx);
4357         rt2800_register_multiread(rt2x00dev, offset,
4358                                       &iveiv_entry, sizeof(iveiv_entry));
4359
4360         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4361         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
4362 }
4363 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
4364
4365 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4366 {
4367         struct rt2x00_dev *rt2x00dev = hw->priv;
4368         u32 reg;
4369         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4370
4371         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4372         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4373         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4374
4375         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4376         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4377         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4378
4379         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4380         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4381         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4382
4383         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4384         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4385         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4386
4387         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4388         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4389         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4390
4391         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4392         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4393         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4394
4395         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4396         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4397         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4398
4399         return 0;
4400 }
4401 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
4402
4403 int rt2800_conf_tx(struct ieee80211_hw *hw,
4404                    struct ieee80211_vif *vif, u16 queue_idx,
4405                    const struct ieee80211_tx_queue_params *params)
4406 {
4407         struct rt2x00_dev *rt2x00dev = hw->priv;
4408         struct data_queue *queue;
4409         struct rt2x00_field32 field;
4410         int retval;
4411         u32 reg;
4412         u32 offset;
4413
4414         /*
4415          * First pass the configuration through rt2x00lib, that will
4416          * update the queue settings and validate the input. After that
4417          * we are free to update the registers based on the value
4418          * in the queue parameter.
4419          */
4420         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
4421         if (retval)
4422                 return retval;
4423
4424         /*
4425          * We only need to perform additional register initialization
4426          * for WMM queues/
4427          */
4428         if (queue_idx >= 4)
4429                 return 0;
4430
4431         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
4432
4433         /* Update WMM TXOP register */
4434         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4435         field.bit_offset = (queue_idx & 1) * 16;
4436         field.bit_mask = 0xffff << field.bit_offset;
4437
4438         rt2800_register_read(rt2x00dev, offset, &reg);
4439         rt2x00_set_field32(&reg, field, queue->txop);
4440         rt2800_register_write(rt2x00dev, offset, reg);
4441
4442         /* Update WMM registers */
4443         field.bit_offset = queue_idx * 4;
4444         field.bit_mask = 0xf << field.bit_offset;
4445
4446         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4447         rt2x00_set_field32(&reg, field, queue->aifs);
4448         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4449
4450         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4451         rt2x00_set_field32(&reg, field, queue->cw_min);
4452         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4453
4454         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4455         rt2x00_set_field32(&reg, field, queue->cw_max);
4456         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4457
4458         /* Update EDCA registers */
4459         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4460
4461         rt2800_register_read(rt2x00dev, offset, &reg);
4462         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4463         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4464         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4465         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4466         rt2800_register_write(rt2x00dev, offset, reg);
4467
4468         return 0;
4469 }
4470 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4471
4472 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
4473 {
4474         struct rt2x00_dev *rt2x00dev = hw->priv;
4475         u64 tsf;
4476         u32 reg;
4477
4478         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4479         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4480         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4481         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4482
4483         return tsf;
4484 }
4485 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4486
4487 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4488                         enum ieee80211_ampdu_mlme_action action,
4489                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4490                         u8 buf_size)
4491 {
4492         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
4493         int ret = 0;
4494
4495         /*
4496          * Don't allow aggregation for stations the hardware isn't aware
4497          * of because tx status reports for frames to an unknown station
4498          * always contain wcid=255 and thus we can't distinguish between
4499          * multiple stations which leads to unwanted situations when the
4500          * hw reorders frames due to aggregation.
4501          */
4502         if (sta_priv->wcid < 0)
4503                 return 1;
4504
4505         switch (action) {
4506         case IEEE80211_AMPDU_RX_START:
4507         case IEEE80211_AMPDU_RX_STOP:
4508                 /*
4509                  * The hw itself takes care of setting up BlockAck mechanisms.
4510                  * So, we only have to allow mac80211 to nagotiate a BlockAck
4511                  * agreement. Once that is done, the hw will BlockAck incoming
4512                  * AMPDUs without further setup.
4513                  */
4514                 break;
4515         case IEEE80211_AMPDU_TX_START:
4516                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4517                 break;
4518         case IEEE80211_AMPDU_TX_STOP:
4519                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4520                 break;
4521         case IEEE80211_AMPDU_TX_OPERATIONAL:
4522                 break;
4523         default:
4524                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4525         }
4526
4527         return ret;
4528 }
4529 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4530
4531 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4532                       struct survey_info *survey)
4533 {
4534         struct rt2x00_dev *rt2x00dev = hw->priv;
4535         struct ieee80211_conf *conf = &hw->conf;
4536         u32 idle, busy, busy_ext;
4537
4538         if (idx != 0)
4539                 return -ENOENT;
4540
4541         survey->channel = conf->channel;
4542
4543         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4544         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4545         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4546
4547         if (idle || busy) {
4548                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4549                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
4550                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4551
4552                 survey->channel_time = (idle + busy) / 1000;
4553                 survey->channel_time_busy = busy / 1000;
4554                 survey->channel_time_ext_busy = busy_ext / 1000;
4555         }
4556
4557         return 0;
4558
4559 }
4560 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4561
4562 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4563 MODULE_VERSION(DRV_VERSION);
4564 MODULE_DESCRIPTION("Ralink RT2800 library");
4565 MODULE_LICENSE("GPL");