drivers/net/wireless/realtek/rtw89/mac.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 /* Copyright(c) 2019-2020  Realtek Corporation
   3  */
   4
   5 #include "cam.h"
   6 #include "chan.h"
   7 #include "debug.h"
   8 #include "fw.h"
   9 #include "mac.h"
  10 #include "pci.h"
  11 #include "ps.h"
  12 #include "reg.h"
  13 #include "util.h"
  14
  15 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = {
  16         [RTW89_MAC_MEM_AXIDMA]          = AXIDMA_BASE_ADDR,
  17         [RTW89_MAC_MEM_SHARED_BUF]      = SHARED_BUF_BASE_ADDR,
  18         [RTW89_MAC_MEM_DMAC_TBL]        = DMAC_TBL_BASE_ADDR,
  19         [RTW89_MAC_MEM_SHCUT_MACHDR]    = SHCUT_MACHDR_BASE_ADDR,
  20         [RTW89_MAC_MEM_STA_SCHED]       = STA_SCHED_BASE_ADDR,
  21         [RTW89_MAC_MEM_RXPLD_FLTR_CAM]  = RXPLD_FLTR_CAM_BASE_ADDR,
  22         [RTW89_MAC_MEM_SECURITY_CAM]    = SECURITY_CAM_BASE_ADDR,
  23         [RTW89_MAC_MEM_WOW_CAM]         = WOW_CAM_BASE_ADDR,
  24         [RTW89_MAC_MEM_CMAC_TBL]        = CMAC_TBL_BASE_ADDR,
  25         [RTW89_MAC_MEM_ADDR_CAM]        = ADDR_CAM_BASE_ADDR,
  26         [RTW89_MAC_MEM_BA_CAM]          = BA_CAM_BASE_ADDR,
  27         [RTW89_MAC_MEM_BCN_IE_CAM0]     = BCN_IE_CAM0_BASE_ADDR,
  28         [RTW89_MAC_MEM_BCN_IE_CAM1]     = BCN_IE_CAM1_BASE_ADDR,
  29         [RTW89_MAC_MEM_TXD_FIFO_0]      = TXD_FIFO_0_BASE_ADDR,
  30         [RTW89_MAC_MEM_TXD_FIFO_1]      = TXD_FIFO_1_BASE_ADDR,
  31         [RTW89_MAC_MEM_TXDATA_FIFO_0]   = TXDATA_FIFO_0_BASE_ADDR,
  32         [RTW89_MAC_MEM_TXDATA_FIFO_1]   = TXDATA_FIFO_1_BASE_ADDR,
  33         [RTW89_MAC_MEM_CPU_LOCAL]       = CPU_LOCAL_BASE_ADDR,
  34         [RTW89_MAC_MEM_BSSID_CAM]       = BSSID_CAM_BASE_ADDR,
  35         [RTW89_MAC_MEM_TXD_FIFO_0_V1]   = TXD_FIFO_0_BASE_ADDR_V1,
  36         [RTW89_MAC_MEM_TXD_FIFO_1_V1]   = TXD_FIFO_1_BASE_ADDR_V1,
  37 };
  38
  39 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset,
  40                                 u32 val, enum rtw89_mac_mem_sel sel)
  41 {
  42         const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
  43         u32 addr = mac->mem_base_addrs[sel] + offset;
  44
  45         rtw89_write32(rtwdev, mac->filter_model_addr, addr);
  46         rtw89_write32(rtwdev, mac->indir_access_addr, val);
  47 }
  48
  49 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset,
  50                               enum rtw89_mac_mem_sel sel)
  51 {
  52         const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
  53         u32 addr = mac->mem_base_addrs[sel] + offset;
  54
  55         rtw89_write32(rtwdev, mac->filter_model_addr, addr);
  56         return rtw89_read32(rtwdev, mac->indir_access_addr);
  57 }
  58
  59 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx,
  60                            enum rtw89_mac_hwmod_sel sel)
  61 {
  62         u32 val, r_val;
  63
  64         if (sel == RTW89_DMAC_SEL) {
  65                 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN);
  66                 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN);
  67         } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) {
  68                 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN);
  69                 val = B_AX_CMAC_EN;
  70         } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) {
  71                 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND);
  72                 val = B_AX_CMAC1_FEN;
  73         } else {
  74                 return -EINVAL;
  75         }
  76         if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD ||
  77             (val & r_val) != val)
  78                 return -EFAULT;
  79
  80         return 0;
  81 }
  82
  83 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val)
  84 {
  85         u8 lte_ctrl;
  86         int ret;
  87
  88         ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0,
  89                                 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);
  90         if (ret)
  91                 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");
  92
  93         rtw89_write32(rtwdev, R_AX_LTE_WDATA, val);
  94         rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset);
  95
  96         return ret;
  97 }
  98
  99 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val)
 100 {
 101         u8 lte_ctrl;
 102         int ret;
 103
 104         ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0,
 105                                 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);
 106         if (ret)
 107                 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");
 108
 109         rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset);
 110         *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA);
 111
 112         return ret;
 113 }
 114
 115 static
 116 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl)
 117 {
 118         u32 ctrl_reg, data_reg, ctrl_data;
 119         u32 val;
 120         int ret;
 121
 122         switch (ctrl->type) {
 123         case DLE_CTRL_TYPE_WDE:
 124                 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL;
 125                 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA;
 126                 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) |
 127                             FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) |
 128                             B_AX_WDE_DFI_ACTIVE;
 129                 break;
 130         case DLE_CTRL_TYPE_PLE:
 131                 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL;
 132                 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA;
 133                 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) |
 134                             FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) |
 135                             B_AX_PLE_DFI_ACTIVE;
 136                 break;
 137         default:
 138                 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type);
 139                 return -EINVAL;
 140         }
 141
 142         rtw89_write32(rtwdev, ctrl_reg, ctrl_data);
 143
 144         ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE),
 145                                        1, 1000, false, rtwdev, ctrl_reg);
 146         if (ret) {
 147                 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n",
 148                            ctrl_reg, ctrl_data);
 149                 return ret;
 150         }
 151
 152         ctrl->out_data = rtw89_read32(rtwdev, data_reg);
 153         return 0;
 154 }
 155
 156 static int dle_dfi_quota(struct rtw89_dev *rtwdev,
 157                          struct rtw89_mac_dle_dfi_quota *quota)
 158 {
 159         struct rtw89_mac_dle_dfi_ctrl ctrl;
 160         int ret;
 161
 162         ctrl.type = quota->dle_type;
 163         ctrl.target = DLE_DFI_TYPE_QUOTA;
 164         ctrl.addr = quota->qtaid;
 165         ret = dle_dfi_ctrl(rtwdev, &ctrl);
 166         if (ret) {
 167                 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret);
 168                 return ret;
 169         }
 170
 171         quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data);
 172         quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data);
 173         return 0;
 174 }
 175
 176 static int dle_dfi_qempty(struct rtw89_dev *rtwdev,
 177                           struct rtw89_mac_dle_dfi_qempty *qempty)
 178 {
 179         struct rtw89_mac_dle_dfi_ctrl ctrl;
 180         u32 ret;
 181
 182         ctrl.type = qempty->dle_type;
 183         ctrl.target = DLE_DFI_TYPE_QEMPTY;
 184         ctrl.addr = qempty->grpsel;
 185         ret = dle_dfi_ctrl(rtwdev, &ctrl);
 186         if (ret) {
 187                 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret);
 188                 return ret;
 189         }
 190
 191         qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data);
 192         return 0;
 193 }
 194
 195 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev)
 196 {
 197         rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ",
 198                    rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
 199         rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n",
 200                    rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
 201         rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ",
 202                    rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
 203         rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n",
 204                    rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
 205         rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ",
 206                    rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
 207         rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n",
 208                    rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
 209 }
 210
 211 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev)
 212 {
 213         struct rtw89_mac_dle_dfi_qempty qempty;
 214         struct rtw89_mac_dle_dfi_quota quota;
 215         struct rtw89_mac_dle_dfi_ctrl ctrl;
 216         u32 val, not_empty, i;
 217         int ret;
 218
 219         qempty.dle_type = DLE_CTRL_TYPE_PLE;
 220         qempty.grpsel = 0;
 221         qempty.qempty = ~(u32)0;
 222         ret = dle_dfi_qempty(rtwdev, &qempty);
 223         if (ret)
 224                 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
 225         else
 226                 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty);
 227
 228         for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) {
 229                 if (!(not_empty & BIT(0)))
 230                         continue;
 231                 ctrl.type = DLE_CTRL_TYPE_PLE;
 232                 ctrl.target = DLE_DFI_TYPE_QLNKTBL;
 233                 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) |
 234                             FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i);
 235                 ret = dle_dfi_ctrl(rtwdev, &ctrl);
 236                 if (ret)
 237                         rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
 238                 else
 239                         rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i,
 240                                    FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK,
 241                                              ctrl.out_data));
 242         }
 243
 244         quota.dle_type = DLE_CTRL_TYPE_PLE;
 245         quota.qtaid = 6;
 246         ret = dle_dfi_quota(rtwdev, &quota);
 247         if (ret)
 248                 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
 249         else
 250                 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n",
 251                            quota.rsv_pgnum, quota.use_pgnum);
 252
 253         val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG);
 254         rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n",
 255                    FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val));
 256         rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n",
 257                    FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val));
 258
 259         dump_err_status_dispatcher(rtwdev);
 260 }
 261
 262 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,
 263                                     enum mac_ax_err_info err)
 264 {
 265         u32 dbg, event;
 266
 267         dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO);
 268         event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg);
 269
 270         switch (event) {
 271         case MAC_AX_L0_TO_L1_RX_QTA_LOST:
 272                 rtw89_info(rtwdev, "quota lost!\n");
 273                 rtw89_mac_dump_qta_lost(rtwdev);
 274                 break;
 275         default:
 276                 break;
 277         }
 278 }
 279
 280 static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev)
 281 {
 282         const struct rtw89_chip_info *chip = rtwdev->chip;
 283         u32 dmac_err;
 284         int i, ret;
 285
 286         ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
 287         if (ret) {
 288                 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n");
 289                 return;
 290         }
 291
 292         dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
 293         rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err);
 294         rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n",
 295                    rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR));
 296
 297         if (dmac_err) {
 298                 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n",
 299                            rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1));
 300                 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n",
 301                            rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1));
 302                 if (chip->chip_id == RTL8852C) {
 303                         rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n",
 304                                    rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG));
 305                         rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n",
 306                                    rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG));
 307                         rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n",
 308                                    rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN));
 309                         rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n",
 310                                    rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS));
 311                 }
 312         }
 313
 314         if (dmac_err & B_AX_WDRLS_ERR_FLAG) {
 315                 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n",
 316                            rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR));
 317                 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n",
 318                            rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
 319                 if (chip->chip_id == RTL8852C)
 320                         rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
 321                                    rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1));
 322                 else
 323                         rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
 324                                    rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX));
 325         }
 326
 327         if (dmac_err & B_AX_WSEC_ERR_FLAG) {
 328                 if (chip->chip_id == RTL8852C) {
 329                         rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n",
 330                                    rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR));
 331                         rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n",
 332                                    rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG));
 333                         rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n",
 334                                    rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
 335                         rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n",
 336                                    rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
 337                         rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
 338                                    rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
 339                         rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n",
 340                                    rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
 341                         rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n",
 342                                    rtw89_read32(rtwdev, R_AX_SEC_DEBUG1));
 343                         rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n",
 344                                    rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
 345                         rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n",
 346                                    rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
 347
 348                         rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
 349                                            B_AX_DBG_SEL0, 0x8B);
 350                         rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
 351                                            B_AX_DBG_SEL1, 0x8B);
 352                         rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
 353                                            B_AX_SEL_0XC0_MASK, 1);
 354                         for (i = 0; i < 0x10; i++) {
 355                                 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
 356                                                    B_AX_SEC_DBG_PORT_FIELD_MASK, i);
 357                                 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n",
 358                                            i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2));
 359                         }
 360                 } else {
 361                         rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
 362                                    rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
 363                         rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n",
 364                                    rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
 365                         rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n",
 366                                    rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
 367                         rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
 368                                    rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
 369                         rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n",
 370                                    rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
 371                         rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n",
 372                                    rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
 373                         rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n",
 374                                    rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
 375                         rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n",
 376                                    rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
 377                         rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n",
 378                                    rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
 379                         rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n",
 380                                    rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
 381                 }
 382         }
 383
 384         if (dmac_err & B_AX_MPDU_ERR_FLAG) {
 385                 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n",
 386                            rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR));
 387                 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
 388                            rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
 389                 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n",
 390                            rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR));
 391                 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
 392                            rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
 393         }
 394
 395         if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) {
 396                 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n",
 397                            rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR));
 398                 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
 399                            rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
 400         }
 401
 402         if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) {
 403                 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n",
 404                            rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
 405                 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
 406                            rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
 407                 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n",
 408                            rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
 409                 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
 410                            rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
 411         }
 412
 413         if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) {
 414                 if (chip->chip_id == RTL8852C) {
 415                         rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n",
 416                                    rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR));
 417                         rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n",
 418                                    rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR));
 419                         rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n",
 420                                    rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR));
 421                         rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n",
 422                                    rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR));
 423                 } else {
 424                         rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
 425                                    rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
 426                         rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
 427                                    rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
 428                 }
 429         }
 430
 431         if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) {
 432                 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n",
 433                            rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
 434                 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
 435                            rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
 436                 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n",
 437                            rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
 438                 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
 439                            rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
 440                 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n",
 441                            rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0));
 442                 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n",
 443                            rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1));
 444                 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n",
 445                            rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2));
 446                 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n",
 447                            rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS));
 448                 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n",
 449                            rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0));
 450                 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n",
 451                            rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1));
 452                 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n",
 453                            rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2));
 454                 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
 455                            rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS));
 456                 if (chip->chip_id == RTL8852C) {
 457                         rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n",
 458                                    rtw89_read32(rtwdev, R_AX_RX_CTRL0));
 459                         rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n",
 460                                    rtw89_read32(rtwdev, R_AX_RX_CTRL1));
 461                         rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n",
 462                                    rtw89_read32(rtwdev, R_AX_RX_CTRL2));
 463                 } else {
 464                         rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
 465                                    rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
 466                         rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
 467                                    rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
 468                         rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
 469                                    rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
 470                 }
 471         }
 472
 473         if (dmac_err & B_AX_PKTIN_ERR_FLAG) {
 474                 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n",
 475                            rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
 476                 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n",
 477                            rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
 478         }
 479
 480         if (dmac_err & B_AX_DISPATCH_ERR_FLAG) {
 481                 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n",
 482                            rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
 483                 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
 484                            rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
 485                 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n",
 486                            rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
 487                 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
 488                            rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
 489                 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n",
 490                            rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
 491                 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
 492                            rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
 493         }
 494
 495         if (dmac_err & B_AX_BBRPT_ERR_FLAG) {
 496                 if (chip->chip_id == RTL8852C) {
 497                         rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n",
 498                                    rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR));
 499                         rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n",
 500                                    rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR));
 501                         rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
 502                                    rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
 503                         rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
 504                                    rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
 505                         rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
 506                                    rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
 507                         rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
 508                                    rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
 509                 } else {
 510                         rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
 511                                    rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
 512                         rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
 513                                    rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
 514                         rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
 515                                    rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
 516                         rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
 517                                    rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
 518                         rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
 519                                    rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
 520                 }
 521         }
 522
 523         if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) {
 524                 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n",
 525                            rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK));
 526                 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n",
 527                            rtw89_read32(rtwdev, R_AX_HAXI_IDCT));
 528         }
 529 }
 530
 531 static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev,
 532                                            u8 band)
 533 {
 534         const struct rtw89_chip_info *chip = rtwdev->chip;
 535         u32 offset = 0;
 536         u32 cmac_err;
 537         int ret;
 538
 539         ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL);
 540         if (ret) {
 541                 if (band)
 542                         rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n");
 543                 else
 544                         rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n");
 545                 return;
 546         }
 547
 548         if (band)
 549                 offset = RTW89_MAC_AX_BAND_REG_OFFSET;
 550
 551         cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset);
 552         rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band,
 553                    rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset));
 554         rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band,
 555                    rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset));
 556         rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band,
 557                    rtw89_read32(rtwdev, R_AX_CK_EN + offset));
 558
 559         if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) {
 560                 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band,
 561                            rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset));
 562                 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band,
 563                            rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset));
 564         }
 565
 566         if (cmac_err & B_AX_PTCL_TOP_ERR_IND) {
 567                 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band,
 568                            rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset));
 569                 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band,
 570                            rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset));
 571         }
 572
 573         if (cmac_err & B_AX_DMA_TOP_ERR_IND) {
 574                 if (chip->chip_id == RTL8852C) {
 575                         rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band,
 576                                    rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset));
 577                         rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band,
 578                                    rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset));
 579                 } else {
 580                         rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band,
 581                                    rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset));
 582                 }
 583         }
 584
 585         if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) {
 586                 if (chip->chip_id == RTL8852C) {
 587                         rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band,
 588                                    rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset));
 589                         rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
 590                                    rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
 591                 } else {
 592                         rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
 593                                    rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
 594                 }
 595         }
 596
 597         if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
 598                 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band,
 599                            rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset));
 600                 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band,
 601                            rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset));
 602         }
 603
 604         if (cmac_err & B_AX_WMAC_TX_ERR_IND) {
 605                 if (chip->chip_id == RTL8852C) {
 606                         rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band,
 607                                    rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset));
 608                         rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band,
 609                                    rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset));
 610                 } else {
 611                         rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band,
 612                                    rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset));
 613                 }
 614                 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band,
 615                            rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset));
 616         }
 617
 618         rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band,
 619                    rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset));
 620 }
 621
 622 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev,
 623                                       enum mac_ax_err_info err)
 624 {
 625         if (err != MAC_AX_ERR_L1_ERR_DMAC &&
 626             err != MAC_AX_ERR_L0_PROMOTE_TO_L1 &&
 627             err != MAC_AX_ERR_L0_ERR_CMAC0 &&
 628             err != MAC_AX_ERR_L0_ERR_CMAC1 &&
 629             err != MAC_AX_ERR_RXI300)
 630                 return;
 631
 632         rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
 633         rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n",
 634                    rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));
 635
 636         rtw89_mac_dump_dmac_err_status(rtwdev);
 637         rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0);
 638         if (rtwdev->dbcc_en)
 639                 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1);
 640
 641         rtwdev->hci.ops->dump_err_status(rtwdev);
 642
 643         if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1)
 644                 rtw89_mac_dump_l0_to_l1(rtwdev, err);
 645
 646         rtw89_info(rtwdev, "<---\n");
 647 }
 648
 649 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err)
 650 {
 651         struct rtw89_ser *ser = &rtwdev->ser;
 652         u32 dmac_err, imr, isr;
 653         int ret;
 654
 655         if (rtwdev->chip->chip_id == RTL8852C) {
 656                 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
 657                 if (ret)
 658                         return true;
 659
 660                 if (err == MAC_AX_ERR_L1_ERR_DMAC) {
 661                         dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
 662                         imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR);
 663                         isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR);
 664
 665                         if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) &&
 666                             ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) {
 667                                 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags);
 668                                 return true;
 669                         }
 670                 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) {
 671                         if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags))
 672                                 return true;
 673                 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) {
 674                         if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags))
 675                                 return true;
 676                 }
 677         }
 678
 679         return false;
 680 }
 681
 682 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev)
 683 {
 684         u32 err, err_scnr;
 685         int ret;
 686
 687         ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000,
 688                                 false, rtwdev, R_AX_HALT_C2H_CTRL);
 689         if (ret) {
 690                 rtw89_warn(rtwdev, "Polling FW err status fail\n");
 691                 return ret;
 692         }
 693
 694         err = rtw89_read32(rtwdev, R_AX_HALT_C2H);
 695         rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
 696
 697         err_scnr = RTW89_ERROR_SCENARIO(err);
 698         if (err_scnr == RTW89_WCPU_CPU_EXCEPTION)
 699                 err = MAC_AX_ERR_CPU_EXCEPTION;
 700         else if (err_scnr == RTW89_WCPU_ASSERTION)
 701                 err = MAC_AX_ERR_ASSERTION;
 702         else if (err_scnr == RTW89_RXI300_ERROR)
 703                 err = MAC_AX_ERR_RXI300;
 704
 705         if (rtw89_mac_suppress_log(rtwdev, err))
 706                 return err;
 707
 708         rtw89_fw_st_dbg_dump(rtwdev);
 709         rtw89_mac_dump_err_status(rtwdev, err);
 710
 711         return err;
 712 }
 713 EXPORT_SYMBOL(rtw89_mac_get_err_status);
 714
 715 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err)
 716 {
 717         struct rtw89_ser *ser = &rtwdev->ser;
 718         u32 halt;
 719         int ret = 0;
 720
 721         if (err > MAC_AX_SET_ERR_MAX) {
 722                 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err);
 723                 return -EINVAL;
 724         }
 725
 726         ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000,
 727                                 100000, false, rtwdev, R_AX_HALT_H2C_CTRL);
 728         if (ret) {
 729                 rtw89_err(rtwdev, "FW doesn't receive previous msg\n");
 730                 return -EFAULT;
 731         }
 732
 733         rtw89_write32(rtwdev, R_AX_HALT_H2C, err);
 734
 735         if (ser->prehandle_l1 &&
 736             (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN))
 737                 return 0;
 738
 739         rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER);
 740
 741         return 0;
 742 }
 743 EXPORT_SYMBOL(rtw89_mac_set_err_status);
 744
 745 static int hfc_reset_param(struct rtw89_dev *rtwdev)
 746 {
 747         struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
 748         struct rtw89_hfc_param_ini param_ini = {NULL};
 749         u8 qta_mode = rtwdev->mac.dle_info.qta_mode;
 750
 751         switch (rtwdev->hci.type) {
 752         case RTW89_HCI_TYPE_PCIE:
 753                 param_ini = rtwdev->chip->hfc_param_ini[qta_mode];
 754                 param->en = 0;
 755                 break;
 756         default:
 757                 return -EINVAL;
 758         }
 759
 760         if (param_ini.pub_cfg)
 761                 param->pub_cfg = *param_ini.pub_cfg;
 762
 763         if (param_ini.prec_cfg)
 764                 param->prec_cfg = *param_ini.prec_cfg;
 765
 766         if (param_ini.ch_cfg)
 767                 param->ch_cfg = param_ini.ch_cfg;
 768
 769         memset(&param->ch_info, 0, sizeof(param->ch_info));
 770         memset(&param->pub_info, 0, sizeof(param->pub_info));
 771         param->mode = param_ini.mode;
 772
 773         return 0;
 774 }
 775
 776 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch)
 777 {
 778         struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
 779         const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg;
 780         const struct rtw89_hfc_pub_cfg *pub_cfg = &param->pub_cfg;
 781         const struct rtw89_hfc_prec_cfg *prec_cfg = &param->prec_cfg;
 782
 783         if (ch >= RTW89_DMA_CH_NUM)
 784                 return -EINVAL;
 785
 786         if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) ||
 787             ch_cfg[ch].max > pub_cfg->pub_max)
 788                 return -EINVAL;
 789         if (ch_cfg[ch].grp >= grp_num)
 790                 return -EINVAL;
 791
 792         return 0;
 793 }
 794
 795 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev)
 796 {
 797         struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
 798         const struct rtw89_hfc_pub_cfg *cfg = &param->pub_cfg;
 799         struct rtw89_hfc_pub_info *info = &param->pub_info;
 800
 801         if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) {
 802                 if (rtwdev->chip->chip_id == RTL8852A)
 803                         return 0;
 804                 else
 805                         return -EFAULT;
 806         }
 807
 808         return 0;
 809 }
 810
 811 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev)
 812 {
 813         struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
 814         const struct rtw89_hfc_pub_cfg *pub_cfg = &param->pub_cfg;
 815
 816         if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max)
 817                 return -EFAULT;
 818
 819         return 0;
 820 }
 821
 822 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch)
 823 {
 824         const struct rtw89_chip_info *chip = rtwdev->chip;
 825         const struct rtw89_page_regs *regs = chip->page_regs;
 826         struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
 827         const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg;
 828         int ret = 0;
 829         u32 val = 0;
 830
 831         ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
 832         if (ret)
 833                 return ret;
 834
 835         ret = hfc_ch_cfg_chk(rtwdev, ch);
 836         if (ret)
 837                 return ret;
 838
 839         if (ch > RTW89_DMA_B1HI)
 840                 return -EINVAL;
 841
 842         val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) |
 843               u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) |
 844               (cfg[ch].grp ? B_AX_GRP : 0);
 845         rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val);
 846
 847         return 0;
 848 }
 849
 850 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch)
 851 {
 852         const struct rtw89_chip_info *chip = rtwdev->chip;
 853         const struct rtw89_page_regs *regs = chip->page_regs;
 854         struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
 855         struct rtw89_hfc_ch_info *info = param->ch_info;
 856         const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg;
 857         u32 val;
 858         u32 ret;
 859
 860         ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
 861         if (ret)
 862                 return ret;
 863
 864         if (ch > RTW89_DMA_H2C)
 865                 return -EINVAL;
 866
 867         val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4);
 868         info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK);
 869         if (ch < RTW89_DMA_H2C)
 870                 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK);
 871         else
 872                 info[ch].used = cfg[ch].min - info[ch].aval;
 873
 874         return 0;
 875 }
 876
 877 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev)
 878 {
 879         const struct rtw89_chip_info *chip = rtwdev->chip;
 880         const struct rtw89_page_regs *regs = chip->page_regs;
 881         const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg;
 882         u32 val;
 883         int ret;
 884
 885         ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
 886         if (ret)
 887                 return ret;
 888
 889         ret = hfc_pub_cfg_chk(rtwdev);
 890         if (ret)
 891                 return ret;
 892
 893         val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) |
 894               u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK);
 895         rtw89_write32(rtwdev, regs->pub_page_ctrl1, val);
 896
 897         val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK);
 898         rtw89_write32(rtwdev, regs->wp_page_ctrl2, val);
 899
 900         return 0;
 901 }
 902
 903 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev)
 904 {
 905         const struct rtw89_chip_info *chip = rtwdev->chip;
 906         const struct rtw89_page_regs *regs = chip->page_regs;
 907         struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
 908         struct rtw89_hfc_pub_cfg *pub_cfg = &param->pub_cfg;
 909         struct rtw89_hfc_prec_cfg *prec_cfg = &param->prec_cfg;
 910         struct rtw89_hfc_pub_info *info = &param->pub_info;
 911         u32 val;
 912         int ret;
 913
 914         ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
 915         if (ret)
 916                 return ret;
 917
 918         val = rtw89_read32(rtwdev, regs->pub_page_info1);
 919         info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK);
 920         info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK);
 921         val = rtw89_read32(rtwdev, regs->pub_page_info3);
 922         info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK);
 923         info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK);
 924         info->pub_aval =
 925                 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2),
 926                              B_AX_PUB_AVAL_PG_MASK);
 927         info->wp_aval =
 928                 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1),
 929                              B_AX_WP_AVAL_PG_MASK);
 930
 931         val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
 932         param->en = val & B_AX_HCI_FC_EN ? 1 : 0;
 933         param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0;
 934         param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK);
 935         prec_cfg->ch011_full_cond =
 936                 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK);
 937         prec_cfg->h2c_full_cond =
 938                 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK);
 939         prec_cfg->wp_ch07_full_cond =
 940                 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK);
 941         prec_cfg->wp_ch811_full_cond =
 942                 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK);
 943
 944         val = rtw89_read32(rtwdev, regs->ch_page_ctrl);
 945         prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK);
 946         prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK);
 947
 948         val = rtw89_read32(rtwdev, regs->pub_page_ctrl2);
 949         pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK);
 950
 951         val = rtw89_read32(rtwdev, regs->wp_page_ctrl1);
 952         prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK);
 953         prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK);
 954
 955         val = rtw89_read32(rtwdev, regs->wp_page_ctrl2);
 956         pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK);
 957
 958         val = rtw89_read32(rtwdev, regs->pub_page_ctrl1);
 959         pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK);
 960         pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK);
 961
 962         ret = hfc_pub_info_chk(rtwdev);
 963         if (param->en && ret)
 964                 return ret;
 965
 966         return 0;
 967 }
 968
 969 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev)
 970 {
 971         const struct rtw89_chip_info *chip = rtwdev->chip;
 972         const struct rtw89_page_regs *regs = chip->page_regs;
 973         struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
 974         const struct rtw89_hfc_prec_cfg *prec_cfg = &param->prec_cfg;
 975         u32 val;
 976
 977         val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK);
 978         rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
 979
 980         rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl,
 981                            B_AX_HCI_FC_CH12_FULL_COND_MASK,
 982                            prec_cfg->h2c_full_cond);
 983 }
 984
 985 static void hfc_mix_cfg(struct rtw89_dev *rtwdev)
 986 {
 987         const struct rtw89_chip_info *chip = rtwdev->chip;
 988         const struct rtw89_page_regs *regs = chip->page_regs;
 989         struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
 990         const struct rtw89_hfc_pub_cfg *pub_cfg = &param->pub_cfg;
 991         const struct rtw89_hfc_prec_cfg *prec_cfg = &param->prec_cfg;
 992         u32 val;
 993
 994         val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) |
 995               u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK);
 996         rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
 997
 998         val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK);
 999         rtw89_write32(rtwdev, regs->pub_page_ctrl2, val);
1000
1001         val = u32_encode_bits(prec_cfg->wp_ch07_prec,
1002                               B_AX_PREC_PAGE_WP_CH07_MASK) |
1003               u32_encode_bits(prec_cfg->wp_ch811_prec,
1004                               B_AX_PREC_PAGE_WP_CH811_MASK);
1005         rtw89_write32(rtwdev, regs->wp_page_ctrl1, val);
1006
1007         val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl),
1008                                param->mode, B_AX_HCI_FC_MODE_MASK);
1009         val = u32_replace_bits(val, prec_cfg->ch011_full_cond,
1010                                B_AX_HCI_FC_WD_FULL_COND_MASK);
1011         val = u32_replace_bits(val, prec_cfg->h2c_full_cond,
1012                                B_AX_HCI_FC_CH12_FULL_COND_MASK);
1013         val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond,
1014                                B_AX_HCI_FC_WP_CH07_FULL_COND_MASK);
1015         val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond,
1016                                B_AX_HCI_FC_WP_CH811_FULL_COND_MASK);
1017         rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1018 }
1019
1020 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en)
1021 {
1022         const struct rtw89_chip_info *chip = rtwdev->chip;
1023         const struct rtw89_page_regs *regs = chip->page_regs;
1024         struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1025         u32 val;
1026
1027         val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
1028         param->en = en;
1029         param->h2c_en = h2c_en;
1030         val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN);
1031         val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) :
1032                          (val & ~B_AX_HCI_FC_CH12_EN);
1033         rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1034 }
1035
1036 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en)
1037 {
1038         const struct rtw89_chip_info *chip = rtwdev->chip;
1039         u32 dma_ch_mask = chip->dma_ch_mask;
1040         u8 ch;
1041         u32 ret = 0;
1042
1043         if (reset)
1044                 ret = hfc_reset_param(rtwdev);
1045         if (ret)
1046                 return ret;
1047
1048         ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1049         if (ret)
1050                 return ret;
1051
1052         hfc_func_en(rtwdev, false, false);
1053
1054         if (!en && h2c_en) {
1055                 hfc_h2c_cfg(rtwdev);
1056                 hfc_func_en(rtwdev, en, h2c_en);
1057                 return ret;
1058         }
1059
1060         for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) {
1061                 if (dma_ch_mask & BIT(ch))
1062                         continue;
1063                 ret = hfc_ch_ctrl(rtwdev, ch);
1064                 if (ret)
1065                         return ret;
1066         }
1067
1068         ret = hfc_pub_ctrl(rtwdev);
1069         if (ret)
1070                 return ret;
1071
1072         hfc_mix_cfg(rtwdev);
1073         if (en || h2c_en) {
1074                 hfc_func_en(rtwdev, en, h2c_en);
1075                 udelay(10);
1076         }
1077         for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) {
1078                 if (dma_ch_mask & BIT(ch))
1079                         continue;
1080                 ret = hfc_upd_ch_info(rtwdev, ch);
1081                 if (ret)
1082                         return ret;
1083         }
1084         ret = hfc_upd_mix_info(rtwdev);
1085
1086         return ret;
1087 }
1088
1089 #define PWR_POLL_CNT    2000
1090 static int pwr_cmd_poll(struct rtw89_dev *rtwdev,
1091                         const struct rtw89_pwr_cfg *cfg)
1092 {
1093         u8 val = 0;
1094         int ret;
1095         u32 addr = cfg->base == PWR_INTF_MSK_SDIO ?
1096                    cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr;
1097
1098         ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk),
1099                                 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr);
1100
1101         if (!ret)
1102                 return 0;
1103
1104         rtw89_warn(rtwdev, "[ERR] Polling timeout\n");
1105         rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr);
1106         rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val);
1107
1108         return -EBUSY;
1109 }
1110
1111 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk,
1112                                  u8 intf_msk, const struct rtw89_pwr_cfg *cfg)
1113 {
1114         const struct rtw89_pwr_cfg *cur_cfg;
1115         u32 addr;
1116         u8 val;
1117
1118         for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) {
1119                 if (!(cur_cfg->intf_msk & intf_msk) ||
1120                     !(cur_cfg->cv_msk & cv_msk))
1121                         continue;
1122
1123                 switch (cur_cfg->cmd) {
1124                 case PWR_CMD_WRITE:
1125                         addr = cur_cfg->addr;
1126
1127                         if (cur_cfg->base == PWR_BASE_SDIO)
1128                                 addr |= SDIO_LOCAL_BASE_ADDR;
1129
1130                         val = rtw89_read8(rtwdev, addr);
1131                         val &= ~(cur_cfg->msk);
1132                         val |= (cur_cfg->val & cur_cfg->msk);
1133
1134                         rtw89_write8(rtwdev, addr, val);
1135                         break;
1136                 case PWR_CMD_POLL:
1137                         if (pwr_cmd_poll(rtwdev, cur_cfg))
1138                                 return -EBUSY;
1139                         break;
1140                 case PWR_CMD_DELAY:
1141                         if (cur_cfg->val == PWR_DELAY_US)
1142                                 udelay(cur_cfg->addr);
1143                         else
1144                                 fsleep(cur_cfg->addr * 1000);
1145                         break;
1146                 default:
1147                         return -EINVAL;
1148                 }
1149         }
1150
1151         return 0;
1152 }
1153
1154 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev,
1155                              const struct rtw89_pwr_cfg * const *cfg_seq)
1156 {
1157         int ret;
1158
1159         for (; *cfg_seq; cfg_seq++) {
1160                 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv),
1161                                             PWR_INTF_MSK_PCIE, *cfg_seq);
1162                 if (ret)
1163                         return -EBUSY;
1164         }
1165
1166         return 0;
1167 }
1168
1169 static enum rtw89_rpwm_req_pwr_state
1170 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev)
1171 {
1172         enum rtw89_rpwm_req_pwr_state state;
1173
1174         switch (rtwdev->ps_mode) {
1175         case RTW89_PS_MODE_RFOFF:
1176                 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF;
1177                 break;
1178         case RTW89_PS_MODE_CLK_GATED:
1179                 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED;
1180                 break;
1181         case RTW89_PS_MODE_PWR_GATED:
1182                 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED;
1183                 break;
1184         default:
1185                 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE;
1186                 break;
1187         }
1188         return state;
1189 }
1190
1191 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev,
1192                                 enum rtw89_rpwm_req_pwr_state req_pwr_state,
1193                                 bool notify_wake)
1194 {
1195         u16 request;
1196
1197         spin_lock_bh(&rtwdev->rpwm_lock);
1198
1199         request = rtw89_read16(rtwdev, R_AX_RPWM);
1200         request ^= request | PS_RPWM_TOGGLE;
1201         request |= req_pwr_state;
1202
1203         if (notify_wake) {
1204                 request |= PS_RPWM_NOTIFY_WAKE;
1205         } else {
1206                 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) &
1207                                             RPWM_SEQ_NUM_MAX;
1208                 request |= FIELD_PREP(PS_RPWM_SEQ_NUM,
1209                                       rtwdev->mac.rpwm_seq_num);
1210
1211                 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED)
1212                         request |= PS_RPWM_ACK;
1213         }
1214         rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request);
1215
1216         spin_unlock_bh(&rtwdev->rpwm_lock);
1217 }
1218
1219 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev,
1220                                       enum rtw89_rpwm_req_pwr_state req_pwr_state)
1221 {
1222         bool request_deep_mode;
1223         bool in_deep_mode;
1224         u8 rpwm_req_num;
1225         u8 cpwm_rsp_seq;
1226         u8 cpwm_seq;
1227         u8 cpwm_status;
1228
1229         if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED)
1230                 request_deep_mode = true;
1231         else
1232                 request_deep_mode = false;
1233
1234         if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K))
1235                 in_deep_mode = true;
1236         else
1237                 in_deep_mode = false;
1238
1239         if (request_deep_mode != in_deep_mode)
1240                 return -EPERM;
1241
1242         if (request_deep_mode)
1243                 return 0;
1244
1245         rpwm_req_num = rtwdev->mac.rpwm_seq_num;
1246         cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr,
1247                                          PS_CPWM_RSP_SEQ_NUM);
1248
1249         if (rpwm_req_num != cpwm_rsp_seq)
1250                 return -EPERM;
1251
1252         rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) &
1253                                     CPWM_SEQ_NUM_MAX;
1254
1255         cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM);
1256         if (cpwm_seq != rtwdev->mac.cpwm_seq_num)
1257                 return -EPERM;
1258
1259         cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE);
1260         if (cpwm_status != req_pwr_state)
1261                 return -EPERM;
1262
1263         return 0;
1264 }
1265
1266 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter)
1267 {
1268         enum rtw89_rpwm_req_pwr_state state;
1269         unsigned long delay = enter ? 10 : 150;
1270         int ret;
1271         int i;
1272
1273         if (enter)
1274                 state = rtw89_mac_get_req_pwr_state(rtwdev);
1275         else
1276                 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE;
1277
1278         for (i = 0; i < RPWM_TRY_CNT; i++) {
1279                 rtw89_mac_send_rpwm(rtwdev, state, false);
1280                 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret,
1281                                                !ret, delay, 15000, false,
1282                                                rtwdev, state);
1283                 if (!ret)
1284                         break;
1285
1286                 if (i == RPWM_TRY_CNT - 1)
1287                         rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n",
1288                                   enter ? "entering" : "leaving");
1289                 else
1290                         rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
1291                                     "%d time firmware failed to ack for %s ps mode\n",
1292                                     i + 1, enter ? "entering" : "leaving");
1293         }
1294 }
1295
1296 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev)
1297 {
1298         enum rtw89_rpwm_req_pwr_state state;
1299
1300         state = rtw89_mac_get_req_pwr_state(rtwdev);
1301         rtw89_mac_send_rpwm(rtwdev, state, true);
1302 }
1303
1304 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on)
1305 {
1306 #define PWR_ACT 1
1307         const struct rtw89_chip_info *chip = rtwdev->chip;
1308         const struct rtw89_pwr_cfg * const *cfg_seq;
1309         int (*cfg_func)(struct rtw89_dev *rtwdev);
1310         int ret;
1311         u8 val;
1312
1313         if (on) {
1314                 cfg_seq = chip->pwr_on_seq;
1315                 cfg_func = chip->ops->pwr_on_func;
1316         } else {
1317                 cfg_seq = chip->pwr_off_seq;
1318                 cfg_func = chip->ops->pwr_off_func;
1319         }
1320
1321         if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
1322                 __rtw89_leave_ps_mode(rtwdev);
1323
1324         val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK);
1325         if (on && val == PWR_ACT) {
1326                 rtw89_err(rtwdev, "MAC has already powered on\n");
1327                 return -EBUSY;
1328         }
1329
1330         ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq);
1331         if (ret)
1332                 return ret;
1333
1334         if (on) {
1335                 set_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1336                 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR);
1337         } else {
1338                 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1339                 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
1340                 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR);
1341                 rtw89_set_entity_state(rtwdev, false);
1342         }
1343
1344         return 0;
1345 #undef PWR_ACT
1346 }
1347
1348 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev)
1349 {
1350         rtw89_mac_power_switch(rtwdev, false);
1351 }
1352
1353 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
1354 {
1355         u32 func_en = 0;
1356         u32 ck_en = 0;
1357         u32 c1pc_en = 0;
1358         u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1};
1359         u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1};
1360
1361         func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
1362                         B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN |
1363                         B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN |
1364                         B_AX_CMAC_CRPRT;
1365         ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN |
1366                       B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN |
1367                       B_AX_RMAC_CKEN;
1368         c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN |
1369                         B_AX_R_SYM_WLCMAC1_P1_PC_EN |
1370                         B_AX_R_SYM_WLCMAC1_P2_PC_EN |
1371                         B_AX_R_SYM_WLCMAC1_P3_PC_EN |
1372                         B_AX_R_SYM_WLCMAC1_P4_PC_EN;
1373
1374         if (en) {
1375                 if (mac_idx == RTW89_MAC_1) {
1376                         rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en);
1377                         rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1378                                           B_AX_R_SYM_ISO_CMAC12PP);
1379                         rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1380                                           B_AX_CMAC1_FEN);
1381                 }
1382                 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en);
1383                 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en);
1384         } else {
1385                 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en);
1386                 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en);
1387                 if (mac_idx == RTW89_MAC_1) {
1388                         rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1389                                           B_AX_CMAC1_FEN);
1390                         rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1391                                           B_AX_R_SYM_ISO_CMAC12PP);
1392                         rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en);
1393                 }
1394         }
1395
1396         return 0;
1397 }
1398
1399 static int dmac_func_en(struct rtw89_dev *rtwdev)
1400 {
1401         enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1402         u32 val32;
1403
1404         if (chip_id == RTL8852C)
1405                 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN |
1406                          B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN |
1407                          B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN |
1408                          B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN |
1409                          B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN |
1410                          B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN |
1411                          B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN);
1412         else
1413                 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN |
1414                          B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN |
1415                          B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN |
1416                          B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN |
1417                          B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN |
1418                          B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN |
1419                          B_AX_DMAC_CRPRT);
1420         rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32);
1421
1422         val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN |
1423                  B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN |
1424                  B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN |
1425                  B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN);
1426         rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32);
1427
1428         return 0;
1429 }
1430
1431 static int chip_func_en(struct rtw89_dev *rtwdev)
1432 {
1433         enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1434
1435         if (chip_id == RTL8852A || chip_id == RTL8852B)
1436                 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
1437                                   B_AX_OCP_L1_MASK);
1438
1439         return 0;
1440 }
1441
1442 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev)
1443 {
1444         int ret;
1445
1446         ret = dmac_func_en(rtwdev);
1447         if (ret)
1448                 return ret;
1449
1450         ret = cmac_func_en(rtwdev, 0, true);
1451         if (ret)
1452                 return ret;
1453
1454         ret = chip_func_en(rtwdev);
1455         if (ret)
1456                 return ret;
1457
1458         return ret;
1459 }
1460
1461 const struct rtw89_mac_size_set rtw89_mac_size = {
1462         .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0},
1463         /* PCIE 64 */
1464         .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,},
1465         /* DLFW */
1466         .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,},
1467         /* PCIE 64 */
1468         .wde_size6 = {RTW89_WDE_PG_64, 512, 0,},
1469         /* 8852B PCIE SCC */
1470         .wde_size7 = {RTW89_WDE_PG_64, 510, 2,},
1471         /* DLFW */
1472         .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,},
1473         /* 8852C DLFW */
1474         .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,},
1475         /* 8852C PCIE SCC */
1476         .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,},
1477         /* PCIE */
1478         .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,},
1479         /* DLFW */
1480         .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,},
1481         /* PCIE 64 */
1482         .ple_size6 = {RTW89_PLE_PG_128, 496, 16,},
1483         /* DLFW */
1484         .ple_size8 = {RTW89_PLE_PG_128, 64, 960,},
1485         /* 8852C DLFW */
1486         .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,},
1487         /* 8852C PCIE SCC */
1488         .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,},
1489         /* PCIE 64 */
1490         .wde_qt0 = {3792, 196, 0, 107,},
1491         /* DLFW */
1492         .wde_qt4 = {0, 0, 0, 0,},
1493         /* PCIE 64 */
1494         .wde_qt6 = {448, 48, 0, 16,},
1495         /* 8852B PCIE SCC */
1496         .wde_qt7 = {446, 48, 0, 16,},
1497         /* 8852C DLFW */
1498         .wde_qt17 = {0, 0, 0,  0,},
1499         /* 8852C PCIE SCC */
1500         .wde_qt18 = {3228, 60, 0, 40,},
1501         /* PCIE SCC */
1502         .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,},
1503         /* PCIE SCC */
1504         .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,},
1505         /* DLFW */
1506         .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,},
1507         /* PCIE 64 */
1508         .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,},
1509         /* DLFW 52C */
1510         .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,},
1511         /* DLFW 52C */
1512         .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,},
1513         /* 8852C PCIE SCC */
1514         .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,},
1515         /* 8852C PCIE SCC */
1516         .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,},
1517         /* PCIE 64 */
1518         .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,},
1519         /* 8852A PCIE WOW */
1520         .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,},
1521         /* 8852B PCIE WOW */
1522         .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,},
1523         /* 8851B PCIE WOW */
1524         .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,},
1525 };
1526 EXPORT_SYMBOL(rtw89_mac_size);
1527
1528 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev,
1529                                                    enum rtw89_qta_mode mode)
1530 {
1531         struct rtw89_mac_info *mac = &rtwdev->mac;
1532         const struct rtw89_dle_mem *cfg;
1533
1534         cfg = &rtwdev->chip->dle_mem[mode];
1535         if (!cfg)
1536                 return NULL;
1537
1538         if (cfg->mode != mode) {
1539                 rtw89_warn(rtwdev, "qta mode unmatch!\n");
1540                 return NULL;
1541         }
1542
1543         mac->dle_info.ple_pg_size = cfg->ple_size->pge_size;
1544         mac->dle_info.qta_mode = mode;
1545         mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma;
1546         mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma;
1547
1548         return cfg;
1549 }
1550
1551 static bool mac_is_txq_empty(struct rtw89_dev *rtwdev)
1552 {
1553         struct rtw89_mac_dle_dfi_qempty qempty;
1554         u32 qnum, qtmp, val32, msk32;
1555         int i, j, ret;
1556
1557         qnum = rtwdev->chip->wde_qempty_acq_num;
1558         qempty.dle_type = DLE_CTRL_TYPE_WDE;
1559
1560         for (i = 0; i < qnum; i++) {
1561                 qempty.grpsel = i;
1562                 ret = dle_dfi_qempty(rtwdev, &qempty);
1563                 if (ret) {
1564                         rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret);
1565                         return false;
1566                 }
1567                 qtmp = qempty.qempty;
1568                 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) {
1569                         val32 = FIELD_GET(QEMP_ACQ_GRP_QSEL_MASK, qtmp);
1570                         if (val32 != QEMP_ACQ_GRP_QSEL_MASK)
1571                                 return false;
1572                         qtmp >>= QEMP_ACQ_GRP_QSEL_SH;
1573                 }
1574         }
1575
1576         qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel;
1577         ret = dle_dfi_qempty(rtwdev, &qempty);
1578         if (ret) {
1579                 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret);
1580                 return false;
1581         }
1582         msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ;
1583         if ((qempty.qempty & msk32) != msk32)
1584                 return false;
1585
1586         if (rtwdev->dbcc_en) {
1587                 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ;
1588                 if ((qempty.qempty & msk32) != msk32)
1589                         return false;
1590         }
1591
1592         msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU |
1593                 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C |
1594                 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX |
1595                 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO |
1596                 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF |
1597                 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN |
1598                 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL |
1599                 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX;
1600         val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0);
1601
1602         return (val32 & msk32) == msk32;
1603 }
1604
1605 static inline u32 dle_used_size(const struct rtw89_dle_size *wde,
1606                                 const struct rtw89_dle_size *ple)
1607 {
1608         return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) +
1609                ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num);
1610 }
1611
1612 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev,
1613                                   enum rtw89_qta_mode mode)
1614 {
1615         u32 size = rtwdev->chip->fifo_size;
1616
1617         if (mode == RTW89_QTA_SCC)
1618                 size -= rtwdev->chip->dle_scc_rsvd_size;
1619
1620         return size;
1621 }
1622
1623 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable)
1624 {
1625         if (enable)
1626                 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
1627                                   B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN);
1628         else
1629                 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN,
1630                                   B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN);
1631 }
1632
1633 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable)
1634 {
1635         u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN;
1636
1637         if (enable) {
1638                 if (rtwdev->chip->chip_id == RTL8851B)
1639                         val |= B_AX_AXIDMA_CLK_EN;
1640                 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val);
1641         } else {
1642                 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val);
1643         }
1644 }
1645
1646 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg)
1647 {
1648         const struct rtw89_dle_size *size_cfg;
1649         u32 val;
1650         u8 bound = 0;
1651
1652         val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG);
1653         size_cfg = cfg->wde_size;
1654
1655         switch (size_cfg->pge_size) {
1656         default:
1657         case RTW89_WDE_PG_64:
1658                 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64,
1659                                        B_AX_WDE_PAGE_SEL_MASK);
1660                 break;
1661         case RTW89_WDE_PG_128:
1662                 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128,
1663                                        B_AX_WDE_PAGE_SEL_MASK);
1664                 break;
1665         case RTW89_WDE_PG_256:
1666                 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n");
1667                 return -EINVAL;
1668         }
1669
1670         val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK);
1671         val = u32_replace_bits(val, size_cfg->lnk_pge_num,
1672                                B_AX_WDE_FREE_PAGE_NUM_MASK);
1673         rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val);
1674
1675         val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG);
1676         bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num)
1677                                 * size_cfg->pge_size / DLE_BOUND_UNIT;
1678         size_cfg = cfg->ple_size;
1679
1680         switch (size_cfg->pge_size) {
1681         default:
1682         case RTW89_PLE_PG_64:
1683                 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n");
1684                 return -EINVAL;
1685         case RTW89_PLE_PG_128:
1686                 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128,
1687                                        B_AX_PLE_PAGE_SEL_MASK);
1688                 break;
1689         case RTW89_PLE_PG_256:
1690                 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256,
1691                                        B_AX_PLE_PAGE_SEL_MASK);
1692                 break;
1693         }
1694
1695         val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK);
1696         val = u32_replace_bits(val, size_cfg->lnk_pge_num,
1697                                B_AX_PLE_FREE_PAGE_NUM_MASK);
1698         rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val);
1699
1700         return 0;
1701 }
1702
1703 #define INVALID_QT_WCPU U16_MAX
1704 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx)                    \
1705         do {                                                            \
1706                 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \
1707                       u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK);  \
1708                 rtw89_write32(rtwdev,                                   \
1709                               R_AX_ ## _module ## _QTA ## _idx ## _CFG, \
1710                               val);                                     \
1711         } while (0)
1712 #define SET_QUOTA(_x, _module, _idx)                                    \
1713         SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx)
1714
1715 static void wde_quota_cfg(struct rtw89_dev *rtwdev,
1716                           const struct rtw89_wde_quota *min_cfg,
1717                           const struct rtw89_wde_quota *max_cfg,
1718                           u16 ext_wde_min_qt_wcpu)
1719 {
1720         u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ?
1721                           ext_wde_min_qt_wcpu : min_cfg->wcpu;
1722         u32 val;
1723
1724         SET_QUOTA(hif, WDE, 0);
1725         SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1);
1726         SET_QUOTA(pkt_in, WDE, 3);
1727         SET_QUOTA(cpu_io, WDE, 4);
1728 }
1729
1730 static void ple_quota_cfg(struct rtw89_dev *rtwdev,
1731                           const struct rtw89_ple_quota *min_cfg,
1732                           const struct rtw89_ple_quota *max_cfg)
1733 {
1734         u32 val;
1735
1736         SET_QUOTA(cma0_tx, PLE, 0);
1737         SET_QUOTA(cma1_tx, PLE, 1);
1738         SET_QUOTA(c2h, PLE, 2);
1739         SET_QUOTA(h2c, PLE, 3);
1740         SET_QUOTA(wcpu, PLE, 4);
1741         SET_QUOTA(mpdu_proc, PLE, 5);
1742         SET_QUOTA(cma0_dma, PLE, 6);
1743         SET_QUOTA(cma1_dma, PLE, 7);
1744         SET_QUOTA(bb_rpt, PLE, 8);
1745         SET_QUOTA(wd_rel, PLE, 9);
1746         SET_QUOTA(cpu_io, PLE, 10);
1747         if (rtwdev->chip->chip_id == RTL8852C)
1748                 SET_QUOTA(tx_rpt, PLE, 11);
1749 }
1750
1751 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow)
1752 {
1753         const struct rtw89_ple_quota *min_cfg, *max_cfg;
1754         const struct rtw89_dle_mem *cfg;
1755         u32 val;
1756
1757         if (rtwdev->chip->chip_id == RTL8852C)
1758                 return 0;
1759
1760         if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) {
1761                 rtw89_err(rtwdev, "[ERR]support SCC mode only\n");
1762                 return -EINVAL;
1763         }
1764
1765         if (wow)
1766                 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW);
1767         else
1768                 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC);
1769         if (!cfg) {
1770                 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
1771                 return -EINVAL;
1772         }
1773
1774         min_cfg = cfg->ple_min_qt;
1775         max_cfg = cfg->ple_max_qt;
1776         SET_QUOTA(cma0_dma, PLE, 6);
1777         SET_QUOTA(cma1_dma, PLE, 7);
1778
1779         return 0;
1780 }
1781 #undef SET_QUOTA
1782
1783 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable)
1784 {
1785         u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC;
1786
1787         if (enable)
1788                 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32);
1789         else
1790                 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32);
1791 }
1792
1793 static void dle_quota_cfg(struct rtw89_dev *rtwdev,
1794                           const struct rtw89_dle_mem *cfg,
1795                           u16 ext_wde_min_qt_wcpu)
1796 {
1797         wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu);
1798         ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt);
1799 }
1800
1801 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1802                     enum rtw89_qta_mode ext_mode)
1803 {
1804         const struct rtw89_dle_mem *cfg, *ext_cfg;
1805         u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU;
1806         int ret = 0;
1807         u32 ini;
1808
1809         ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1810         if (ret)
1811                 return ret;
1812
1813         cfg = get_dle_mem_cfg(rtwdev, mode);
1814         if (!cfg) {
1815                 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
1816                 ret = -EINVAL;
1817                 goto error;
1818         }
1819
1820         if (mode == RTW89_QTA_DLFW) {
1821                 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode);
1822                 if (!ext_cfg) {
1823                         rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n",
1824                                   ext_mode);
1825                         ret = -EINVAL;
1826                         goto error;
1827                 }
1828                 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu;
1829         }
1830
1831         if (dle_used_size(cfg->wde_size, cfg->ple_size) !=
1832             dle_expected_used_size(rtwdev, mode)) {
1833                 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
1834                 ret = -EINVAL;
1835                 goto error;
1836         }
1837
1838         dle_func_en(rtwdev, false);
1839         dle_clk_en(rtwdev, true);
1840
1841         ret = dle_mix_cfg(rtwdev, cfg);
1842         if (ret) {
1843                 rtw89_err(rtwdev, "[ERR] dle mix cfg\n");
1844                 goto error;
1845         }
1846         dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu);
1847
1848         dle_func_en(rtwdev, true);
1849
1850         ret = read_poll_timeout(rtw89_read32, ini,
1851                                 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1,
1852                                 2000, false, rtwdev, R_AX_WDE_INI_STATUS);
1853         if (ret) {
1854                 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n");
1855                 return ret;
1856         }
1857
1858         ret = read_poll_timeout(rtw89_read32, ini,
1859                                 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1,
1860                                 2000, false, rtwdev, R_AX_PLE_INI_STATUS);
1861         if (ret) {
1862                 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n");
1863                 return ret;
1864         }
1865
1866         return 0;
1867 error:
1868         dle_func_en(rtwdev, false);
1869         rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n",
1870                   rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS));
1871         rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n",
1872                   rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS));
1873
1874         return ret;
1875 }
1876
1877 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
1878                             enum rtw89_qta_mode mode)
1879 {
1880         u32 reg, max_preld_size, min_rsvd_size;
1881
1882         max_preld_size = (mac_idx == RTW89_MAC_0 ?
1883                           PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE;
1884         reg = mac_idx == RTW89_MAC_0 ?
1885               R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0;
1886         rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size);
1887         rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN);
1888
1889         min_rsvd_size = PRELD_AMSDU_SIZE;
1890         reg = mac_idx == RTW89_MAC_0 ?
1891               R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1;
1892         rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND);
1893         rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size);
1894
1895         return 0;
1896 }
1897
1898 static bool is_qta_poh(struct rtw89_dev *rtwdev)
1899 {
1900         return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE;
1901 }
1902
1903 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
1904                         enum rtw89_qta_mode mode)
1905 {
1906         const struct rtw89_chip_info *chip = rtwdev->chip;
1907
1908         if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B ||
1909             chip->chip_id == RTL8851B || !is_qta_poh(rtwdev))
1910                 return 0;
1911
1912         return preload_init_set(rtwdev, mac_idx, mode);
1913 }
1914
1915 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev)
1916 {
1917         u32 msk32;
1918         u32 val32;
1919
1920         msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH |
1921                 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 |
1922                 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS |
1923                 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C |
1924                 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN |
1925                 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU |
1926                 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO |
1927                 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL |
1928                 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL |
1929                 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX |
1930                 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO |
1931                 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU |
1932                 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU;
1933         val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0);
1934
1935         if ((val32 & msk32) == msk32)
1936                 return true;
1937
1938         return false;
1939 }
1940
1941 static void _patch_ss2f_path(struct rtw89_dev *rtwdev)
1942 {
1943         const struct rtw89_chip_info *chip = rtwdev->chip;
1944
1945         if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B ||
1946             chip->chip_id == RTL8851B)
1947                 return;
1948
1949         rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK,
1950                            SS2F_PATH_WLCPU);
1951 }
1952
1953 static int sta_sch_init(struct rtw89_dev *rtwdev)
1954 {
1955         u32 p_val;
1956         u8 val;
1957         int ret;
1958
1959         ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1960         if (ret)
1961                 return ret;
1962
1963         val = rtw89_read8(rtwdev, R_AX_SS_CTRL);
1964         val |= B_AX_SS_EN;
1965         rtw89_write8(rtwdev, R_AX_SS_CTRL, val);
1966
1967         ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1,
1968                                 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL);
1969         if (ret) {
1970                 rtw89_err(rtwdev, "[ERR]STA scheduler init\n");
1971                 return ret;
1972         }
1973
1974         rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG);
1975         rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN);
1976
1977         _patch_ss2f_path(rtwdev);
1978
1979         return 0;
1980 }
1981
1982 static int mpdu_proc_init(struct rtw89_dev *rtwdev)
1983 {
1984         int ret;
1985
1986         ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1987         if (ret)
1988                 return ret;
1989
1990         rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);
1991         rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);
1992         rtw89_write32_set(rtwdev, R_AX_MPDU_PROC,
1993                           B_AX_APPEND_FCS | B_AX_A_ICV_ERR);
1994         rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL);
1995
1996         return 0;
1997 }
1998
1999 static int sec_eng_init(struct rtw89_dev *rtwdev)
2000 {
2001         const struct rtw89_chip_info *chip = rtwdev->chip;
2002         u32 val = 0;
2003         int ret;
2004
2005         ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
2006         if (ret)
2007                 return ret;
2008
2009         val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL);
2010         /* init clock */
2011         val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP);
2012         /* init TX encryption */
2013         val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC);
2014         val |= (B_AX_MC_DEC | B_AX_BC_DEC);
2015         if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B ||
2016             chip->chip_id == RTL8851B)
2017                 val &= ~B_AX_TX_PARTIAL_MODE;
2018         rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val);
2019
2020         /* init MIC ICV append */
2021         val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC);
2022         val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC);
2023
2024         /* option init */
2025         rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val);
2026
2027         if (chip->chip_id == RTL8852C)
2028                 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1,
2029                                    B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL);
2030
2031         return 0;
2032 }
2033
2034 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2035 {
2036         int ret;
2037
2038         ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID);
2039         if (ret) {
2040                 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret);
2041                 return ret;
2042         }
2043
2044         ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode);
2045         if (ret) {
2046                 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret);
2047                 return ret;
2048         }
2049
2050         ret = hfc_init(rtwdev, true, true, true);
2051         if (ret) {
2052                 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret);
2053                 return ret;
2054         }
2055
2056         ret = sta_sch_init(rtwdev);
2057         if (ret) {
2058                 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret);
2059                 return ret;
2060         }
2061
2062         ret = mpdu_proc_init(rtwdev);
2063         if (ret) {
2064                 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret);
2065                 return ret;
2066         }
2067
2068         ret = sec_eng_init(rtwdev);
2069         if (ret) {
2070                 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret);
2071                 return ret;
2072         }
2073
2074         return ret;
2075 }
2076
2077 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2078 {
2079         u32 val, reg;
2080         u16 p_val;
2081         int ret;
2082
2083         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2084         if (ret)
2085                 return ret;
2086
2087         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx);
2088
2089         val = rtw89_read32(rtwdev, reg);
2090         val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) |
2091                B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN;
2092         rtw89_write32(rtwdev, reg, val);
2093
2094         ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR),
2095                                 1, TRXCFG_WAIT_CNT, false, rtwdev, reg);
2096         if (ret) {
2097                 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n");
2098                 return ret;
2099         }
2100
2101         return 0;
2102 }
2103
2104 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2105 {
2106         u32 ret;
2107         u32 reg;
2108         u32 val;
2109
2110         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2111         if (ret)
2112                 return ret;
2113
2114         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx);
2115         if (rtwdev->chip->chip_id == RTL8852C)
2116                 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
2117                                    SIFS_MACTXEN_T1_V1);
2118         else
2119                 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
2120                                    SIFS_MACTXEN_T1);
2121
2122         if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) {
2123                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx);
2124                 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV);
2125         }
2126
2127         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx);
2128         rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN);
2129
2130         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx);
2131         if (rtwdev->chip->chip_id == RTL8852C) {
2132                 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
2133                                         B_AX_TX_PARTIAL_MODE);
2134                 if (!val)
2135                         rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK,
2136                                            SCH_PREBKF_24US);
2137         } else {
2138                 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK,
2139                                    SCH_PREBKF_24US);
2140         }
2141
2142         return 0;
2143 }
2144
2145 int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev,
2146                            enum rtw89_machdr_frame_type type,
2147                            enum rtw89_mac_fwd_target fwd_target,
2148                            u8 mac_idx)
2149 {
2150         u32 reg;
2151         u32 val;
2152
2153         switch (fwd_target) {
2154         case RTW89_FWD_DONT_CARE:
2155                 val = RX_FLTR_FRAME_DROP;
2156                 break;
2157         case RTW89_FWD_TO_HOST:
2158                 val = RX_FLTR_FRAME_TO_HOST;
2159                 break;
2160         case RTW89_FWD_TO_WLAN_CPU:
2161                 val = RX_FLTR_FRAME_TO_WLCPU;
2162                 break;
2163         default:
2164                 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n");
2165                 return -EINVAL;
2166         }
2167
2168         switch (type) {
2169         case RTW89_MGNT:
2170                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx);
2171                 break;
2172         case RTW89_CTRL:
2173                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx);
2174                 break;
2175         case RTW89_DATA:
2176                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx);
2177                 break;
2178         default:
2179                 rtw89_err(rtwdev, "[ERR]set rx filter type err\n");
2180                 return -EINVAL;
2181         }
2182         rtw89_write32(rtwdev, reg, val);
2183
2184         return 0;
2185 }
2186
2187 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2188 {
2189         int ret, i;
2190         u32 mac_ftlr, plcp_ftlr;
2191
2192         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2193         if (ret)
2194                 return ret;
2195
2196         for (i = RTW89_MGNT; i <= RTW89_DATA; i++) {
2197                 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST,
2198                                              mac_idx);
2199                 if (ret)
2200                         return ret;
2201         }
2202         mac_ftlr = rtwdev->hal.rx_fltr;
2203         plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK |
2204                     B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK |
2205                     B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK |
2206                     B_AX_HE_SIGB_CRC_CHK;
2207         rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx),
2208                       mac_ftlr);
2209         rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx),
2210                       plcp_ftlr);
2211
2212         return 0;
2213 }
2214
2215 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx)
2216 {
2217         u32 reg, val32;
2218         u32 b_rsp_chk_nav, b_rsp_chk_cca;
2219
2220         b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV |
2221                         B_AX_RSP_CHK_BASIC_NAV;
2222         b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 |
2223                         B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA |
2224                         B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA;
2225
2226         switch (rtwdev->chip->chip_id) {
2227         case RTL8852A:
2228         case RTL8852B:
2229                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx);
2230                 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav;
2231                 rtw89_write32(rtwdev, reg, val32);
2232
2233                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);
2234                 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca;
2235                 rtw89_write32(rtwdev, reg, val32);
2236                 break;
2237         default:
2238                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx);
2239                 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav;
2240                 rtw89_write32(rtwdev, reg, val32);
2241
2242                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);
2243                 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca;
2244                 rtw89_write32(rtwdev, reg, val32);
2245                 break;
2246         }
2247 }
2248
2249 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2250 {
2251         u32 val, reg;
2252         int ret;
2253
2254         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2255         if (ret)
2256                 return ret;
2257
2258         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx);
2259         val = rtw89_read32(rtwdev, reg);
2260         val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA |
2261                 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 |
2262                 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 |
2263                 B_AX_CTN_CHK_INTRA_NAV |
2264                 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA |
2265                 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 |
2266                 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 |
2267                 B_AX_CTN_CHK_CCA_P20);
2268         val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 |
2269                  B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 |
2270                  B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 |
2271                  B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV |
2272                  B_AX_SIFS_CHK_EDCCA);
2273
2274         rtw89_write32(rtwdev, reg, val);
2275
2276         _patch_dis_resp_chk(rtwdev, mac_idx);
2277
2278         return 0;
2279 }
2280
2281 static int nav_ctrl_init(struct rtw89_dev *rtwdev)
2282 {
2283         rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN |
2284                                                      B_AX_WMAC_TF_UP_NAV_EN |
2285                                                      B_AX_WMAC_NAV_UPPER_EN);
2286         rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS);
2287
2288         return 0;
2289 }
2290
2291 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2292 {
2293         u32 reg;
2294         int ret;
2295
2296         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2297         if (ret)
2298                 return ret;
2299         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx);
2300         rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN);
2301
2302         return 0;
2303 }
2304
2305 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2306 {
2307         u32 reg;
2308         int ret;
2309
2310         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2311         if (ret)
2312                 return ret;
2313
2314         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx);
2315         rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN);
2316
2317         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx);
2318         rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD);
2319
2320         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx);
2321         rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE);
2322         rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE);
2323
2324         return 0;
2325 }
2326
2327 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2328 {
2329         const struct rtw89_chip_info *chip = rtwdev->chip;
2330         const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs;
2331         u32 reg, val, sifs;
2332         int ret;
2333
2334         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2335         if (ret)
2336                 return ret;
2337
2338         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);
2339         val = rtw89_read32(rtwdev, reg);
2340         val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK;
2341         val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK);
2342
2343         switch (rtwdev->chip->chip_id) {
2344         case RTL8852A:
2345                 sifs = WMAC_SPEC_SIFS_OFDM_52A;
2346                 break;
2347         case RTL8852B:
2348                 sifs = WMAC_SPEC_SIFS_OFDM_52B;
2349                 break;
2350         default:
2351                 sifs = WMAC_SPEC_SIFS_OFDM_52C;
2352                 break;
2353         }
2354         val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK;
2355         val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs);
2356         rtw89_write32(rtwdev, reg, val);
2357
2358         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx);
2359         rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN);
2360
2361         reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx);
2362         rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);
2363         reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx);
2364         rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data);
2365
2366         return 0;
2367 }
2368
2369 static void rst_bacam(struct rtw89_dev *rtwdev)
2370 {
2371         u32 val32;
2372         int ret;
2373
2374         rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK,
2375                            S_AX_BACAM_RST_ALL);
2376
2377         ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0,
2378                                        1, 1000, false,
2379                                        rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK);
2380         if (ret)
2381                 rtw89_warn(rtwdev, "failed to reset BA CAM\n");
2382 }
2383
2384 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2385 {
2386 #define TRXCFG_RMAC_CCA_TO      32
2387 #define TRXCFG_RMAC_DATA_TO     15
2388 #define RX_MAX_LEN_UNIT 512
2389 #define PLD_RLS_MAX_PG 127
2390 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT)
2391         int ret;
2392         u32 reg, rx_max_len, rx_qta;
2393         u16 val;
2394
2395         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2396         if (ret)
2397                 return ret;
2398
2399         if (mac_idx == RTW89_MAC_0)
2400                 rst_bacam(rtwdev);
2401
2402         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx);
2403         rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL);
2404
2405         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx);
2406         val = rtw89_read16(rtwdev, reg);
2407         val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO,
2408                                B_AX_RX_DLK_DATA_TIME_MASK);
2409         val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO,
2410                                B_AX_RX_DLK_CCA_TIME_MASK);
2411         rtw89_write16(rtwdev, reg, val);
2412
2413         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx);
2414         rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1);
2415
2416         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx);
2417         if (mac_idx == RTW89_MAC_0)
2418                 rx_qta = rtwdev->mac.dle_info.c0_rx_qta;
2419         else
2420                 rx_qta = rtwdev->mac.dle_info.c1_rx_qta;
2421         rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG);
2422         rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size;
2423         rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN);
2424         rx_max_len /= RX_MAX_LEN_UNIT;
2425         rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len);
2426
2427         if (rtwdev->chip->chip_id == RTL8852A &&
2428             rtwdev->hal.cv == CHIP_CBV) {
2429                 rtw89_write16_mask(rtwdev,
2430                                    rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx),
2431                                    B_AX_RX_DLK_CCA_TIME_MASK, 0);
2432                 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx),
2433                                   BIT(12));
2434         }
2435
2436         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx);
2437         rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK);
2438
2439         return ret;
2440 }
2441
2442 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2443 {
2444         enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2445         u32 val, reg;
2446         int ret;
2447
2448         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2449         if (ret)
2450                 return ret;
2451
2452         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
2453         val = rtw89_read32(rtwdev, reg);
2454         val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK);
2455         val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK);
2456         val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK);
2457         rtw89_write32(rtwdev, reg, val);
2458
2459         if (chip_id == RTL8852A || chip_id == RTL8852B) {
2460                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx);
2461                 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN);
2462         }
2463
2464         return 0;
2465 }
2466
2467 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode)
2468 {
2469         const struct rtw89_dle_mem *cfg;
2470
2471         cfg = get_dle_mem_cfg(rtwdev, mode);
2472         if (!cfg) {
2473                 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
2474                 return false;
2475         }
2476
2477         return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma);
2478 }
2479
2480 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2481 {
2482         u32 val, reg;
2483         int ret;
2484
2485         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2486         if (ret)
2487                 return ret;
2488
2489         if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
2490                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx);
2491                 val = rtw89_read32(rtwdev, reg);
2492                 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K,
2493                                        B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK);
2494                 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B,
2495                                        B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK);
2496                 val |= B_AX_HW_CTS2SELF_EN;
2497                 rtw89_write32(rtwdev, reg, val);
2498
2499                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx);
2500                 val = rtw89_read32(rtwdev, reg);
2501                 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK);
2502                 val &= ~B_AX_PTCL_TX_ARB_TO_MODE;
2503                 rtw89_write32(rtwdev, reg, val);
2504         }
2505
2506         if (mac_idx == RTW89_MAC_0) {
2507                 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0,
2508                                  B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1);
2509                 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0,
2510                                  B_AX_PTCL_TRIGGER_SS_EN_0 |
2511                                  B_AX_PTCL_TRIGGER_SS_EN_1 |
2512                                  B_AX_PTCL_TRIGGER_SS_EN_UL);
2513                 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL,
2514                                   B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU);
2515         } else if (mac_idx == RTW89_MAC_1) {
2516                 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1,
2517                                   B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU);
2518         }
2519
2520         return 0;
2521 }
2522
2523 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2524 {
2525         enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2526         u32 reg;
2527         int ret;
2528
2529         if (chip_id != RTL8852B)
2530                 return 0;
2531
2532         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2533         if (ret)
2534                 return ret;
2535
2536         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx);
2537         rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE);
2538
2539         return 0;
2540 }
2541
2542 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2543 {
2544         int ret;
2545
2546         ret = scheduler_init(rtwdev, mac_idx);
2547         if (ret) {
2548                 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret);
2549                 return ret;
2550         }
2551
2552         ret = addr_cam_init(rtwdev, mac_idx);
2553         if (ret) {
2554                 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx,
2555                           ret);
2556                 return ret;
2557         }
2558
2559         ret = rx_fltr_init(rtwdev, mac_idx);
2560         if (ret) {
2561                 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx,
2562                           ret);
2563                 return ret;
2564         }
2565
2566         ret = cca_ctrl_init(rtwdev, mac_idx);
2567         if (ret) {
2568                 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx,
2569                           ret);
2570                 return ret;
2571         }
2572
2573         ret = nav_ctrl_init(rtwdev);
2574         if (ret) {
2575                 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx,
2576                           ret);
2577                 return ret;
2578         }
2579
2580         ret = spatial_reuse_init(rtwdev, mac_idx);
2581         if (ret) {
2582                 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n",
2583                           mac_idx, ret);
2584                 return ret;
2585         }
2586
2587         ret = tmac_init(rtwdev, mac_idx);
2588         if (ret) {
2589                 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret);
2590                 return ret;
2591         }
2592
2593         ret = trxptcl_init(rtwdev, mac_idx);
2594         if (ret) {
2595                 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret);
2596                 return ret;
2597         }
2598
2599         ret = rmac_init(rtwdev, mac_idx);
2600         if (ret) {
2601                 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret);
2602                 return ret;
2603         }
2604
2605         ret = cmac_com_init(rtwdev, mac_idx);
2606         if (ret) {
2607                 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret);
2608                 return ret;
2609         }
2610
2611         ret = ptcl_init(rtwdev, mac_idx);
2612         if (ret) {
2613                 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret);
2614                 return ret;
2615         }
2616
2617         ret = cmac_dma_init(rtwdev, mac_idx);
2618         if (ret) {
2619                 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret);
2620                 return ret;
2621         }
2622
2623         return ret;
2624 }
2625
2626 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev,
2627                                  struct rtw89_mac_c2h_info *c2h_info)
2628 {
2629         struct rtw89_mac_h2c_info h2c_info = {0};
2630         u32 ret;
2631
2632         h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE;
2633         h2c_info.content_len = 0;
2634
2635         ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info);
2636         if (ret)
2637                 return ret;
2638
2639         if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP)
2640                 return -EINVAL;
2641
2642         return 0;
2643 }
2644
2645 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev)
2646 {
2647         struct rtw89_efuse *efuse = &rtwdev->efuse;
2648         struct rtw89_hal *hal = &rtwdev->hal;
2649         const struct rtw89_chip_info *chip = rtwdev->chip;
2650         struct rtw89_mac_c2h_info c2h_info = {0};
2651         const struct rtw89_c2hreg_phycap *phycap;
2652         u8 tx_nss;
2653         u8 rx_nss;
2654         u8 tx_ant;
2655         u8 rx_ant;
2656         u32 ret;
2657
2658         ret = rtw89_mac_read_phycap(rtwdev, &c2h_info);
2659         if (ret)
2660                 return ret;
2661
2662         phycap = &c2h_info.u.phycap;
2663
2664         tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS);
2665         rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS);
2666         tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM);
2667         rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM);
2668
2669         hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss;
2670         hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss;
2671
2672         if (tx_ant == 1)
2673                 hal->antenna_tx = RF_B;
2674         if (rx_ant == 1)
2675                 hal->antenna_rx = RF_B;
2676
2677         if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) {
2678                 hal->antenna_tx = RF_B;
2679                 hal->tx_path_diversity = true;
2680         }
2681
2682         if (chip->rf_path_num == 1) {
2683                 hal->antenna_tx = RF_A;
2684                 hal->antenna_rx = RF_A;
2685                 if ((efuse->rfe_type % 3) == 2)
2686                         hal->ant_diversity = true;
2687         }
2688
2689         rtw89_debug(rtwdev, RTW89_DBG_FW,
2690                     "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n",
2691                     hal->tx_nss, tx_nss, chip->tx_nss,
2692                     hal->rx_nss, rx_nss, chip->rx_nss);
2693         rtw89_debug(rtwdev, RTW89_DBG_FW,
2694                     "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n",
2695                     tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx);
2696         rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity);
2697         rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity);
2698
2699         return 0;
2700 }
2701
2702 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band,
2703                                   u16 tx_en_u16, u16 mask_u16)
2704 {
2705         u32 ret;
2706         struct rtw89_mac_c2h_info c2h_info = {0};
2707         struct rtw89_mac_h2c_info h2c_info = {0};
2708         struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en;
2709
2710         h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN;
2711         h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN;
2712
2713         u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN);
2714         u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK);
2715         u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND);
2716
2717         ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info);
2718         if (ret)
2719                 return ret;
2720
2721         if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT)
2722                 return -EINVAL;
2723
2724         return 0;
2725 }
2726
2727 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx,
2728                                   u16 tx_en, u16 tx_en_mask)
2729 {
2730         u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx);
2731         u16 val;
2732         int ret;
2733
2734         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2735         if (ret)
2736                 return ret;
2737
2738         if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
2739                 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx,
2740                                               tx_en, tx_en_mask);
2741
2742         val = rtw89_read16(rtwdev, reg);
2743         val = (val & ~tx_en_mask) | (tx_en & tx_en_mask);
2744         rtw89_write16(rtwdev, reg, val);
2745
2746         return 0;
2747 }
2748
2749 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
2750                                      u32 tx_en, u32 tx_en_mask)
2751 {
2752         u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx);
2753         u32 val;
2754         int ret;
2755
2756         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2757         if (ret)
2758                 return ret;
2759
2760         val = rtw89_read32(rtwdev, reg);
2761         val = (val & ~tx_en_mask) | (tx_en & tx_en_mask);
2762         rtw89_write32(rtwdev, reg, val);
2763
2764         return 0;
2765 }
2766
2767 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
2768                           u32 *tx_en, enum rtw89_sch_tx_sel sel)
2769 {
2770         int ret;
2771
2772         *tx_en = rtw89_read16(rtwdev,
2773                               rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx));
2774
2775         switch (sel) {
2776         case RTW89_SCH_TX_SEL_ALL:
2777                 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0,
2778                                              B_AX_CTN_TXEN_ALL_MASK);
2779                 if (ret)
2780                         return ret;
2781                 break;
2782         case RTW89_SCH_TX_SEL_HIQ:
2783                 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx,
2784                                              0, B_AX_CTN_TXEN_HGQ);
2785                 if (ret)
2786                         return ret;
2787                 break;
2788         case RTW89_SCH_TX_SEL_MG0:
2789                 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx,
2790                                              0, B_AX_CTN_TXEN_MGQ);
2791                 if (ret)
2792                         return ret;
2793                 break;
2794         case RTW89_SCH_TX_SEL_MACID:
2795                 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0,
2796                                              B_AX_CTN_TXEN_ALL_MASK);
2797                 if (ret)
2798                         return ret;
2799                 break;
2800         default:
2801                 return 0;
2802         }
2803
2804         return 0;
2805 }
2806 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx);
2807
2808 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
2809                              u32 *tx_en, enum rtw89_sch_tx_sel sel)
2810 {
2811         int ret;
2812
2813         *tx_en = rtw89_read32(rtwdev,
2814                               rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx));
2815
2816         switch (sel) {
2817         case RTW89_SCH_TX_SEL_ALL:
2818                 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0,
2819                                                 B_AX_CTN_TXEN_ALL_MASK_V1);
2820                 if (ret)
2821                         return ret;
2822                 break;
2823         case RTW89_SCH_TX_SEL_HIQ:
2824                 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx,
2825                                                 0, B_AX_CTN_TXEN_HGQ);
2826                 if (ret)
2827                         return ret;
2828                 break;
2829         case RTW89_SCH_TX_SEL_MG0:
2830                 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx,
2831                                                 0, B_AX_CTN_TXEN_MGQ);
2832                 if (ret)
2833                         return ret;
2834                 break;
2835         case RTW89_SCH_TX_SEL_MACID:
2836                 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0,
2837                                                 B_AX_CTN_TXEN_ALL_MASK_V1);
2838                 if (ret)
2839                         return ret;
2840                 break;
2841         default:
2842                 return 0;
2843         }
2844
2845         return 0;
2846 }
2847 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1);
2848
2849 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
2850 {
2851         int ret;
2852
2853         ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK);
2854         if (ret)
2855                 return ret;
2856
2857         return 0;
2858 }
2859 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx);
2860
2861 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
2862 {
2863         int ret;
2864
2865         ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en,
2866                                         B_AX_CTN_TXEN_ALL_MASK_V1);
2867         if (ret)
2868                 return ret;
2869
2870         return 0;
2871 }
2872 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1);
2873
2874 int rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id)
2875 {
2876         u32 val, reg;
2877         int ret;
2878
2879         reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ;
2880         val = buf_len;
2881         val |= B_AX_WD_BUF_REQ_EXEC;
2882         rtw89_write32(rtwdev, reg, val);
2883
2884         reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS;
2885
2886         ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE,
2887                                 1, 2000, false, rtwdev, reg);
2888         if (ret)
2889                 return ret;
2890
2891         *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val);
2892         if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID)
2893                 return -ENOENT;
2894
2895         return 0;
2896 }
2897
2898 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev,
2899                         struct rtw89_cpuio_ctrl *ctrl_para, bool wd)
2900 {
2901         u32 val, cmd_type, reg;
2902         int ret;
2903
2904         cmd_type = ctrl_para->cmd_type;
2905
2906         reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2;
2907         val = 0;
2908         val = u32_replace_bits(val, ctrl_para->start_pktid,
2909                                B_AX_WD_CPUQ_OP_STRT_PKTID_MASK);
2910         val = u32_replace_bits(val, ctrl_para->end_pktid,
2911                                B_AX_WD_CPUQ_OP_END_PKTID_MASK);
2912         rtw89_write32(rtwdev, reg, val);
2913
2914         reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1;
2915         val = 0;
2916         val = u32_replace_bits(val, ctrl_para->src_pid,
2917                                B_AX_CPUQ_OP_SRC_PID_MASK);
2918         val = u32_replace_bits(val, ctrl_para->src_qid,
2919                                B_AX_CPUQ_OP_SRC_QID_MASK);
2920         val = u32_replace_bits(val, ctrl_para->dst_pid,
2921                                B_AX_CPUQ_OP_DST_PID_MASK);
2922         val = u32_replace_bits(val, ctrl_para->dst_qid,
2923                                B_AX_CPUQ_OP_DST_QID_MASK);
2924         rtw89_write32(rtwdev, reg, val);
2925
2926         reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0;
2927         val = 0;
2928         val = u32_replace_bits(val, cmd_type,
2929                                B_AX_CPUQ_OP_CMD_TYPE_MASK);
2930         val = u32_replace_bits(val, ctrl_para->macid,
2931                                B_AX_CPUQ_OP_MACID_MASK);
2932         val = u32_replace_bits(val, ctrl_para->pkt_num,
2933                                B_AX_CPUQ_OP_PKTNUM_MASK);
2934         val |= B_AX_WD_CPUQ_OP_EXEC;
2935         rtw89_write32(rtwdev, reg, val);
2936
2937         reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS;
2938
2939         ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE,
2940                                 1, 2000, false, rtwdev, reg);
2941         if (ret)
2942                 return ret;
2943
2944         if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID ||
2945             cmd_type == CPUIO_OP_CMD_GET_NEXT_PID)
2946                 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val);
2947
2948         return 0;
2949 }
2950
2951 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode)
2952 {
2953         const struct rtw89_dle_mem *cfg;
2954         struct rtw89_cpuio_ctrl ctrl_para = {0};
2955         u16 pkt_id;
2956         int ret;
2957
2958         cfg = get_dle_mem_cfg(rtwdev, mode);
2959         if (!cfg) {
2960                 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
2961                 return -EINVAL;
2962         }
2963
2964         if (dle_used_size(cfg->wde_size, cfg->ple_size) !=
2965             dle_expected_used_size(rtwdev, mode)) {
2966                 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
2967                 return -EINVAL;
2968         }
2969
2970         dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU);
2971
2972         ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id);
2973         if (ret) {
2974                 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n");
2975                 return ret;
2976         }
2977
2978         ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD;
2979         ctrl_para.start_pktid = pkt_id;
2980         ctrl_para.end_pktid = pkt_id;
2981         ctrl_para.pkt_num = 0;
2982         ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS;
2983         ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT;
2984         ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true);
2985         if (ret) {
2986                 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n");
2987                 return -EFAULT;
2988         }
2989
2990         ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, false, &pkt_id);
2991         if (ret) {
2992                 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n");
2993                 return ret;
2994         }
2995
2996         ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD;
2997         ctrl_para.start_pktid = pkt_id;
2998         ctrl_para.end_pktid = pkt_id;
2999         ctrl_para.pkt_num = 0;
3000         ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS;
3001         ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT;
3002         ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false);
3003         if (ret) {
3004                 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n");
3005                 return -EFAULT;
3006         }
3007
3008         return 0;
3009 }
3010
3011 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx)
3012 {
3013         int ret;
3014         u32 reg;
3015         u8 val;
3016
3017         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
3018         if (ret)
3019                 return ret;
3020
3021         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx);
3022
3023         ret = read_poll_timeout(rtw89_read8, val,
3024                                 (val & B_AX_PTCL_TX_ON_STAT) == 0,
3025                                 SW_CVR_DUR_US,
3026                                 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT,
3027                                 false, rtwdev, reg);
3028         if (ret)
3029                 return ret;
3030
3031         return 0;
3032 }
3033
3034 static int band1_enable(struct rtw89_dev *rtwdev)
3035 {
3036         int ret, i;
3037         u32 sleep_bak[4] = {0};
3038         u32 pause_bak[4] = {0};
3039         u32 tx_en;
3040
3041         ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL);
3042         if (ret) {
3043                 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret);
3044                 return ret;
3045         }
3046
3047         for (i = 0; i < 4; i++) {
3048                 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4);
3049                 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4);
3050                 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX);
3051                 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX);
3052         }
3053
3054         ret = band_idle_ck_b(rtwdev, 0);
3055         if (ret) {
3056                 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret);
3057                 return ret;
3058         }
3059
3060         ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode);
3061         if (ret) {
3062                 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);
3063                 return ret;
3064         }
3065
3066         for (i = 0; i < 4; i++) {
3067                 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]);
3068                 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]);
3069         }
3070
3071         ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en);
3072         if (ret) {
3073                 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret);
3074                 return ret;
3075         }
3076
3077         ret = cmac_func_en(rtwdev, 1, true);
3078         if (ret) {
3079                 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret);
3080                 return ret;
3081         }
3082
3083         ret = cmac_init(rtwdev, 1);
3084         if (ret) {
3085                 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret);
3086                 return ret;
3087         }
3088
3089         rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
3090                           B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1);
3091
3092         return 0;
3093 }
3094
3095 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev)
3096 {
3097         const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3098
3099         rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR);
3100         rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set);
3101 }
3102
3103 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev)
3104 {
3105         const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3106
3107         rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set);
3108 }
3109
3110 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev)
3111 {
3112         enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3113         const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3114
3115         rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,
3116                           B_AX_TX_GET_ERRPKTID_INT_EN |
3117                           B_AX_TX_NXT_ERRPKTID_INT_EN |
3118                           B_AX_TX_MPDU_SIZE_ZERO_INT_EN |
3119                           B_AX_TX_OFFSET_ERR_INT_EN |
3120                           B_AX_TX_HDR3_SIZE_ERR_INT_EN);
3121         if (chip_id == RTL8852C)
3122                 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,
3123                                   B_AX_TX_ETH_TYPE_ERR_EN |
3124                                   B_AX_TX_LLC_PRE_ERR_EN |
3125                                   B_AX_TX_NW_TYPE_ERR_EN |
3126                                   B_AX_TX_KSRCH_ERR_EN);
3127         rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR,
3128                           imr->mpdu_tx_imr_set);
3129
3130         rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR,
3131                           B_AX_GETPKTID_ERR_INT_EN |
3132                           B_AX_MHDRLEN_ERR_INT_EN |
3133                           B_AX_RPT_ERR_INT_EN);
3134         rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR,
3135                           imr->mpdu_rx_imr_set);
3136 }
3137
3138 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev)
3139 {
3140         const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3141
3142         rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,
3143                           B_AX_SEARCH_HANG_TIMEOUT_INT_EN |
3144                           B_AX_RPT_HANG_TIMEOUT_INT_EN |
3145                           B_AX_PLE_B_PKTID_ERR_INT_EN);
3146         rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,
3147                           imr->sta_sch_imr_set);
3148 }
3149
3150 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev)
3151 {
3152         const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3153
3154         rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg,
3155                           imr->txpktctl_imr_b0_clr);
3156         rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg,
3157                           imr->txpktctl_imr_b0_set);
3158         rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg,
3159                           imr->txpktctl_imr_b1_clr);
3160         rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg,
3161                           imr->txpktctl_imr_b1_set);
3162 }
3163
3164 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev)
3165 {
3166         const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3167
3168         rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr);
3169         rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set);
3170 }
3171
3172 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev)
3173 {
3174         const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3175
3176         rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr);
3177         rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set);
3178 }
3179
3180 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev)
3181 {
3182         rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR,
3183                           B_AX_PKTIN_GETPKTID_ERR_INT_EN);
3184 }
3185
3186 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev)
3187 {
3188         const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3189
3190         rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,
3191                           imr->host_disp_imr_clr);
3192         rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,
3193                           imr->host_disp_imr_set);
3194         rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,
3195                           imr->cpu_disp_imr_clr);
3196         rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,
3197                           imr->cpu_disp_imr_set);
3198         rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,
3199                           imr->other_disp_imr_clr);
3200         rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,
3201                           imr->other_disp_imr_set);
3202 }
3203
3204 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev)
3205 {
3206         rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR);
3207         rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET);
3208 }
3209
3210 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev)
3211 {
3212         const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3213
3214         rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg,
3215                           B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN);
3216         rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3217                           B_AX_BBRPT_CHINFO_IMR_CLR);
3218         rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3219                           imr->bbrpt_err_imr_set);
3220         rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg,
3221                           B_AX_BBRPT_DFS_TO_ERR_INT_EN);
3222         rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR);
3223 }
3224
3225 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3226 {
3227         u32 reg;
3228
3229         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx);
3230         rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN |
3231                                        B_AX_FSM_TIMEOUT_ERR_INT_EN);
3232         rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN);
3233 }
3234
3235 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3236 {
3237         const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3238         u32 reg;
3239
3240         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx);
3241         rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr);
3242         rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set);
3243 }
3244
3245 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3246 {
3247         const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3248         enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3249         u32 reg;
3250
3251         reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx);
3252         rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr);
3253         rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set);
3254
3255         if (chip_id == RTL8852C) {
3256                 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx);
3257                 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr);
3258                 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set);
3259         }
3260 }
3261
3262 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3263 {
3264         const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3265         u32 reg;
3266
3267         reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx);
3268         rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr);
3269         rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set);
3270 }
3271
3272 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3273 {
3274         const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3275         u32 reg;
3276
3277         reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx);
3278         rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr);
3279         rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set);
3280 }
3281
3282 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3283 {
3284         const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3285         u32 reg;
3286
3287         reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx);
3288         rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr);
3289         rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set);
3290 }
3291
3292 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx,
3293                                 enum rtw89_mac_hwmod_sel sel)
3294 {
3295         int ret;
3296
3297         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel);
3298         if (ret) {
3299                 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n",
3300                           sel, mac_idx);
3301                 return ret;
3302         }
3303
3304         if (sel == RTW89_DMAC_SEL) {
3305                 rtw89_wdrls_imr_enable(rtwdev);
3306                 rtw89_wsec_imr_enable(rtwdev);
3307                 rtw89_mpdu_trx_imr_enable(rtwdev);
3308                 rtw89_sta_sch_imr_enable(rtwdev);
3309                 rtw89_txpktctl_imr_enable(rtwdev);
3310                 rtw89_wde_imr_enable(rtwdev);
3311                 rtw89_ple_imr_enable(rtwdev);
3312                 rtw89_pktin_imr_enable(rtwdev);
3313                 rtw89_dispatcher_imr_enable(rtwdev);
3314                 rtw89_cpuio_imr_enable(rtwdev);
3315                 rtw89_bbrpt_imr_enable(rtwdev);
3316         } else if (sel == RTW89_CMAC_SEL) {
3317                 rtw89_scheduler_imr_enable(rtwdev, mac_idx);
3318                 rtw89_ptcl_imr_enable(rtwdev, mac_idx);
3319                 rtw89_cdma_imr_enable(rtwdev, mac_idx);
3320                 rtw89_phy_intf_imr_enable(rtwdev, mac_idx);
3321                 rtw89_rmac_imr_enable(rtwdev, mac_idx);
3322                 rtw89_tmac_imr_enable(rtwdev, mac_idx);
3323         } else {
3324                 return -EINVAL;
3325         }
3326
3327         return 0;
3328 }
3329
3330 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en)
3331 {
3332         enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3333
3334         rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR,
3335                       en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS);
3336         rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR,
3337                       en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS);
3338         if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta)
3339                 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1,
3340                               en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS);
3341 }
3342
3343 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable)
3344 {
3345         int ret = 0;
3346
3347         if (enable) {
3348                 ret = band1_enable(rtwdev);
3349                 if (ret) {
3350                         rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret);
3351                         return ret;
3352                 }
3353
3354                 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL);
3355                 if (ret) {
3356                         rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret);
3357                         return ret;
3358                 }
3359         } else {
3360                 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n");
3361                 return -EINVAL;
3362         }
3363
3364         return 0;
3365 }
3366
3367 static int set_host_rpr(struct rtw89_dev *rtwdev)
3368 {
3369         if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
3370                 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG,
3371                                    B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH);
3372                 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0,
3373                                   B_AX_RLSRPT0_FLTR_MAP_MASK);
3374         } else {
3375                 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG,
3376                                    B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF);
3377                 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0,
3378                                   B_AX_RLSRPT0_FLTR_MAP_MASK);
3379         }
3380
3381         rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30);
3382         rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255);
3383
3384         return 0;
3385 }
3386
3387 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev)
3388 {
3389         enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode;
3390         int ret;
3391
3392         ret = dmac_init(rtwdev, 0);
3393         if (ret) {
3394                 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret);
3395                 return ret;
3396         }
3397
3398         ret = cmac_init(rtwdev, 0);
3399         if (ret) {
3400                 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret);
3401                 return ret;
3402         }
3403
3404         if (is_qta_dbcc(rtwdev, qta_mode)) {
3405                 ret = rtw89_mac_dbcc_enable(rtwdev, true);
3406                 if (ret) {
3407                         rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret);
3408                         return ret;
3409                 }
3410         }
3411
3412         ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
3413         if (ret) {
3414                 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret);
3415                 return ret;
3416         }
3417
3418         ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
3419         if (ret) {
3420                 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret);
3421                 return ret;
3422         }
3423
3424         rtw89_mac_err_imr_ctrl(rtwdev, true);
3425
3426         ret = set_host_rpr(rtwdev);
3427         if (ret) {
3428                 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret);
3429                 return ret;
3430         }
3431
3432         return 0;
3433 }
3434
3435 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev)
3436 {
3437         enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3438         u32 val32;
3439
3440         if (chip_id == RTL8852B || chip_id == RTL8851B) {
3441                 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN);
3442                 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN);
3443                 return;
3444         }
3445
3446         rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL,
3447                             WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL);
3448
3449         val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL);
3450         val32 |= B_AX_FS_WDT_INT;
3451         val32 &= ~B_AX_FS_WDT_INT_MSK;
3452         rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL);
3453 }
3454
3455 void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev)
3456 {
3457         clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
3458
3459         rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN);
3460         rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN |
3461                           B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY);
3462         rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);
3463
3464         rtw89_disable_fw_watchdog(rtwdev);
3465
3466         rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
3467         rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
3468 }
3469
3470 int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw)
3471 {
3472         u32 val;
3473         int ret;
3474
3475         if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN)
3476                 return -EFAULT;
3477
3478         rtw89_write32(rtwdev, R_AX_UDM1, 0);
3479         rtw89_write32(rtwdev, R_AX_UDM2, 0);
3480         rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0);
3481         rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
3482         rtw89_write32(rtwdev, R_AX_HALT_H2C, 0);
3483         rtw89_write32(rtwdev, R_AX_HALT_C2H, 0);
3484
3485         rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);
3486
3487         val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL);
3488         val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY);
3489         val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE,
3490                                B_AX_WCPU_FWDL_STS_MASK);
3491
3492         if (dlfw)
3493                 val |= B_AX_WCPU_FWDL_EN;
3494
3495         rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val);
3496
3497         if (rtwdev->chip->chip_id == RTL8852B)
3498                 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL,
3499                                    B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2);
3500
3501         rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK,
3502                            boot_reason);
3503         rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN);
3504
3505         if (!dlfw) {
3506                 mdelay(5);
3507
3508                 ret = rtw89_fw_check_rdy(rtwdev);
3509                 if (ret)
3510                         return ret;
3511         }
3512
3513         return 0;
3514 }
3515
3516 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev)
3517 {
3518         enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3519         u32 val;
3520         int ret;
3521
3522         if (chip_id == RTL8852C)
3523                 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN |
3524                       B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN;
3525         else
3526                 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN |
3527                       B_AX_PKT_BUF_EN;
3528         rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val);
3529
3530         if (chip_id == RTL8851B)
3531                 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN;
3532         else
3533                 val = B_AX_DISPATCHER_CLK_EN;
3534         rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val);
3535
3536         if (chip_id != RTL8852C)
3537                 goto dle;
3538
3539         val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1);
3540         val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST);
3541         val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) |
3542                B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1;
3543         rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val);
3544
3545         rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1,
3546                           B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 |
3547                           B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 |
3548                           B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 |
3549                           B_AX_STOP_CH12 | B_AX_STOP_ACH2);
3550         rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11);
3551         rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN);
3552
3553 dle:
3554         ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode);
3555         if (ret) {
3556                 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret);
3557                 return ret;
3558         }
3559
3560         ret = hfc_init(rtwdev, true, false, true);
3561         if (ret) {
3562                 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret);
3563                 return ret;
3564         }
3565
3566         return ret;
3567 }
3568
3569 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
3570 {
3571         rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
3572                          B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
3573         rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL,
3574                           B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 |
3575                           B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1);
3576         rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
3577
3578         return 0;
3579 }
3580 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf);
3581
3582 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
3583 {
3584         rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
3585                          B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
3586         rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL,
3587                           B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 |
3588                           B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1);
3589         rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
3590
3591         return 0;
3592 }
3593 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf);
3594
3595 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev)
3596 {
3597         int ret;
3598
3599         ret = rtw89_mac_power_switch(rtwdev, true);
3600         if (ret) {
3601                 rtw89_mac_power_switch(rtwdev, false);
3602                 ret = rtw89_mac_power_switch(rtwdev, true);
3603                 if (ret)
3604                         return ret;
3605         }
3606
3607         rtw89_mac_ctrl_hci_dma_trx(rtwdev, true);
3608
3609         ret = rtw89_mac_dmac_pre_init(rtwdev);
3610         if (ret)
3611                 return ret;
3612
3613         if (rtwdev->hci.ops->mac_pre_init) {
3614                 ret = rtwdev->hci.ops->mac_pre_init(rtwdev);
3615                 if (ret)
3616                         return ret;
3617         }
3618
3619         ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL);
3620         if (ret)
3621                 return ret;
3622
3623         return 0;
3624 }
3625
3626 int rtw89_mac_init(struct rtw89_dev *rtwdev)
3627 {
3628         int ret;
3629
3630         ret = rtw89_mac_partial_init(rtwdev);
3631         if (ret)
3632                 goto fail;
3633
3634         ret = rtw89_chip_enable_bb_rf(rtwdev);
3635         if (ret)
3636                 goto fail;
3637
3638         ret = rtw89_mac_sys_init(rtwdev);
3639         if (ret)
3640                 goto fail;
3641
3642         ret = rtw89_mac_trx_init(rtwdev);
3643         if (ret)
3644                 goto fail;
3645
3646         if (rtwdev->hci.ops->mac_post_init) {
3647                 ret = rtwdev->hci.ops->mac_post_init(rtwdev);
3648                 if (ret)
3649                         goto fail;
3650         }
3651
3652         rtw89_fw_send_all_early_h2c(rtwdev);
3653         rtw89_fw_h2c_set_ofld_cfg(rtwdev);
3654
3655         return ret;
3656 fail:
3657         rtw89_mac_power_switch(rtwdev, false);
3658
3659         return ret;
3660 }
3661
3662 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)
3663 {
3664         u8 i;
3665
3666         if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
3667                 return;
3668
3669         for (i = 0; i < 4; i++) {
3670                 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR,
3671                               DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2));
3672                 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0);
3673         }
3674 }
3675
3676 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)
3677 {
3678         if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
3679                 return;
3680
3681         rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR,
3682                       CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE);
3683         rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4);
3684         rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004);
3685         rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0);
3686         rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0);
3687         rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0);
3688         rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B);
3689         rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0);
3690         rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109);
3691 }
3692
3693 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause)
3694 {
3695         u8 sh =  FIELD_GET(GENMASK(4, 0), macid);
3696         u8 grp = macid >> 5;
3697         int ret;
3698
3699         /* If this is called by change_interface() in the case of P2P, it could
3700          * be power-off, so ignore this operation.
3701          */
3702         if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) &&
3703             !test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
3704                 return 0;
3705
3706         ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
3707         if (ret)
3708                 return ret;
3709
3710         rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause);
3711
3712         return 0;
3713 }
3714
3715 static const struct rtw89_port_reg rtw_port_base = {
3716         .port_cfg = R_AX_PORT_CFG_P0,
3717         .tbtt_prohib = R_AX_TBTT_PROHIB_P0,
3718         .bcn_area = R_AX_BCN_AREA_P0,
3719         .bcn_early = R_AX_BCNERLYINT_CFG_P0,
3720         .tbtt_early = R_AX_TBTTERLYINT_CFG_P0,
3721         .tbtt_agg = R_AX_TBTT_AGG_P0,
3722         .bcn_space = R_AX_BCN_SPACE_CFG_P0,
3723         .bcn_forcetx = R_AX_BCN_FORCETX_P0,
3724         .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0,
3725         .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0,
3726         .dtim_ctrl = R_AX_DTIM_CTRL_P0,
3727         .tbtt_shift = R_AX_TBTT_SHIFT_P0,
3728         .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0,
3729         .tsftr_l = R_AX_TSFTR_LOW_P0,
3730         .tsftr_h = R_AX_TSFTR_HIGH_P0
3731 };
3732
3733 #define BCN_INTERVAL 100
3734 #define BCN_ERLY_DEF 160
3735 #define BCN_SETUP_DEF 2
3736 #define BCN_HOLD_DEF 200
3737 #define BCN_MASK_DEF 0
3738 #define TBTT_ERLY_DEF 5
3739 #define BCN_SET_UNIT 32
3740 #define BCN_ERLY_SET_DLY (10 * 2)
3741
3742 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev,
3743                                        struct rtw89_vif *rtwvif)
3744 {
3745         struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3746         const struct rtw89_port_reg *p = &rtw_port_base;
3747
3748         if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN))
3749                 return;
3750
3751         rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK);
3752         rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1);
3753         rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK);
3754         rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK);
3755
3756         msleep(vif->bss_conf.beacon_int + 1);
3757
3758         rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN |
3759                                                             B_AX_BRK_SETUP);
3760         rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST);
3761         rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0);
3762 }
3763
3764 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev,
3765                                       struct rtw89_vif *rtwvif, bool en)
3766 {
3767         const struct rtw89_port_reg *p = &rtw_port_base;
3768
3769         if (en)
3770                 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN);
3771         else
3772                 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN);
3773 }
3774
3775 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev,
3776                                       struct rtw89_vif *rtwvif, bool en)
3777 {
3778         const struct rtw89_port_reg *p = &rtw_port_base;
3779
3780         if (en)
3781                 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN);
3782         else
3783                 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN);
3784 }
3785
3786 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev,
3787                                         struct rtw89_vif *rtwvif)
3788 {
3789         const struct rtw89_port_reg *p = &rtw_port_base;
3790
3791         rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK,
3792                                 rtwvif->net_type);
3793 }
3794
3795 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev,
3796                                         struct rtw89_vif *rtwvif)
3797 {
3798         const struct rtw89_port_reg *p = &rtw_port_base;
3799         bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK;
3800         u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP;
3801
3802         if (en)
3803                 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits);
3804         else
3805                 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits);
3806 }
3807
3808 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev,
3809                                      struct rtw89_vif *rtwvif)
3810 {
3811         const struct rtw89_port_reg *p = &rtw_port_base;
3812         bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA ||
3813                   rtwvif->net_type == RTW89_NET_TYPE_AD_HOC;
3814         u32 bit = B_AX_RX_BSSID_FIT_EN;
3815
3816         if (en)
3817                 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit);
3818         else
3819                 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit);
3820 }
3821
3822 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev,
3823                                        struct rtw89_vif *rtwvif)
3824 {
3825         const struct rtw89_port_reg *p = &rtw_port_base;
3826         bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA ||
3827                   rtwvif->net_type == RTW89_NET_TYPE_AD_HOC;
3828
3829         if (en)
3830                 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN);
3831         else
3832                 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN);
3833 }
3834
3835 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev,
3836                                      struct rtw89_vif *rtwvif)
3837 {
3838         const struct rtw89_port_reg *p = &rtw_port_base;
3839         bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ||
3840                   rtwvif->net_type == RTW89_NET_TYPE_AD_HOC;
3841
3842         if (en)
3843                 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);
3844         else
3845                 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);
3846 }
3847
3848 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev,
3849                                         struct rtw89_vif *rtwvif)
3850 {
3851         struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3852         const struct rtw89_port_reg *p = &rtw_port_base;
3853         u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL;
3854
3855         rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK,
3856                                 bcn_int);
3857 }
3858
3859 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev,
3860                                        struct rtw89_vif *rtwvif)
3861 {
3862         static const u32 hiq_win_addr[RTW89_PORT_NUM] = {
3863                 R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG,
3864                 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2,
3865                 R_AX_PORT_HGQ_WINDOW_CFG + 3,
3866         };
3867         u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0;
3868         u8 port = rtwvif->port;
3869         u32 reg;
3870
3871         reg = rtw89_mac_reg_by_idx(rtwdev, hiq_win_addr[port], rtwvif->mac_idx);
3872         rtw89_write8(rtwdev, reg, win);
3873 }
3874
3875 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev,
3876                                         struct rtw89_vif *rtwvif)
3877 {
3878         struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3879         const struct rtw89_port_reg *p = &rtw_port_base;
3880         u32 addr;
3881
3882         addr = rtw89_mac_reg_by_idx(rtwdev, R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx);
3883         rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE);
3884
3885         rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK,
3886                                 vif->bss_conf.dtim_period);
3887 }
3888
3889 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev,
3890                                               struct rtw89_vif *rtwvif)
3891 {
3892         const struct rtw89_port_reg *p = &rtw_port_base;
3893
3894         rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib,
3895                                 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF);
3896 }
3897
3898 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev,
3899                                              struct rtw89_vif *rtwvif)
3900 {
3901         const struct rtw89_port_reg *p = &rtw_port_base;
3902
3903         rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib,
3904                                 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF);
3905 }
3906
3907 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev,
3908                                              struct rtw89_vif *rtwvif)
3909 {
3910         const struct rtw89_port_reg *p = &rtw_port_base;
3911
3912         rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area,
3913                                 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF);
3914 }
3915
3916 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev,
3917                                           struct rtw89_vif *rtwvif)
3918 {
3919         const struct rtw89_port_reg *p = &rtw_port_base;
3920
3921         rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early,
3922                                 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF);
3923 }
3924
3925 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev,
3926                                          struct rtw89_vif *rtwvif)
3927 {
3928         struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3929         static const u32 masks[RTW89_PORT_NUM] = {
3930                 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK,
3931                 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK,
3932                 B_AX_BSS_COLOB_AX_PORT_4_MASK,
3933         };
3934         u8 port = rtwvif->port;
3935         u32 reg_base;
3936         u32 reg;
3937         u8 bss_color;
3938
3939         bss_color = vif->bss_conf.he_bss_color.color;
3940         reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0;
3941         reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx);
3942         rtw89_write32_mask(rtwdev, reg, masks[port], bss_color);
3943 }
3944
3945 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev,
3946                                       struct rtw89_vif *rtwvif)
3947 {
3948         u8 port = rtwvif->port;
3949         u32 reg;
3950
3951         if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE)
3952                 return;
3953
3954         if (port == 0) {
3955                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MBSSID_CTRL, rtwvif->mac_idx);
3956                 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK);
3957         }
3958 }
3959
3960 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev,
3961                                         struct rtw89_vif *rtwvif)
3962 {
3963         u8 port = rtwvif->port;
3964         u32 reg;
3965         u32 val;
3966
3967         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MBSSID_DROP_0, rtwvif->mac_idx);
3968         val = rtw89_read32(rtwdev, reg);
3969         val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port));
3970         if (port == 0)
3971                 val &= ~BIT(0);
3972         rtw89_write32(rtwdev, reg, val);
3973 }
3974
3975 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev,
3976                                        struct rtw89_vif *rtwvif, bool enable)
3977 {
3978         const struct rtw89_port_reg *p = &rtw_port_base;
3979
3980         if (enable)
3981                 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg,
3982                                        B_AX_PORT_FUNC_EN);
3983         else
3984                 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg,
3985                                        B_AX_PORT_FUNC_EN);
3986 }
3987
3988 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev,
3989                                          struct rtw89_vif *rtwvif)
3990 {
3991         const struct rtw89_port_reg *p = &rtw_port_base;
3992
3993         rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK,
3994                                 BCN_ERLY_DEF);
3995 }
3996
3997 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev,
3998                                           struct rtw89_vif *rtwvif)
3999 {
4000         const struct rtw89_port_reg *p = &rtw_port_base;
4001         u16 val;
4002
4003         if (rtwdev->chip->chip_id != RTL8852C)
4004                 return;
4005
4006         if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT &&
4007             rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION)
4008                 return;
4009
4010         val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) |
4011                          B_AX_TBTT_SHIFT_OFST_SIGN;
4012
4013         rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift,
4014                                 B_AX_TBTT_SHIFT_OFST_MASK, val);
4015 }
4016
4017 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev,
4018                              struct rtw89_vif *rtwvif,
4019                              struct rtw89_vif *rtwvif_src,
4020                              u16 offset_tu)
4021 {
4022         u32 val, reg;
4023
4024         val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu);
4025         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PORT0_TSF_SYNC + rtwvif->port * 4,
4026                                    rtwvif->mac_idx);
4027
4028         rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port);
4029         rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val);
4030         rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW);
4031 }
4032
4033 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev,
4034                                          struct rtw89_vif *rtwvif,
4035                                          struct rtw89_vif *rtwvif_src,
4036                                          u8 offset, int *n_offset)
4037 {
4038         if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src)
4039                 return;
4040
4041         /* adjust offset randomly to avoid beacon conflict */
4042         offset = offset - offset / 4 + get_random_u32() % (offset / 2);
4043         rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src,
4044                                 (*n_offset) * offset);
4045
4046         (*n_offset)++;
4047 }
4048
4049 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev)
4050 {
4051         struct rtw89_vif *src = NULL, *tmp;
4052         u8 offset = 100, vif_aps = 0;
4053         int n_offset = 1;
4054
4055         rtw89_for_each_rtwvif(rtwdev, tmp) {
4056                 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA)
4057                         src = tmp;
4058                 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE)
4059                         vif_aps++;
4060         }
4061
4062         if (vif_aps == 0)
4063                 return;
4064
4065         offset /= (vif_aps + 1);
4066
4067         rtw89_for_each_rtwvif(rtwdev, tmp)
4068                 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset);
4069 }
4070
4071 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4072 {
4073         int ret;
4074
4075         ret = rtw89_mac_port_update(rtwdev, rtwvif);
4076         if (ret)
4077                 return ret;
4078
4079         rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id);
4080         rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id);
4081
4082         ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false);
4083         if (ret)
4084                 return ret;
4085
4086         ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE);
4087         if (ret)
4088                 return ret;
4089
4090         ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true);
4091         if (ret)
4092                 return ret;
4093
4094         ret = rtw89_cam_init(rtwdev, rtwvif);
4095         if (ret)
4096                 return ret;
4097
4098         ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL);
4099         if (ret)
4100                 return ret;
4101
4102         ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif);
4103         if (ret)
4104                 return ret;
4105
4106         return 0;
4107 }
4108
4109 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4110 {
4111         int ret;
4112
4113         ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE);
4114         if (ret)
4115                 return ret;
4116
4117         rtw89_cam_deinit(rtwdev, rtwvif);
4118
4119         ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL);
4120         if (ret)
4121                 return ret;
4122
4123         return 0;
4124 }
4125
4126 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4127 {
4128         u8 port = rtwvif->port;
4129
4130         if (port >= RTW89_PORT_NUM)
4131                 return -EINVAL;
4132
4133         rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif);
4134         rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false);
4135         rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false);
4136         rtw89_mac_port_cfg_net_type(rtwdev, rtwvif);
4137         rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif);
4138         rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif);
4139         rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif);
4140         rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif);
4141         rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif);
4142         rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif);
4143         rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif);
4144         rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif);
4145         rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif);
4146         rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif);
4147         rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif);
4148         rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif);
4149         rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif);
4150         rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif);
4151         rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif);
4152         rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true);
4153         rtw89_mac_port_tsf_resync_all(rtwdev);
4154         fsleep(BCN_ERLY_SET_DLY);
4155         rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif);
4156
4157         return 0;
4158 }
4159
4160 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4161                            u64 *tsf)
4162 {
4163         const struct rtw89_port_reg *p = &rtw_port_base;
4164         u32 tsf_low, tsf_high;
4165         int ret;
4166
4167         ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL);
4168         if (ret)
4169                 return ret;
4170
4171         tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l);
4172         tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h);
4173         *tsf = (u64)tsf_high << 32 | tsf_low;
4174
4175         return 0;
4176 }
4177
4178 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy,
4179                                                       struct cfg80211_bss *bss,
4180                                                       void *data)
4181 {
4182         const struct cfg80211_bss_ies *ies;
4183         const struct element *elem;
4184         bool *tolerated = data;
4185
4186         rcu_read_lock();
4187         ies = rcu_dereference(bss->ies);
4188         elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data,
4189                                   ies->len);
4190
4191         if (!elem || elem->datalen < 10 ||
4192             !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT))
4193                 *tolerated = false;
4194         rcu_read_unlock();
4195 }
4196
4197 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
4198                                         struct ieee80211_vif *vif)
4199 {
4200         struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
4201         struct ieee80211_hw *hw = rtwdev->hw;
4202         bool tolerated = true;
4203         u32 reg;
4204
4205         if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION)
4206                 return;
4207
4208         if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR))
4209                 return;
4210
4211         cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef,
4212                           rtw89_mac_check_he_obss_narrow_bw_ru_iter,
4213                           &tolerated);
4214
4215         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx);
4216         if (tolerated)
4217                 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS);
4218         else
4219                 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS);
4220 }
4221
4222 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4223 {
4224         rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false);
4225 }
4226
4227 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4228 {
4229         int ret;
4230
4231         rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map,
4232                                                     RTW89_MAX_MAC_ID_NUM);
4233         if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM)
4234                 return -ENOSPC;
4235
4236         ret = rtw89_mac_vif_init(rtwdev, rtwvif);
4237         if (ret)
4238                 goto release_mac_id;
4239
4240         return 0;
4241
4242 release_mac_id:
4243         rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id);
4244
4245         return ret;
4246 }
4247
4248 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4249 {
4250         int ret;
4251
4252         ret = rtw89_mac_vif_deinit(rtwdev, rtwvif);
4253         rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id);
4254
4255         return ret;
4256 }
4257
4258 static void
4259 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4260 {
4261 }
4262
4263 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel)
4264 {
4265         const struct rtw89_chan *op = &rtwdev->scan_info.op_chan;
4266
4267         return band == op->band_type && channel == op->primary_channel;
4268 }
4269
4270 static void
4271 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
4272                            u32 len)
4273 {
4274         struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
4275         struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif);
4276         struct rtw89_chan new;
4277         u8 reason, status, tx_fail, band, actual_period;
4278         u32 last_chan = rtwdev->scan_info.last_chan_idx;
4279         u16 chan;
4280         int ret;
4281
4282         if (!rtwvif)
4283                 return;
4284
4285         tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data);
4286         status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data);
4287         chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data);
4288         reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data);
4289         band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data);
4290         actual_period = RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h->data);
4291
4292         if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))
4293                 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G;
4294
4295         rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN,
4296                     "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n",
4297                     band, chan, reason, status, tx_fail, actual_period);
4298
4299         switch (reason) {
4300         case RTW89_SCAN_LEAVE_CH_NOTIFY:
4301                 if (rtw89_is_op_chan(rtwdev, band, chan))
4302                         ieee80211_stop_queues(rtwdev->hw);
4303                 return;
4304         case RTW89_SCAN_END_SCAN_NOTIFY:
4305                 if (rtwvif && rtwvif->scan_req &&
4306                     last_chan < rtwvif->scan_req->n_channels) {
4307                         ret = rtw89_hw_scan_offload(rtwdev, vif, true);
4308                         if (ret) {
4309                                 rtw89_hw_scan_abort(rtwdev, vif);
4310                                 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret);
4311                         }
4312                 } else {
4313                         rtw89_hw_scan_complete(rtwdev, vif, false);
4314                 }
4315                 break;
4316         case RTW89_SCAN_ENTER_CH_NOTIFY:
4317                 if (rtw89_is_op_chan(rtwdev, band, chan)) {
4318                         rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx,
4319                                                  &rtwdev->scan_info.op_chan);
4320                         ieee80211_wake_queues(rtwdev->hw);
4321                 } else {
4322                         rtw89_chan_create(&new, chan, chan, band,
4323                                           RTW89_CHANNEL_WIDTH_20);
4324                         rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx,
4325                                                  &new);
4326                 }
4327                 break;
4328         default:
4329                 return;
4330         }
4331 }
4332
4333 static void
4334 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4335                        struct sk_buff *skb)
4336 {
4337         struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif);
4338         enum nl80211_cqm_rssi_threshold_event nl_event;
4339         const struct rtw89_c2h_mac_bcnfltr_rpt *c2h =
4340                 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data;
4341         u8 type, event, mac_id;
4342         s8 sig;
4343
4344         type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE);
4345         sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI;
4346         event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT);
4347         mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID);
4348
4349         if (mac_id != rtwvif->mac_id)
4350                 return;
4351
4352         rtw89_debug(rtwdev, RTW89_DBG_FW,
4353                     "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n",
4354                     mac_id, type, sig, event);
4355
4356         switch (type) {
4357         case RTW89_BCN_FLTR_BEACON_LOSS:
4358                 if (!rtwdev->scanning && !rtwvif->offchan)
4359                         ieee80211_connection_loss(vif);
4360                 else
4361                         rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true);
4362                 return;
4363         case RTW89_BCN_FLTR_NOTIFY:
4364                 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH;
4365                 break;
4366         case RTW89_BCN_FLTR_RSSI:
4367                 if (event == RTW89_BCN_FLTR_RSSI_LOW)
4368                         nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW;
4369                 else if (event == RTW89_BCN_FLTR_RSSI_HIGH)
4370                         nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH;
4371                 else
4372                         return;
4373                 break;
4374         default:
4375                 return;
4376         }
4377
4378         ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL);
4379 }
4380
4381 static void
4382 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
4383                            u32 len)
4384 {
4385         struct rtw89_vif *rtwvif;
4386
4387         rtw89_for_each_rtwvif(rtwdev, rtwvif)
4388                 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h);
4389 }
4390
4391 static void
4392 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4393 {
4394         /* N.B. This will run in interrupt context. */
4395
4396         rtw89_debug(rtwdev, RTW89_DBG_FW,
4397                     "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n",
4398                     RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data),
4399                     RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data),
4400                     RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data),
4401                     RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data));
4402 }
4403
4404 static void
4405 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len)
4406 {
4407         /* N.B. This will run in interrupt context. */
4408         struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait;
4409         const struct rtw89_c2h_done_ack *c2h =
4410                 (const struct rtw89_c2h_done_ack *)skb_c2h->data;
4411         u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT);
4412         u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS);
4413         u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC);
4414         u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN);
4415         u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ);
4416         struct rtw89_completion_data data = {};
4417         unsigned int cond;
4418
4419         rtw89_debug(rtwdev, RTW89_DBG_FW,
4420                     "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n",
4421                     h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq);
4422
4423         if (h2c_cat != H2C_CAT_MAC)
4424                 return;
4425
4426         switch (h2c_class) {
4427         default:
4428                 return;
4429         case H2C_CL_MAC_FW_OFLD:
4430                 switch (h2c_func) {
4431                 default:
4432                         return;
4433                 case H2C_FUNC_ADD_SCANOFLD_CH:
4434                 case H2C_FUNC_SCANOFLD:
4435                         cond = RTW89_FW_OFLD_WAIT_COND(0, h2c_func);
4436                         break;
4437                 }
4438
4439                 data.err = !!h2c_return;
4440                 rtw89_complete_cond(fw_ofld_wait, cond, &data);
4441                 return;
4442         }
4443 }
4444
4445 static void
4446 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4447 {
4448         rtw89_fw_log_dump(rtwdev, c2h->data, len);
4449 }
4450
4451 static void
4452 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4453 {
4454 }
4455
4456 static void
4457 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h,
4458                            u32 len)
4459 {
4460         struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
4461         const struct rtw89_c2h_pkt_ofld_rsp *c2h =
4462                 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data;
4463         u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN);
4464         u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID);
4465         u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP);
4466         struct rtw89_completion_data data = {};
4467         unsigned int cond;
4468
4469         rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n",
4470                     pkt_id, pkt_op, pkt_len);
4471
4472         data.err = !pkt_len;
4473         cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op);
4474
4475         rtw89_complete_cond(wait, cond, &data);
4476 }
4477
4478 static void
4479 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
4480                                u32 len)
4481 {
4482 }
4483
4484 static void
4485 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4486 {
4487         u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data);
4488         u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data);
4489
4490         switch (func) {
4491         case H2C_FUNC_ADD_MCC:
4492         case H2C_FUNC_START_MCC:
4493         case H2C_FUNC_STOP_MCC:
4494         case H2C_FUNC_DEL_MCC_GROUP:
4495         case H2C_FUNC_RESET_MCC_GROUP:
4496         case H2C_FUNC_MCC_REQ_TSF:
4497         case H2C_FUNC_MCC_MACID_BITMAP:
4498         case H2C_FUNC_MCC_SYNC:
4499         case H2C_FUNC_MCC_SET_DURATION:
4500                 break;
4501         default:
4502                 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4503                             "invalid MCC C2H RCV ACK: func %d\n", func);
4504                 return;
4505         }
4506
4507         rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4508                     "MCC C2H RCV ACK: group %d, func %d\n", group, func);
4509 }
4510
4511 static void
4512 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4513 {
4514         u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data);
4515         u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data);
4516         u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data);
4517         struct rtw89_completion_data data = {};
4518         unsigned int cond;
4519         bool next = false;
4520
4521         switch (func) {
4522         case H2C_FUNC_MCC_REQ_TSF:
4523                 next = true;
4524                 break;
4525         case H2C_FUNC_MCC_MACID_BITMAP:
4526         case H2C_FUNC_MCC_SYNC:
4527         case H2C_FUNC_MCC_SET_DURATION:
4528                 break;
4529         case H2C_FUNC_ADD_MCC:
4530         case H2C_FUNC_START_MCC:
4531         case H2C_FUNC_STOP_MCC:
4532         case H2C_FUNC_DEL_MCC_GROUP:
4533         case H2C_FUNC_RESET_MCC_GROUP:
4534         default:
4535                 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4536                             "invalid MCC C2H REQ ACK: func %d\n", func);
4537                 return;
4538         }
4539
4540         rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4541                     "MCC C2H REQ ACK: group %d, func %d, return code %d\n",
4542                     group, func, retcode);
4543
4544         if (!retcode && next)
4545                 return;
4546
4547         data.err = !!retcode;
4548         cond = RTW89_MCC_WAIT_COND(group, func);
4549         rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
4550 }
4551
4552 static void
4553 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4554 {
4555         u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data);
4556         struct rtw89_completion_data data = {};
4557         struct rtw89_mac_mcc_tsf_rpt *rpt;
4558         unsigned int cond;
4559
4560         rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf;
4561         rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data);
4562         rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data);
4563         rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data);
4564         rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data);
4565         rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data);
4566         rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data);
4567
4568         rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4569                     "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n",
4570                     rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low,
4571                     rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low);
4572
4573         cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF);
4574         rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
4575 }
4576
4577 static void
4578 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4579 {
4580         u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data);
4581         u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data);
4582         u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data);
4583         u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data);
4584         u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data);
4585         struct rtw89_completion_data data = {};
4586         unsigned int cond;
4587         bool rsp = true;
4588         bool err;
4589         u8 func;
4590
4591         switch (status) {
4592         case RTW89_MAC_MCC_ADD_ROLE_OK:
4593         case RTW89_MAC_MCC_ADD_ROLE_FAIL:
4594                 func = H2C_FUNC_ADD_MCC;
4595                 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL;
4596                 break;
4597         case RTW89_MAC_MCC_START_GROUP_OK:
4598         case RTW89_MAC_MCC_START_GROUP_FAIL:
4599                 func = H2C_FUNC_START_MCC;
4600                 err = status == RTW89_MAC_MCC_START_GROUP_FAIL;
4601                 break;
4602         case RTW89_MAC_MCC_STOP_GROUP_OK:
4603         case RTW89_MAC_MCC_STOP_GROUP_FAIL:
4604                 func = H2C_FUNC_STOP_MCC;
4605                 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL;
4606                 break;
4607         case RTW89_MAC_MCC_DEL_GROUP_OK:
4608         case RTW89_MAC_MCC_DEL_GROUP_FAIL:
4609                 func = H2C_FUNC_DEL_MCC_GROUP;
4610                 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL;
4611                 break;
4612         case RTW89_MAC_MCC_RESET_GROUP_OK:
4613         case RTW89_MAC_MCC_RESET_GROUP_FAIL:
4614                 func = H2C_FUNC_RESET_MCC_GROUP;
4615                 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL;
4616                 break;
4617         case RTW89_MAC_MCC_SWITCH_CH_OK:
4618         case RTW89_MAC_MCC_SWITCH_CH_FAIL:
4619         case RTW89_MAC_MCC_TXNULL0_OK:
4620         case RTW89_MAC_MCC_TXNULL0_FAIL:
4621         case RTW89_MAC_MCC_TXNULL1_OK:
4622         case RTW89_MAC_MCC_TXNULL1_FAIL:
4623         case RTW89_MAC_MCC_SWITCH_EARLY:
4624         case RTW89_MAC_MCC_TBTT:
4625         case RTW89_MAC_MCC_DURATION_START:
4626         case RTW89_MAC_MCC_DURATION_END:
4627                 rsp = false;
4628                 break;
4629         default:
4630                 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4631                             "invalid MCC C2H STS RPT: status %d\n", status);
4632                 return;
4633         }
4634
4635         rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4636                     "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n",
4637                      group, macid, status, (u64)tsf_high << 32 | tsf_low);
4638
4639         if (!rsp)
4640                 return;
4641
4642         data.err = err;
4643         cond = RTW89_MCC_WAIT_COND(group, func);
4644         rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
4645 }
4646
4647 static
4648 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev,
4649                                             struct sk_buff *c2h, u32 len) = {
4650         [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL,
4651         [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL,
4652         [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp,
4653         [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL,
4654         [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause,
4655         [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp,
4656         [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt,
4657         [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt,
4658 };
4659
4660 static
4661 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev,
4662                                             struct sk_buff *c2h, u32 len) = {
4663         [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack,
4664         [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack,
4665         [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log,
4666         [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt,
4667 };
4668
4669 static
4670 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev,
4671                                            struct sk_buff *c2h, u32 len) = {
4672         [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack,
4673         [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack,
4674         [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt,
4675         [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt,
4676 };
4677
4678 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func)
4679 {
4680         switch (class) {
4681         default:
4682                 return false;
4683         case RTW89_MAC_C2H_CLASS_INFO:
4684                 switch (func) {
4685                 default:
4686                         return false;
4687                 case RTW89_MAC_C2H_FUNC_REC_ACK:
4688                 case RTW89_MAC_C2H_FUNC_DONE_ACK:
4689                         return true;
4690                 }
4691         case RTW89_MAC_C2H_CLASS_OFLD:
4692                 switch (func) {
4693                 default:
4694                         return false;
4695                 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP:
4696                         return true;
4697                 }
4698         case RTW89_MAC_C2H_CLASS_MCC:
4699                 return true;
4700         }
4701 }
4702
4703 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
4704                           u32 len, u8 class, u8 func)
4705 {
4706         void (*handler)(struct rtw89_dev *rtwdev,
4707                         struct sk_buff *c2h, u32 len) = NULL;
4708
4709         switch (class) {
4710         case RTW89_MAC_C2H_CLASS_INFO:
4711                 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX)
4712                         handler = rtw89_mac_c2h_info_handler[func];
4713                 break;
4714         case RTW89_MAC_C2H_CLASS_OFLD:
4715                 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX)
4716                         handler = rtw89_mac_c2h_ofld_handler[func];
4717                 break;
4718         case RTW89_MAC_C2H_CLASS_MCC:
4719                 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC)
4720                         handler = rtw89_mac_c2h_mcc_handler[func];
4721                 break;
4722         case RTW89_MAC_C2H_CLASS_FWDBG:
4723                 return;
4724         default:
4725                 rtw89_info(rtwdev, "c2h class %d not support\n", class);
4726                 return;
4727         }
4728         if (!handler) {
4729                 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class,
4730                            func);
4731                 return;
4732         }
4733         handler(rtwdev, skb, len);
4734 }
4735
4736 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev,
4737                             enum rtw89_phy_idx phy_idx,
4738                             u32 reg_base, u32 *cr)
4739 {
4740         const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem;
4741         enum rtw89_qta_mode mode = dle_mem->mode;
4742         u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx);
4743
4744         if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) {
4745                 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n",
4746                           addr);
4747                 goto error;
4748         }
4749
4750         if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR)
4751                 if (mode == RTW89_QTA_SCC) {
4752                         rtw89_err(rtwdev,
4753                                   "[TXPWR] addr=0x%x but hw not enable\n",
4754                                   addr);
4755                         goto error;
4756                 }
4757
4758         *cr = addr;
4759         return true;
4760
4761 error:
4762         rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n",
4763                   addr, phy_idx);
4764
4765         return false;
4766 }
4767 EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr);
4768
4769 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
4770 {
4771         u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx);
4772         int ret;
4773
4774         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4775         if (ret)
4776                 return ret;
4777
4778         if (!enable) {
4779                 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN);
4780                 return 0;
4781         }
4782
4783         rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN |
4784                                    B_AX_APP_MAC_INFO_RPT |
4785                                    B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT |
4786                                    B_AX_PPDU_STAT_RPT_CRC32);
4787         rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK,
4788                            RTW89_PRPT_DEST_HOST);
4789
4790         return 0;
4791 }
4792 EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status);
4793
4794 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx)
4795 {
4796 #define MAC_AX_TIME_TH_SH  5
4797 #define MAC_AX_LEN_TH_SH   4
4798 #define MAC_AX_TIME_TH_MAX 255
4799 #define MAC_AX_LEN_TH_MAX  255
4800 #define MAC_AX_TIME_TH_DEF 88
4801 #define MAC_AX_LEN_TH_DEF  4080
4802         struct ieee80211_hw *hw = rtwdev->hw;
4803         u32 rts_threshold = hw->wiphy->rts_threshold;
4804         u32 time_th, len_th;
4805         u32 reg;
4806
4807         if (rts_threshold == (u32)-1) {
4808                 time_th = MAC_AX_TIME_TH_DEF;
4809                 len_th = MAC_AX_LEN_TH_DEF;
4810         } else {
4811                 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH;
4812                 len_th = rts_threshold;
4813         }
4814
4815         time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX);
4816         len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX);
4817
4818         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_HT_0, mac_idx);
4819         rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th);
4820         rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th);
4821 }
4822
4823 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop)
4824 {
4825         bool empty;
4826         int ret;
4827
4828         if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
4829                 return;
4830
4831         ret = read_poll_timeout(dle_is_txq_empty, empty, empty,
4832                                 10000, 200000, false, rtwdev);
4833         if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning))
4834                 rtw89_info(rtwdev, "timed out to flush queues\n");
4835 }
4836
4837 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex)
4838 {
4839         u8 val;
4840         u16 val16;
4841         u32 val32;
4842         int ret;
4843
4844         rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT);
4845         if (rtwdev->chip->chip_id != RTL8851B)
4846                 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN);
4847         rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8);
4848         rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK);
4849         rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16);
4850         if (rtwdev->chip->chip_id != RTL8851B)
4851                 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24);
4852
4853         val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0);
4854         val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN;
4855         rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16);
4856
4857         ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32);
4858         if (ret) {
4859                 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n");
4860                 return ret;
4861         }
4862         val32 = val32 & B_AX_WL_RX_CTRL;
4863         ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32);
4864         if (ret) {
4865                 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n");
4866                 return ret;
4867         }
4868
4869         switch (coex->pta_mode) {
4870         case RTW89_MAC_AX_COEX_RTK_MODE:
4871                 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
4872                 val &= ~B_AX_BTMODE_MASK;
4873                 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3);
4874                 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
4875
4876                 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE);
4877                 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE);
4878
4879                 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5);
4880                 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK;
4881                 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE);
4882                 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val);
4883                 break;
4884         case RTW89_MAC_AX_COEX_CSR_MODE:
4885                 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
4886                 val &= ~B_AX_BTMODE_MASK;
4887                 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2);
4888                 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
4889
4890                 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE);
4891                 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK;
4892                 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO);
4893                 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK;
4894                 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO);
4895                 val16 &= ~B_AX_BT_STAT_DELAY_MASK;
4896                 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY);
4897                 val16 |= B_AX_ENHANCED_BT;
4898                 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16);
4899
4900                 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE);
4901                 break;
4902         default:
4903                 return -EINVAL;
4904         }
4905
4906         switch (coex->direction) {
4907         case RTW89_MAC_AX_COEX_INNER:
4908                 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
4909                 val = (val & ~BIT(2)) | BIT(1);
4910                 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
4911                 break;
4912         case RTW89_MAC_AX_COEX_OUTPUT:
4913                 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
4914                 val = val | BIT(1) | BIT(0);
4915                 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
4916                 break;
4917         case RTW89_MAC_AX_COEX_INPUT:
4918                 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
4919                 val = val & ~(BIT(2) | BIT(1));
4920                 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
4921                 break;
4922         default:
4923                 return -EINVAL;
4924         }
4925
4926         return 0;
4927 }
4928 EXPORT_SYMBOL(rtw89_mac_coex_init);
4929
4930 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
4931                            const struct rtw89_mac_ax_coex *coex)
4932 {
4933         rtw89_write32_set(rtwdev, R_AX_BTC_CFG,
4934                           B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL);
4935         rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN);
4936         rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN);
4937         rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN);
4938
4939         switch (coex->pta_mode) {
4940         case RTW89_MAC_AX_COEX_RTK_MODE:
4941                 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,
4942                                    MAC_AX_RTK_MODE);
4943                 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1,
4944                                    B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE);
4945                 break;
4946         case RTW89_MAC_AX_COEX_CSR_MODE:
4947                 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,
4948                                    MAC_AX_CSR_MODE);
4949                 break;
4950         default:
4951                 return -EINVAL;
4952         }
4953
4954         return 0;
4955 }
4956 EXPORT_SYMBOL(rtw89_mac_coex_init_v1);
4957
4958 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
4959                       const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
4960 {
4961         u32 val = 0, ret;
4962
4963         if (gnt_cfg->band[0].gnt_bt)
4964                 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL;
4965
4966         if (gnt_cfg->band[0].gnt_bt_sw_en)
4967                 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL;
4968
4969         if (gnt_cfg->band[0].gnt_wl)
4970                 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL;
4971
4972         if (gnt_cfg->band[0].gnt_wl_sw_en)
4973                 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL;
4974
4975         if (gnt_cfg->band[1].gnt_bt)
4976                 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL;
4977
4978         if (gnt_cfg->band[1].gnt_bt_sw_en)
4979                 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL;
4980
4981         if (gnt_cfg->band[1].gnt_wl)
4982                 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL;
4983
4984         if (gnt_cfg->band[1].gnt_wl_sw_en)
4985                 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL;
4986
4987         ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val);
4988         if (ret) {
4989                 rtw89_err(rtwdev, "Write LTE fail!\n");
4990                 return ret;
4991         }
4992
4993         return 0;
4994 }
4995 EXPORT_SYMBOL(rtw89_mac_cfg_gnt);
4996
4997 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
4998                          const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
4999 {
5000         u32 val = 0;
5001
5002         if (gnt_cfg->band[0].gnt_bt)
5003                 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL |
5004                        B_AX_GNT_BT_TX_VAL;
5005         else
5006                 val |= B_AX_WL_ACT_VAL;
5007
5008         if (gnt_cfg->band[0].gnt_bt_sw_en)
5009                 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL |
5010                        B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL;
5011
5012         if (gnt_cfg->band[0].gnt_wl)
5013                 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL |
5014                        B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL;
5015
5016         if (gnt_cfg->band[0].gnt_wl_sw_en)
5017                 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL |
5018                        B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL;
5019
5020         if (gnt_cfg->band[1].gnt_bt)
5021                 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL |
5022                        B_AX_GNT_BT_TX_VAL;
5023         else
5024                 val |= B_AX_WL_ACT_VAL;
5025
5026         if (gnt_cfg->band[1].gnt_bt_sw_en)
5027                 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL |
5028                        B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL;
5029
5030         if (gnt_cfg->band[1].gnt_wl)
5031                 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL |
5032                        B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL;
5033
5034         if (gnt_cfg->band[1].gnt_wl_sw_en)
5035                 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL |
5036                        B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL;
5037
5038         rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val);
5039
5040         return 0;
5041 }
5042 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1);
5043
5044 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
5045 {
5046         u32 reg;
5047         u16 val;
5048         int ret;
5049
5050         ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL);
5051         if (ret)
5052                 return ret;
5053
5054         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band);
5055         val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) |
5056               (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) |
5057               (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) |
5058               (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) |
5059               (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) |
5060               (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) |
5061               (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) |
5062               (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) |
5063               B_AX_PLT_EN;
5064         rtw89_write16(rtwdev, reg, val);
5065
5066         return 0;
5067 }
5068
5069 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val)
5070 {
5071         u32 fw_sb;
5072
5073         fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD);
5074         fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb);
5075         fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY;
5076         if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
5077                 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR;
5078         else
5079                 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR;
5080         val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val);
5081         val = B_AX_TOGGLE |
5082               FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) |
5083               FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb);
5084         rtw89_write32(rtwdev, R_AX_SCOREBOARD, val);
5085         fsleep(1000); /* avoid BT FW loss information */
5086 }
5087
5088 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev)
5089 {
5090         return rtw89_read32(rtwdev, R_AX_SCOREBOARD);
5091 }
5092
5093 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
5094 {
5095         u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3);
5096
5097         val = wl ? val | BIT(2) : val & ~BIT(2);
5098         rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val);
5099
5100         return 0;
5101 }
5102 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path);
5103
5104 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl)
5105 {
5106         struct rtw89_btc *btc = &rtwdev->btc;
5107         struct rtw89_btc_dm *dm = &btc->dm;
5108         struct rtw89_mac_ax_gnt *g = dm->gnt.band;
5109         int i;
5110
5111         if (wl)
5112                 return 0;
5113
5114         for (i = 0; i < RTW89_PHY_MAX; i++) {
5115                 g[i].gnt_bt_sw_en = 1;
5116                 g[i].gnt_bt = 1;
5117                 g[i].gnt_wl_sw_en = 1;
5118                 g[i].gnt_wl = 0;
5119         }
5120
5121         return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt);
5122 }
5123 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1);
5124
5125 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev)
5126 {
5127         const struct rtw89_chip_info *chip = rtwdev->chip;
5128         u8 val = 0;
5129
5130         if (chip->chip_id == RTL8852C)
5131                 return false;
5132         else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B)
5133                 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3,
5134                                        B_AX_LTE_MUX_CTRL_PATH >> 24);
5135
5136         return !!val;
5137 }
5138
5139 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band)
5140 {
5141         u32 reg;
5142         u16 cnt;
5143
5144         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band);
5145         cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK);
5146         rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST);
5147
5148         return cnt;
5149 }
5150
5151 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx,
5152                                          bool keep)
5153 {
5154         u32 reg;
5155
5156         rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep);
5157         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx);
5158         if (keep) {
5159                 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
5160                 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK,
5161                                    BFRP_RX_STANDBY_TIMER_KEEP);
5162         } else {
5163                 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
5164                 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK,
5165                                    BFRP_RX_STANDBY_TIMER_RELEASE);
5166         }
5167 }
5168
5169 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
5170 {
5171         u32 reg;
5172         u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN |
5173                    B_AX_BFMEE_HE_NDPA_EN;
5174
5175         rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en);
5176         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx);
5177         if (en) {
5178                 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
5179                 rtw89_write32_set(rtwdev, reg, mask);
5180         } else {
5181                 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
5182                 rtw89_write32_clr(rtwdev, reg, mask);
5183         }
5184 }
5185
5186 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx)
5187 {
5188         u32 reg;
5189         u32 val32;
5190         int ret;
5191
5192         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5193         if (ret)
5194                 return ret;
5195
5196         /* AP mode set tx gid to 63 */
5197         /* STA mode set tx gid to 0(default) */
5198         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx);
5199         rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN);
5200
5201         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx);
5202         rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP);
5203
5204         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx);
5205         val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER);
5206         rtw89_write32(rtwdev, reg, val32);
5207         rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true);
5208         rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true);
5209
5210         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
5211         rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL |
5212                                        B_AX_BFMEE_USE_NSTS |
5213                                        B_AX_BFMEE_CSI_GID_SEL |
5214                                        B_AX_BFMEE_CSI_FORCE_RETE_EN);
5215         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx);
5216         rtw89_write32(rtwdev, reg,
5217                       u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) |
5218                       u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) |
5219                       u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK));
5220
5221         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx);
5222         rtw89_write32_set(rtwdev, reg,
5223                           B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN);
5224
5225         return 0;
5226 }
5227
5228 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev,
5229                                       struct ieee80211_vif *vif,
5230                                       struct ieee80211_sta *sta)
5231 {
5232         struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
5233         u8 mac_idx = rtwvif->mac_idx;
5234         u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1;
5235         u8 port_sel = rtwvif->port;
5236         u8 sound_dim = 3, t;
5237         u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info;
5238         u32 reg;
5239         u16 val;
5240         int ret;
5241
5242         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5243         if (ret)
5244                 return ret;
5245
5246         if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
5247             (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) {
5248                 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD);
5249                 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ);
5250                 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
5251                               phy_cap[5]);
5252                 sound_dim = min(sound_dim, t);
5253         }
5254         if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
5255             (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {
5256                 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC);
5257                 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK);
5258                 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK,
5259                               sta->deflink.vht_cap.cap);
5260                 sound_dim = min(sound_dim, t);
5261         }
5262         nc = min(nc, sound_dim);
5263         nr = min(nr, sound_dim);
5264
5265         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
5266         rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);
5267
5268         val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) |
5269               FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) |
5270               FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) |
5271               FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) |
5272               FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) |
5273               FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) |
5274               FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en);
5275
5276         if (port_sel == 0)
5277                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
5278         else
5279                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx);
5280
5281         rtw89_write16(rtwdev, reg, val);
5282
5283         return 0;
5284 }
5285
5286 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev,
5287                               struct ieee80211_vif *vif,
5288                               struct ieee80211_sta *sta)
5289 {
5290         struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
5291         u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M);
5292         u32 reg;
5293         u8 mac_idx = rtwvif->mac_idx;
5294         int ret;
5295
5296         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5297         if (ret)
5298                 return ret;
5299
5300         if (sta->deflink.he_cap.has_he) {
5301                 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) |
5302                          BIT(RTW89_MAC_BF_RRSC_HE_MSC3) |
5303                          BIT(RTW89_MAC_BF_RRSC_HE_MSC5));
5304         }
5305         if (sta->deflink.vht_cap.vht_supported) {
5306                 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) |
5307                          BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) |
5308                          BIT(RTW89_MAC_BF_RRSC_VHT_MSC5));
5309         }
5310         if (sta->deflink.ht_cap.ht_supported) {
5311                 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) |
5312                          BIT(RTW89_MAC_BF_RRSC_HT_MSC3) |
5313                          BIT(RTW89_MAC_BF_RRSC_HT_MSC5));
5314         }
5315         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
5316         rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);
5317         rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN);
5318         rtw89_write32(rtwdev,
5319                       rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx),
5320                       rrsc);
5321
5322         return 0;
5323 }
5324
5325 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
5326                         struct ieee80211_sta *sta)
5327 {
5328         struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
5329
5330         if (rtw89_sta_has_beamformer_cap(sta)) {
5331                 rtw89_debug(rtwdev, RTW89_DBG_BF,
5332                             "initialize bfee for new association\n");
5333                 rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx);
5334                 rtw89_mac_set_csi_para_reg(rtwdev, vif, sta);
5335                 rtw89_mac_csi_rrsc(rtwdev, vif, sta);
5336         }
5337 }
5338
5339 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
5340                            struct ieee80211_sta *sta)
5341 {
5342         struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
5343
5344         rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false);
5345 }
5346
5347 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
5348                                 struct ieee80211_bss_conf *conf)
5349 {
5350         struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
5351         u8 mac_idx = rtwvif->mac_idx;
5352         __le32 *p;
5353
5354         rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n");
5355
5356         p = (__le32 *)conf->mu_group.membership;
5357         rtw89_write32(rtwdev,
5358                       rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx),
5359                       le32_to_cpu(p[0]));
5360         rtw89_write32(rtwdev,
5361                       rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx),
5362                       le32_to_cpu(p[1]));
5363
5364         p = (__le32 *)conf->mu_group.position;
5365         rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx),
5366                       le32_to_cpu(p[0]));
5367         rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx),
5368                       le32_to_cpu(p[1]));
5369         rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx),
5370                       le32_to_cpu(p[2]));
5371         rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx),
5372                       le32_to_cpu(p[3]));
5373 }
5374
5375 struct rtw89_mac_bf_monitor_iter_data {
5376         struct rtw89_dev *rtwdev;
5377         struct ieee80211_sta *down_sta;
5378         int count;
5379 };
5380
5381 static
5382 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta)
5383 {
5384         struct rtw89_mac_bf_monitor_iter_data *iter_data =
5385                                 (struct rtw89_mac_bf_monitor_iter_data *)data;
5386         struct ieee80211_sta *down_sta = iter_data->down_sta;
5387         int *count = &iter_data->count;
5388
5389         if (down_sta == sta)
5390                 return;
5391
5392         if (rtw89_sta_has_beamformer_cap(sta))
5393                 (*count)++;
5394 }
5395
5396 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
5397                                struct ieee80211_sta *sta, bool disconnect)
5398 {
5399         struct rtw89_mac_bf_monitor_iter_data data;
5400
5401         data.rtwdev = rtwdev;
5402         data.down_sta = disconnect ? sta : NULL;
5403         data.count = 0;
5404         ieee80211_iterate_stations_atomic(rtwdev->hw,
5405                                           rtw89_mac_bf_monitor_calc_iter,
5406                                           &data);
5407
5408         rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count);
5409         if (data.count)
5410                 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
5411         else
5412                 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
5413 }
5414
5415 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
5416 {
5417         struct rtw89_traffic_stats *stats = &rtwdev->stats;
5418         struct rtw89_vif *rtwvif;
5419         bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv;
5420         bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
5421         bool keep_timer = true;
5422         bool old_keep_timer;
5423
5424         old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
5425
5426         if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW)
5427                 keep_timer = false;
5428
5429         if (keep_timer != old_keep_timer) {
5430                 rtw89_for_each_rtwvif(rtwdev, rtwvif)
5431                         rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx,
5432                                                      keep_timer);
5433         }
5434
5435         if (en == old)
5436                 return;
5437
5438         rtw89_for_each_rtwvif(rtwdev, rtwvif)
5439                 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en);
5440 }
5441
5442 static int
5443 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
5444                         u32 tx_time)
5445 {
5446 #define MAC_AX_DFLT_TX_TIME 5280
5447         u8 mac_idx = rtwsta->rtwvif->mac_idx;
5448         u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time;
5449         u32 reg;
5450         int ret = 0;
5451
5452         if (rtwsta->cctl_tx_time) {
5453                 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9;
5454                 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);
5455         } else {
5456                 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5457                 if (ret) {
5458                         rtw89_warn(rtwdev, "failed to check cmac in set txtime\n");
5459                         return ret;
5460                 }
5461
5462                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx);
5463                 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK,
5464                                    max_tx_time >> 5);
5465         }
5466
5467         return ret;
5468 }
5469
5470 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
5471                           bool resume, u32 tx_time)
5472 {
5473         int ret = 0;
5474
5475         if (!resume) {
5476                 rtwsta->cctl_tx_time = true;
5477                 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time);
5478         } else {
5479                 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time);
5480                 rtwsta->cctl_tx_time = false;
5481         }
5482
5483         return ret;
5484 }
5485
5486 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
5487                           u32 *tx_time)
5488 {
5489         u8 mac_idx = rtwsta->rtwvif->mac_idx;
5490         u32 reg;
5491         int ret = 0;
5492
5493         if (rtwsta->cctl_tx_time) {
5494                 *tx_time = (rtwsta->ampdu_max_time + 1) << 9;
5495         } else {
5496                 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5497                 if (ret) {
5498                         rtw89_warn(rtwdev, "failed to check cmac in tx_time\n");
5499                         return ret;
5500                 }
5501
5502                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx);
5503                 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5;
5504         }
5505
5506         return ret;
5507 }
5508
5509 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
5510                                  struct rtw89_sta *rtwsta,
5511                                  bool resume, u8 tx_retry)
5512 {
5513         int ret = 0;
5514
5515         rtwsta->data_tx_cnt_lmt = tx_retry;
5516
5517         if (!resume) {
5518                 rtwsta->cctl_tx_retry_limit = true;
5519                 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);
5520         } else {
5521                 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);
5522                 rtwsta->cctl_tx_retry_limit = false;
5523         }
5524
5525         return ret;
5526 }
5527
5528 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
5529                                  struct rtw89_sta *rtwsta, u8 *tx_retry)
5530 {
5531         u8 mac_idx = rtwsta->rtwvif->mac_idx;
5532         u32 reg;
5533         int ret = 0;
5534
5535         if (rtwsta->cctl_tx_retry_limit) {
5536                 *tx_retry = rtwsta->data_tx_cnt_lmt;
5537         } else {
5538                 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5539                 if (ret) {
5540                         rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n");
5541                         return ret;
5542                 }
5543
5544                 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx);
5545                 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK);
5546         }
5547
5548         return ret;
5549 }
5550
5551 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
5552                                  struct rtw89_vif *rtwvif, bool en)
5553 {
5554         u8 mac_idx = rtwvif->mac_idx;
5555         u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0;
5556         u32 reg;
5557         u32 ret;
5558
5559         ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5560         if (ret)
5561                 return ret;
5562
5563         reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MUEDCA_EN, mac_idx);
5564         if (en)
5565                 rtw89_write16_set(rtwdev, reg, set);
5566         else
5567                 rtw89_write16_clr(rtwdev, reg, set);
5568
5569         return 0;
5570 }
5571
5572 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
5573 {
5574         u32 val32;
5575         int ret;
5576
5577         val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) |
5578                 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) |
5579                 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) |
5580                 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) |
5581                 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1);
5582         rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32);
5583
5584         ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL),
5585                                 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL);
5586         if (ret) {
5587                 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n",
5588                            offset, val, mask);
5589                 return ret;
5590         }
5591
5592         return 0;
5593 }
5594 EXPORT_SYMBOL(rtw89_mac_write_xtal_si);
5595
5596 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
5597 {
5598         u32 val32;
5599         int ret;
5600
5601         val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) |
5602                 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) |
5603                 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) |
5604                 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) |
5605                 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1);
5606         rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32);
5607
5608         ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL),
5609                                 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL);
5610         if (ret) {
5611                 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset);
5612                 return ret;
5613         }
5614
5615         *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1);
5616
5617         return 0;
5618 }
5619 EXPORT_SYMBOL(rtw89_mac_read_xtal_si);
5620
5621 static
5622 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta)
5623 {
5624         static const enum rtw89_pkt_drop_sel sels[] = {
5625                 RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
5626                 RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
5627                 RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
5628                 RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
5629         };
5630         struct rtw89_vif *rtwvif = rtwsta->rtwvif;
5631         struct rtw89_pkt_drop_params params = {0};
5632         int i;
5633
5634         params.mac_band = RTW89_MAC_0;
5635         params.macid = rtwsta->mac_id;
5636         params.port = rtwvif->port;
5637         params.mbssid = 0;
5638         params.tf_trs = rtwvif->trigger;
5639
5640         for (i = 0; i < ARRAY_SIZE(sels); i++) {
5641                 params.sel = sels[i];
5642                 rtw89_fw_h2c_pkt_drop(rtwdev, &params);
5643         }
5644 }
5645
5646 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta)
5647 {
5648         struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
5649         struct rtw89_vif *rtwvif = rtwsta->rtwvif;
5650         struct rtw89_dev *rtwdev = rtwvif->rtwdev;
5651         struct rtw89_vif *target = data;
5652
5653         if (rtwvif != target)
5654                 return;
5655
5656         rtw89_mac_pkt_drop_sta(rtwdev, rtwsta);
5657 }
5658
5659 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
5660 {
5661         ieee80211_iterate_stations_atomic(rtwdev->hw,
5662                                           rtw89_mac_pkt_drop_vif_iter,
5663                                           rtwvif);
5664 }
5665
5666 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
5667                                         enum rtw89_mac_idx band)
5668 {
5669         struct rtw89_pkt_drop_params params = {0};
5670         bool empty;
5671         int i, ret = 0, try_cnt = 3;
5672
5673         params.mac_band = band;
5674         params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE;
5675
5676         for (i = 0; i < try_cnt; i++) {
5677                 ret = read_poll_timeout(mac_is_txq_empty, empty, empty, 50,
5678                                         50000, false, rtwdev);
5679                 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw))
5680                         rtw89_fw_h2c_pkt_drop(rtwdev, &params);
5681                 else
5682                         return 0;
5683         }
5684         return ret;
5685 }
5686
5687 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = {
5688         .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET,
5689         .filter_model_addr = R_AX_FILTER_MODEL_ADDR,
5690         .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY,
5691         .mem_base_addrs = rtw89_mac_mem_base_addrs_ax,
5692         .rx_fltr = R_AX_RX_FLTR_OPT,
5693 };
5694 EXPORT_SYMBOL(rtw89_mac_gen_ax);