drivers/net/wireless/ralink/rt2x00/rt2800lib.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   4         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   5         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   6         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   7
   8         Based on the original rt2800pci.c and rt2800usb.c.
   9           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
  10           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  11           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  12           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  13           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  14           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  15           <http://rt2x00.serialmonkey.com>
  16
  17  */
  18
  19 /*
  20         Module: rt2800lib
  21         Abstract: rt2800 generic device routines.
  22  */
  23
  24 #include <linux/crc-ccitt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/slab.h>
  28
  29 #include "rt2x00.h"
  30 #include "rt2800lib.h"
  31 #include "rt2800.h"
  32
  33 static bool modparam_watchdog;
  34 module_param_named(watchdog, modparam_watchdog, bool, S_IRUGO);
  35 MODULE_PARM_DESC(watchdog, "Enable watchdog to detect tx/rx hangs and reset hardware if detected");
  36
  37 /*
  38  * Register access.
  39  * All access to the CSR registers will go through the methods
  40  * rt2800_register_read and rt2800_register_write.
  41  * BBP and RF register require indirect register access,
  42  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  43  * These indirect registers work with busy bits,
  44  * and we will try maximal REGISTER_BUSY_COUNT times to access
  45  * the register while taking a REGISTER_BUSY_DELAY us delay
  46  * between each attampt. When the busy bit is still set at that time,
  47  * the access attempt is considered to have failed,
  48  * and we will print an error.
  49  * The _lock versions must be used if you already hold the csr_mutex
  50  */
  51 #define WAIT_FOR_BBP(__dev, __reg) \
  52         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  53 #define WAIT_FOR_RFCSR(__dev, __reg) \
  54         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  55 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
  56         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
  57                             (__reg))
  58 #define WAIT_FOR_RF(__dev, __reg) \
  59         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  60 #define WAIT_FOR_MCU(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  62                             H2M_MAILBOX_CSR_OWNER, (__reg))
  63
  64 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  65 {
  66         /* check for rt2872 on SoC */
  67         if (!rt2x00_is_soc(rt2x00dev) ||
  68             !rt2x00_rt(rt2x00dev, RT2872))
  69                 return false;
  70
  71         /* we know for sure that these rf chipsets are used on rt305x boards */
  72         if (rt2x00_rf(rt2x00dev, RF3020) ||
  73             rt2x00_rf(rt2x00dev, RF3021) ||
  74             rt2x00_rf(rt2x00dev, RF3022))
  75                 return true;
  76
  77         rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
  78         return false;
  79 }
  80
  81 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  82                              const unsigned int word, const u8 value)
  83 {
  84         u32 reg;
  85
  86         mutex_lock(&rt2x00dev->csr_mutex);
  87
  88         /*
  89          * Wait until the BBP becomes available, afterwards we
  90          * can safely write the new data into the register.
  91          */
  92         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  93                 reg = 0;
  94                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  95                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  96                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  97                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  98                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  99
 100                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 101         }
 102
 103         mutex_unlock(&rt2x00dev->csr_mutex);
 104 }
 105
 106 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
 107 {
 108         u32 reg;
 109         u8 value;
 110
 111         mutex_lock(&rt2x00dev->csr_mutex);
 112
 113         /*
 114          * Wait until the BBP becomes available, afterwards we
 115          * can safely write the read request into the register.
 116          * After the data has been written, we wait until hardware
 117          * returns the correct value, if at any time the register
 118          * doesn't become available in time, reg will be 0xffffffff
 119          * which means we return 0xff to the caller.
 120          */
 121         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 122                 reg = 0;
 123                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 124                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 125                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 126                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 127
 128                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 129
 130                 WAIT_FOR_BBP(rt2x00dev, &reg);
 131         }
 132
 133         value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 134
 135         mutex_unlock(&rt2x00dev->csr_mutex);
 136
 137         return value;
 138 }
 139
 140 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 141                                const unsigned int word, const u8 value)
 142 {
 143         u32 reg;
 144
 145         mutex_lock(&rt2x00dev->csr_mutex);
 146
 147         /*
 148          * Wait until the RFCSR becomes available, afterwards we
 149          * can safely write the new data into the register.
 150          */
 151         switch (rt2x00dev->chip.rt) {
 152         case RT6352:
 153                 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
 154                         reg = 0;
 155                         rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
 156                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
 157                                            word);
 158                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
 159                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
 160
 161                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 162                 }
 163                 break;
 164
 165         default:
 166                 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 167                         reg = 0;
 168                         rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 169                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 170                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 171                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 172
 173                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 174                 }
 175                 break;
 176         }
 177
 178         mutex_unlock(&rt2x00dev->csr_mutex);
 179 }
 180
 181 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
 182                                     const unsigned int reg, const u8 value)
 183 {
 184         rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
 185 }
 186
 187 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
 188                                        const unsigned int reg, const u8 value)
 189 {
 190         rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
 191         rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
 192 }
 193
 194 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
 195                                      const unsigned int reg, const u8 value)
 196 {
 197         rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
 198         rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
 199 }
 200
 201 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 202                             const unsigned int word)
 203 {
 204         u32 reg;
 205         u8 value;
 206
 207         mutex_lock(&rt2x00dev->csr_mutex);
 208
 209         /*
 210          * Wait until the RFCSR becomes available, afterwards we
 211          * can safely write the read request into the register.
 212          * After the data has been written, we wait until hardware
 213          * returns the correct value, if at any time the register
 214          * doesn't become available in time, reg will be 0xffffffff
 215          * which means we return 0xff to the caller.
 216          */
 217         switch (rt2x00dev->chip.rt) {
 218         case RT6352:
 219                 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
 220                         reg = 0;
 221                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
 222                                            word);
 223                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
 224                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
 225
 226                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 227
 228                         WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
 229                 }
 230
 231                 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
 232                 break;
 233
 234         default:
 235                 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 236                         reg = 0;
 237                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 238                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 239                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 240
 241                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 242
 243                         WAIT_FOR_RFCSR(rt2x00dev, &reg);
 244                 }
 245
 246                 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 247                 break;
 248         }
 249
 250         mutex_unlock(&rt2x00dev->csr_mutex);
 251
 252         return value;
 253 }
 254
 255 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
 256                                  const unsigned int reg)
 257 {
 258         return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
 259 }
 260
 261 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 262                             const unsigned int word, const u32 value)
 263 {
 264         u32 reg;
 265
 266         mutex_lock(&rt2x00dev->csr_mutex);
 267
 268         /*
 269          * Wait until the RF becomes available, afterwards we
 270          * can safely write the new data into the register.
 271          */
 272         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 273                 reg = 0;
 274                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 275                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 276                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 277                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 278
 279                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 280                 rt2x00_rf_write(rt2x00dev, word, value);
 281         }
 282
 283         mutex_unlock(&rt2x00dev->csr_mutex);
 284 }
 285
 286 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
 287         [EEPROM_CHIP_ID]                = 0x0000,
 288         [EEPROM_VERSION]                = 0x0001,
 289         [EEPROM_MAC_ADDR_0]             = 0x0002,
 290         [EEPROM_MAC_ADDR_1]             = 0x0003,
 291         [EEPROM_MAC_ADDR_2]             = 0x0004,
 292         [EEPROM_NIC_CONF0]              = 0x001a,
 293         [EEPROM_NIC_CONF1]              = 0x001b,
 294         [EEPROM_FREQ]                   = 0x001d,
 295         [EEPROM_LED_AG_CONF]            = 0x001e,
 296         [EEPROM_LED_ACT_CONF]           = 0x001f,
 297         [EEPROM_LED_POLARITY]           = 0x0020,
 298         [EEPROM_NIC_CONF2]              = 0x0021,
 299         [EEPROM_LNA]                    = 0x0022,
 300         [EEPROM_RSSI_BG]                = 0x0023,
 301         [EEPROM_RSSI_BG2]               = 0x0024,
 302         [EEPROM_TXMIXER_GAIN_BG]        = 0x0024, /* overlaps with RSSI_BG2 */
 303         [EEPROM_RSSI_A]                 = 0x0025,
 304         [EEPROM_RSSI_A2]                = 0x0026,
 305         [EEPROM_TXMIXER_GAIN_A]         = 0x0026, /* overlaps with RSSI_A2 */
 306         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0027,
 307         [EEPROM_TXPOWER_DELTA]          = 0x0028,
 308         [EEPROM_TXPOWER_BG1]            = 0x0029,
 309         [EEPROM_TXPOWER_BG2]            = 0x0030,
 310         [EEPROM_TSSI_BOUND_BG1]         = 0x0037,
 311         [EEPROM_TSSI_BOUND_BG2]         = 0x0038,
 312         [EEPROM_TSSI_BOUND_BG3]         = 0x0039,
 313         [EEPROM_TSSI_BOUND_BG4]         = 0x003a,
 314         [EEPROM_TSSI_BOUND_BG5]         = 0x003b,
 315         [EEPROM_TXPOWER_A1]             = 0x003c,
 316         [EEPROM_TXPOWER_A2]             = 0x0053,
 317         [EEPROM_TXPOWER_INIT]           = 0x0068,
 318         [EEPROM_TSSI_BOUND_A1]          = 0x006a,
 319         [EEPROM_TSSI_BOUND_A2]          = 0x006b,
 320         [EEPROM_TSSI_BOUND_A3]          = 0x006c,
 321         [EEPROM_TSSI_BOUND_A4]          = 0x006d,
 322         [EEPROM_TSSI_BOUND_A5]          = 0x006e,
 323         [EEPROM_TXPOWER_BYRATE]         = 0x006f,
 324         [EEPROM_BBP_START]              = 0x0078,
 325 };
 326
 327 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
 328         [EEPROM_CHIP_ID]                = 0x0000,
 329         [EEPROM_VERSION]                = 0x0001,
 330         [EEPROM_MAC_ADDR_0]             = 0x0002,
 331         [EEPROM_MAC_ADDR_1]             = 0x0003,
 332         [EEPROM_MAC_ADDR_2]             = 0x0004,
 333         [EEPROM_NIC_CONF0]              = 0x001a,
 334         [EEPROM_NIC_CONF1]              = 0x001b,
 335         [EEPROM_NIC_CONF2]              = 0x001c,
 336         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0020,
 337         [EEPROM_FREQ]                   = 0x0022,
 338         [EEPROM_LED_AG_CONF]            = 0x0023,
 339         [EEPROM_LED_ACT_CONF]           = 0x0024,
 340         [EEPROM_LED_POLARITY]           = 0x0025,
 341         [EEPROM_LNA]                    = 0x0026,
 342         [EEPROM_EXT_LNA2]               = 0x0027,
 343         [EEPROM_RSSI_BG]                = 0x0028,
 344         [EEPROM_RSSI_BG2]               = 0x0029,
 345         [EEPROM_RSSI_A]                 = 0x002a,
 346         [EEPROM_RSSI_A2]                = 0x002b,
 347         [EEPROM_TXPOWER_BG1]            = 0x0030,
 348         [EEPROM_TXPOWER_BG2]            = 0x0037,
 349         [EEPROM_EXT_TXPOWER_BG3]        = 0x003e,
 350         [EEPROM_TSSI_BOUND_BG1]         = 0x0045,
 351         [EEPROM_TSSI_BOUND_BG2]         = 0x0046,
 352         [EEPROM_TSSI_BOUND_BG3]         = 0x0047,
 353         [EEPROM_TSSI_BOUND_BG4]         = 0x0048,
 354         [EEPROM_TSSI_BOUND_BG5]         = 0x0049,
 355         [EEPROM_TXPOWER_A1]             = 0x004b,
 356         [EEPROM_TXPOWER_A2]             = 0x0065,
 357         [EEPROM_EXT_TXPOWER_A3]         = 0x007f,
 358         [EEPROM_TSSI_BOUND_A1]          = 0x009a,
 359         [EEPROM_TSSI_BOUND_A2]          = 0x009b,
 360         [EEPROM_TSSI_BOUND_A3]          = 0x009c,
 361         [EEPROM_TSSI_BOUND_A4]          = 0x009d,
 362         [EEPROM_TSSI_BOUND_A5]          = 0x009e,
 363         [EEPROM_TXPOWER_BYRATE]         = 0x00a0,
 364 };
 365
 366 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
 367                                              const enum rt2800_eeprom_word word)
 368 {
 369         const unsigned int *map;
 370         unsigned int index;
 371
 372         if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
 373                       "%s: invalid EEPROM word %d\n",
 374                       wiphy_name(rt2x00dev->hw->wiphy), word))
 375                 return 0;
 376
 377         if (rt2x00_rt(rt2x00dev, RT3593) ||
 378             rt2x00_rt(rt2x00dev, RT3883))
 379                 map = rt2800_eeprom_map_ext;
 380         else
 381                 map = rt2800_eeprom_map;
 382
 383         index = map[word];
 384
 385         /* Index 0 is valid only for EEPROM_CHIP_ID.
 386          * Otherwise it means that the offset of the
 387          * given word is not initialized in the map,
 388          * or that the field is not usable on the
 389          * actual chipset.
 390          */
 391         WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
 392                   "%s: invalid access of EEPROM word %d\n",
 393                   wiphy_name(rt2x00dev->hw->wiphy), word);
 394
 395         return index;
 396 }
 397
 398 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
 399                                 const enum rt2800_eeprom_word word)
 400 {
 401         unsigned int index;
 402
 403         index = rt2800_eeprom_word_index(rt2x00dev, word);
 404         return rt2x00_eeprom_addr(rt2x00dev, index);
 405 }
 406
 407 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
 408                               const enum rt2800_eeprom_word word)
 409 {
 410         unsigned int index;
 411
 412         index = rt2800_eeprom_word_index(rt2x00dev, word);
 413         return rt2x00_eeprom_read(rt2x00dev, index);
 414 }
 415
 416 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
 417                                 const enum rt2800_eeprom_word word, u16 data)
 418 {
 419         unsigned int index;
 420
 421         index = rt2800_eeprom_word_index(rt2x00dev, word);
 422         rt2x00_eeprom_write(rt2x00dev, index, data);
 423 }
 424
 425 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
 426                                          const enum rt2800_eeprom_word array,
 427                                          unsigned int offset)
 428 {
 429         unsigned int index;
 430
 431         index = rt2800_eeprom_word_index(rt2x00dev, array);
 432         return rt2x00_eeprom_read(rt2x00dev, index + offset);
 433 }
 434
 435 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 436 {
 437         u32 reg;
 438         int i, count;
 439
 440         reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
 441         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 442         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 443         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 444         rt2x00_set_field32(&reg, WLAN_EN, 1);
 445         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 446
 447         udelay(REGISTER_BUSY_DELAY);
 448
 449         count = 0;
 450         do {
 451                 /*
 452                  * Check PLL_LD & XTAL_RDY.
 453                  */
 454                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 455                         reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
 456                         if (rt2x00_get_field32(reg, PLL_LD) &&
 457                             rt2x00_get_field32(reg, XTAL_RDY))
 458                                 break;
 459                         udelay(REGISTER_BUSY_DELAY);
 460                 }
 461
 462                 if (i >= REGISTER_BUSY_COUNT) {
 463
 464                         if (count >= 10)
 465                                 return -EIO;
 466
 467                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 468                         udelay(REGISTER_BUSY_DELAY);
 469                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 470                         udelay(REGISTER_BUSY_DELAY);
 471                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 472                         udelay(REGISTER_BUSY_DELAY);
 473                         count++;
 474                 } else {
 475                         count = 0;
 476                 }
 477
 478                 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
 479                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 480                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 481                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 482                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 483                 udelay(10);
 484                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 485                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 486                 udelay(10);
 487                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 488         } while (count != 0);
 489
 490         return 0;
 491 }
 492
 493 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 494                         const u8 command, const u8 token,
 495                         const u8 arg0, const u8 arg1)
 496 {
 497         u32 reg;
 498
 499         /*
 500          * SOC devices don't support MCU requests.
 501          */
 502         if (rt2x00_is_soc(rt2x00dev))
 503                 return;
 504
 505         mutex_lock(&rt2x00dev->csr_mutex);
 506
 507         /*
 508          * Wait until the MCU becomes available, afterwards we
 509          * can safely write the new data into the register.
 510          */
 511         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 512                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 513                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 514                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 515                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 516                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 517
 518                 reg = 0;
 519                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 520                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 521         }
 522
 523         mutex_unlock(&rt2x00dev->csr_mutex);
 524 }
 525 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 526
 527 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 528 {
 529         unsigned int i = 0;
 530         u32 reg;
 531
 532         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 533                 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
 534                 if (reg && reg != ~0)
 535                         return 0;
 536                 msleep(1);
 537         }
 538
 539         rt2x00_err(rt2x00dev, "Unstable hardware\n");
 540         return -EBUSY;
 541 }
 542 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 543
 544 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 545 {
 546         unsigned int i;
 547         u32 reg;
 548
 549         /*
 550          * Some devices are really slow to respond here. Wait a whole second
 551          * before timing out.
 552          */
 553         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 554                 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
 555                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 556                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 557                         return 0;
 558
 559                 msleep(10);
 560         }
 561
 562         rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
 563         return -EACCES;
 564 }
 565 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 566
 567 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 568 {
 569         u32 reg;
 570
 571         reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
 572         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 573         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 574         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 575         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 576         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 577         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 578 }
 579 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 580
 581 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
 582                                unsigned short *txwi_size,
 583                                unsigned short *rxwi_size)
 584 {
 585         switch (rt2x00dev->chip.rt) {
 586         case RT3593:
 587         case RT3883:
 588                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 589                 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
 590                 break;
 591
 592         case RT5592:
 593         case RT6352:
 594                 *txwi_size = TXWI_DESC_SIZE_5WORDS;
 595                 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
 596                 break;
 597
 598         default:
 599                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 600                 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
 601                 break;
 602         }
 603 }
 604 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
 605
 606 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 607 {
 608         u16 fw_crc;
 609         u16 crc;
 610
 611         /*
 612          * The last 2 bytes in the firmware array are the crc checksum itself,
 613          * this means that we should never pass those 2 bytes to the crc
 614          * algorithm.
 615          */
 616         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 617
 618         /*
 619          * Use the crc ccitt algorithm.
 620          * This will return the same value as the legacy driver which
 621          * used bit ordering reversion on the both the firmware bytes
 622          * before input input as well as on the final output.
 623          * Obviously using crc ccitt directly is much more efficient.
 624          */
 625         crc = crc_ccitt(~0, data, len - 2);
 626
 627         /*
 628          * There is a small difference between the crc-itu-t + bitrev and
 629          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 630          * will be swapped, use swab16 to convert the crc to the correct
 631          * value.
 632          */
 633         crc = swab16(crc);
 634
 635         return fw_crc == crc;
 636 }
 637
 638 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 639                           const u8 *data, const size_t len)
 640 {
 641         size_t offset = 0;
 642         size_t fw_len;
 643         bool multiple;
 644
 645         /*
 646          * PCI(e) & SOC devices require firmware with a length
 647          * of 8kb. USB devices require firmware files with a length
 648          * of 4kb. Certain USB chipsets however require different firmware,
 649          * which Ralink only provides attached to the original firmware
 650          * file. Thus for USB devices, firmware files have a length
 651          * which is a multiple of 4kb. The firmware for rt3290 chip also
 652          * have a length which is a multiple of 4kb.
 653          */
 654         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 655                 fw_len = 4096;
 656         else
 657                 fw_len = 8192;
 658
 659         multiple = true;
 660         /*
 661          * Validate the firmware length
 662          */
 663         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 664                 return FW_BAD_LENGTH;
 665
 666         /*
 667          * Check if the chipset requires one of the upper parts
 668          * of the firmware.
 669          */
 670         if (rt2x00_is_usb(rt2x00dev) &&
 671             !rt2x00_rt(rt2x00dev, RT2860) &&
 672             !rt2x00_rt(rt2x00dev, RT2872) &&
 673             !rt2x00_rt(rt2x00dev, RT3070) &&
 674             ((len / fw_len) == 1))
 675                 return FW_BAD_VERSION;
 676
 677         /*
 678          * 8kb firmware files must be checked as if it were
 679          * 2 separate firmware files.
 680          */
 681         while (offset < len) {
 682                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 683                         return FW_BAD_CRC;
 684
 685                 offset += fw_len;
 686         }
 687
 688         return FW_OK;
 689 }
 690 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 691
 692 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 693                          const u8 *data, const size_t len)
 694 {
 695         unsigned int i;
 696         u32 reg;
 697         int retval;
 698
 699         if (rt2x00_rt(rt2x00dev, RT3290)) {
 700                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 701                 if (retval)
 702                         return -EBUSY;
 703         }
 704
 705         /*
 706          * If driver doesn't wake up firmware here,
 707          * rt2800_load_firmware will hang forever when interface is up again.
 708          */
 709         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 710
 711         /*
 712          * Wait for stable hardware.
 713          */
 714         if (rt2800_wait_csr_ready(rt2x00dev))
 715                 return -EBUSY;
 716
 717         if (rt2x00_is_pci(rt2x00dev)) {
 718                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 719                     rt2x00_rt(rt2x00dev, RT3572) ||
 720                     rt2x00_rt(rt2x00dev, RT5390) ||
 721                     rt2x00_rt(rt2x00dev, RT5392)) {
 722                         reg = rt2800_register_read(rt2x00dev, AUX_CTRL);
 723                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 724                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 725                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 726                 }
 727                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 728         }
 729
 730         rt2800_disable_wpdma(rt2x00dev);
 731
 732         /*
 733          * Write firmware to the device.
 734          */
 735         rt2800_drv_write_firmware(rt2x00dev, data, len);
 736
 737         /*
 738          * Wait for device to stabilize.
 739          */
 740         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 741                 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL);
 742                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 743                         break;
 744                 msleep(1);
 745         }
 746
 747         if (i == REGISTER_BUSY_COUNT) {
 748                 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
 749                 return -EBUSY;
 750         }
 751
 752         /*
 753          * Disable DMA, will be reenabled later when enabling
 754          * the radio.
 755          */
 756         rt2800_disable_wpdma(rt2x00dev);
 757
 758         /*
 759          * Initialize firmware.
 760          */
 761         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 762         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 763         if (rt2x00_is_usb(rt2x00dev)) {
 764                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 765                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 766         }
 767         msleep(1);
 768
 769         return 0;
 770 }
 771 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 772
 773 void rt2800_write_tx_data(struct queue_entry *entry,
 774                           struct txentry_desc *txdesc)
 775 {
 776         __le32 *txwi = rt2800_drv_get_txwi(entry);
 777         u32 word;
 778         int i;
 779
 780         /*
 781          * Initialize TX Info descriptor
 782          */
 783         word = rt2x00_desc_read(txwi, 0);
 784         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 785                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 786         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 787                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 788         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 789         rt2x00_set_field32(&word, TXWI_W0_TS,
 790                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 791         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 792                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 793         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 794                            txdesc->u.ht.mpdu_density);
 795         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 796         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 797         rt2x00_set_field32(&word, TXWI_W0_BW,
 798                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 799         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 800                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 801         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 802         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 803         rt2x00_desc_write(txwi, 0, word);
 804
 805         word = rt2x00_desc_read(txwi, 1);
 806         rt2x00_set_field32(&word, TXWI_W1_ACK,
 807                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 808         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 809                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 810         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 811         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 812                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 813                            txdesc->key_idx : txdesc->u.ht.wcid);
 814         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 815                            txdesc->length);
 816         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 817         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 818         rt2x00_desc_write(txwi, 1, word);
 819
 820         /*
 821          * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
 822          * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
 823          * When TXD_W3_WIV is set to 1 it will use the IV data
 824          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 825          * crypto entry in the registers should be used to encrypt the frame.
 826          *
 827          * Nulify all remaining words as well, we don't know how to program them.
 828          */
 829         for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
 830                 _rt2x00_desc_write(txwi, i, 0);
 831 }
 832 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 833
 834 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 835 {
 836         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 837         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 838         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 839         u16 eeprom;
 840         u8 offset0;
 841         u8 offset1;
 842         u8 offset2;
 843
 844         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
 845                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
 846                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 847                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 848                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
 849                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 850         } else {
 851                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
 852                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 853                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 854                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
 855                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 856         }
 857
 858         /*
 859          * Convert the value from the descriptor into the RSSI value
 860          * If the value in the descriptor is 0, it is considered invalid
 861          * and the default (extremely low) rssi value is assumed
 862          */
 863         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 864         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 865         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 866
 867         /*
 868          * mac80211 only accepts a single RSSI value. Calculating the
 869          * average doesn't deliver a fair answer either since -60:-60 would
 870          * be considered equally good as -50:-70 while the second is the one
 871          * which gives less energy...
 872          */
 873         rssi0 = max(rssi0, rssi1);
 874         return (int)max(rssi0, rssi2);
 875 }
 876
 877 void rt2800_process_rxwi(struct queue_entry *entry,
 878                          struct rxdone_entry_desc *rxdesc)
 879 {
 880         __le32 *rxwi = (__le32 *) entry->skb->data;
 881         u32 word;
 882
 883         word = rt2x00_desc_read(rxwi, 0);
 884
 885         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 886         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 887
 888         word = rt2x00_desc_read(rxwi, 1);
 889
 890         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 891                 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
 892
 893         if (rt2x00_get_field32(word, RXWI_W1_BW))
 894                 rxdesc->bw = RATE_INFO_BW_40;
 895
 896         /*
 897          * Detect RX rate, always use MCS as signal type.
 898          */
 899         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 900         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 901         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 902
 903         /*
 904          * Mask of 0x8 bit to remove the short preamble flag.
 905          */
 906         if (rxdesc->rate_mode == RATE_MODE_CCK)
 907                 rxdesc->signal &= ~0x8;
 908
 909         word = rt2x00_desc_read(rxwi, 2);
 910
 911         /*
 912          * Convert descriptor AGC value to RSSI value.
 913          */
 914         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 915         /*
 916          * Remove RXWI descriptor from start of the buffer.
 917          */
 918         skb_pull(entry->skb, entry->queue->winfo_size);
 919 }
 920 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 921
 922 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc,
 923                                     u32 status, enum nl80211_band band)
 924 {
 925         u8 flags = 0;
 926         u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 927
 928         switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) {
 929         case RATE_MODE_HT_GREENFIELD:
 930                 flags |= IEEE80211_TX_RC_GREEN_FIELD;
 931                 /* fall through */
 932         case RATE_MODE_HT_MIX:
 933                 flags |= IEEE80211_TX_RC_MCS;
 934                 break;
 935         case RATE_MODE_OFDM:
 936                 if (band == NL80211_BAND_2GHZ)
 937                         idx += 4;
 938                 break;
 939         case RATE_MODE_CCK:
 940                 if (idx >= 8)
 941                         idx -= 8;
 942                 break;
 943         }
 944
 945         if (rt2x00_get_field32(status, TX_STA_FIFO_BW))
 946                 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
 947
 948         if (rt2x00_get_field32(status, TX_STA_FIFO_SGI))
 949                 flags |= IEEE80211_TX_RC_SHORT_GI;
 950
 951         skbdesc->tx_rate_idx = idx;
 952         skbdesc->tx_rate_flags = flags;
 953 }
 954
 955 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
 956 {
 957         __le32 *txwi;
 958         u32 word;
 959         int wcid, ack, pid;
 960         int tx_wcid, tx_ack, tx_pid, is_agg;
 961
 962         /*
 963          * This frames has returned with an IO error,
 964          * so the status report is not intended for this
 965          * frame.
 966          */
 967         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
 968                 return false;
 969
 970         wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
 971         ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
 972         pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
 973         is_agg  = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE);
 974
 975         /*
 976          * Validate if this TX status report is intended for
 977          * this entry by comparing the WCID/ACK/PID fields.
 978          */
 979         txwi = rt2800_drv_get_txwi(entry);
 980
 981         word = rt2x00_desc_read(txwi, 1);
 982         tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 983         tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
 984         tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
 985
 986         if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) {
 987                 rt2x00_dbg(entry->queue->rt2x00dev,
 988                            "TX status report missed for queue %d entry %d\n",
 989                            entry->queue->qid, entry->entry_idx);
 990                 return false;
 991         }
 992
 993         return true;
 994 }
 995
 996 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,
 997                          bool match)
 998 {
 999         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1000         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1001         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1002         struct txdone_entry_desc txdesc;
1003         u32 word;
1004         u16 mcs, real_mcs;
1005         int aggr, ampdu, wcid, ack_req;
1006
1007         /*
1008          * Obtain the status about this packet.
1009          */
1010         txdesc.flags = 0;
1011         word = rt2x00_desc_read(txwi, 0);
1012
1013         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1014         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
1015
1016         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
1017         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
1018         wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
1019         ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED);
1020
1021         /*
1022          * If a frame was meant to be sent as a single non-aggregated MPDU
1023          * but ended up in an aggregate the used tx rate doesn't correlate
1024          * with the one specified in the TXWI as the whole aggregate is sent
1025          * with the same rate.
1026          *
1027          * For example: two frames are sent to rt2x00, the first one sets
1028          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
1029          * and requests MCS15. If the hw aggregates both frames into one
1030          * AMDPU the tx status for both frames will contain MCS7 although
1031          * the frame was sent successfully.
1032          *
1033          * Hence, replace the requested rate with the real tx rate to not
1034          * confuse the rate control algortihm by providing clearly wrong
1035          * data.
1036          *
1037          * FIXME: if we do not find matching entry, we tell that frame was
1038          * posted without any retries. We need to find a way to fix that
1039          * and provide retry count.
1040          */
1041         if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {
1042                 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
1043                 mcs = real_mcs;
1044         }
1045
1046         if (aggr == 1 || ampdu == 1)
1047                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
1048
1049         if (!ack_req)
1050                 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags);
1051
1052         /*
1053          * Ralink has a retry mechanism using a global fallback
1054          * table. We setup this fallback table to try the immediate
1055          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
1056          * always contains the MCS used for the last transmission, be
1057          * it successful or not.
1058          */
1059         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
1060                 /*
1061                  * Transmission succeeded. The number of retries is
1062                  * mcs - real_mcs
1063                  */
1064                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1065                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1066         } else {
1067                 /*
1068                  * Transmission failed. The number of retries is
1069                  * always 7 in this case (for a total number of 8
1070                  * frames sent).
1071                  */
1072                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1073                 txdesc.retry = rt2x00dev->long_retry;
1074         }
1075
1076         /*
1077          * the frame was retried at least once
1078          * -> hw used fallback rates
1079          */
1080         if (txdesc.retry)
1081                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1082
1083         if (!match) {
1084                 /* RCU assures non-null sta will not be freed by mac80211. */
1085                 rcu_read_lock();
1086                 if (likely(wcid >= WCID_START && wcid <= WCID_END))
1087                         skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START];
1088                 else
1089                         skbdesc->sta = NULL;
1090                 rt2x00lib_txdone_nomatch(entry, &txdesc);
1091                 rcu_read_unlock();
1092         } else {
1093                 rt2x00lib_txdone(entry, &txdesc);
1094         }
1095 }
1096 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
1097
1098 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota)
1099 {
1100         struct data_queue *queue;
1101         struct queue_entry *entry;
1102         u32 reg;
1103         u8 qid;
1104         bool match;
1105
1106         while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, &reg)) {
1107                 /*
1108                  * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is
1109                  * guaranteed to be one of the TX QIDs .
1110                  */
1111                 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
1112                 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
1113
1114                 if (unlikely(rt2x00queue_empty(queue))) {
1115                         rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
1116                                    qid);
1117                         break;
1118                 }
1119
1120                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1121
1122                 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1123                              !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) {
1124                         rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n",
1125                                     entry->entry_idx, qid);
1126                         break;
1127                 }
1128
1129                 match = rt2800_txdone_entry_check(entry, reg);
1130                 rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match);
1131         }
1132 }
1133 EXPORT_SYMBOL_GPL(rt2800_txdone);
1134
1135 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev,
1136                                                  struct queue_entry *entry)
1137 {
1138         bool ret;
1139         unsigned long tout;
1140
1141         if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1142                 return false;
1143
1144         if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags))
1145                 tout = msecs_to_jiffies(50);
1146         else
1147                 tout = msecs_to_jiffies(2000);
1148
1149         ret = time_after(jiffies, entry->last_action + tout);
1150         if (unlikely(ret))
1151                 rt2x00_dbg(entry->queue->rt2x00dev,
1152                            "TX status timeout for entry %d in queue %d\n",
1153                            entry->entry_idx, entry->queue->qid);
1154         return ret;
1155 }
1156
1157 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev)
1158 {
1159         struct data_queue *queue;
1160         struct queue_entry *entry;
1161
1162         tx_queue_for_each(rt2x00dev, queue) {
1163                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1164                 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1165                         return true;
1166         }
1167
1168         return false;
1169 }
1170 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout);
1171
1172 /*
1173  * test if there is an entry in any TX queue for which DMA is done
1174  * but the TX status has not been returned yet
1175  */
1176 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev)
1177 {
1178         struct data_queue *queue;
1179
1180         tx_queue_for_each(rt2x00dev, queue) {
1181                 if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) !=
1182                     rt2x00queue_get_entry(queue, Q_INDEX_DONE))
1183                         return true;
1184         }
1185         return false;
1186 }
1187 EXPORT_SYMBOL_GPL(rt2800_txstatus_pending);
1188
1189 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev)
1190 {
1191         struct data_queue *queue;
1192         struct queue_entry *entry;
1193
1194         /*
1195          * Process any trailing TX status reports for IO failures,
1196          * we loop until we find the first non-IO error entry. This
1197          * can either be a frame which is free, is being uploaded,
1198          * or has completed the upload but didn't have an entry
1199          * in the TX_STAT_FIFO register yet.
1200          */
1201         tx_queue_for_each(rt2x00dev, queue) {
1202                 while (!rt2x00queue_empty(queue)) {
1203                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1204
1205                         if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1206                             !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1207                                 break;
1208
1209                         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) ||
1210                             rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1211                                 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
1212                         else
1213                                 break;
1214                 }
1215         }
1216 }
1217 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus);
1218
1219 static int rt2800_check_hung(struct data_queue *queue)
1220 {
1221         unsigned int cur_idx = rt2800_drv_get_dma_done(queue);
1222
1223         if (queue->wd_idx != cur_idx)
1224                 queue->wd_count = 0;
1225         else
1226                 queue->wd_count++;
1227
1228         return queue->wd_count > 16;
1229 }
1230
1231 void rt2800_watchdog(struct rt2x00_dev *rt2x00dev)
1232 {
1233         struct data_queue *queue;
1234         bool hung_tx = false;
1235         bool hung_rx = false;
1236
1237         if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags))
1238                 return;
1239
1240         queue_for_each(rt2x00dev, queue) {
1241                 switch (queue->qid) {
1242                 case QID_AC_VO:
1243                 case QID_AC_VI:
1244                 case QID_AC_BE:
1245                 case QID_AC_BK:
1246                 case QID_MGMT:
1247                         if (rt2x00queue_empty(queue))
1248                                 continue;
1249                         hung_tx = rt2800_check_hung(queue);
1250                         break;
1251                 case QID_RX:
1252                         /* For station mode we should reactive at least
1253                          * beacons. TODO: need to find good way detect
1254                          * RX hung for AP mode.
1255                          */
1256                         if (rt2x00dev->intf_sta_count == 0)
1257                                 continue;
1258                         hung_rx = rt2800_check_hung(queue);
1259                         break;
1260                 default:
1261                         break;
1262                 }
1263         }
1264
1265         if (hung_tx)
1266                 rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n");
1267
1268         if (hung_rx)
1269                 rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n");
1270
1271         if (hung_tx || hung_rx)
1272                 ieee80211_restart_hw(rt2x00dev->hw);
1273 }
1274 EXPORT_SYMBOL_GPL(rt2800_watchdog);
1275
1276 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1277                                           unsigned int index)
1278 {
1279         return HW_BEACON_BASE(index);
1280 }
1281
1282 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1283                                           unsigned int index)
1284 {
1285         return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1286 }
1287
1288 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1289 {
1290         struct data_queue *queue = rt2x00dev->bcn;
1291         struct queue_entry *entry;
1292         int i, bcn_num = 0;
1293         u64 off, reg = 0;
1294         u32 bssid_dw1;
1295
1296         /*
1297          * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
1298          */
1299         for (i = 0; i < queue->limit; i++) {
1300                 entry = &queue->entries[i];
1301                 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
1302                         continue;
1303                 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1304                 reg |= off << (8 * bcn_num);
1305                 bcn_num++;
1306         }
1307
1308         rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1309         rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1310
1311         /*
1312          * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
1313          */
1314         bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1);
1315         rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
1316                            bcn_num > 0 ? bcn_num - 1 : 0);
1317         rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1318 }
1319
1320 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
1321 {
1322         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1323         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1324         unsigned int beacon_base;
1325         unsigned int padding_len;
1326         u32 orig_reg, reg;
1327         const int txwi_desc_size = entry->queue->winfo_size;
1328
1329         /*
1330          * Disable beaconing while we are reloading the beacon data,
1331          * otherwise we might be sending out invalid data.
1332          */
1333         reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1334         orig_reg = reg;
1335         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1336         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1337
1338         /*
1339          * Add space for the TXWI in front of the skb.
1340          */
1341         memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
1342
1343         /*
1344          * Register descriptor details in skb frame descriptor.
1345          */
1346         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1347         skbdesc->desc = entry->skb->data;
1348         skbdesc->desc_len = txwi_desc_size;
1349
1350         /*
1351          * Add the TXWI for the beacon to the skb.
1352          */
1353         rt2800_write_tx_data(entry, txdesc);
1354
1355         /*
1356          * Dump beacon to userspace through debugfs.
1357          */
1358         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1359
1360         /*
1361          * Write entire beacon with TXWI and padding to register.
1362          */
1363         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1364         if (padding_len && skb_pad(entry->skb, padding_len)) {
1365                 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1366                 /* skb freed by skb_pad() on failure */
1367                 entry->skb = NULL;
1368                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1369                 return;
1370         }
1371
1372         beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1373
1374         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1375                                    entry->skb->len + padding_len);
1376         __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1377
1378         /*
1379          * Change global beacons settings.
1380          */
1381         rt2800_update_beacons_setup(rt2x00dev);
1382
1383         /*
1384          * Restore beaconing state.
1385          */
1386         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1387
1388         /*
1389          * Clean up beacon skb.
1390          */
1391         dev_kfree_skb_any(entry->skb);
1392         entry->skb = NULL;
1393 }
1394 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1395
1396 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1397                                                 unsigned int index)
1398 {
1399         int i;
1400         const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1401         unsigned int beacon_base;
1402
1403         beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1404
1405         /*
1406          * For the Beacon base registers we only need to clear
1407          * the whole TXWI which (when set to 0) will invalidate
1408          * the entire beacon.
1409          */
1410         for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1411                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1412 }
1413
1414 void rt2800_clear_beacon(struct queue_entry *entry)
1415 {
1416         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1417         u32 orig_reg, reg;
1418
1419         /*
1420          * Disable beaconing while we are reloading the beacon data,
1421          * otherwise we might be sending out invalid data.
1422          */
1423         orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1424         reg = orig_reg;
1425         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1426         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1427
1428         /*
1429          * Clear beacon.
1430          */
1431         rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1432         __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
1433
1434         /*
1435          * Change global beacons settings.
1436          */
1437         rt2800_update_beacons_setup(rt2x00dev);
1438         /*
1439          * Restore beaconing state.
1440          */
1441         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1442 }
1443 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1444
1445 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1446 const struct rt2x00debug rt2800_rt2x00debug = {
1447         .owner  = THIS_MODULE,
1448         .csr    = {
1449                 .read           = rt2800_register_read,
1450                 .write          = rt2800_register_write,
1451                 .flags          = RT2X00DEBUGFS_OFFSET,
1452                 .word_base      = CSR_REG_BASE,
1453                 .word_size      = sizeof(u32),
1454                 .word_count     = CSR_REG_SIZE / sizeof(u32),
1455         },
1456         .eeprom = {
1457                 /* NOTE: The local EEPROM access functions can't
1458                  * be used here, use the generic versions instead.
1459                  */
1460                 .read           = rt2x00_eeprom_read,
1461                 .write          = rt2x00_eeprom_write,
1462                 .word_base      = EEPROM_BASE,
1463                 .word_size      = sizeof(u16),
1464                 .word_count     = EEPROM_SIZE / sizeof(u16),
1465         },
1466         .bbp    = {
1467                 .read           = rt2800_bbp_read,
1468                 .write          = rt2800_bbp_write,
1469                 .word_base      = BBP_BASE,
1470                 .word_size      = sizeof(u8),
1471                 .word_count     = BBP_SIZE / sizeof(u8),
1472         },
1473         .rf     = {
1474                 .read           = rt2x00_rf_read,
1475                 .write          = rt2800_rf_write,
1476                 .word_base      = RF_BASE,
1477                 .word_size      = sizeof(u32),
1478                 .word_count     = RF_SIZE / sizeof(u32),
1479         },
1480         .rfcsr  = {
1481                 .read           = rt2800_rfcsr_read,
1482                 .write          = rt2800_rfcsr_write,
1483                 .word_base      = RFCSR_BASE,
1484                 .word_size      = sizeof(u8),
1485                 .word_count     = RFCSR_SIZE / sizeof(u8),
1486         },
1487 };
1488 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1489 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1490
1491 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1492 {
1493         u32 reg;
1494
1495         if (rt2x00_rt(rt2x00dev, RT3290)) {
1496                 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
1497                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1498         } else {
1499                 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1500                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1501         }
1502 }
1503 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1504
1505 #ifdef CONFIG_RT2X00_LIB_LEDS
1506 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1507                                   enum led_brightness brightness)
1508 {
1509         struct rt2x00_led *led =
1510             container_of(led_cdev, struct rt2x00_led, led_dev);
1511         unsigned int enabled = brightness != LED_OFF;
1512         unsigned int bg_mode =
1513             (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
1514         unsigned int polarity =
1515                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1516                                    EEPROM_FREQ_LED_POLARITY);
1517         unsigned int ledmode =
1518                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1519                                    EEPROM_FREQ_LED_MODE);
1520         u32 reg;
1521
1522         /* Check for SoC (SOC devices don't support MCU requests) */
1523         if (rt2x00_is_soc(led->rt2x00dev)) {
1524                 reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
1525
1526                 /* Set LED Polarity */
1527                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1528
1529                 /* Set LED Mode */
1530                 if (led->type == LED_TYPE_RADIO) {
1531                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1532                                            enabled ? 3 : 0);
1533                 } else if (led->type == LED_TYPE_ASSOC) {
1534                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1535                                            enabled ? 3 : 0);
1536                 } else if (led->type == LED_TYPE_QUALITY) {
1537                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1538                                            enabled ? 3 : 0);
1539                 }
1540
1541                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1542
1543         } else {
1544                 if (led->type == LED_TYPE_RADIO) {
1545                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1546                                               enabled ? 0x20 : 0);
1547                 } else if (led->type == LED_TYPE_ASSOC) {
1548                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1549                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1550                 } else if (led->type == LED_TYPE_QUALITY) {
1551                         /*
1552                          * The brightness is divided into 6 levels (0 - 5),
1553                          * The specs tell us the following levels:
1554                          *      0, 1 ,3, 7, 15, 31
1555                          * to determine the level in a simple way we can simply
1556                          * work with bitshifting:
1557                          *      (1 << level) - 1
1558                          */
1559                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1560                                               (1 << brightness / (LED_FULL / 6)) - 1,
1561                                               polarity);
1562                 }
1563         }
1564 }
1565
1566 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1567                      struct rt2x00_led *led, enum led_type type)
1568 {
1569         led->rt2x00dev = rt2x00dev;
1570         led->type = type;
1571         led->led_dev.brightness_set = rt2800_brightness_set;
1572         led->flags = LED_INITIALIZED;
1573 }
1574 #endif /* CONFIG_RT2X00_LIB_LEDS */
1575
1576 /*
1577  * Configuration handlers.
1578  */
1579 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1580                                const u8 *address,
1581                                int wcid)
1582 {
1583         struct mac_wcid_entry wcid_entry;
1584         u32 offset;
1585
1586         offset = MAC_WCID_ENTRY(wcid);
1587
1588         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1589         if (address)
1590                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1591
1592         rt2800_register_multiwrite(rt2x00dev, offset,
1593                                       &wcid_entry, sizeof(wcid_entry));
1594 }
1595
1596 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1597 {
1598         u32 offset;
1599         offset = MAC_WCID_ATTR_ENTRY(wcid);
1600         rt2800_register_write(rt2x00dev, offset, 0);
1601 }
1602
1603 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1604                                            int wcid, u32 bssidx)
1605 {
1606         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1607         u32 reg;
1608
1609         /*
1610          * The BSS Idx numbers is split in a main value of 3 bits,
1611          * and a extended field for adding one additional bit to the value.
1612          */
1613         reg = rt2800_register_read(rt2x00dev, offset);
1614         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1615         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1616                            (bssidx & 0x8) >> 3);
1617         rt2800_register_write(rt2x00dev, offset, reg);
1618 }
1619
1620 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1621                                            struct rt2x00lib_crypto *crypto,
1622                                            struct ieee80211_key_conf *key)
1623 {
1624         struct mac_iveiv_entry iveiv_entry;
1625         u32 offset;
1626         u32 reg;
1627
1628         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1629
1630         if (crypto->cmd == SET_KEY) {
1631                 reg = rt2800_register_read(rt2x00dev, offset);
1632                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1633                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1634                 /*
1635                  * Both the cipher as the BSS Idx numbers are split in a main
1636                  * value of 3 bits, and a extended field for adding one additional
1637                  * bit to the value.
1638                  */
1639                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1640                                    (crypto->cipher & 0x7));
1641                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1642                                    (crypto->cipher & 0x8) >> 3);
1643                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1644                 rt2800_register_write(rt2x00dev, offset, reg);
1645         } else {
1646                 /* Delete the cipher without touching the bssidx */
1647                 reg = rt2800_register_read(rt2x00dev, offset);
1648                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1649                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1650                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1651                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1652                 rt2800_register_write(rt2x00dev, offset, reg);
1653         }
1654
1655         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1656
1657         rt2800_register_multiread(rt2x00dev, offset,
1658                                   &iveiv_entry, sizeof(iveiv_entry));
1659         if ((crypto->cipher == CIPHER_TKIP) ||
1660             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1661             (crypto->cipher == CIPHER_AES))
1662                 iveiv_entry.iv[3] |= 0x20;
1663         iveiv_entry.iv[3] |= key->keyidx << 6;
1664         rt2800_register_multiwrite(rt2x00dev, offset,
1665                                    &iveiv_entry, sizeof(iveiv_entry));
1666 }
1667
1668 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1669                              struct rt2x00lib_crypto *crypto,
1670                              struct ieee80211_key_conf *key)
1671 {
1672         struct hw_key_entry key_entry;
1673         struct rt2x00_field32 field;
1674         u32 offset;
1675         u32 reg;
1676
1677         if (crypto->cmd == SET_KEY) {
1678                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1679
1680                 memcpy(key_entry.key, crypto->key,
1681                        sizeof(key_entry.key));
1682                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1683                        sizeof(key_entry.tx_mic));
1684                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1685                        sizeof(key_entry.rx_mic));
1686
1687                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1688                 rt2800_register_multiwrite(rt2x00dev, offset,
1689                                               &key_entry, sizeof(key_entry));
1690         }
1691
1692         /*
1693          * The cipher types are stored over multiple registers
1694          * starting with SHARED_KEY_MODE_BASE each word will have
1695          * 32 bits and contains the cipher types for 2 bssidx each.
1696          * Using the correct defines correctly will cause overhead,
1697          * so just calculate the correct offset.
1698          */
1699         field.bit_offset = 4 * (key->hw_key_idx % 8);
1700         field.bit_mask = 0x7 << field.bit_offset;
1701
1702         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1703
1704         reg = rt2800_register_read(rt2x00dev, offset);
1705         rt2x00_set_field32(&reg, field,
1706                            (crypto->cmd == SET_KEY) * crypto->cipher);
1707         rt2800_register_write(rt2x00dev, offset, reg);
1708
1709         /*
1710          * Update WCID information
1711          */
1712         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1713         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1714                                        crypto->bssidx);
1715         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1716
1717         return 0;
1718 }
1719 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1720
1721 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1722                                struct rt2x00lib_crypto *crypto,
1723                                struct ieee80211_key_conf *key)
1724 {
1725         struct hw_key_entry key_entry;
1726         u32 offset;
1727
1728         if (crypto->cmd == SET_KEY) {
1729                 /*
1730                  * Allow key configuration only for STAs that are
1731                  * known by the hw.
1732                  */
1733                 if (crypto->wcid > WCID_END)
1734                         return -ENOSPC;
1735                 key->hw_key_idx = crypto->wcid;
1736
1737                 memcpy(key_entry.key, crypto->key,
1738                        sizeof(key_entry.key));
1739                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1740                        sizeof(key_entry.tx_mic));
1741                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1742                        sizeof(key_entry.rx_mic));
1743
1744                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1745                 rt2800_register_multiwrite(rt2x00dev, offset,
1746                                               &key_entry, sizeof(key_entry));
1747         }
1748
1749         /*
1750          * Update WCID information
1751          */
1752         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1753
1754         return 0;
1755 }
1756 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1757
1758 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1759 {
1760         u8 i, max_psdu;
1761         u32 reg;
1762         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1763
1764         for (i = 0; i < 3; i++)
1765                 if (drv_data->ampdu_factor_cnt[i] > 0)
1766                         break;
1767
1768         max_psdu = min(drv_data->max_psdu, i);
1769
1770         reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
1771         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, max_psdu);
1772         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1773 }
1774
1775 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1776                    struct ieee80211_sta *sta)
1777 {
1778         struct rt2x00_dev *rt2x00dev = hw->priv;
1779         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1780         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1781         int wcid;
1782
1783         /*
1784          * Limit global maximum TX AMPDU length to smallest value of all
1785          * connected stations. In AP mode this can be suboptimal, but we
1786          * do not have a choice if some connected STA is not capable to
1787          * receive the same amount of data like the others.
1788          */
1789         if (sta->ht_cap.ht_supported) {
1790                 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++;
1791                 rt2800_set_max_psdu_len(rt2x00dev);
1792         }
1793
1794         /*
1795          * Search for the first free WCID entry and return the corresponding
1796          * index.
1797          */
1798         wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
1799
1800         /*
1801          * Store selected wcid even if it is invalid so that we can
1802          * later decide if the STA is uploaded into the hw.
1803          */
1804         sta_priv->wcid = wcid;
1805
1806         /*
1807          * No space left in the device, however, we can still communicate
1808          * with the STA -> No error.
1809          */
1810         if (wcid > WCID_END)
1811                 return 0;
1812
1813         __set_bit(wcid - WCID_START, drv_data->sta_ids);
1814         drv_data->wcid_to_sta[wcid - WCID_START] = sta;
1815
1816         /*
1817          * Clean up WCID attributes and write STA address to the device.
1818          */
1819         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1820         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1821         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1822                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1823         return 0;
1824 }
1825 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1826
1827 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1828                       struct ieee80211_sta *sta)
1829 {
1830         struct rt2x00_dev *rt2x00dev = hw->priv;
1831         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1832         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1833         int wcid = sta_priv->wcid;
1834
1835         if (sta->ht_cap.ht_supported) {
1836                 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--;
1837                 rt2800_set_max_psdu_len(rt2x00dev);
1838         }
1839
1840         if (wcid > WCID_END)
1841                 return 0;
1842         /*
1843          * Remove WCID entry, no need to clean the attributes as they will
1844          * get renewed when the WCID is reused.
1845          */
1846         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1847         drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1848         __clear_bit(wcid - WCID_START, drv_data->sta_ids);
1849
1850         return 0;
1851 }
1852 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1853
1854 void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev)
1855 {
1856         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1857         struct data_queue *queue = rt2x00dev->bcn;
1858         struct queue_entry *entry;
1859         int i, wcid;
1860
1861         for (wcid = WCID_START; wcid < WCID_END; wcid++) {
1862                 drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1863                 __clear_bit(wcid - WCID_START, drv_data->sta_ids);
1864         }
1865
1866         for (i = 0; i < queue->limit; i++) {
1867                 entry = &queue->entries[i];
1868                 clear_bit(ENTRY_BCN_ASSIGNED, &entry->flags);
1869         }
1870 }
1871 EXPORT_SYMBOL_GPL(rt2800_pre_reset_hw);
1872
1873 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1874                           const unsigned int filter_flags)
1875 {
1876         u32 reg;
1877
1878         /*
1879          * Start configuration steps.
1880          * Note that the version error will always be dropped
1881          * and broadcast frames will always be accepted since
1882          * there is no filter for it at this time.
1883          */
1884         reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG);
1885         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1886                            !(filter_flags & FIF_FCSFAIL));
1887         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1888                            !(filter_flags & FIF_PLCPFAIL));
1889         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1890                            !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
1891         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1892         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1893         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1894                            !(filter_flags & FIF_ALLMULTI));
1895         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1896         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1897         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1898                            !(filter_flags & FIF_CONTROL));
1899         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1900                            !(filter_flags & FIF_CONTROL));
1901         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1902                            !(filter_flags & FIF_CONTROL));
1903         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1904                            !(filter_flags & FIF_CONTROL));
1905         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1906                            !(filter_flags & FIF_CONTROL));
1907         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1908                            !(filter_flags & FIF_PSPOLL));
1909         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1910         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1911                            !(filter_flags & FIF_CONTROL));
1912         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1913                            !(filter_flags & FIF_CONTROL));
1914         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1915 }
1916 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1917
1918 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1919                         struct rt2x00intf_conf *conf, const unsigned int flags)
1920 {
1921         u32 reg;
1922         bool update_bssid = false;
1923
1924         if (flags & CONFIG_UPDATE_TYPE) {
1925                 /*
1926                  * Enable synchronisation.
1927                  */
1928                 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1929                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1930                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1931
1932                 if (conf->sync == TSF_SYNC_AP_NONE) {
1933                         /*
1934                          * Tune beacon queue transmit parameters for AP mode
1935                          */
1936                         reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1937                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1938                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1939                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1940                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1941                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1942                 } else {
1943                         reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1944                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1945                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1946                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1947                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1948                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1949                 }
1950         }
1951
1952         if (flags & CONFIG_UPDATE_MAC) {
1953                 if (flags & CONFIG_UPDATE_TYPE &&
1954                     conf->sync == TSF_SYNC_AP_NONE) {
1955                         /*
1956                          * The BSSID register has to be set to our own mac
1957                          * address in AP mode.
1958                          */
1959                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1960                         update_bssid = true;
1961                 }
1962
1963                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1964                         reg = le32_to_cpu(conf->mac[1]);
1965                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1966                         conf->mac[1] = cpu_to_le32(reg);
1967                 }
1968
1969                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1970                                               conf->mac, sizeof(conf->mac));
1971         }
1972
1973         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1974                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1975                         reg = le32_to_cpu(conf->bssid[1]);
1976                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1977                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
1978                         conf->bssid[1] = cpu_to_le32(reg);
1979                 }
1980
1981                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1982                                               conf->bssid, sizeof(conf->bssid));
1983         }
1984 }
1985 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1986
1987 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1988                                     struct rt2x00lib_erp *erp)
1989 {
1990         bool any_sta_nongf = !!(erp->ht_opmode &
1991                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1992         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1993         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1994         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1995         u32 reg;
1996
1997         /* default protection rate for HT20: OFDM 24M */
1998         mm20_rate = gf20_rate = 0x4004;
1999
2000         /* default protection rate for HT40: duplicate OFDM 24M */
2001         mm40_rate = gf40_rate = 0x4084;
2002
2003         switch (protection) {
2004         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
2005                 /*
2006                  * All STAs in this BSS are HT20/40 but there might be
2007                  * STAs not supporting greenfield mode.
2008                  * => Disable protection for HT transmissions.
2009                  */
2010                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
2011
2012                 break;
2013         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2014                 /*
2015                  * All STAs in this BSS are HT20 or HT20/40 but there
2016                  * might be STAs not supporting greenfield mode.
2017                  * => Protect all HT40 transmissions.
2018                  */
2019                 mm20_mode = gf20_mode = 0;
2020                 mm40_mode = gf40_mode = 1;
2021
2022                 break;
2023         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
2024                 /*
2025                  * Nonmember protection:
2026                  * According to 802.11n we _should_ protect all
2027                  * HT transmissions (but we don't have to).
2028                  *
2029                  * But if cts_protection is enabled we _shall_ protect
2030                  * all HT transmissions using a CCK rate.
2031                  *
2032                  * And if any station is non GF we _shall_ protect
2033                  * GF transmissions.
2034                  *
2035                  * We decide to protect everything
2036                  * -> fall through to mixed mode.
2037                  */
2038         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2039                 /*
2040                  * Legacy STAs are present
2041                  * => Protect all HT transmissions.
2042                  */
2043                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
2044
2045                 /*
2046                  * If erp protection is needed we have to protect HT
2047                  * transmissions with CCK 11M long preamble.
2048                  */
2049                 if (erp->cts_protection) {
2050                         /* don't duplicate RTS/CTS in CCK mode */
2051                         mm20_rate = mm40_rate = 0x0003;
2052                         gf20_rate = gf40_rate = 0x0003;
2053                 }
2054                 break;
2055         }
2056
2057         /* check for STAs not supporting greenfield mode */
2058         if (any_sta_nongf)
2059                 gf20_mode = gf40_mode = 1;
2060
2061         /* Update HT protection config */
2062         reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
2063         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
2064         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
2065         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2066
2067         reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
2068         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
2069         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
2070         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2071
2072         reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
2073         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
2074         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
2075         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2076
2077         reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
2078         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
2079         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
2080         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2081 }
2082
2083 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
2084                        u32 changed)
2085 {
2086         u32 reg;
2087
2088         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2089                 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
2090                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
2091                                    !!erp->short_preamble);
2092                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2093         }
2094
2095         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2096                 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
2097                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
2098                                    erp->cts_protection ? 2 : 0);
2099                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2100         }
2101
2102         if (changed & BSS_CHANGED_BASIC_RATES) {
2103                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
2104                                       0xff0 | erp->basic_rates);
2105                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2106         }
2107
2108         if (changed & BSS_CHANGED_ERP_SLOT) {
2109                 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
2110                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
2111                                    erp->slot_time);
2112                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2113
2114                 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
2115                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
2116                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2117         }
2118
2119         if (changed & BSS_CHANGED_BEACON_INT) {
2120                 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
2121                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
2122                                    erp->beacon_int * 16);
2123                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2124         }
2125
2126         if (changed & BSS_CHANGED_HT)
2127                 rt2800_config_ht_opmode(rt2x00dev, erp);
2128 }
2129 EXPORT_SYMBOL_GPL(rt2800_config_erp);
2130
2131 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
2132 {
2133         u32 reg;
2134         u16 eeprom;
2135         u8 led_ctrl, led_g_mode, led_r_mode;
2136
2137         reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
2138         if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
2139                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
2140                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
2141         } else {
2142                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
2143                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
2144         }
2145         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2146
2147         reg = rt2800_register_read(rt2x00dev, LED_CFG);
2148         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
2149         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
2150         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
2151             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
2152                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
2153                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
2154                 if (led_ctrl == 0 || led_ctrl > 0x40) {
2155                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
2156                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
2157                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2158                 } else {
2159                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
2160                                            (led_g_mode << 2) | led_r_mode, 1);
2161                 }
2162         }
2163 }
2164
2165 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
2166                                      enum antenna ant)
2167 {
2168         u32 reg;
2169         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
2170         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
2171
2172         if (rt2x00_is_pci(rt2x00dev)) {
2173                 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR);
2174                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
2175                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
2176         } else if (rt2x00_is_usb(rt2x00dev))
2177                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
2178                                    eesk_pin, 0);
2179
2180         reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2181         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
2182         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
2183         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2184 }
2185
2186 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
2187 {
2188         u8 r1;
2189         u8 r3;
2190         u16 eeprom;
2191
2192         r1 = rt2800_bbp_read(rt2x00dev, 1);
2193         r3 = rt2800_bbp_read(rt2x00dev, 3);
2194
2195         if (rt2x00_rt(rt2x00dev, RT3572) &&
2196             rt2x00_has_cap_bt_coexist(rt2x00dev))
2197                 rt2800_config_3572bt_ant(rt2x00dev);
2198
2199         /*
2200          * Configure the TX antenna.
2201          */
2202         switch (ant->tx_chain_num) {
2203         case 1:
2204                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
2205                 break;
2206         case 2:
2207                 if (rt2x00_rt(rt2x00dev, RT3572) &&
2208                     rt2x00_has_cap_bt_coexist(rt2x00dev))
2209                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
2210                 else
2211                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2212                 break;
2213         case 3:
2214                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2215                 break;
2216         }
2217
2218         /*
2219          * Configure the RX antenna.
2220          */
2221         switch (ant->rx_chain_num) {
2222         case 1:
2223                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2224                     rt2x00_rt(rt2x00dev, RT3090) ||
2225                     rt2x00_rt(rt2x00dev, RT3352) ||
2226                     rt2x00_rt(rt2x00dev, RT3390)) {
2227                         eeprom = rt2800_eeprom_read(rt2x00dev,
2228                                                     EEPROM_NIC_CONF1);
2229                         if (rt2x00_get_field16(eeprom,
2230                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
2231                                 rt2800_set_ant_diversity(rt2x00dev,
2232                                                 rt2x00dev->default_ant.rx);
2233                 }
2234                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
2235                 break;
2236         case 2:
2237                 if (rt2x00_rt(rt2x00dev, RT3572) &&
2238                     rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2239                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
2240                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
2241                                 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
2242                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2243                 } else {
2244                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
2245                 }
2246                 break;
2247         case 3:
2248                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
2249                 break;
2250         }
2251
2252         rt2800_bbp_write(rt2x00dev, 3, r3);
2253         rt2800_bbp_write(rt2x00dev, 1, r1);
2254
2255         if (rt2x00_rt(rt2x00dev, RT3593) ||
2256             rt2x00_rt(rt2x00dev, RT3883)) {
2257                 if (ant->rx_chain_num == 1)
2258                         rt2800_bbp_write(rt2x00dev, 86, 0x00);
2259                 else
2260                         rt2800_bbp_write(rt2x00dev, 86, 0x46);
2261         }
2262 }
2263 EXPORT_SYMBOL_GPL(rt2800_config_ant);
2264
2265 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2266                                    struct rt2x00lib_conf *libconf)
2267 {
2268         u16 eeprom;
2269         short lna_gain;
2270
2271         if (libconf->rf.channel <= 14) {
2272                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2273                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
2274         } else if (libconf->rf.channel <= 64) {
2275                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2276                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
2277         } else if (libconf->rf.channel <= 128) {
2278                 if (rt2x00_rt(rt2x00dev, RT3593) ||
2279                     rt2x00_rt(rt2x00dev, RT3883)) {
2280                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2281                         lna_gain = rt2x00_get_field16(eeprom,
2282                                                       EEPROM_EXT_LNA2_A1);
2283                 } else {
2284                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
2285                         lna_gain = rt2x00_get_field16(eeprom,
2286                                                       EEPROM_RSSI_BG2_LNA_A1);
2287                 }
2288         } else {
2289                 if (rt2x00_rt(rt2x00dev, RT3593) ||
2290                     rt2x00_rt(rt2x00dev, RT3883)) {
2291                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2292                         lna_gain = rt2x00_get_field16(eeprom,
2293                                                       EEPROM_EXT_LNA2_A2);
2294                 } else {
2295                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
2296                         lna_gain = rt2x00_get_field16(eeprom,
2297                                                       EEPROM_RSSI_A2_LNA_A2);
2298                 }
2299         }
2300
2301         rt2x00dev->lna_gain = lna_gain;
2302 }
2303
2304 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2305 {
2306         return clk_get_rate(rt2x00dev->clk) == 20000000;
2307 }
2308
2309 #define FREQ_OFFSET_BOUND       0x5f
2310
2311 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
2312 {
2313         u8 freq_offset, prev_freq_offset;
2314         u8 rfcsr, prev_rfcsr;
2315
2316         freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2317         freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
2318
2319         rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
2320         prev_rfcsr = rfcsr;
2321
2322         rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
2323         if (rfcsr == prev_rfcsr)
2324                 return;
2325
2326         if (rt2x00_is_usb(rt2x00dev)) {
2327                 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2328                                    freq_offset, prev_rfcsr);
2329                 return;
2330         }
2331
2332         prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
2333         while (prev_freq_offset != freq_offset) {
2334                 if (prev_freq_offset < freq_offset)
2335                         prev_freq_offset++;
2336                 else
2337                         prev_freq_offset--;
2338
2339                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
2340                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2341
2342                 usleep_range(1000, 1500);
2343         }
2344 }
2345
2346 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2347                                          struct ieee80211_conf *conf,
2348                                          struct rf_channel *rf,
2349                                          struct channel_info *info)
2350 {
2351         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2352
2353         if (rt2x00dev->default_ant.tx_chain_num == 1)
2354                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
2355
2356         if (rt2x00dev->default_ant.rx_chain_num == 1) {
2357                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
2358                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2359         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
2360                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2361
2362         if (rf->channel > 14) {
2363                 /*
2364                  * When TX power is below 0, we should increase it by 7 to
2365                  * make it a positive value (Minimum value is -7).
2366                  * However this means that values between 0 and 7 have
2367                  * double meaning, and we should set a 7DBm boost flag.
2368                  */
2369                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
2370                                    (info->default_power1 >= 0));
2371
2372                 if (info->default_power1 < 0)
2373                         info->default_power1 += 7;
2374
2375                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
2376
2377                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
2378                                    (info->default_power2 >= 0));
2379
2380                 if (info->default_power2 < 0)
2381                         info->default_power2 += 7;
2382
2383                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
2384         } else {
2385                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2386                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
2387         }
2388
2389         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2390
2391         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2392         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2393         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2394         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2395
2396         udelay(200);
2397
2398         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2399         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2400         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2401         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2402
2403         udelay(200);
2404
2405         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2406         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2407         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2408         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2409 }
2410
2411 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2412                                          struct ieee80211_conf *conf,
2413                                          struct rf_channel *rf,
2414                                          struct channel_info *info)
2415 {
2416         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2417         u8 rfcsr, calib_tx, calib_rx;
2418
2419         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2420
2421         rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2422         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2423         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2424
2425         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2426         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2427         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2428
2429         rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2430         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2431         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2432
2433         rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2434         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2435         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2436
2437         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2438         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2439         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2440                           rt2x00dev->default_ant.rx_chain_num <= 1);
2441         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2442                           rt2x00dev->default_ant.rx_chain_num <= 2);
2443         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2444         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2445                           rt2x00dev->default_ant.tx_chain_num <= 1);
2446         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2447                           rt2x00dev->default_ant.tx_chain_num <= 2);
2448         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2449
2450         rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2451         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2452         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2453
2454         if (rt2x00_rt(rt2x00dev, RT3390)) {
2455                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2456                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2457         } else {
2458                 if (conf_is_ht40(conf)) {
2459                         calib_tx = drv_data->calibration_bw40;
2460                         calib_rx = drv_data->calibration_bw40;
2461                 } else {
2462                         calib_tx = drv_data->calibration_bw20;
2463                         calib_rx = drv_data->calibration_bw20;
2464                 }
2465         }
2466
2467         rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
2468         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2469         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2470
2471         rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
2472         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2473         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2474
2475         rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2476         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2477         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2478
2479         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2480         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2481         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2482
2483         usleep_range(1000, 1500);
2484
2485         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2486         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2487 }
2488
2489 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2490                                          struct ieee80211_conf *conf,
2491                                          struct rf_channel *rf,
2492                                          struct channel_info *info)
2493 {
2494         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2495         u8 rfcsr;
2496         u32 reg;
2497
2498         if (rf->channel <= 14) {
2499                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2500                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2501         } else {
2502                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2503                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2504         }
2505
2506         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2507         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2508
2509         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2510         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2511         if (rf->channel <= 14)
2512                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2513         else
2514                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2515         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2516
2517         rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
2518         if (rf->channel <= 14)
2519                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2520         else
2521                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2522         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2523
2524         rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2525         if (rf->channel <= 14) {
2526                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2527                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2528                                   info->default_power1);
2529         } else {
2530                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2531                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2532                                 (info->default_power1 & 0x3) |
2533                                 ((info->default_power1 & 0xC) << 1));
2534         }
2535         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2536
2537         rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2538         if (rf->channel <= 14) {
2539                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2540                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2541                                   info->default_power2);
2542         } else {
2543                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2544                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2545                                 (info->default_power2 & 0x3) |
2546                                 ((info->default_power2 & 0xC) << 1));
2547         }
2548         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2549
2550         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2551         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2552         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2553         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2554         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2555         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2556         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2557         if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2558                 if (rf->channel <= 14) {
2559                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2560                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2561                 }
2562                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2563                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2564         } else {
2565                 switch (rt2x00dev->default_ant.tx_chain_num) {
2566                 case 1:
2567                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2568                         /* fall through */
2569                 case 2:
2570                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2571                         break;
2572                 }
2573
2574                 switch (rt2x00dev->default_ant.rx_chain_num) {
2575                 case 1:
2576                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2577                         /* fall through */
2578                 case 2:
2579                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2580                         break;
2581                 }
2582         }
2583         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2584
2585         rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2586         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2587         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2588
2589         if (conf_is_ht40(conf)) {
2590                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2591                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2592         } else {
2593                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2594                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2595         }
2596
2597         if (rf->channel <= 14) {
2598                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2599                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2600                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2601                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2602                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2603                 rfcsr = 0x4c;
2604                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2605                                   drv_data->txmixer_gain_24g);
2606                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2607                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2608                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2609                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2610                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2611                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2612                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2613                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2614         } else {
2615                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2616                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2617                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2618                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2619                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2620                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2621                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2622                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2623                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2624                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2625                 rfcsr = 0x7a;
2626                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2627                                   drv_data->txmixer_gain_5g);
2628                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2629                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2630                 if (rf->channel <= 64) {
2631                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2632                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2633                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2634                 } else if (rf->channel <= 128) {
2635                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2636                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2637                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2638                 } else {
2639                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2640                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2641                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2642                 }
2643                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2644                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2645                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2646         }
2647
2648         reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2649         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2650         if (rf->channel <= 14)
2651                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2652         else
2653                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2654         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2655
2656         rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2657         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2658         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2659 }
2660
2661 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2662                                          struct ieee80211_conf *conf,
2663                                          struct rf_channel *rf,
2664                                          struct channel_info *info)
2665 {
2666         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2667         u8 txrx_agc_fc;
2668         u8 txrx_h20m;
2669         u8 rfcsr;
2670         u8 bbp;
2671         const bool txbf_enabled = false; /* TODO */
2672
2673         /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2674         bbp = rt2800_bbp_read(rt2x00dev, 109);
2675         rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2676         rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2677         rt2800_bbp_write(rt2x00dev, 109, bbp);
2678
2679         bbp = rt2800_bbp_read(rt2x00dev, 110);
2680         rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2681         rt2800_bbp_write(rt2x00dev, 110, bbp);
2682
2683         if (rf->channel <= 14) {
2684                 /* Restore BBP 25 & 26 for 2.4 GHz */
2685                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2686                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2687         } else {
2688                 /* Hard code BBP 25 & 26 for 5GHz */
2689
2690                 /* Enable IQ Phase correction */
2691                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2692                 /* Setup IQ Phase correction value */
2693                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2694         }
2695
2696         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2697         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2698
2699         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2700         rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2701         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2702
2703         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2704         rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2705         if (rf->channel <= 14)
2706                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2707         else
2708                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2709         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2710
2711         rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
2712         if (rf->channel <= 14) {
2713                 rfcsr = 0;
2714                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2715                                   info->default_power1 & 0x1f);
2716         } else {
2717                 if (rt2x00_is_usb(rt2x00dev))
2718                         rfcsr = 0x40;
2719
2720                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2721                                   ((info->default_power1 & 0x18) << 1) |
2722                                   (info->default_power1 & 7));
2723         }
2724         rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2725
2726         rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
2727         if (rf->channel <= 14) {
2728                 rfcsr = 0;
2729                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2730                                   info->default_power2 & 0x1f);
2731         } else {
2732                 if (rt2x00_is_usb(rt2x00dev))
2733                         rfcsr = 0x40;
2734
2735                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2736                                   ((info->default_power2 & 0x18) << 1) |
2737                                   (info->default_power2 & 7));
2738         }
2739         rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2740
2741         rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
2742         if (rf->channel <= 14) {
2743                 rfcsr = 0;
2744                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2745                                   info->default_power3 & 0x1f);
2746         } else {
2747                 if (rt2x00_is_usb(rt2x00dev))
2748                         rfcsr = 0x40;
2749
2750                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2751                                   ((info->default_power3 & 0x18) << 1) |
2752                                   (info->default_power3 & 7));
2753         }
2754         rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2755
2756         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2757         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2758         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2759         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2760         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2761         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2762         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2763         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2764         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2765
2766         switch (rt2x00dev->default_ant.tx_chain_num) {
2767         case 3:
2768                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2769                 /* fallthrough */
2770         case 2:
2771                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2772                 /* fallthrough */
2773         case 1:
2774                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2775                 break;
2776         }
2777
2778         switch (rt2x00dev->default_ant.rx_chain_num) {
2779         case 3:
2780                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2781                 /* fallthrough */
2782         case 2:
2783                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2784                 /* fallthrough */
2785         case 1:
2786                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2787                 break;
2788         }
2789         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2790
2791         rt2800_freq_cal_mode1(rt2x00dev);
2792
2793         if (conf_is_ht40(conf)) {
2794                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2795                                                 RFCSR24_TX_AGC_FC);
2796                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2797                                               RFCSR24_TX_H20M);
2798         } else {
2799                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2800                                                 RFCSR24_TX_AGC_FC);
2801                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2802                                               RFCSR24_TX_H20M);
2803         }
2804
2805         /* NOTE: the reference driver does not writes the new value
2806          * back to RFCSR 32
2807          */
2808         rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
2809         rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2810
2811         if (rf->channel <= 14)
2812                 rfcsr = 0xa0;
2813         else
2814                 rfcsr = 0x80;
2815         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2816
2817         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2818         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2819         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2820         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2821
2822         /* Band selection */
2823         rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2824         if (rf->channel <= 14)
2825                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2826         else
2827                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2828         rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2829
2830         rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
2831         if (rf->channel <= 14)
2832                 rfcsr = 0x3c;
2833         else
2834                 rfcsr = 0x20;
2835         rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2836
2837         rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2838         if (rf->channel <= 14)
2839                 rfcsr = 0x1a;
2840         else
2841                 rfcsr = 0x12;
2842         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2843
2844         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2845         if (rf->channel >= 1 && rf->channel <= 14)
2846                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2847         else if (rf->channel >= 36 && rf->channel <= 64)
2848                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2849         else if (rf->channel >= 100 && rf->channel <= 128)
2850                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2851         else
2852                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2853         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2854
2855         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2856         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2857         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2858
2859         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2860
2861         if (rf->channel <= 14) {
2862                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2863                 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2864         } else {
2865                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2866                 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2867         }
2868
2869         rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2870         rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2871         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2872
2873         rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2874         if (rf->channel <= 14) {
2875                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2876                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2877         } else {
2878                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2879                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2880         }
2881         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2882
2883         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2884         if (rf->channel <= 14)
2885                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2886         else
2887                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2888
2889         if (txbf_enabled)
2890                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2891
2892         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2893
2894         rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2895         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2896         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2897
2898         rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
2899         if (rf->channel <= 14)
2900                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2901         else
2902                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2903         rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2904
2905         if (rf->channel <= 14) {
2906                 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2907                 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2908         } else {
2909                 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2910                 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2911         }
2912
2913         /* Initiate VCO calibration */
2914         rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2915         if (rf->channel <= 14) {
2916                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2917         } else {
2918                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2919                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2920                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2921                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2922                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2923                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2924         }
2925         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2926
2927         if (rf->channel >= 1 && rf->channel <= 14) {
2928                 rfcsr = 0x23;
2929                 if (txbf_enabled)
2930                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2931                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2932
2933                 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2934         } else if (rf->channel >= 36 && rf->channel <= 64) {
2935                 rfcsr = 0x36;
2936                 if (txbf_enabled)
2937                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2938                 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2939
2940                 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2941         } else if (rf->channel >= 100 && rf->channel <= 128) {
2942                 rfcsr = 0x32;
2943                 if (txbf_enabled)
2944                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2945                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2946
2947                 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2948         } else {
2949                 rfcsr = 0x30;
2950                 if (txbf_enabled)
2951                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2952                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2953
2954                 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2955         }
2956 }
2957
2958 static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev,
2959                                          struct ieee80211_conf *conf,
2960                                          struct rf_channel *rf,
2961                                          struct channel_info *info)
2962 {
2963         u8 rfcsr;
2964         u8 bbp;
2965         u8 pwr1, pwr2, pwr3;
2966
2967         const bool txbf_enabled = false; /* TODO */
2968
2969         /* TODO: add band selection */
2970
2971         if (rf->channel <= 14)
2972                 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
2973         else if (rf->channel < 132)
2974                 rt2800_rfcsr_write(rt2x00dev, 6, 0x80);
2975         else
2976                 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
2977
2978         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2979         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2980
2981         if (rf->channel <= 14)
2982                 rt2800_rfcsr_write(rt2x00dev, 11, 0x46);
2983         else
2984                 rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
2985
2986         if (rf->channel <= 14)
2987                 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
2988         else
2989                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2990
2991         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2992
2993         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2994         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2995         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2996         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2997         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2998         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2999         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3000         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3001         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3002
3003         switch (rt2x00dev->default_ant.tx_chain_num) {
3004         case 3:
3005                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
3006                 /* fallthrough */
3007         case 2:
3008                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3009                 /* fallthrough */
3010         case 1:
3011                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3012                 break;
3013         }
3014
3015         switch (rt2x00dev->default_ant.rx_chain_num) {
3016         case 3:
3017                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
3018                 /* fallthrough */
3019         case 2:
3020                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3021                 /* fallthrough */
3022         case 1:
3023                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3024                 break;
3025         }
3026         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3027
3028         rt2800_freq_cal_mode1(rt2x00dev);
3029
3030         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
3031         if (!conf_is_ht40(conf))
3032                 rfcsr &= ~(0x06);
3033         else
3034                 rfcsr |= 0x06;
3035         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3036
3037         if (rf->channel <= 14)
3038                 rt2800_rfcsr_write(rt2x00dev, 31, 0xa0);
3039         else
3040                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3041
3042         if (conf_is_ht40(conf))
3043                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3044         else
3045                 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
3046
3047         if (rf->channel <= 14)
3048                 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
3049         else
3050                 rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
3051
3052         /* loopback RF_BS */
3053         rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
3054         if (rf->channel <= 14)
3055                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
3056         else
3057                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
3058         rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
3059
3060         if (rf->channel <= 14)
3061                 rfcsr = 0x23;
3062         else if (rf->channel < 100)
3063                 rfcsr = 0x36;
3064         else if (rf->channel < 132)
3065                 rfcsr = 0x32;
3066         else
3067                 rfcsr = 0x30;
3068
3069         if (txbf_enabled)
3070                 rfcsr |= 0x40;
3071
3072         rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3073
3074         if (rf->channel <= 14)
3075                 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
3076         else
3077                 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
3078
3079         if (rf->channel <= 14)
3080                 rfcsr = 0xbb;
3081         else if (rf->channel < 100)
3082                 rfcsr = 0xeb;
3083         else if (rf->channel < 132)
3084                 rfcsr = 0xb3;
3085         else
3086                 rfcsr = 0x9b;
3087         rt2800_rfcsr_write(rt2x00dev, 45, rfcsr);
3088
3089         if (rf->channel <= 14)
3090                 rfcsr = 0x8e;
3091         else
3092                 rfcsr = 0x8a;
3093
3094         if (txbf_enabled)
3095                 rfcsr |= 0x20;
3096
3097         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3098
3099         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
3100
3101         rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3102         if (rf->channel <= 14)
3103                 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
3104         else
3105                 rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
3106
3107         rfcsr = rt2800_rfcsr_read(rt2x00dev, 52);
3108         if (rf->channel <= 14)
3109                 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
3110         else
3111                 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
3112
3113         if (rf->channel <= 14) {
3114                 pwr1 = info->default_power1 & 0x1f;
3115                 pwr2 = info->default_power2 & 0x1f;
3116                 pwr3 = info->default_power3 & 0x1f;
3117         } else {
3118                 pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) |
3119                         (info->default_power1 & 0x7);
3120                 pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) |
3121                         (info->default_power2 & 0x7);
3122                 pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) |
3123                         (info->default_power3 & 0x7);
3124         }
3125
3126         rt2800_rfcsr_write(rt2x00dev, 53, pwr1);
3127         rt2800_rfcsr_write(rt2x00dev, 54, pwr2);
3128         rt2800_rfcsr_write(rt2x00dev, 55, pwr3);
3129
3130         rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n",
3131                    rf->channel, pwr1, pwr2, pwr3);
3132
3133         bbp = (info->default_power1 >> 5) |
3134               ((info->default_power2 & 0xe0) >> 1);
3135         rt2800_bbp_write(rt2x00dev, 109, bbp);
3136
3137         bbp = rt2800_bbp_read(rt2x00dev, 110);
3138         bbp &= 0x0f;
3139         bbp |= (info->default_power3 & 0xe0) >> 1;
3140         rt2800_bbp_write(rt2x00dev, 110, bbp);
3141
3142         rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
3143         if (rf->channel <= 14)
3144                 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
3145         else
3146                 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
3147
3148         /* Enable RF tuning */
3149         rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3150         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3151         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3152
3153         udelay(2000);
3154
3155         bbp = rt2800_bbp_read(rt2x00dev, 49);
3156         /* clear update flag */
3157         rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe);
3158         rt2800_bbp_write(rt2x00dev, 49, bbp);
3159
3160         /* TODO: add calibration for TxBF */
3161 }
3162
3163 #define POWER_BOUND             0x27
3164 #define POWER_BOUND_5G          0x2b
3165
3166 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
3167                                          struct ieee80211_conf *conf,
3168                                          struct rf_channel *rf,
3169                                          struct channel_info *info)
3170 {
3171         u8 rfcsr;
3172
3173         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3174         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3175         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3176         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3177         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3178
3179         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3180         if (info->default_power1 > POWER_BOUND)
3181                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3182         else
3183                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3184         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3185
3186         rt2800_freq_cal_mode1(rt2x00dev);
3187
3188         if (rf->channel <= 14) {
3189                 if (rf->channel == 6)
3190                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
3191                 else
3192                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3193
3194                 if (rf->channel >= 1 && rf->channel <= 6)
3195                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
3196                 else if (rf->channel >= 7 && rf->channel <= 11)
3197                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
3198                 else if (rf->channel >= 12 && rf->channel <= 14)
3199                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
3200         }
3201 }
3202
3203 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
3204                                          struct ieee80211_conf *conf,
3205                                          struct rf_channel *rf,
3206                                          struct channel_info *info)
3207 {
3208         u8 rfcsr;
3209
3210         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3211         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3212
3213         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
3214         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
3215         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
3216
3217         if (info->default_power1 > POWER_BOUND)
3218                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
3219         else
3220                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
3221
3222         if (info->default_power2 > POWER_BOUND)
3223                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
3224         else
3225                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
3226
3227         rt2800_freq_cal_mode1(rt2x00dev);
3228
3229         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3230         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3231         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3232
3233         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
3234                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3235         else
3236                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
3237
3238         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
3239                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3240         else
3241                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
3242
3243         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3244         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3245
3246         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3247
3248         rt2800_rfcsr_write(rt2x00dev, 31, 80);
3249 }
3250
3251 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
3252                                          struct ieee80211_conf *conf,
3253                                          struct rf_channel *rf,
3254                                          struct channel_info *info)
3255 {
3256         u8 rfcsr;
3257         int idx = rf->channel-1;
3258
3259         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3260         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3261         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3262         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3263         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3264
3265         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3266         if (info->default_power1 > POWER_BOUND)
3267                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3268         else
3269                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3270         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3271
3272         if (rt2x00_rt(rt2x00dev, RT5392)) {
3273                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3274                 if (info->default_power2 > POWER_BOUND)
3275                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
3276                 else
3277                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
3278                                           info->default_power2);
3279                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3280         }
3281
3282         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3283         if (rt2x00_rt(rt2x00dev, RT5392)) {
3284                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3285                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3286         }
3287         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3288         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3289         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3290         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3291         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3292
3293         rt2800_freq_cal_mode1(rt2x00dev);
3294
3295         if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
3296                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3297                         /* r55/r59 value array of channel 1~14 */
3298                         static const char r55_bt_rev[] = {0x83, 0x83,
3299                                 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
3300                                 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
3301                         static const char r59_bt_rev[] = {0x0e, 0x0e,
3302                                 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
3303                                 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
3304
3305                         rt2800_rfcsr_write(rt2x00dev, 55,
3306                                            r55_bt_rev[idx]);
3307                         rt2800_rfcsr_write(rt2x00dev, 59,
3308                                            r59_bt_rev[idx]);
3309                 } else {
3310                         static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
3311                                 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
3312                                 0x88, 0x88, 0x86, 0x85, 0x84};
3313
3314                         rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
3315                 }
3316         } else {
3317                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3318                         static const char r55_nonbt_rev[] = {0x23, 0x23,
3319                                 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
3320                                 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
3321                         static const char r59_nonbt_rev[] = {0x07, 0x07,
3322                                 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
3323                                 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
3324
3325                         rt2800_rfcsr_write(rt2x00dev, 55,
3326                                            r55_nonbt_rev[idx]);
3327                         rt2800_rfcsr_write(rt2x00dev, 59,
3328                                            r59_nonbt_rev[idx]);
3329                 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3330                            rt2x00_rt(rt2x00dev, RT5392) ||
3331                            rt2x00_rt(rt2x00dev, RT6352)) {
3332                         static const char r59_non_bt[] = {0x8f, 0x8f,
3333                                 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
3334                                 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
3335
3336                         rt2800_rfcsr_write(rt2x00dev, 59,
3337                                            r59_non_bt[idx]);
3338                 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
3339                         static const char r59_non_bt[] = {0x0b, 0x0b,
3340                                 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
3341                                 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
3342
3343                         rt2800_rfcsr_write(rt2x00dev, 59,
3344                                            r59_non_bt[idx]);
3345                 }
3346         }
3347 }
3348
3349 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
3350                                          struct ieee80211_conf *conf,
3351                                          struct rf_channel *rf,
3352                                          struct channel_info *info)
3353 {
3354         u8 rfcsr, ep_reg;
3355         u32 reg;
3356         int power_bound;
3357
3358         /* TODO */
3359         const bool is_11b = false;
3360         const bool is_type_ep = false;
3361
3362         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
3363         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
3364                            (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
3365         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3366
3367         /* Order of values on rf_channel entry: N, K, mod, R */
3368         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
3369
3370         rfcsr = rt2800_rfcsr_read(rt2x00dev,  9);
3371         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
3372         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
3373         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
3374         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
3375
3376         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3377         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
3378         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
3379         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3380
3381         if (rf->channel <= 14) {
3382                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
3383                 /* FIXME: RF11 owerwrite ? */
3384                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
3385                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3386                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3387                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3388                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
3389                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3390                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3391                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
3392                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3393                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3394                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
3395                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
3396                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
3397                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
3398                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
3399                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
3400                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
3401                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
3402                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3403                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
3404                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3405                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3406                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
3407                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3408                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3409                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3410                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3411                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3412
3413                 /* TODO RF27 <- tssi */
3414
3415                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
3416                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
3417                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
3418
3419                 if (is_11b) {
3420                         /* CCK */
3421                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
3422                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
3423                         if (is_type_ep)
3424                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
3425                         else
3426                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
3427                 } else {
3428                         /* OFDM */
3429                         if (is_type_ep)
3430                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
3431                         else
3432                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3433                 }
3434
3435                 power_bound = POWER_BOUND;
3436                 ep_reg = 0x2;
3437         } else {
3438                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
3439                 /* FIMXE: RF11 overwrite */
3440                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
3441                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
3442                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3443                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3444                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
3445                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3446                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
3447                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3448                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3449                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3450                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3451                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3452                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3453                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3454
3455                 /* TODO RF27 <- tssi */
3456
3457                 if (rf->channel >= 36 && rf->channel <= 64) {
3458
3459                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3460                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3461                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3462                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3463                         if (rf->channel <= 50)
3464                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3465                         else if (rf->channel >= 52)
3466                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3467                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3468                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3469                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3470                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3471                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3472                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3473                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3474                         if (rf->channel <= 50) {
3475                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
3476                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3477                         } else if (rf->channel >= 52) {
3478                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3479                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3480                         }
3481
3482                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3483                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3484                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3485
3486                 } else if (rf->channel >= 100 && rf->channel <= 165) {
3487
3488                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3489                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3490                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3491                         if (rf->channel <= 153) {
3492                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3493                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3494                         } else if (rf->channel >= 155) {
3495                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3496                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3497                         }
3498                         if (rf->channel <= 138) {
3499                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3500                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3501                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3502                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3503                         } else if (rf->channel >= 140) {
3504                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3505                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3506                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3507                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3508                         }
3509                         if (rf->channel <= 124)
3510                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3511                         else if (rf->channel >= 126)
3512                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3513                         if (rf->channel <= 138)
3514                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3515                         else if (rf->channel >= 140)
3516                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3517                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3518                         if (rf->channel <= 138)
3519                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3520                         else if (rf->channel >= 140)
3521                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3522                         if (rf->channel <= 128)
3523                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3524                         else if (rf->channel >= 130)
3525                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3526                         if (rf->channel <= 116)
3527                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3528                         else if (rf->channel >= 118)
3529                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3530                         if (rf->channel <= 138)
3531                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3532                         else if (rf->channel >= 140)
3533                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3534                         if (rf->channel <= 116)
3535                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3536                         else if (rf->channel >= 118)
3537                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3538                 }
3539
3540                 power_bound = POWER_BOUND_5G;
3541                 ep_reg = 0x3;
3542         }
3543
3544         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3545         if (info->default_power1 > power_bound)
3546                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
3547         else
3548                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3549         if (is_type_ep)
3550                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
3551         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3552
3553         rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3554         if (info->default_power2 > power_bound)
3555                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
3556         else
3557                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
3558         if (is_type_ep)
3559                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
3560         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3561
3562         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3563         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3564         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3565
3566         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
3567                           rt2x00dev->default_ant.tx_chain_num >= 1);
3568         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
3569                           rt2x00dev->default_ant.tx_chain_num == 2);
3570         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3571
3572         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
3573                           rt2x00dev->default_ant.rx_chain_num >= 1);
3574         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
3575                           rt2x00dev->default_ant.rx_chain_num == 2);
3576         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3577
3578         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3579         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3580
3581         if (conf_is_ht40(conf))
3582                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3583         else
3584                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3585
3586         if (!is_11b) {
3587                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3588                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3589         }
3590
3591         /* TODO proper frequency adjustment */
3592         rt2800_freq_cal_mode1(rt2x00dev);
3593
3594         /* TODO merge with others */
3595         rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3596         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3597         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3598
3599         /* BBP settings */
3600         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3601         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3602         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3603
3604         rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3605         rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3606         rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3607         rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3608
3609         /* GLRT band configuration */
3610         rt2800_bbp_write(rt2x00dev, 195, 128);
3611         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3612         rt2800_bbp_write(rt2x00dev, 195, 129);
3613         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3614         rt2800_bbp_write(rt2x00dev, 195, 130);
3615         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3616         rt2800_bbp_write(rt2x00dev, 195, 131);
3617         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3618         rt2800_bbp_write(rt2x00dev, 195, 133);
3619         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3620         rt2800_bbp_write(rt2x00dev, 195, 124);
3621         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3622 }
3623
3624 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3625                                          struct ieee80211_conf *conf,
3626                                          struct rf_channel *rf,
3627                                          struct channel_info *info)
3628 {
3629         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3630         u8 rx_agc_fc, tx_agc_fc;
3631         u8 rfcsr;
3632
3633         /* Frequeny plan setting */
3634         /* Rdiv setting (set 0x03 if Xtal==20)
3635          * R13[1:0]
3636          */
3637         rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
3638         rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
3639                           rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3640         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3641
3642         /* N setting
3643          * R20[7:0] in rf->rf1
3644          * R21[0] always 0
3645          */
3646         rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
3647         rfcsr = (rf->rf1 & 0x00ff);
3648         rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3649
3650         rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3651         rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
3652         rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3653
3654         /* K setting (always 0)
3655          * R16[3:0] (RF PLL freq selection)
3656          */
3657         rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3658         rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
3659         rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3660
3661         /* D setting (always 0)
3662          * R22[2:0] (D=15, R22[2:0]=<111>)
3663          */
3664         rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
3665         rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
3666         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3667
3668         /* Ksd setting
3669          * Ksd: R17<7:0> in rf->rf2
3670          *      R18<7:0> in rf->rf3
3671          *      R19<1:0> in rf->rf4
3672          */
3673         rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3674         rfcsr = rf->rf2;
3675         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3676
3677         rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
3678         rfcsr = rf->rf3;
3679         rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3680
3681         rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
3682         rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
3683         rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3684
3685         /* Default: XO=20MHz , SDM mode */
3686         rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3687         rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
3688         rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3689
3690         rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3691         rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
3692         rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3693
3694         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3695         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
3696                           rt2x00dev->default_ant.tx_chain_num != 1);
3697         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3698
3699         rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
3700         rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
3701                           rt2x00dev->default_ant.tx_chain_num != 1);
3702         rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
3703                           rt2x00dev->default_ant.rx_chain_num != 1);
3704         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3705
3706         rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
3707         rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
3708                           rt2x00dev->default_ant.tx_chain_num != 1);
3709         rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3710
3711         /* RF for DC Cal BW */
3712         if (conf_is_ht40(conf)) {
3713                 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3714                 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3715                 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3716                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3717                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3718         } else {
3719                 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3720                 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3721                 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3722                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3723                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3724         }
3725
3726         if (conf_is_ht40(conf)) {
3727                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3728                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3729         } else {
3730                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3731                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3732         }
3733
3734         rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
3735         rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
3736                           conf_is_ht40(conf) && (rf->channel == 11));
3737         rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3738
3739         if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3740                 if (conf_is_ht40(conf)) {
3741                         rx_agc_fc = drv_data->rx_calibration_bw40;
3742                         tx_agc_fc = drv_data->tx_calibration_bw40;
3743                 } else {
3744                         rx_agc_fc = drv_data->rx_calibration_bw20;
3745                         tx_agc_fc = drv_data->tx_calibration_bw20;
3746                 }
3747                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
3748                 rfcsr &= (~0x3F);
3749                 rfcsr |= rx_agc_fc;
3750                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3751                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
3752                 rfcsr &= (~0x3F);
3753                 rfcsr |= rx_agc_fc;
3754                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3755                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
3756                 rfcsr &= (~0x3F);
3757                 rfcsr |= rx_agc_fc;
3758                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3759                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
3760                 rfcsr &= (~0x3F);
3761                 rfcsr |= rx_agc_fc;
3762                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3763
3764                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
3765                 rfcsr &= (~0x3F);
3766                 rfcsr |= tx_agc_fc;
3767                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3768                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
3769                 rfcsr &= (~0x3F);
3770                 rfcsr |= tx_agc_fc;
3771                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3772                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
3773                 rfcsr &= (~0x3F);
3774                 rfcsr |= tx_agc_fc;
3775                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3776                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
3777                 rfcsr &= (~0x3F);
3778                 rfcsr |= tx_agc_fc;
3779                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3780         }
3781 }
3782
3783 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
3784                               struct ieee80211_channel *chan,
3785                               int power_level) {
3786         u16 eeprom, target_power, max_power;
3787         u32 mac_sys_ctrl, mac_status;
3788         u32 reg;
3789         u8 bbp;
3790         int i;
3791
3792         /* hardware unit is 0.5dBm, limited to 23.5dBm */
3793         power_level *= 2;
3794         if (power_level > 0x2f)
3795                 power_level = 0x2f;
3796
3797         max_power = chan->max_power * 2;
3798         if (max_power > 0x2f)
3799                 max_power = 0x2f;
3800
3801         reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
3802         rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, power_level);
3803         rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, power_level);
3804         rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, max_power);
3805         rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, max_power);
3806
3807         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3808         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
3809                 /* init base power by eeprom target power */
3810                 target_power = rt2800_eeprom_read(rt2x00dev,
3811                                                   EEPROM_TXPOWER_INIT);
3812                 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
3813                 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
3814         }
3815         rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3816
3817         reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
3818         rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
3819         rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3820
3821         /* Save MAC SYS CTRL registers */
3822         mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
3823         /* Disable Tx/Rx */
3824         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3825         /* Check MAC Tx/Rx idle */
3826         for (i = 0; i < 10000; i++) {
3827                 mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
3828                 if (mac_status & 0x3)
3829                         usleep_range(50, 200);
3830                 else
3831                         break;
3832         }
3833
3834         if (i == 10000)
3835                 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
3836
3837         if (chan->center_freq > 2457) {
3838                 bbp = rt2800_bbp_read(rt2x00dev, 30);
3839                 bbp = 0x40;
3840                 rt2800_bbp_write(rt2x00dev, 30, bbp);
3841                 rt2800_rfcsr_write(rt2x00dev, 39, 0);
3842                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3843                         rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3844                 else
3845                         rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3846         } else {
3847                 bbp = rt2800_bbp_read(rt2x00dev, 30);
3848                 bbp = 0x1f;
3849                 rt2800_bbp_write(rt2x00dev, 30, bbp);
3850                 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
3851                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3852                         rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
3853                 else
3854                         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
3855         }
3856         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
3857
3858         rt2800_vco_calibration(rt2x00dev);
3859 }
3860
3861 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3862                                            const unsigned int word,
3863                                            const u8 value)
3864 {
3865         u8 chain, reg;
3866
3867         for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3868                 reg = rt2800_bbp_read(rt2x00dev, 27);
3869                 rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
3870                 rt2800_bbp_write(rt2x00dev, 27, reg);
3871
3872                 rt2800_bbp_write(rt2x00dev, word, value);
3873         }
3874 }
3875
3876 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3877 {
3878         u8 cal;
3879
3880         /* TX0 IQ Gain */
3881         rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3882         if (channel <= 14)
3883                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3884         else if (channel >= 36 && channel <= 64)
3885                 cal = rt2x00_eeprom_byte(rt2x00dev,
3886                                          EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3887         else if (channel >= 100 && channel <= 138)
3888                 cal = rt2x00_eeprom_byte(rt2x00dev,
3889                                          EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3890         else if (channel >= 140 && channel <= 165)
3891                 cal = rt2x00_eeprom_byte(rt2x00dev,
3892                                          EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3893         else
3894                 cal = 0;
3895         rt2800_bbp_write(rt2x00dev, 159, cal);
3896
3897         /* TX0 IQ Phase */
3898         rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3899         if (channel <= 14)
3900                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3901         else if (channel >= 36 && channel <= 64)
3902                 cal = rt2x00_eeprom_byte(rt2x00dev,
3903                                          EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3904         else if (channel >= 100 && channel <= 138)
3905                 cal = rt2x00_eeprom_byte(rt2x00dev,
3906                                          EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3907         else if (channel >= 140 && channel <= 165)
3908                 cal = rt2x00_eeprom_byte(rt2x00dev,
3909                                          EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3910         else
3911                 cal = 0;
3912         rt2800_bbp_write(rt2x00dev, 159, cal);
3913
3914         /* TX1 IQ Gain */
3915         rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3916         if (channel <= 14)
3917                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3918         else if (channel >= 36 && channel <= 64)
3919                 cal = rt2x00_eeprom_byte(rt2x00dev,
3920                                          EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3921         else if (channel >= 100 && channel <= 138)
3922                 cal = rt2x00_eeprom_byte(rt2x00dev,
3923                                          EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3924         else if (channel >= 140 && channel <= 165)
3925                 cal = rt2x00_eeprom_byte(rt2x00dev,
3926                                          EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3927         else
3928                 cal = 0;
3929         rt2800_bbp_write(rt2x00dev, 159, cal);
3930
3931         /* TX1 IQ Phase */
3932         rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3933         if (channel <= 14)
3934                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3935         else if (channel >= 36 && channel <= 64)
3936                 cal = rt2x00_eeprom_byte(rt2x00dev,
3937                                          EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3938         else if (channel >= 100 && channel <= 138)
3939                 cal = rt2x00_eeprom_byte(rt2x00dev,
3940                                          EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3941         else if (channel >= 140 && channel <= 165)
3942                 cal = rt2x00_eeprom_byte(rt2x00dev,
3943                                          EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3944         else
3945                 cal = 0;
3946         rt2800_bbp_write(rt2x00dev, 159, cal);
3947
3948         /* FIXME: possible RX0, RX1 callibration ? */
3949
3950         /* RF IQ compensation control */
3951         rt2800_bbp_write(rt2x00dev, 158, 0x04);
3952         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3953         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3954
3955         /* RF IQ imbalance compensation control */
3956         rt2800_bbp_write(rt2x00dev, 158, 0x03);
3957         cal = rt2x00_eeprom_byte(rt2x00dev,
3958                                  EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3959         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3960 }
3961
3962 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3963                                   unsigned int channel,
3964                                   char txpower)
3965 {
3966         if (rt2x00_rt(rt2x00dev, RT3593) ||
3967             rt2x00_rt(rt2x00dev, RT3883))
3968                 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3969
3970         if (channel <= 14)
3971                 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3972
3973         if (rt2x00_rt(rt2x00dev, RT3593) ||
3974             rt2x00_rt(rt2x00dev, RT3883))
3975                 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3976                                MAX_A_TXPOWER_3593);
3977         else
3978                 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3979 }
3980
3981 static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,
3982                               struct rf_channel *rf)
3983 {
3984         u8 bbp;
3985
3986         bbp = (rf->channel > 14) ? 0x48 : 0x38;
3987         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
3988
3989         rt2800_bbp_write(rt2x00dev, 69, 0x12);
3990
3991         if (rf->channel <= 14) {
3992                 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3993         } else {
3994                 /* Disable CCK packet detection */
3995                 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3996         }
3997
3998         rt2800_bbp_write(rt2x00dev, 73, 0x10);
3999
4000         if (rf->channel > 14) {
4001                 rt2800_bbp_write(rt2x00dev, 62, 0x1d);
4002                 rt2800_bbp_write(rt2x00dev, 63, 0x1d);
4003                 rt2800_bbp_write(rt2x00dev, 64, 0x1d);
4004         } else {
4005                 rt2800_bbp_write(rt2x00dev, 62, 0x2d);
4006                 rt2800_bbp_write(rt2x00dev, 63, 0x2d);
4007                 rt2800_bbp_write(rt2x00dev, 64, 0x2d);
4008         }
4009 }
4010
4011 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
4012                                   struct ieee80211_conf *conf,
4013                                   struct rf_channel *rf,
4014                                   struct channel_info *info)
4015 {
4016         u32 reg;
4017         u32 tx_pin;
4018         u8 bbp, rfcsr;
4019
4020         info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4021                                                      info->default_power1);
4022         info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4023                                                      info->default_power2);
4024         if (rt2x00dev->default_ant.tx_chain_num > 2)
4025                 info->default_power3 =
4026                         rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4027                                               info->default_power3);
4028
4029         switch (rt2x00dev->chip.rt) {
4030         case RT3883:
4031                 rt3883_bbp_adjust(rt2x00dev, rf);
4032                 break;
4033         }
4034
4035         switch (rt2x00dev->chip.rf) {
4036         case RF2020:
4037         case RF3020:
4038         case RF3021:
4039         case RF3022:
4040         case RF3320:
4041                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
4042                 break;
4043         case RF3052:
4044                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
4045                 break;
4046         case RF3053:
4047                 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
4048                 break;
4049         case RF3290:
4050                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
4051                 break;
4052         case RF3322:
4053                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
4054                 break;
4055         case RF3853:
4056                 rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info);
4057                 break;
4058         case RF3070:
4059         case RF5350:
4060         case RF5360:
4061         case RF5362:
4062         case RF5370:
4063         case RF5372:
4064         case RF5390:
4065         case RF5392:
4066                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
4067                 break;
4068         case RF5592:
4069                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
4070                 break;
4071         case RF7620:
4072                 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
4073                 break;
4074         default:
4075                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
4076         }
4077
4078         if (rt2x00_rf(rt2x00dev, RF3070) ||
4079             rt2x00_rf(rt2x00dev, RF3290) ||
4080             rt2x00_rf(rt2x00dev, RF3322) ||
4081             rt2x00_rf(rt2x00dev, RF5350) ||
4082             rt2x00_rf(rt2x00dev, RF5360) ||
4083             rt2x00_rf(rt2x00dev, RF5362) ||
4084             rt2x00_rf(rt2x00dev, RF5370) ||
4085             rt2x00_rf(rt2x00dev, RF5372) ||
4086             rt2x00_rf(rt2x00dev, RF5390) ||
4087             rt2x00_rf(rt2x00dev, RF5392)) {
4088                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
4089                 if (rt2x00_rf(rt2x00dev, RF3322)) {
4090                         rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M,
4091                                           conf_is_ht40(conf));
4092                         rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M,
4093                                           conf_is_ht40(conf));
4094                 } else {
4095                         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M,
4096                                           conf_is_ht40(conf));
4097                         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M,
4098                                           conf_is_ht40(conf));
4099                 }
4100                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4101
4102                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
4103                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4104                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4105         }
4106
4107         /*
4108          * Change BBP settings
4109          */
4110
4111         if (rt2x00_rt(rt2x00dev, RT3352)) {
4112                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4113                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4114                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4115
4116                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
4117                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4118                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
4119                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4120                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4121                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4122         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4123                 if (rf->channel > 14) {
4124                         /* Disable CCK Packet detection on 5GHz */
4125                         rt2800_bbp_write(rt2x00dev, 70, 0x00);
4126                 } else {
4127                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4128                 }
4129
4130                 if (conf_is_ht40(conf))
4131                         rt2800_bbp_write(rt2x00dev, 105, 0x04);
4132                 else
4133                         rt2800_bbp_write(rt2x00dev, 105, 0x34);
4134
4135                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4136                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4137                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4138                 rt2800_bbp_write(rt2x00dev, 77, 0x98);
4139         } else if (rt2x00_rt(rt2x00dev, RT3883)) {
4140                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4141                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4142                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4143
4144                 if (rt2x00dev->default_ant.rx_chain_num > 1)
4145                         rt2800_bbp_write(rt2x00dev, 86, 0x46);
4146                 else
4147                         rt2800_bbp_write(rt2x00dev, 86, 0);
4148         } else {
4149                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4150                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4151                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4152                 rt2800_bbp_write(rt2x00dev, 86, 0);
4153         }
4154
4155         if (rf->channel <= 14) {
4156                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4157                     !rt2x00_rt(rt2x00dev, RT5392) &&
4158                     !rt2x00_rt(rt2x00dev, RT6352)) {
4159                         if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4160                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4161                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4162                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4163                         } else {
4164                                 if (rt2x00_rt(rt2x00dev, RT3593))
4165                                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4166                                 else
4167                                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
4168                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
4169                         }
4170                         if (rt2x00_rt(rt2x00dev, RT3593) ||
4171                             rt2x00_rt(rt2x00dev, RT3883))
4172                                 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
4173                 }
4174
4175         } else {
4176                 if (rt2x00_rt(rt2x00dev, RT3572))
4177                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
4178                 else if (rt2x00_rt(rt2x00dev, RT3593) ||
4179                          rt2x00_rt(rt2x00dev, RT3883))
4180                         rt2800_bbp_write(rt2x00dev, 82, 0x82);
4181                 else if (!rt2x00_rt(rt2x00dev, RT6352))
4182                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
4183
4184                 if (rt2x00_rt(rt2x00dev, RT3593) ||
4185                     rt2x00_rt(rt2x00dev, RT3883))
4186                         rt2800_bbp_write(rt2x00dev, 83, 0x9a);
4187
4188                 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
4189                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
4190                 else
4191                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
4192         }
4193
4194         reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG);
4195         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
4196         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
4197         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
4198         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
4199
4200         if (rt2x00_rt(rt2x00dev, RT3572))
4201                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
4202
4203         if (rt2x00_rt(rt2x00dev, RT6352)) {
4204                 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4205                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1);
4206         } else {
4207                 tx_pin = 0;
4208         }
4209
4210         switch (rt2x00dev->default_ant.tx_chain_num) {
4211         case 3:
4212                 /* Turn on tertiary PAs */
4213                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
4214                                    rf->channel > 14);
4215                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
4216                                    rf->channel <= 14);
4217                 /* fall-through */
4218         case 2:
4219                 /* Turn on secondary PAs */
4220                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
4221                                    rf->channel > 14);
4222                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
4223                                    rf->channel <= 14);
4224                 /* fall-through */
4225         case 1:
4226                 /* Turn on primary PAs */
4227                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
4228                                    rf->channel > 14);
4229                 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
4230                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4231                 else
4232                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
4233                                            rf->channel <= 14);
4234                 break;
4235         }
4236
4237         switch (rt2x00dev->default_ant.rx_chain_num) {
4238         case 3:
4239                 /* Turn on tertiary LNAs */
4240                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN,
4241                                    rf->channel > 14);
4242                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN,
4243                                    rf->channel <= 14);
4244                 /* fall-through */
4245         case 2:
4246                 /* Turn on secondary LNAs */
4247                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN,
4248                                    rf->channel > 14);
4249                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN,
4250                                    rf->channel <= 14);
4251                 /* fall-through */
4252         case 1:
4253                 /* Turn on primary LNAs */
4254                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN,
4255                                    rf->channel > 14);
4256                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN,
4257                                    rf->channel <= 14);
4258                 break;
4259         }
4260
4261         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
4262         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
4263
4264         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4265
4266         if (rt2x00_rt(rt2x00dev, RT3572)) {
4267                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
4268
4269                 /* AGC init */
4270                 if (rf->channel <= 14)
4271                         reg = 0x1c + (2 * rt2x00dev->lna_gain);
4272                 else
4273                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4274
4275                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4276         }
4277
4278         if (rt2x00_rt(rt2x00dev, RT3593)) {
4279                 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
4280
4281                 /* Band selection */
4282                 if (rt2x00_is_usb(rt2x00dev) ||
4283                     rt2x00_is_pcie(rt2x00dev)) {
4284                         /* GPIO #8 controls all paths */
4285                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
4286                         if (rf->channel <= 14)
4287                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
4288                         else
4289                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
4290                 }
4291
4292                 /* LNA PE control. */
4293                 if (rt2x00_is_usb(rt2x00dev)) {
4294                         /* GPIO #4 controls PE0 and PE1,
4295                          * GPIO #7 controls PE2
4296                          */
4297                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
4298                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
4299
4300                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
4301                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
4302                 } else if (rt2x00_is_pcie(rt2x00dev)) {
4303                         /* GPIO #4 controls PE0, PE1 and PE2 */
4304                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
4305                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
4306                 }
4307
4308                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4309
4310                 /* AGC init */
4311                 if (rf->channel <= 14)
4312                         reg = 0x1c + 2 * rt2x00dev->lna_gain;
4313                 else
4314                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4315
4316                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4317
4318                 usleep_range(1000, 1500);
4319         }
4320
4321         if (rt2x00_rt(rt2x00dev, RT3883)) {
4322                 if (!conf_is_ht40(conf))
4323                         rt2800_bbp_write(rt2x00dev, 105, 0x34);
4324                 else
4325                         rt2800_bbp_write(rt2x00dev, 105, 0x04);
4326
4327                 /* AGC init */
4328                 if (rf->channel <= 14)
4329                         reg = 0x2e + rt2x00dev->lna_gain;
4330                 else
4331                         reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3);
4332
4333                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4334
4335                 usleep_range(1000, 1500);
4336         }
4337
4338         if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
4339                 reg = 0x10;
4340                 if (!conf_is_ht40(conf)) {
4341                         if (rt2x00_rt(rt2x00dev, RT6352) &&
4342                             rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4343                                 reg |= 0x5;
4344                         } else {
4345                                 reg |= 0xa;
4346                         }
4347                 }
4348                 rt2800_bbp_write(rt2x00dev, 195, 141);
4349                 rt2800_bbp_write(rt2x00dev, 196, reg);
4350
4351                 /* AGC init.
4352                  * Despite the vendor driver using different values here for
4353                  * RT6352 chip, we use 0x1c for now. This may have to be changed
4354                  * once TSSI got implemented.
4355                  */
4356                 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
4357                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4358
4359                 rt2800_iq_calibrate(rt2x00dev, rf->channel);
4360         }
4361
4362         bbp = rt2800_bbp_read(rt2x00dev, 4);
4363         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
4364         rt2800_bbp_write(rt2x00dev, 4, bbp);
4365
4366         bbp = rt2800_bbp_read(rt2x00dev, 3);
4367         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
4368         rt2800_bbp_write(rt2x00dev, 3, bbp);
4369
4370         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4371                 if (conf_is_ht40(conf)) {
4372                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
4373                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4374                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
4375                 } else {
4376                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
4377                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
4378                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
4379                 }
4380         }
4381
4382         usleep_range(1000, 1500);
4383
4384         /*
4385          * Clear channel statistic counters
4386          */
4387         reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
4388         reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
4389         reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
4390
4391         /*
4392          * Clear update flag
4393          */
4394         if (rt2x00_rt(rt2x00dev, RT3352) ||
4395             rt2x00_rt(rt2x00dev, RT5350)) {
4396                 bbp = rt2800_bbp_read(rt2x00dev, 49);
4397                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
4398                 rt2800_bbp_write(rt2x00dev, 49, bbp);
4399         }
4400 }
4401
4402 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
4403 {
4404         u8 tssi_bounds[9];
4405         u8 current_tssi;
4406         u16 eeprom;
4407         u8 step;
4408         int i;
4409
4410         /*
4411          * First check if temperature compensation is supported.
4412          */
4413         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
4414         if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
4415                 return 0;
4416
4417         /*
4418          * Read TSSI boundaries for temperature compensation from
4419          * the EEPROM.
4420          *
4421          * Array idx               0    1    2    3    4    5    6    7    8
4422          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
4423          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
4424          */
4425         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
4426                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1);
4427                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
4428                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
4429                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
4430                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
4431
4432                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2);
4433                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
4434                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
4435                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
4436                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
4437
4438                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3);
4439                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
4440                                         EEPROM_TSSI_BOUND_BG3_REF);
4441                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
4442                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
4443
4444                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4);
4445                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
4446                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
4447                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
4448                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
4449
4450                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5);
4451                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
4452                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
4453
4454                 step = rt2x00_get_field16(eeprom,
4455                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
4456         } else {
4457                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1);
4458                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
4459                                         EEPROM_TSSI_BOUND_A1_MINUS4);
4460                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
4461                                         EEPROM_TSSI_BOUND_A1_MINUS3);
4462
4463                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2);
4464                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
4465                                         EEPROM_TSSI_BOUND_A2_MINUS2);
4466                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
4467                                         EEPROM_TSSI_BOUND_A2_MINUS1);
4468
4469                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3);
4470                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
4471                                         EEPROM_TSSI_BOUND_A3_REF);
4472                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
4473                                         EEPROM_TSSI_BOUND_A3_PLUS1);
4474
4475                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4);
4476                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
4477                                         EEPROM_TSSI_BOUND_A4_PLUS2);
4478                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
4479                                         EEPROM_TSSI_BOUND_A4_PLUS3);
4480
4481                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5);
4482                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
4483                                         EEPROM_TSSI_BOUND_A5_PLUS4);
4484
4485                 step = rt2x00_get_field16(eeprom,
4486                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
4487         }
4488
4489         /*
4490          * Check if temperature compensation is supported.
4491          */
4492         if (tssi_bounds[4] == 0xff || step == 0xff)
4493                 return 0;
4494
4495         /*
4496          * Read current TSSI (BBP 49).
4497          */
4498         current_tssi = rt2800_bbp_read(rt2x00dev, 49);
4499
4500         /*
4501          * Compare TSSI value (BBP49) with the compensation boundaries
4502          * from the EEPROM and increase or decrease tx power.
4503          */
4504         for (i = 0; i <= 3; i++) {
4505                 if (current_tssi > tssi_bounds[i])
4506                         break;
4507         }
4508
4509         if (i == 4) {
4510                 for (i = 8; i >= 5; i--) {
4511                         if (current_tssi < tssi_bounds[i])
4512                                 break;
4513                 }
4514         }
4515
4516         return (i - 4) * step;
4517 }
4518
4519 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
4520                                       enum nl80211_band band)
4521 {
4522         u16 eeprom;
4523         u8 comp_en;
4524         u8 comp_type;
4525         int comp_value = 0;
4526
4527         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA);
4528
4529         /*
4530          * HT40 compensation not required.
4531          */
4532         if (eeprom == 0xffff ||
4533             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4534                 return 0;
4535
4536         if (band == NL80211_BAND_2GHZ) {
4537                 comp_en = rt2x00_get_field16(eeprom,
4538                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
4539                 if (comp_en) {
4540                         comp_type = rt2x00_get_field16(eeprom,
4541                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
4542                         comp_value = rt2x00_get_field16(eeprom,
4543                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
4544                         if (!comp_type)
4545                                 comp_value = -comp_value;
4546                 }
4547         } else {
4548                 comp_en = rt2x00_get_field16(eeprom,
4549                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
4550                 if (comp_en) {
4551                         comp_type = rt2x00_get_field16(eeprom,
4552                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
4553                         comp_value = rt2x00_get_field16(eeprom,
4554                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
4555                         if (!comp_type)
4556                                 comp_value = -comp_value;
4557                 }
4558         }
4559
4560         return comp_value;
4561 }
4562
4563 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4564                                         int power_level, int max_power)
4565 {
4566         int delta;
4567
4568         if (rt2x00_has_cap_power_limit(rt2x00dev))
4569                 return 0;
4570
4571         /*
4572          * XXX: We don't know the maximum transmit power of our hardware since
4573          * the EEPROM doesn't expose it. We only know that we are calibrated
4574          * to 100% tx power.
4575          *
4576          * Hence, we assume the regulatory limit that cfg80211 calulated for
4577          * the current channel is our maximum and if we are requested to lower
4578          * the value we just reduce our tx power accordingly.
4579          */
4580         delta = power_level - max_power;
4581         return min(delta, 0);
4582 }
4583
4584 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
4585                                    enum nl80211_band band, int power_level,
4586                                    u8 txpower, int delta)
4587 {
4588         u16 eeprom;
4589         u8 criterion;
4590         u8 eirp_txpower;
4591         u8 eirp_txpower_criterion;
4592         u8 reg_limit;
4593
4594         if (rt2x00_rt(rt2x00dev, RT3593))
4595                 return min_t(u8, txpower, 0xc);
4596
4597         if (rt2x00_rt(rt2x00dev, RT3883))
4598                 return min_t(u8, txpower, 0xf);
4599
4600         if (rt2x00_has_cap_power_limit(rt2x00dev)) {
4601                 /*
4602                  * Check if eirp txpower exceed txpower_limit.
4603                  * We use OFDM 6M as criterion and its eirp txpower
4604                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
4605                  * .11b data rate need add additional 4dbm
4606                  * when calculating eirp txpower.
4607                  */
4608                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4609                                                        EEPROM_TXPOWER_BYRATE,
4610                                                        1);
4611                 criterion = rt2x00_get_field16(eeprom,
4612                                                EEPROM_TXPOWER_BYRATE_RATE0);
4613
4614                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
4615
4616                 if (band == NL80211_BAND_2GHZ)
4617                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4618                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
4619                 else
4620                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4621                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
4622
4623                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
4624                                (is_rate_b ? 4 : 0) + delta;
4625
4626                 reg_limit = (eirp_txpower > power_level) ?
4627                                         (eirp_txpower - power_level) : 0;
4628         } else
4629                 reg_limit = 0;
4630
4631         txpower = max(0, txpower + delta - reg_limit);
4632         return min_t(u8, txpower, 0xc);
4633 }
4634
4635
4636 enum {
4637         TX_PWR_CFG_0_IDX,
4638         TX_PWR_CFG_1_IDX,
4639         TX_PWR_CFG_2_IDX,
4640         TX_PWR_CFG_3_IDX,
4641         TX_PWR_CFG_4_IDX,
4642         TX_PWR_CFG_5_IDX,
4643         TX_PWR_CFG_6_IDX,
4644         TX_PWR_CFG_7_IDX,
4645         TX_PWR_CFG_8_IDX,
4646         TX_PWR_CFG_9_IDX,
4647         TX_PWR_CFG_0_EXT_IDX,
4648         TX_PWR_CFG_1_EXT_IDX,
4649         TX_PWR_CFG_2_EXT_IDX,
4650         TX_PWR_CFG_3_EXT_IDX,
4651         TX_PWR_CFG_4_EXT_IDX,
4652         TX_PWR_CFG_IDX_COUNT,
4653 };
4654
4655 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4656                                          struct ieee80211_channel *chan,
4657                                          int power_level)
4658 {
4659         u8 txpower;
4660         u16 eeprom;
4661         u32 regs[TX_PWR_CFG_IDX_COUNT];
4662         unsigned int offset;
4663         enum nl80211_band band = chan->band;
4664         int delta;
4665         int i;
4666
4667         memset(regs, '\0', sizeof(regs));
4668
4669         /* TODO: adapt TX power reduction from the rt28xx code */
4670
4671         /* calculate temperature compensation delta */
4672         delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4673
4674         if (band == NL80211_BAND_5GHZ)
4675                 offset = 16;
4676         else
4677                 offset = 0;
4678
4679         if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4680                 offset += 8;
4681
4682         /* read the next four txpower values */
4683         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4684                                                offset);
4685
4686         /* CCK 1MBS,2MBS */
4687         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4688         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4689                                             txpower, delta);
4690         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4691                            TX_PWR_CFG_0_CCK1_CH0, txpower);
4692         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4693                            TX_PWR_CFG_0_CCK1_CH1, txpower);
4694         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4695                            TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
4696
4697         /* CCK 5.5MBS,11MBS */
4698         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4699         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4700                                             txpower, delta);
4701         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4702                            TX_PWR_CFG_0_CCK5_CH0, txpower);
4703         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4704                            TX_PWR_CFG_0_CCK5_CH1, txpower);
4705         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4706                            TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
4707
4708         /* OFDM 6MBS,9MBS */
4709         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4710         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4711                                             txpower, delta);
4712         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4713                            TX_PWR_CFG_0_OFDM6_CH0, txpower);
4714         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4715                            TX_PWR_CFG_0_OFDM6_CH1, txpower);
4716         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4717                            TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
4718
4719         /* OFDM 12MBS,18MBS */
4720         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4721         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4722                                             txpower, delta);
4723         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4724                            TX_PWR_CFG_0_OFDM12_CH0, txpower);
4725         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4726                            TX_PWR_CFG_0_OFDM12_CH1, txpower);
4727         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4728                            TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
4729
4730         /* read the next four txpower values */
4731         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4732                                                offset + 1);
4733
4734         /* OFDM 24MBS,36MBS */
4735         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4736         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4737                                             txpower, delta);
4738         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4739                            TX_PWR_CFG_1_OFDM24_CH0, txpower);
4740         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4741                            TX_PWR_CFG_1_OFDM24_CH1, txpower);
4742         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4743                            TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
4744
4745         /* OFDM 48MBS */
4746         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4747         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4748                                             txpower, delta);
4749         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4750                            TX_PWR_CFG_1_OFDM48_CH0, txpower);
4751         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4752                            TX_PWR_CFG_1_OFDM48_CH1, txpower);
4753         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4754                            TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
4755
4756         /* OFDM 54MBS */
4757         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4758         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4759                                             txpower, delta);
4760         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4761                            TX_PWR_CFG_7_OFDM54_CH0, txpower);
4762         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4763                            TX_PWR_CFG_7_OFDM54_CH1, txpower);
4764         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4765                            TX_PWR_CFG_7_OFDM54_CH2, txpower);
4766
4767         /* read the next four txpower values */
4768         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4769                                                offset + 2);
4770
4771         /* MCS 0,1 */
4772         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4773         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4774                                             txpower, delta);
4775         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4776                            TX_PWR_CFG_1_MCS0_CH0, txpower);
4777         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4778                            TX_PWR_CFG_1_MCS0_CH1, txpower);
4779         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4780                            TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
4781
4782         /* MCS 2,3 */
4783         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4784         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4785                                             txpower, delta);
4786         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4787                            TX_PWR_CFG_1_MCS2_CH0, txpower);
4788         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4789                            TX_PWR_CFG_1_MCS2_CH1, txpower);
4790         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4791                            TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
4792
4793         /* MCS 4,5 */
4794         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4795         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4796                                             txpower, delta);
4797         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4798                            TX_PWR_CFG_2_MCS4_CH0, txpower);
4799         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4800                            TX_PWR_CFG_2_MCS4_CH1, txpower);
4801         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4802                            TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
4803
4804         /* MCS 6 */
4805         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4806         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4807                                             txpower, delta);
4808         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4809                            TX_PWR_CFG_2_MCS6_CH0, txpower);
4810         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4811                            TX_PWR_CFG_2_MCS6_CH1, txpower);
4812         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4813                            TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
4814
4815         /* read the next four txpower values */
4816         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4817                                                offset + 3);
4818
4819         /* MCS 7 */
4820         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4821         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4822                                             txpower, delta);
4823         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4824                            TX_PWR_CFG_7_MCS7_CH0, txpower);
4825         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4826                            TX_PWR_CFG_7_MCS7_CH1, txpower);
4827         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4828                            TX_PWR_CFG_7_MCS7_CH2, txpower);
4829
4830         /* MCS 8,9 */
4831         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4832         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4833                                             txpower, delta);
4834         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4835                            TX_PWR_CFG_2_MCS8_CH0, txpower);
4836         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4837                            TX_PWR_CFG_2_MCS8_CH1, txpower);
4838         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4839                            TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
4840
4841         /* MCS 10,11 */
4842         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4843         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4844                                             txpower, delta);
4845         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4846                            TX_PWR_CFG_2_MCS10_CH0, txpower);
4847         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4848                            TX_PWR_CFG_2_MCS10_CH1, txpower);
4849         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4850                            TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
4851
4852         /* MCS 12,13 */
4853         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4854         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4855                                             txpower, delta);
4856         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4857                            TX_PWR_CFG_3_MCS12_CH0, txpower);
4858         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4859                            TX_PWR_CFG_3_MCS12_CH1, txpower);
4860         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4861                            TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
4862
4863         /* read the next four txpower values */
4864         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4865                                                offset + 4);
4866
4867         /* MCS 14 */
4868         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4869         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4870                                             txpower, delta);
4871         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4872                            TX_PWR_CFG_3_MCS14_CH0, txpower);
4873         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4874                            TX_PWR_CFG_3_MCS14_CH1, txpower);
4875         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4876                            TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
4877
4878         /* MCS 15 */
4879         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4880         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4881                                             txpower, delta);
4882         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4883                            TX_PWR_CFG_8_MCS15_CH0, txpower);
4884         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4885                            TX_PWR_CFG_8_MCS15_CH1, txpower);
4886         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4887                            TX_PWR_CFG_8_MCS15_CH2, txpower);
4888
4889         /* MCS 16,17 */
4890         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4891         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4892                                             txpower, delta);
4893         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4894                            TX_PWR_CFG_5_MCS16_CH0, txpower);
4895         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4896                            TX_PWR_CFG_5_MCS16_CH1, txpower);
4897         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4898                            TX_PWR_CFG_5_MCS16_CH2, txpower);
4899
4900         /* MCS 18,19 */
4901         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4902         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4903                                             txpower, delta);
4904         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4905                            TX_PWR_CFG_5_MCS18_CH0, txpower);
4906         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4907                            TX_PWR_CFG_5_MCS18_CH1, txpower);
4908         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4909                            TX_PWR_CFG_5_MCS18_CH2, txpower);
4910
4911         /* read the next four txpower values */
4912         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4913                                                offset + 5);
4914
4915         /* MCS 20,21 */
4916         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4917         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4918                                             txpower, delta);
4919         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4920                            TX_PWR_CFG_6_MCS20_CH0, txpower);
4921         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4922                            TX_PWR_CFG_6_MCS20_CH1, txpower);
4923         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4924                            TX_PWR_CFG_6_MCS20_CH2, txpower);
4925
4926         /* MCS 22 */
4927         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4928         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4929                                             txpower, delta);
4930         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4931                            TX_PWR_CFG_6_MCS22_CH0, txpower);
4932         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4933                            TX_PWR_CFG_6_MCS22_CH1, txpower);
4934         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4935                            TX_PWR_CFG_6_MCS22_CH2, txpower);
4936
4937         /* MCS 23 */
4938         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4939         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4940                                             txpower, delta);
4941         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4942                            TX_PWR_CFG_8_MCS23_CH0, txpower);
4943         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4944                            TX_PWR_CFG_8_MCS23_CH1, txpower);
4945         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4946                            TX_PWR_CFG_8_MCS23_CH2, txpower);
4947
4948         /* read the next four txpower values */
4949         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4950                                                offset + 6);
4951
4952         /* STBC, MCS 0,1 */
4953         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4954         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4955                                             txpower, delta);
4956         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4957                            TX_PWR_CFG_3_STBC0_CH0, txpower);
4958         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4959                            TX_PWR_CFG_3_STBC0_CH1, txpower);
4960         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4961                            TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
4962
4963         /* STBC, MCS 2,3 */
4964         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4965         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4966                                             txpower, delta);
4967         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4968                            TX_PWR_CFG_3_STBC2_CH0, txpower);
4969         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4970                            TX_PWR_CFG_3_STBC2_CH1, txpower);
4971         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4972                            TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
4973
4974         /* STBC, MCS 4,5 */
4975         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4976         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4977                                             txpower, delta);
4978         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4979         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4980         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4981                            txpower);
4982
4983         /* STBC, MCS 6 */
4984         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4985         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4986                                             txpower, delta);
4987         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4988         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4989         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4990                            txpower);
4991
4992         /* read the next four txpower values */
4993         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4994                                                offset + 7);
4995
4996         /* STBC, MCS 7 */
4997         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4998         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4999                                             txpower, delta);
5000         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
5001                            TX_PWR_CFG_9_STBC7_CH0, txpower);
5002         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
5003                            TX_PWR_CFG_9_STBC7_CH1, txpower);
5004         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
5005                            TX_PWR_CFG_9_STBC7_CH2, txpower);
5006
5007         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
5008         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
5009         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
5010         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
5011         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
5012         rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
5013         rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
5014         rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
5015         rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
5016         rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
5017
5018         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
5019                               regs[TX_PWR_CFG_0_EXT_IDX]);
5020         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
5021                               regs[TX_PWR_CFG_1_EXT_IDX]);
5022         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
5023                               regs[TX_PWR_CFG_2_EXT_IDX]);
5024         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
5025                               regs[TX_PWR_CFG_3_EXT_IDX]);
5026         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
5027                               regs[TX_PWR_CFG_4_EXT_IDX]);
5028
5029         for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
5030                 rt2x00_dbg(rt2x00dev,
5031                            "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
5032                            (band == NL80211_BAND_5GHZ) ? '5' : '2',
5033                            (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
5034                                                                 '4' : '2',
5035                            (i > TX_PWR_CFG_9_IDX) ?
5036                                         (i - TX_PWR_CFG_9_IDX - 1) : i,
5037                            (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
5038                            (unsigned long) regs[i]);
5039 }
5040
5041 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
5042                                          struct ieee80211_channel *chan,
5043                                          int power_level)
5044 {
5045         u32 reg, pwreg;
5046         u16 eeprom;
5047         u32 data, gdata;
5048         u8 t, i;
5049         enum nl80211_band band = chan->band;
5050         int delta;
5051
5052         /* Warn user if bw_comp is set in EEPROM */
5053         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5054
5055         if (delta)
5056                 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
5057                             delta);
5058
5059         /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
5060          * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
5061          * driver does as well, though it looks kinda wrong.
5062          * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
5063          * the hardware has a problem handling 0x20, and as the code initially
5064          * used a fixed offset between HT20 and HT40 rates they had to work-
5065          * around that issue and most likely just forgot about it later on.
5066          * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
5067          * however, the corresponding EEPROM value is not respected by the
5068          * vendor driver, so maybe this is rather being taken care of the
5069          * TXALC and the driver doesn't need to handle it...?
5070          * Though this is all very awkward, just do as they did, as that's what
5071          * board vendors expected when they populated the EEPROM...
5072          */
5073         for (i = 0; i < 5; i++) {
5074                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5075                                                        EEPROM_TXPOWER_BYRATE,
5076                                                        i * 2);
5077
5078                 data = eeprom;
5079
5080                 t = eeprom & 0x3f;
5081                 if (t == 32)
5082                         t++;
5083
5084                 gdata = t;
5085
5086                 t = (eeprom & 0x3f00) >> 8;
5087                 if (t == 32)
5088                         t++;
5089
5090                 gdata |= (t << 8);
5091
5092                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5093                                                        EEPROM_TXPOWER_BYRATE,
5094                                                        (i * 2) + 1);
5095
5096                 t = eeprom & 0x3f;
5097                 if (t == 32)
5098                         t++;
5099
5100                 gdata |= (t << 16);
5101
5102                 t = (eeprom & 0x3f00) >> 8;
5103                 if (t == 32)
5104                         t++;
5105
5106                 gdata |= (t << 24);
5107                 data |= (eeprom << 16);
5108
5109                 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
5110                         /* HT20 */
5111                         if (data != 0xffffffff)
5112                                 rt2800_register_write(rt2x00dev,
5113                                                       TX_PWR_CFG_0 + (i * 4),
5114                                                       data);
5115                 } else {
5116                         /* HT40 */
5117                         if (gdata != 0xffffffff)
5118                                 rt2800_register_write(rt2x00dev,
5119                                                       TX_PWR_CFG_0 + (i * 4),
5120                                                       gdata);
5121                 }
5122         }
5123
5124         /* Aparently Ralink ran out of space in the BYRATE calibration section
5125          * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
5126          * registers. As recent 2T chips use 8-bit instead of 4-bit values for
5127          * power-offsets more space would be needed. Ralink decided to keep the
5128          * EEPROM layout untouched and rather have some shared values covering
5129          * multiple bitrates.
5130          * Populate the registers not covered by the EEPROM in the same way the
5131          * vendor driver does.
5132          */
5133
5134         /* For OFDM 54MBS use value from OFDM 48MBS */
5135         pwreg = 0;
5136         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1);
5137         t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
5138         rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
5139
5140         /* For MCS 7 use value from MCS 6 */
5141         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2);
5142         t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
5143         rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
5144         rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
5145
5146         /* For MCS 15 use value from MCS 14 */
5147         pwreg = 0;
5148         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3);
5149         t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
5150         rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
5151         rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
5152
5153         /* For STBC MCS 7 use value from STBC MCS 6 */
5154         pwreg = 0;
5155         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4);
5156         t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
5157         rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
5158         rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
5159
5160         rt2800_config_alc(rt2x00dev, chan, power_level);
5161
5162         /* TODO: temperature compensation code! */
5163 }
5164
5165 /*
5166  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
5167  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
5168  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
5169  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
5170  * Reference per rate transmit power values are located in the EEPROM at
5171  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
5172  * current conditions (i.e. band, bandwidth, temperature, user settings).
5173  */
5174 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
5175                                          struct ieee80211_channel *chan,
5176                                          int power_level)
5177 {
5178         u8 txpower, r1;
5179         u16 eeprom;
5180         u32 reg, offset;
5181         int i, is_rate_b, delta, power_ctrl;
5182         enum nl80211_band band = chan->band;
5183
5184         /*
5185          * Calculate HT40 compensation. For 40MHz we need to add or subtract
5186          * value read from EEPROM (different for 2GHz and for 5GHz).
5187          */
5188         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5189
5190         /*
5191          * Calculate temperature compensation. Depends on measurement of current
5192          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
5193          * to temperature or maybe other factors) is smaller or bigger than
5194          * expected. We adjust it, based on TSSI reference and boundaries values
5195          * provided in EEPROM.
5196          */
5197         switch (rt2x00dev->chip.rt) {
5198         case RT2860:
5199         case RT2872:
5200         case RT2883:
5201         case RT3070:
5202         case RT3071:
5203         case RT3090:
5204         case RT3572:
5205                 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
5206                 break;
5207         default:
5208                 /* TODO: temperature compensation code for other chips. */
5209                 break;
5210         }
5211
5212         /*
5213          * Decrease power according to user settings, on devices with unknown
5214          * maximum tx power. For other devices we take user power_level into
5215          * consideration on rt2800_compensate_txpower().
5216          */
5217         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
5218                                               chan->max_power);
5219
5220         /*
5221          * BBP_R1 controls TX power for all rates, it allow to set the following
5222          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
5223          *
5224          * TODO: we do not use +6 dBm option to do not increase power beyond
5225          * regulatory limit, however this could be utilized for devices with
5226          * CAPABILITY_POWER_LIMIT.
5227          */
5228         if (delta <= -12) {
5229                 power_ctrl = 2;
5230                 delta += 12;
5231         } else if (delta <= -6) {
5232                 power_ctrl = 1;
5233                 delta += 6;
5234         } else {
5235                 power_ctrl = 0;
5236         }
5237         r1 = rt2800_bbp_read(rt2x00dev, 1);
5238         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
5239         rt2800_bbp_write(rt2x00dev, 1, r1);
5240
5241         offset = TX_PWR_CFG_0;
5242
5243         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
5244                 /* just to be safe */
5245                 if (offset > TX_PWR_CFG_4)
5246                         break;
5247
5248                 reg = rt2800_register_read(rt2x00dev, offset);
5249
5250                 /* read the next four txpower values */
5251                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5252                                                        EEPROM_TXPOWER_BYRATE,
5253                                                        i);
5254
5255                 is_rate_b = i ? 0 : 1;
5256                 /*
5257                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5258                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
5259                  * TX_PWR_CFG_4: unknown
5260                  */
5261                 txpower = rt2x00_get_field16(eeprom,
5262                                              EEPROM_TXPOWER_BYRATE_RATE0);
5263                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5264                                              power_level, txpower, delta);
5265                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5266
5267                 /*
5268                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5269                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
5270                  * TX_PWR_CFG_4: unknown
5271                  */
5272                 txpower = rt2x00_get_field16(eeprom,
5273                                              EEPROM_TXPOWER_BYRATE_RATE1);
5274                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5275                                              power_level, txpower, delta);
5276                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5277
5278                 /*
5279                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5280                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
5281                  * TX_PWR_CFG_4: unknown
5282                  */
5283                 txpower = rt2x00_get_field16(eeprom,
5284                                              EEPROM_TXPOWER_BYRATE_RATE2);
5285                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5286                                              power_level, txpower, delta);
5287                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5288
5289                 /*
5290                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5291                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
5292                  * TX_PWR_CFG_4: unknown
5293                  */
5294                 txpower = rt2x00_get_field16(eeprom,
5295                                              EEPROM_TXPOWER_BYRATE_RATE3);
5296                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5297                                              power_level, txpower, delta);
5298                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5299
5300                 /* read the next four txpower values */
5301                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5302                                                        EEPROM_TXPOWER_BYRATE,
5303                                                        i + 1);
5304
5305                 is_rate_b = 0;
5306                 /*
5307                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5308                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
5309                  * TX_PWR_CFG_4: unknown
5310                  */
5311                 txpower = rt2x00_get_field16(eeprom,
5312                                              EEPROM_TXPOWER_BYRATE_RATE0);
5313                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5314                                              power_level, txpower, delta);
5315                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5316
5317                 /*
5318                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5319                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
5320                  * TX_PWR_CFG_4: unknown
5321                  */
5322                 txpower = rt2x00_get_field16(eeprom,
5323                                              EEPROM_TXPOWER_BYRATE_RATE1);
5324                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5325                                              power_level, txpower, delta);
5326                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5327
5328                 /*
5329                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5330                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
5331                  * TX_PWR_CFG_4: unknown
5332                  */
5333                 txpower = rt2x00_get_field16(eeprom,
5334                                              EEPROM_TXPOWER_BYRATE_RATE2);
5335                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5336                                              power_level, txpower, delta);
5337                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5338
5339                 /*
5340                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5341                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
5342                  * TX_PWR_CFG_4: unknown
5343                  */
5344                 txpower = rt2x00_get_field16(eeprom,
5345                                              EEPROM_TXPOWER_BYRATE_RATE3);
5346                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5347                                              power_level, txpower, delta);
5348                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5349
5350                 rt2800_register_write(rt2x00dev, offset, reg);
5351
5352                 /* next TX_PWR_CFG register */
5353                 offset += 4;
5354         }
5355 }
5356
5357 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5358                                   struct ieee80211_channel *chan,
5359                                   int power_level)
5360 {
5361         if (rt2x00_rt(rt2x00dev, RT3593) ||
5362             rt2x00_rt(rt2x00dev, RT3883))
5363                 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
5364         else if (rt2x00_rt(rt2x00dev, RT6352))
5365                 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
5366         else
5367                 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
5368 }
5369
5370 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
5371 {
5372         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
5373                               rt2x00dev->tx_power);
5374 }
5375 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
5376
5377 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
5378 {
5379         u32     tx_pin;
5380         u8      rfcsr;
5381         unsigned long min_sleep = 0;
5382
5383         /*
5384          * A voltage-controlled oscillator(VCO) is an electronic oscillator
5385          * designed to be controlled in oscillation frequency by a voltage
5386          * input. Maybe the temperature will affect the frequency of
5387          * oscillation to be shifted. The VCO calibration will be called
5388          * periodically to adjust the frequency to be precision.
5389         */
5390
5391         tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5392         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
5393         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5394
5395         switch (rt2x00dev->chip.rf) {
5396         case RF2020:
5397         case RF3020:
5398         case RF3021:
5399         case RF3022:
5400         case RF3320:
5401         case RF3052:
5402                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
5403                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
5404                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
5405                 break;
5406         case RF3053:
5407         case RF3070:
5408         case RF3290:
5409         case RF3853:
5410         case RF5350:
5411         case RF5360:
5412         case RF5362:
5413         case RF5370:
5414         case RF5372:
5415         case RF5390:
5416         case RF5392:
5417         case RF5592:
5418                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
5419                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
5420                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
5421                 min_sleep = 1000;
5422                 break;
5423         case RF7620:
5424                 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
5425                 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
5426                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
5427                 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
5428                 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
5429                 min_sleep = 2000;
5430                 break;
5431         default:
5432                 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration",
5433                           rt2x00dev->chip.rf);
5434                 return;
5435         }
5436
5437         if (min_sleep > 0)
5438                 usleep_range(min_sleep, min_sleep * 2);
5439
5440         tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5441         if (rt2x00dev->rf_channel <= 14) {
5442                 switch (rt2x00dev->default_ant.tx_chain_num) {
5443                 case 3:
5444                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
5445                         /* fall through */
5446                 case 2:
5447                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
5448                         /* fall through */
5449                 case 1:
5450                 default:
5451                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
5452                         break;
5453                 }
5454         } else {
5455                 switch (rt2x00dev->default_ant.tx_chain_num) {
5456                 case 3:
5457                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
5458                         /* fall through */
5459                 case 2:
5460                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
5461                         /* fall through */
5462                 case 1:
5463                 default:
5464                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
5465                         break;
5466                 }
5467         }
5468         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5469
5470         if (rt2x00_rt(rt2x00dev, RT6352)) {
5471                 if (rt2x00dev->default_ant.rx_chain_num == 1) {
5472                         rt2800_bbp_write(rt2x00dev, 91, 0x07);
5473                         rt2800_bbp_write(rt2x00dev, 95, 0x1A);
5474                         rt2800_bbp_write(rt2x00dev, 195, 128);
5475                         rt2800_bbp_write(rt2x00dev, 196, 0xA0);
5476                         rt2800_bbp_write(rt2x00dev, 195, 170);
5477                         rt2800_bbp_write(rt2x00dev, 196, 0x12);
5478                         rt2800_bbp_write(rt2x00dev, 195, 171);
5479                         rt2800_bbp_write(rt2x00dev, 196, 0x10);
5480                 } else {
5481                         rt2800_bbp_write(rt2x00dev, 91, 0x06);
5482                         rt2800_bbp_write(rt2x00dev, 95, 0x9A);
5483                         rt2800_bbp_write(rt2x00dev, 195, 128);
5484                         rt2800_bbp_write(rt2x00dev, 196, 0xE0);
5485                         rt2800_bbp_write(rt2x00dev, 195, 170);
5486                         rt2800_bbp_write(rt2x00dev, 196, 0x30);
5487                         rt2800_bbp_write(rt2x00dev, 195, 171);
5488                         rt2800_bbp_write(rt2x00dev, 196, 0x30);
5489                 }
5490
5491                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
5492                         rt2800_bbp_write(rt2x00dev, 75, 0x68);
5493                         rt2800_bbp_write(rt2x00dev, 76, 0x4C);
5494                         rt2800_bbp_write(rt2x00dev, 79, 0x1C);
5495                         rt2800_bbp_write(rt2x00dev, 80, 0x0C);
5496                         rt2800_bbp_write(rt2x00dev, 82, 0xB6);
5497                 }
5498
5499                 /* On 11A, We should delay and wait RF/BBP to be stable
5500                  * and the appropriate time should be 1000 micro seconds
5501                  * 2005/06/05 - On 11G, we also need this delay time.
5502                  * Otherwise it's difficult to pass the WHQL.
5503                  */
5504                 usleep_range(1000, 1500);
5505         }
5506 }
5507 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
5508
5509 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5510                                       struct rt2x00lib_conf *libconf)
5511 {
5512         u32 reg;
5513
5514         reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5515         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
5516                            libconf->conf->short_frame_max_tx_count);
5517         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
5518                            libconf->conf->long_frame_max_tx_count);
5519         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5520 }
5521
5522 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
5523                              struct rt2x00lib_conf *libconf)
5524 {
5525         enum dev_state state =
5526             (libconf->conf->flags & IEEE80211_CONF_PS) ?
5527                 STATE_SLEEP : STATE_AWAKE;
5528         u32 reg;
5529
5530         if (state == STATE_SLEEP) {
5531                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
5532
5533                 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5534                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
5535                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
5536                                    libconf->conf->listen_interval - 1);
5537                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
5538                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5539
5540                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5541         } else {
5542                 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5543                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
5544                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
5545                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
5546                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5547
5548                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5549         }
5550 }
5551
5552 void rt2800_config(struct rt2x00_dev *rt2x00dev,
5553                    struct rt2x00lib_conf *libconf,
5554                    const unsigned int flags)
5555 {
5556         /* Always recalculate LNA gain before changing configuration */
5557         rt2800_config_lna_gain(rt2x00dev, libconf);
5558
5559         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
5560                 rt2800_config_channel(rt2x00dev, libconf->conf,
5561                                       &libconf->rf, &libconf->channel);
5562                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5563                                       libconf->conf->power_level);
5564         }
5565         if (flags & IEEE80211_CONF_CHANGE_POWER)
5566                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5567                                       libconf->conf->power_level);
5568         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
5569                 rt2800_config_retry_limit(rt2x00dev, libconf);
5570         if (flags & IEEE80211_CONF_CHANGE_PS)
5571                 rt2800_config_ps(rt2x00dev, libconf);
5572 }
5573 EXPORT_SYMBOL_GPL(rt2800_config);
5574
5575 /*
5576  * Link tuning
5577  */
5578 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5579 {
5580         u32 reg;
5581
5582         /*
5583          * Update FCS error count from register.
5584          */
5585         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5586         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5587 }
5588 EXPORT_SYMBOL_GPL(rt2800_link_stats);
5589
5590 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5591 {
5592         u8 vgc;
5593
5594         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
5595                 if (rt2x00_rt(rt2x00dev, RT3070) ||
5596                     rt2x00_rt(rt2x00dev, RT3071) ||
5597                     rt2x00_rt(rt2x00dev, RT3090) ||
5598                     rt2x00_rt(rt2x00dev, RT3290) ||
5599                     rt2x00_rt(rt2x00dev, RT3390) ||
5600                     rt2x00_rt(rt2x00dev, RT3572) ||
5601                     rt2x00_rt(rt2x00dev, RT3593) ||
5602                     rt2x00_rt(rt2x00dev, RT5390) ||
5603                     rt2x00_rt(rt2x00dev, RT5392) ||
5604                     rt2x00_rt(rt2x00dev, RT5592) ||
5605                     rt2x00_rt(rt2x00dev, RT6352))
5606                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5607                 else
5608                         vgc = 0x2e + rt2x00dev->lna_gain;
5609         } else { /* 5GHZ band */
5610                 if (rt2x00_rt(rt2x00dev, RT3593) ||
5611                     rt2x00_rt(rt2x00dev, RT3883))
5612                         vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
5613                 else if (rt2x00_rt(rt2x00dev, RT5592))
5614                         vgc = 0x24 + (2 * rt2x00dev->lna_gain);
5615                 else {
5616                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5617                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5618                         else
5619                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5620                 }
5621         }
5622
5623         return vgc;
5624 }
5625
5626 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5627                                   struct link_qual *qual, u8 vgc_level)
5628 {
5629         if (qual->vgc_level != vgc_level) {
5630                 if (rt2x00_rt(rt2x00dev, RT3572) ||
5631                     rt2x00_rt(rt2x00dev, RT3593) ||
5632                     rt2x00_rt(rt2x00dev, RT3883)) {
5633                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5634                                                        vgc_level);
5635                 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5636                         rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5637                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
5638                 } else {
5639                         rt2800_bbp_write(rt2x00dev, 66, vgc_level);
5640                 }
5641
5642                 qual->vgc_level = vgc_level;
5643                 qual->vgc_level_reg = vgc_level;
5644         }
5645 }
5646
5647 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5648 {
5649         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5650 }
5651 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
5652
5653 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5654                        const u32 count)
5655 {
5656         u8 vgc;
5657
5658         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
5659                 return;
5660
5661         /* When RSSI is better than a certain threshold, increase VGC
5662          * with a chip specific value in order to improve the balance
5663          * between sensibility and noise isolation.
5664          */
5665
5666         vgc = rt2800_get_default_vgc(rt2x00dev);
5667
5668         switch (rt2x00dev->chip.rt) {
5669         case RT3572:
5670         case RT3593:
5671                 if (qual->rssi > -65) {
5672                         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
5673                                 vgc += 0x20;
5674                         else
5675                                 vgc += 0x10;
5676                 }
5677                 break;
5678
5679         case RT3883:
5680                 if (qual->rssi > -65)
5681                         vgc += 0x10;
5682                 break;
5683
5684         case RT5592:
5685                 if (qual->rssi > -65)
5686                         vgc += 0x20;
5687                 break;
5688
5689         default:
5690                 if (qual->rssi > -80)
5691                         vgc += 0x10;
5692                 break;
5693         }
5694
5695         rt2800_set_vgc(rt2x00dev, qual, vgc);
5696 }
5697 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
5698
5699 /*
5700  * Initialization functions.
5701  */
5702 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
5703 {
5704         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5705         u32 reg;
5706         u16 eeprom;
5707         unsigned int i;
5708         int ret;
5709
5710         rt2800_disable_wpdma(rt2x00dev);
5711
5712         ret = rt2800_drv_init_registers(rt2x00dev);
5713         if (ret)
5714                 return ret;
5715
5716         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5717         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5718
5719         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5720
5721         reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
5722         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
5723         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
5724         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
5725         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
5726         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
5727         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
5728         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5729
5730         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5731
5732         reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
5733         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
5734         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
5735         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5736
5737         if (rt2x00_rt(rt2x00dev, RT3290)) {
5738                 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
5739                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
5740                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
5741                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5742                 }
5743
5744                 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
5745                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
5746                         rt2x00_set_field32(&reg, LDO0_EN, 1);
5747                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
5748                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5749                 }
5750
5751                 reg = rt2800_register_read(rt2x00dev, OSC_CTRL);
5752                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
5753                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
5754                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
5755                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5756
5757                 reg = rt2800_register_read(rt2x00dev, COEX_CFG0);
5758                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
5759                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5760
5761                 reg = rt2800_register_read(rt2x00dev, COEX_CFG2);
5762                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
5763                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
5764                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
5765                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
5766                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5767
5768                 reg = rt2800_register_read(rt2x00dev, PLL_CTRL);
5769                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
5770                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5771         }
5772
5773         if (rt2x00_rt(rt2x00dev, RT3071) ||
5774             rt2x00_rt(rt2x00dev, RT3090) ||
5775             rt2x00_rt(rt2x00dev, RT3290) ||
5776             rt2x00_rt(rt2x00dev, RT3390)) {
5777
5778                 if (rt2x00_rt(rt2x00dev, RT3290))
5779                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5780                                               0x00000404);
5781                 else
5782                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5783                                               0x00000400);
5784
5785                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5786                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5787                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5788                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5789                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5790                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5791                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5792                                                       0x0000002c);
5793                         else
5794                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5795                                                       0x0000000f);
5796                 } else {
5797                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5798                 }
5799         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
5800                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5801
5802                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5803                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5804                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5805                 } else {
5806                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5807                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5808                 }
5809         } else if (rt2800_is_305x_soc(rt2x00dev)) {
5810                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5811                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5812                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
5813         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
5814                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5815                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5816                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5817         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
5818                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5819                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5820         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
5821                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5822                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5823                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5824                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5825                         if (rt2x00_get_field16(eeprom,
5826                                                EEPROM_NIC_CONF1_DAC_TEST))
5827                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5828                                                       0x0000001f);
5829                         else
5830                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5831                                                       0x0000000f);
5832                 } else {
5833                         rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5834                                               0x00000000);
5835                 }
5836         } else if (rt2x00_rt(rt2x00dev, RT3883)) {
5837                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5838                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5839                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000);
5840                 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21);
5841                 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40);
5842         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
5843                    rt2x00_rt(rt2x00dev, RT5392) ||
5844                    rt2x00_rt(rt2x00dev, RT6352)) {
5845                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5846                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5847                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5848         } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5849                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5850                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5851                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5852         } else if (rt2x00_rt(rt2x00dev, RT5350)) {
5853                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5854         } else if (rt2x00_rt(rt2x00dev, RT6352)) {
5855                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
5856                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
5857                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5858                 rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002);
5859                 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F);
5860                 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
5861                 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
5862                 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
5863                 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
5864                 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
5865                 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
5866                                       0x3630363A);
5867                 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
5868                                       0x3630363A);
5869                 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
5870                 rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
5871                 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
5872         } else {
5873                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
5874                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5875         }
5876
5877         reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG);
5878         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
5879         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
5880         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
5881         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
5882         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
5883         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
5884         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
5885         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
5886         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
5887
5888         reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG);
5889         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
5890         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
5891         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
5892         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5893
5894         reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
5895         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
5896         if (rt2x00_is_usb(rt2x00dev)) {
5897                 drv_data->max_psdu = 3;
5898         } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
5899                    rt2x00_rt(rt2x00dev, RT2883) ||
5900                    rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
5901                 drv_data->max_psdu = 2;
5902         } else {
5903                 drv_data->max_psdu = 1;
5904         }
5905         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu);
5906         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 10);
5907         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 10);
5908         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
5909
5910         reg = rt2800_register_read(rt2x00dev, LED_CFG);
5911         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
5912         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
5913         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
5914         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
5915         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
5916         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
5917         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
5918         rt2800_register_write(rt2x00dev, LED_CFG, reg);
5919
5920         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
5921
5922         reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5923         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 2);
5924         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 2);
5925         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
5926         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
5927         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
5928         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
5929         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5930
5931         reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
5932         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
5933         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
5934         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 1);
5935         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
5936         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 0);
5937         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
5938         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
5939         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5940
5941         reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
5942         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
5943         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
5944         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
5945         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5946         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5947         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5948         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5949         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5950         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5951         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
5952         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5953
5954         reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
5955         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
5956         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
5957         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
5958         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5959         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5960         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5961         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5962         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5963         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5964         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
5965         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5966
5967         reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
5968         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
5969         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 1);
5970         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5971         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5972         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5973         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5974         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5975         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5976         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5977         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
5978         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5979
5980         reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
5981         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
5982         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 1);
5983         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
5984         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5985         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5986         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5987         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5988         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5989         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5990         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
5991         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5992
5993         reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
5994         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
5995         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 1);
5996         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5997         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5998         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5999         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6000         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
6001         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6002         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
6003         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
6004         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6005
6006         reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
6007         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
6008         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 1);
6009         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
6010         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
6011         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6012         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6013         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
6014         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6015         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
6016         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
6017         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6018
6019         if (rt2x00_is_usb(rt2x00dev)) {
6020                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
6021
6022                 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
6023                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
6024                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
6025                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
6026                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
6027                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
6028                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
6029                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
6030                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
6031                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
6032                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6033         }
6034
6035         /*
6036          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
6037          * although it is reserved.
6038          */
6039         reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG);
6040         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
6041         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
6042         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
6043         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
6044         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
6045         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
6046         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
6047         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
6048         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
6049         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
6050         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
6051
6052         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
6053         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
6054
6055         if (rt2x00_rt(rt2x00dev, RT3883)) {
6056                 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008);
6057                 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413);
6058         }
6059
6060         reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
6061         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
6062         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
6063                            IEEE80211_MAX_RTS_THRESHOLD);
6064         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 1);
6065         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6066
6067         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
6068
6069         /*
6070          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
6071          * time should be set to 16. However, the original Ralink driver uses
6072          * 16 for both and indeed using a value of 10 for CCK SIFS results in
6073          * connection problems with 11g + CTS protection. Hence, use the same
6074          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
6075          */
6076         reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
6077         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
6078         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
6079         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
6080         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
6081         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
6082         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
6083
6084         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
6085
6086         /*
6087          * ASIC will keep garbage value after boot, clear encryption keys.
6088          */
6089         for (i = 0; i < 4; i++)
6090                 rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0);
6091
6092         for (i = 0; i < 256; i++) {
6093                 rt2800_config_wcid(rt2x00dev, NULL, i);
6094                 rt2800_delete_wcid_attr(rt2x00dev, i);
6095         }
6096
6097         /*
6098          * Clear all beacons
6099          */
6100         for (i = 0; i < 8; i++)
6101                 rt2800_clear_beacon_register(rt2x00dev, i);
6102
6103         if (rt2x00_is_usb(rt2x00dev)) {
6104                 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6105                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
6106                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6107         } else if (rt2x00_is_pcie(rt2x00dev)) {
6108                 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6109                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
6110                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6111         }
6112
6113         reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
6114         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
6115         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
6116         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
6117         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
6118         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
6119         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
6120         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
6121         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
6122         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
6123
6124         reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1);
6125         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
6126         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
6127         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
6128         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
6129         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
6130         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
6131         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
6132         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
6133         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
6134
6135         reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0);
6136         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
6137         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
6138         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
6139         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
6140         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
6141         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
6142         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
6143         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
6144         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
6145
6146         reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1);
6147         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
6148         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
6149         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
6150         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
6151         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
6152
6153         /*
6154          * Do not force the BA window size, we use the TXWI to set it
6155          */
6156         reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE);
6157         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
6158         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
6159         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
6160
6161         /*
6162          * We must clear the error counters.
6163          * These registers are cleared on read,
6164          * so we may pass a useless variable to store the value.
6165          */
6166         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
6167         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1);
6168         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2);
6169         reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0);
6170         reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1);
6171         reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2);
6172
6173         /*
6174          * Setup leadtime for pre tbtt interrupt to 6ms
6175          */
6176         reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG);
6177         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
6178         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
6179
6180         /*
6181          * Set up channel statistics timer
6182          */
6183         reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG);
6184         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
6185         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
6186         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
6187         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
6188         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
6189         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
6190
6191         return 0;
6192 }
6193
6194 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
6195 {
6196         unsigned int i;
6197         u32 reg;
6198
6199         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
6200                 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
6201                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
6202                         return 0;
6203
6204                 udelay(REGISTER_BUSY_DELAY);
6205         }
6206
6207         rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
6208         return -EACCES;
6209 }
6210
6211 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
6212 {
6213         unsigned int i;
6214         u8 value;
6215
6216         /*
6217          * BBP was enabled after firmware was loaded,
6218          * but we need to reactivate it now.
6219          */
6220         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6221         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6222         msleep(1);
6223
6224         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
6225                 value = rt2800_bbp_read(rt2x00dev, 0);
6226                 if ((value != 0xff) && (value != 0x00))
6227                         return 0;
6228                 udelay(REGISTER_BUSY_DELAY);
6229         }
6230
6231         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
6232         return -EACCES;
6233 }
6234
6235 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
6236 {
6237         u8 value;
6238
6239         value = rt2800_bbp_read(rt2x00dev, 4);
6240         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
6241         rt2800_bbp_write(rt2x00dev, 4, value);
6242 }
6243
6244 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
6245 {
6246         rt2800_bbp_write(rt2x00dev, 142, 1);
6247         rt2800_bbp_write(rt2x00dev, 143, 57);
6248 }
6249
6250 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
6251 {
6252         static const u8 glrt_table[] = {
6253                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
6254                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
6255                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
6256                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
6257                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
6258                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
6259                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
6260                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
6261                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
6262         };
6263         int i;
6264
6265         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
6266                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
6267                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
6268         }
6269 };
6270
6271 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
6272 {
6273         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6274         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6275         rt2800_bbp_write(rt2x00dev, 68, 0x0B);
6276         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6277         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6278         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6279         rt2800_bbp_write(rt2x00dev, 81, 0x37);
6280         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6281         rt2800_bbp_write(rt2x00dev, 83, 0x6A);
6282         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6283         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6284         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6285         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6286         rt2800_bbp_write(rt2x00dev, 103, 0x00);
6287         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6288         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6289 }
6290
6291 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
6292 {
6293         u16 eeprom;
6294         u8 value;
6295
6296         value = rt2800_bbp_read(rt2x00dev, 138);
6297         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6298         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6299                 value |= 0x20;
6300         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6301                 value &= ~0x02;
6302         rt2800_bbp_write(rt2x00dev, 138, value);
6303 }
6304
6305 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
6306 {
6307         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6308
6309         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6310         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6311
6312         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6313         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6314
6315         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6316
6317         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6318         rt2800_bbp_write(rt2x00dev, 80, 0x08);
6319
6320         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6321
6322         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6323
6324         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6325
6326         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6327
6328         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6329
6330         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6331
6332         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6333
6334         rt2800_bbp_write(rt2x00dev, 105, 0x01);
6335
6336         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6337 }
6338
6339 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
6340 {
6341         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6342         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6343
6344         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
6345                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
6346                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
6347         } else {
6348                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6349                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6350         }
6351
6352         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6353
6354         rt2800_bbp_write(rt2x00dev, 81, 0x37);
6355
6356         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6357
6358         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6359
6360         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
6361                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6362         else
6363                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6364
6365         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6366
6367         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6368
6369         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6370
6371         rt2800_bbp_write(rt2x00dev, 103, 0x00);
6372
6373         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6374
6375         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6376 }
6377
6378 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
6379 {
6380         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6381         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6382
6383         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6384         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6385
6386         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6387
6388         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6389         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6390         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6391
6392         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6393
6394         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6395
6396         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6397
6398         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6399
6400         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6401
6402         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6403
6404         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
6405             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
6406             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
6407                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6408         else
6409                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6410
6411         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6412
6413         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6414
6415         if (rt2x00_rt(rt2x00dev, RT3071) ||
6416             rt2x00_rt(rt2x00dev, RT3090))
6417                 rt2800_disable_unused_dac_adc(rt2x00dev);
6418 }
6419
6420 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
6421 {
6422         u8 value;
6423
6424         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6425
6426         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6427
6428         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6429         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6430
6431         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6432
6433         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6434         rt2800_bbp_write(rt2x00dev, 73, 0x13);
6435         rt2800_bbp_write(rt2x00dev, 75, 0x46);
6436         rt2800_bbp_write(rt2x00dev, 76, 0x28);
6437
6438         rt2800_bbp_write(rt2x00dev, 77, 0x58);
6439
6440         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6441
6442         rt2800_bbp_write(rt2x00dev, 74, 0x0b);
6443         rt2800_bbp_write(rt2x00dev, 79, 0x18);
6444         rt2800_bbp_write(rt2x00dev, 80, 0x09);
6445         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6446
6447         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6448
6449         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6450
6451         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6452
6453         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6454
6455         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6456
6457         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6458
6459         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6460
6461         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6462
6463         rt2800_bbp_write(rt2x00dev, 105, 0x1c);
6464
6465         rt2800_bbp_write(rt2x00dev, 106, 0x03);
6466
6467         rt2800_bbp_write(rt2x00dev, 128, 0x12);
6468
6469         rt2800_bbp_write(rt2x00dev, 67, 0x24);
6470         rt2800_bbp_write(rt2x00dev, 143, 0x04);
6471         rt2800_bbp_write(rt2x00dev, 142, 0x99);
6472         rt2800_bbp_write(rt2x00dev, 150, 0x30);
6473         rt2800_bbp_write(rt2x00dev, 151, 0x2e);
6474         rt2800_bbp_write(rt2x00dev, 152, 0x20);
6475         rt2800_bbp_write(rt2x00dev, 153, 0x34);
6476         rt2800_bbp_write(rt2x00dev, 154, 0x40);
6477         rt2800_bbp_write(rt2x00dev, 155, 0x3b);
6478         rt2800_bbp_write(rt2x00dev, 253, 0x04);
6479
6480         value = rt2800_bbp_read(rt2x00dev, 47);
6481         rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
6482         rt2800_bbp_write(rt2x00dev, 47, value);
6483
6484         /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
6485         value = rt2800_bbp_read(rt2x00dev, 3);
6486         rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
6487         rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
6488         rt2800_bbp_write(rt2x00dev, 3, value);
6489 }
6490
6491 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
6492 {
6493         rt2800_bbp_write(rt2x00dev, 3, 0x00);
6494         rt2800_bbp_write(rt2x00dev, 4, 0x50);
6495
6496         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6497
6498         rt2800_bbp_write(rt2x00dev, 47, 0x48);
6499
6500         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6501         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6502
6503         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6504
6505         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6506         rt2800_bbp_write(rt2x00dev, 73, 0x13);
6507         rt2800_bbp_write(rt2x00dev, 75, 0x46);
6508         rt2800_bbp_write(rt2x00dev, 76, 0x28);
6509
6510         rt2800_bbp_write(rt2x00dev, 77, 0x59);
6511
6512         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6513
6514         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6515         rt2800_bbp_write(rt2x00dev, 80, 0x08);
6516         rt2800_bbp_write(rt2x00dev, 81, 0x37);
6517
6518         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6519
6520         if (rt2x00_rt(rt2x00dev, RT5350)) {
6521                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6522                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6523         } else {
6524                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6525                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6526         }
6527
6528         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6529
6530         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6531
6532         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6533
6534         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6535
6536         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6537
6538         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6539
6540         if (rt2x00_rt(rt2x00dev, RT5350)) {
6541                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6542                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6543         } else {
6544                 rt2800_bbp_write(rt2x00dev, 105, 0x34);
6545                 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6546         }
6547
6548         rt2800_bbp_write(rt2x00dev, 120, 0x50);
6549
6550         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6551
6552         rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6553         /* Set ITxBF timeout to 0x9c40=1000msec */
6554         rt2800_bbp_write(rt2x00dev, 179, 0x02);
6555         rt2800_bbp_write(rt2x00dev, 180, 0x00);
6556         rt2800_bbp_write(rt2x00dev, 182, 0x40);
6557         rt2800_bbp_write(rt2x00dev, 180, 0x01);
6558         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6559         rt2800_bbp_write(rt2x00dev, 179, 0x00);
6560         /* Reprogram the inband interface to put right values in RXWI */
6561         rt2800_bbp_write(rt2x00dev, 142, 0x04);
6562         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6563         rt2800_bbp_write(rt2x00dev, 142, 0x06);
6564         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6565         rt2800_bbp_write(rt2x00dev, 142, 0x07);
6566         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6567         rt2800_bbp_write(rt2x00dev, 142, 0x08);
6568         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6569
6570         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6571
6572         if (rt2x00_rt(rt2x00dev, RT5350)) {
6573                 /* Antenna Software OFDM */
6574                 rt2800_bbp_write(rt2x00dev, 150, 0x40);
6575                 /* Antenna Software CCK */
6576                 rt2800_bbp_write(rt2x00dev, 151, 0x30);
6577                 rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6578                 /* Clear previously selected antenna */
6579                 rt2800_bbp_write(rt2x00dev, 154, 0);
6580         }
6581 }
6582
6583 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6584 {
6585         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6586         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6587
6588         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6589         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6590
6591         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6592
6593         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6594         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6595         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6596
6597         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6598
6599         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6600
6601         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6602
6603         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6604
6605         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6606
6607         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6608
6609         if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6610                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6611         else
6612                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6613
6614         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6615
6616         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6617
6618         rt2800_disable_unused_dac_adc(rt2x00dev);
6619 }
6620
6621 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6622 {
6623         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6624
6625         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6626         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6627
6628         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6629         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6630
6631         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6632
6633         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6634         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6635         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6636
6637         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6638
6639         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6640
6641         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6642
6643         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6644
6645         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6646
6647         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6648
6649         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6650
6651         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6652
6653         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6654
6655         rt2800_disable_unused_dac_adc(rt2x00dev);
6656 }
6657
6658 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6659 {
6660         rt2800_init_bbp_early(rt2x00dev);
6661
6662         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6663         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6664         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6665         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6666
6667         rt2800_bbp_write(rt2x00dev, 84, 0x19);
6668
6669         /* Enable DC filter */
6670         if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6671                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6672 }
6673
6674 static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev)
6675 {
6676         rt2800_init_bbp_early(rt2x00dev);
6677
6678         rt2800_bbp_write(rt2x00dev, 4, 0x50);
6679         rt2800_bbp_write(rt2x00dev, 47, 0x48);
6680
6681         rt2800_bbp_write(rt2x00dev, 86, 0x46);
6682         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6683
6684         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6685
6686         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6687         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6688         rt2800_bbp_write(rt2x00dev, 105, 0x34);
6689         rt2800_bbp_write(rt2x00dev, 106, 0x12);
6690         rt2800_bbp_write(rt2x00dev, 120, 0x50);
6691         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6692         rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6693
6694         /* Set ITxBF timeout to 0x9C40=1000msec */
6695         rt2800_bbp_write(rt2x00dev, 179, 0x02);
6696         rt2800_bbp_write(rt2x00dev, 180, 0x00);
6697         rt2800_bbp_write(rt2x00dev, 182, 0x40);
6698         rt2800_bbp_write(rt2x00dev, 180, 0x01);
6699         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6700
6701         rt2800_bbp_write(rt2x00dev, 179, 0x00);
6702
6703         /* Reprogram the inband interface to put right values in RXWI */
6704         rt2800_bbp_write(rt2x00dev, 142, 0x04);
6705         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6706         rt2800_bbp_write(rt2x00dev, 142, 0x06);
6707         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6708         rt2800_bbp_write(rt2x00dev, 142, 0x07);
6709         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6710         rt2800_bbp_write(rt2x00dev, 142, 0x08);
6711         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6712         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6713 }
6714
6715 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6716 {
6717         int ant, div_mode;
6718         u16 eeprom;
6719         u8 value;
6720
6721         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6722
6723         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6724
6725         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6726         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6727
6728         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6729
6730         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6731         rt2800_bbp_write(rt2x00dev, 73, 0x13);
6732         rt2800_bbp_write(rt2x00dev, 75, 0x46);
6733         rt2800_bbp_write(rt2x00dev, 76, 0x28);
6734
6735         rt2800_bbp_write(rt2x00dev, 77, 0x59);
6736
6737         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6738
6739         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6740         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6741         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6742
6743         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6744
6745         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6746
6747         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6748
6749         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6750
6751         if (rt2x00_rt(rt2x00dev, RT5392))
6752                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6753
6754         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6755
6756         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6757
6758         if (rt2x00_rt(rt2x00dev, RT5392)) {
6759                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6760                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6761         }
6762
6763         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6764
6765         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6766
6767         rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6768
6769         if (rt2x00_rt(rt2x00dev, RT5390))
6770                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6771         else if (rt2x00_rt(rt2x00dev, RT5392))
6772                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6773         else
6774                 WARN_ON(1);
6775
6776         rt2800_bbp_write(rt2x00dev, 128, 0x12);
6777
6778         if (rt2x00_rt(rt2x00dev, RT5392)) {
6779                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6780                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6781         }
6782
6783         rt2800_disable_unused_dac_adc(rt2x00dev);
6784
6785         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6786         div_mode = rt2x00_get_field16(eeprom,
6787                                       EEPROM_NIC_CONF1_ANT_DIVERSITY);
6788         ant = (div_mode == 3) ? 1 : 0;
6789
6790         /* check if this is a Bluetooth combo card */
6791         if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
6792                 u32 reg;
6793
6794                 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
6795                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
6796                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
6797                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
6798                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
6799                 if (ant == 0)
6800                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
6801                 else if (ant == 1)
6802                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
6803                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6804         }
6805
6806         /* These chips have hardware RX antenna diversity */
6807         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
6808             rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
6809                 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6810                 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6811                 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6812         }
6813
6814         value = rt2800_bbp_read(rt2x00dev, 152);
6815         if (ant == 0)
6816                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6817         else
6818                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6819         rt2800_bbp_write(rt2x00dev, 152, value);
6820
6821         rt2800_init_freq_calibration(rt2x00dev);
6822 }
6823
6824 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6825 {
6826         int ant, div_mode;
6827         u16 eeprom;
6828         u8 value;
6829
6830         rt2800_init_bbp_early(rt2x00dev);
6831
6832         value = rt2800_bbp_read(rt2x00dev, 105);
6833         rt2x00_set_field8(&value, BBP105_MLD,
6834                           rt2x00dev->default_ant.rx_chain_num == 2);
6835         rt2800_bbp_write(rt2x00dev, 105, value);
6836
6837         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6838
6839         rt2800_bbp_write(rt2x00dev, 20, 0x06);
6840         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6841         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6842         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6843         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6844         rt2800_bbp_write(rt2x00dev, 70, 0x05);
6845         rt2800_bbp_write(rt2x00dev, 73, 0x13);
6846         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6847         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6848         rt2800_bbp_write(rt2x00dev, 76, 0x28);
6849         rt2800_bbp_write(rt2x00dev, 77, 0x59);
6850         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6851         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6852         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6853         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6854         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6855         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6856         rt2800_bbp_write(rt2x00dev, 98, 0x12);
6857         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6858         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6859         /* FIXME BBP105 owerwrite */
6860         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6861         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6862         rt2800_bbp_write(rt2x00dev, 128, 0x12);
6863         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
6864         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
6865         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
6866
6867         /* Initialize GLRT (Generalized Likehood Radio Test) */
6868         rt2800_init_bbp_5592_glrt(rt2x00dev);
6869
6870         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6871
6872         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6873         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
6874         ant = (div_mode == 3) ? 1 : 0;
6875         value = rt2800_bbp_read(rt2x00dev, 152);
6876         if (ant == 0) {
6877                 /* Main antenna */
6878                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6879         } else {
6880                 /* Auxiliary antenna */
6881                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6882         }
6883         rt2800_bbp_write(rt2x00dev, 152, value);
6884
6885         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
6886                 value = rt2800_bbp_read(rt2x00dev, 254);
6887                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
6888                 rt2800_bbp_write(rt2x00dev, 254, value);
6889         }
6890
6891         rt2800_init_freq_calibration(rt2x00dev);
6892
6893         rt2800_bbp_write(rt2x00dev, 84, 0x19);
6894         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6895                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6896 }
6897
6898 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
6899                                   const u8 reg, const u8 value)
6900 {
6901         rt2800_bbp_write(rt2x00dev, 195, reg);
6902         rt2800_bbp_write(rt2x00dev, 196, value);
6903 }
6904
6905 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
6906                                   const u8 reg, const u8 value)
6907 {
6908         rt2800_bbp_write(rt2x00dev, 158, reg);
6909         rt2800_bbp_write(rt2x00dev, 159, value);
6910 }
6911
6912 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)
6913 {
6914         rt2800_bbp_write(rt2x00dev, 158, reg);
6915         return rt2800_bbp_read(rt2x00dev, 159);
6916 }
6917
6918 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
6919 {
6920         u8 bbp;
6921
6922         /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
6923         bbp = rt2800_bbp_read(rt2x00dev, 105);
6924         rt2x00_set_field8(&bbp, BBP105_MLD,
6925                           rt2x00dev->default_ant.rx_chain_num == 2);
6926         rt2800_bbp_write(rt2x00dev, 105, bbp);
6927
6928         /* Avoid data loss and CRC errors */
6929         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6930
6931         /* Fix I/Q swap issue */
6932         bbp = rt2800_bbp_read(rt2x00dev, 1);
6933         bbp |= 0x04;
6934         rt2800_bbp_write(rt2x00dev, 1, bbp);
6935
6936         /* BBP for G band */
6937         rt2800_bbp_write(rt2x00dev, 3, 0x08);
6938         rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
6939         rt2800_bbp_write(rt2x00dev, 6, 0x08);
6940         rt2800_bbp_write(rt2x00dev, 14, 0x09);
6941         rt2800_bbp_write(rt2x00dev, 15, 0xFF);
6942         rt2800_bbp_write(rt2x00dev, 16, 0x01);
6943         rt2800_bbp_write(rt2x00dev, 20, 0x06);
6944         rt2800_bbp_write(rt2x00dev, 21, 0x00);
6945         rt2800_bbp_write(rt2x00dev, 22, 0x00);
6946         rt2800_bbp_write(rt2x00dev, 27, 0x00);
6947         rt2800_bbp_write(rt2x00dev, 28, 0x00);
6948         rt2800_bbp_write(rt2x00dev, 30, 0x00);
6949         rt2800_bbp_write(rt2x00dev, 31, 0x48);
6950         rt2800_bbp_write(rt2x00dev, 47, 0x40);
6951         rt2800_bbp_write(rt2x00dev, 62, 0x00);
6952         rt2800_bbp_write(rt2x00dev, 63, 0x00);
6953         rt2800_bbp_write(rt2x00dev, 64, 0x00);
6954         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6955         rt2800_bbp_write(rt2x00dev, 66, 0x1C);
6956         rt2800_bbp_write(rt2x00dev, 67, 0x20);
6957         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6958         rt2800_bbp_write(rt2x00dev, 69, 0x10);
6959         rt2800_bbp_write(rt2x00dev, 70, 0x05);
6960         rt2800_bbp_write(rt2x00dev, 73, 0x18);
6961         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6962         rt2800_bbp_write(rt2x00dev, 75, 0x60);
6963         rt2800_bbp_write(rt2x00dev, 76, 0x44);
6964         rt2800_bbp_write(rt2x00dev, 77, 0x59);
6965         rt2800_bbp_write(rt2x00dev, 78, 0x1E);
6966         rt2800_bbp_write(rt2x00dev, 79, 0x1C);
6967         rt2800_bbp_write(rt2x00dev, 80, 0x0C);
6968         rt2800_bbp_write(rt2x00dev, 81, 0x3A);
6969         rt2800_bbp_write(rt2x00dev, 82, 0xB6);
6970         rt2800_bbp_write(rt2x00dev, 83, 0x9A);
6971         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6972         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6973         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6974         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6975         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6976         rt2800_bbp_write(rt2x00dev, 95, 0x9A);
6977         rt2800_bbp_write(rt2x00dev, 96, 0x00);
6978         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6979         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6980         /* FIXME BBP105 owerwrite */
6981         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6982         rt2800_bbp_write(rt2x00dev, 106, 0x12);
6983         rt2800_bbp_write(rt2x00dev, 109, 0x00);
6984         rt2800_bbp_write(rt2x00dev, 134, 0x10);
6985         rt2800_bbp_write(rt2x00dev, 135, 0xA6);
6986         rt2800_bbp_write(rt2x00dev, 137, 0x04);
6987         rt2800_bbp_write(rt2x00dev, 142, 0x30);
6988         rt2800_bbp_write(rt2x00dev, 143, 0xF7);
6989         rt2800_bbp_write(rt2x00dev, 160, 0xEC);
6990         rt2800_bbp_write(rt2x00dev, 161, 0xC4);
6991         rt2800_bbp_write(rt2x00dev, 162, 0x77);
6992         rt2800_bbp_write(rt2x00dev, 163, 0xF9);
6993         rt2800_bbp_write(rt2x00dev, 164, 0x00);
6994         rt2800_bbp_write(rt2x00dev, 165, 0x00);
6995         rt2800_bbp_write(rt2x00dev, 186, 0x00);
6996         rt2800_bbp_write(rt2x00dev, 187, 0x00);
6997         rt2800_bbp_write(rt2x00dev, 188, 0x00);
6998         rt2800_bbp_write(rt2x00dev, 186, 0x00);
6999         rt2800_bbp_write(rt2x00dev, 187, 0x01);
7000         rt2800_bbp_write(rt2x00dev, 188, 0x00);
7001         rt2800_bbp_write(rt2x00dev, 189, 0x00);
7002
7003         rt2800_bbp_write(rt2x00dev, 91, 0x06);
7004         rt2800_bbp_write(rt2x00dev, 92, 0x04);
7005         rt2800_bbp_write(rt2x00dev, 93, 0x54);
7006         rt2800_bbp_write(rt2x00dev, 99, 0x50);
7007         rt2800_bbp_write(rt2x00dev, 148, 0x84);
7008         rt2800_bbp_write(rt2x00dev, 167, 0x80);
7009         rt2800_bbp_write(rt2x00dev, 178, 0xFF);
7010         rt2800_bbp_write(rt2x00dev, 106, 0x13);
7011
7012         /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
7013         rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
7014         rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
7015         rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
7016         rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
7017         rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
7018         rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
7019         rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
7020         rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
7021         rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
7022         rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
7023         rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
7024         rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
7025         rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
7026         rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
7027         rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
7028         rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
7029         rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
7030         rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
7031         rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
7032         rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
7033         rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
7034         rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
7035         rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
7036         rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
7037         rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
7038         rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
7039         rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
7040         rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
7041         rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
7042         rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
7043         rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
7044         rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
7045         rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
7046         rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
7047         rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
7048         rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
7049         rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
7050         rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
7051         rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
7052         rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
7053         rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
7054         rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
7055         rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
7056         rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
7057         rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
7058         rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
7059         rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
7060         rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
7061         rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
7062         rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
7063         rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
7064         rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
7065         rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
7066         rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
7067         rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
7068         rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
7069         rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
7070         rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
7071         rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
7072         rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
7073         rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
7074         rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
7075         rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
7076         rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
7077         rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
7078         rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
7079         rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
7080         rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
7081         rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
7082         rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
7083         rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
7084         rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
7085         rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
7086         rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
7087         rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
7088         rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
7089         rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
7090         rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
7091         rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
7092         rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
7093         rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
7094         rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
7095         rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
7096
7097         /* BBP for G band DCOC function */
7098         rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
7099         rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
7100         rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
7101         rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
7102         rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
7103         rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
7104         rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
7105         rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
7106         rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
7107         rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
7108         rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
7109         rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
7110         rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
7111         rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
7112         rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
7113         rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
7114         rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
7115         rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
7116         rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
7117         rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
7118
7119         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7120 }
7121
7122 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
7123 {
7124         unsigned int i;
7125         u16 eeprom;
7126         u8 reg_id;
7127         u8 value;
7128
7129         if (rt2800_is_305x_soc(rt2x00dev))
7130                 rt2800_init_bbp_305x_soc(rt2x00dev);
7131
7132         switch (rt2x00dev->chip.rt) {
7133         case RT2860:
7134         case RT2872:
7135         case RT2883:
7136                 rt2800_init_bbp_28xx(rt2x00dev);
7137                 break;
7138         case RT3070:
7139         case RT3071:
7140         case RT3090:
7141                 rt2800_init_bbp_30xx(rt2x00dev);
7142                 break;
7143         case RT3290:
7144                 rt2800_init_bbp_3290(rt2x00dev);
7145                 break;
7146         case RT3352:
7147         case RT5350:
7148                 rt2800_init_bbp_3352(rt2x00dev);
7149                 break;
7150         case RT3390:
7151                 rt2800_init_bbp_3390(rt2x00dev);
7152                 break;
7153         case RT3572:
7154                 rt2800_init_bbp_3572(rt2x00dev);
7155                 break;
7156         case RT3593:
7157                 rt2800_init_bbp_3593(rt2x00dev);
7158                 return;
7159         case RT3883:
7160                 rt2800_init_bbp_3883(rt2x00dev);
7161                 return;
7162         case RT5390:
7163         case RT5392:
7164                 rt2800_init_bbp_53xx(rt2x00dev);
7165                 break;
7166         case RT5592:
7167                 rt2800_init_bbp_5592(rt2x00dev);
7168                 return;
7169         case RT6352:
7170                 rt2800_init_bbp_6352(rt2x00dev);
7171                 break;
7172         }
7173
7174         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
7175                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
7176                                                        EEPROM_BBP_START, i);
7177
7178                 if (eeprom != 0xffff && eeprom != 0x0000) {
7179                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
7180                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
7181                         rt2800_bbp_write(rt2x00dev, reg_id, value);
7182                 }
7183         }
7184 }
7185
7186 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
7187 {
7188         u32 reg;
7189
7190         reg = rt2800_register_read(rt2x00dev, OPT_14_CSR);
7191         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
7192         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
7193 }
7194
7195 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
7196                                 u8 filter_target)
7197 {
7198         unsigned int i;
7199         u8 bbp;
7200         u8 rfcsr;
7201         u8 passband;
7202         u8 stopband;
7203         u8 overtuned = 0;
7204         u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
7205
7206         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7207
7208         bbp = rt2800_bbp_read(rt2x00dev, 4);
7209         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
7210         rt2800_bbp_write(rt2x00dev, 4, bbp);
7211
7212         rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
7213         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
7214         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
7215
7216         rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7217         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
7218         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7219
7220         /*
7221          * Set power & frequency of passband test tone
7222          */
7223         rt2800_bbp_write(rt2x00dev, 24, 0);
7224
7225         for (i = 0; i < 100; i++) {
7226                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
7227                 msleep(1);
7228
7229                 passband = rt2800_bbp_read(rt2x00dev, 55);
7230                 if (passband)
7231                         break;
7232         }
7233
7234         /*
7235          * Set power & frequency of stopband test tone
7236          */
7237         rt2800_bbp_write(rt2x00dev, 24, 0x06);
7238
7239         for (i = 0; i < 100; i++) {
7240                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
7241                 msleep(1);
7242
7243                 stopband = rt2800_bbp_read(rt2x00dev, 55);
7244
7245                 if ((passband - stopband) <= filter_target) {
7246                         rfcsr24++;
7247                         overtuned += ((passband - stopband) == filter_target);
7248                 } else
7249                         break;
7250
7251                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7252         }
7253
7254         rfcsr24 -= !!overtuned;
7255
7256         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7257         return rfcsr24;
7258 }
7259
7260 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
7261                                        const unsigned int rf_reg)
7262 {
7263         u8 rfcsr;
7264
7265         rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
7266         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
7267         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7268         msleep(1);
7269         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
7270         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7271 }
7272
7273 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
7274 {
7275         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7276         u8 filter_tgt_bw20;
7277         u8 filter_tgt_bw40;
7278         u8 rfcsr, bbp;
7279
7280         /*
7281          * TODO: sync filter_tgt values with vendor driver
7282          */
7283         if (rt2x00_rt(rt2x00dev, RT3070)) {
7284                 filter_tgt_bw20 = 0x16;
7285                 filter_tgt_bw40 = 0x19;
7286         } else {
7287                 filter_tgt_bw20 = 0x13;
7288                 filter_tgt_bw40 = 0x15;
7289         }
7290
7291         drv_data->calibration_bw20 =
7292                 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
7293         drv_data->calibration_bw40 =
7294                 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
7295
7296         /*
7297          * Save BBP 25 & 26 values for later use in channel switching (for 3052)
7298          */
7299         drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7300         drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7301
7302         /*
7303          * Set back to initial state
7304          */
7305         rt2800_bbp_write(rt2x00dev, 24, 0);
7306
7307         rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7308         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
7309         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7310
7311         /*
7312          * Set BBP back to BW20
7313          */
7314         bbp = rt2800_bbp_read(rt2x00dev, 4);
7315         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
7316         rt2800_bbp_write(rt2x00dev, 4, bbp);
7317 }
7318
7319 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
7320 {
7321         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7322         u8 min_gain, rfcsr, bbp;
7323         u16 eeprom;
7324
7325         rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
7326
7327         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
7328         if (rt2x00_rt(rt2x00dev, RT3070) ||
7329             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7330             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
7331             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7332                 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
7333                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
7334         }
7335
7336         min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
7337         if (drv_data->txmixer_gain_24g >= min_gain) {
7338                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
7339                                   drv_data->txmixer_gain_24g);
7340         }
7341
7342         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
7343
7344         if (rt2x00_rt(rt2x00dev, RT3090)) {
7345                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
7346                 bbp = rt2800_bbp_read(rt2x00dev, 138);
7347                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7348                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
7349                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
7350                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
7351                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
7352                 rt2800_bbp_write(rt2x00dev, 138, bbp);
7353         }
7354
7355         if (rt2x00_rt(rt2x00dev, RT3070)) {
7356                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
7357                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
7358                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
7359                 else
7360                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
7361                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
7362                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
7363                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
7364                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
7365         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
7366                    rt2x00_rt(rt2x00dev, RT3090) ||
7367                    rt2x00_rt(rt2x00dev, RT3390)) {
7368                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7369                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7370                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7371                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7372                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
7373                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
7374                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7375
7376                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
7377                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
7378                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
7379
7380                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
7381                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
7382                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
7383
7384                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
7385                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
7386                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
7387         }
7388 }
7389
7390 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
7391 {
7392         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7393         u8 rfcsr;
7394         u8 tx_gain;
7395
7396         rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
7397         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
7398         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7399
7400         rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
7401         tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
7402                                     RFCSR17_TXMIXER_GAIN);
7403         rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
7404         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
7405
7406         rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
7407         rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
7408         rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
7409
7410         rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
7411         rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
7412         rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
7413
7414         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7415         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7416         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
7417         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7418
7419         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
7420         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
7421         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
7422
7423         /* TODO: enable stream mode */
7424 }
7425
7426 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
7427 {
7428         u8 reg;
7429         u16 eeprom;
7430
7431         /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
7432         reg = rt2800_bbp_read(rt2x00dev, 138);
7433         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7434         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
7435                 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
7436         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
7437                 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
7438         rt2800_bbp_write(rt2x00dev, 138, reg);
7439
7440         reg = rt2800_rfcsr_read(rt2x00dev, 38);
7441         rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
7442         rt2800_rfcsr_write(rt2x00dev, 38, reg);
7443
7444         reg = rt2800_rfcsr_read(rt2x00dev, 39);
7445         rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
7446         rt2800_rfcsr_write(rt2x00dev, 39, reg);
7447
7448         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7449
7450         reg = rt2800_rfcsr_read(rt2x00dev, 30);
7451         rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
7452         rt2800_rfcsr_write(rt2x00dev, 30, reg);
7453 }
7454
7455 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
7456 {
7457         rt2800_rf_init_calibration(rt2x00dev, 30);
7458
7459         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
7460         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
7461         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
7462         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
7463         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7464         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7465         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7466         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
7467         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
7468         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7469         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
7470         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7471         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
7472         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
7473         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7474         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7475         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7476         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7477         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7478         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7479         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7480         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7481         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7482         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
7483         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7484         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
7485         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
7486         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
7487         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
7488         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
7489         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
7490         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
7491 }
7492
7493 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
7494 {
7495         u8 rfcsr;
7496         u16 eeprom;
7497         u32 reg;
7498
7499         /* XXX vendor driver do this only for 3070 */
7500         rt2800_rf_init_calibration(rt2x00dev, 30);
7501
7502         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7503         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7504         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7505         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
7506         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7507         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
7508         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7509         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
7510         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7511         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7512         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7513         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7514         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7515         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7516         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7517         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7518         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7519         rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
7520         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
7521
7522         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
7523                 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7524                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7525                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7526                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7527         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
7528                    rt2x00_rt(rt2x00dev, RT3090)) {
7529                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
7530
7531                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7532                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7533                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7534
7535                 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7536                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7537                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7538                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
7539                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
7540                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
7541                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7542                         else
7543                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7544                 }
7545                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7546
7547                 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7548                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7549                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7550         }
7551
7552         rt2800_rx_filter_calibration(rt2x00dev);
7553
7554         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
7555             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7556             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
7557                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7558
7559         rt2800_led_open_drain_enable(rt2x00dev);
7560         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7561 }
7562
7563 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
7564 {
7565         u8 rfcsr;
7566
7567         rt2800_rf_init_calibration(rt2x00dev, 2);
7568
7569         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7570         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7571         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7572         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7573         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7574         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
7575         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7576         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7577         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7578         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7579         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7580         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
7581         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7582         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
7583         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7584         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7585         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7586         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7587         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7588         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7589         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7590         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
7591         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7592         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7593         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7594         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7595         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7596         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7597         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7598         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7599         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7600         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7601         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7602         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7603         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7604         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7605         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7606         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7607         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7608         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7609         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7610         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7611         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7612         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7613         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7614         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
7615
7616         rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
7617         rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
7618         rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
7619
7620         rt2800_led_open_drain_enable(rt2x00dev);
7621         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7622 }
7623
7624 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7625 {
7626         int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0,
7627                                   &rt2x00dev->cap_flags);
7628         int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1,
7629                                   &rt2x00dev->cap_flags);
7630         u8 rfcsr;
7631
7632         rt2800_rf_init_calibration(rt2x00dev, 30);
7633
7634         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7635         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7636         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7637         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7638         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7639         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7640         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7641         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7642         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7643         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7644         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7645         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7646         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7647         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7648         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7649         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7650         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7651         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7652         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7653         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7654         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7655         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7656         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7657         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7658         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7659         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7660         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7661         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7662         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7663         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7664         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7665         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7666         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7667         rfcsr = 0x01;
7668         if (tx0_ext_pa)
7669                 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1);
7670         if (tx1_ext_pa)
7671                 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1);
7672         rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
7673         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7674         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7675         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7676         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7677         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7678         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
7679         rfcsr = 0x52;
7680         if (!tx0_ext_pa) {
7681                 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1);
7682                 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1);
7683         }
7684         rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7685         rfcsr = 0x52;
7686         if (!tx1_ext_pa) {
7687                 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1);
7688                 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1);
7689         }
7690         rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
7691         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7692         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7693         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7694         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7695         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7696         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7697         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
7698         rfcsr = 0x2d;
7699         if (tx0_ext_pa)
7700                 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1);
7701         if (tx1_ext_pa)
7702                 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1);
7703         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7704         rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7705         rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7706         rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7707         rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7708         rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7709         rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7710         rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7711         rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
7712         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7713         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7714         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7715         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7716         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7717
7718         rt2800_rx_filter_calibration(rt2x00dev);
7719         rt2800_led_open_drain_enable(rt2x00dev);
7720         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7721 }
7722
7723 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7724 {
7725         u32 reg;
7726
7727         rt2800_rf_init_calibration(rt2x00dev, 30);
7728
7729         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7730         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7731         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7732         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7733         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7734         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7735         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7736         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7737         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7738         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7739         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7740         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7741         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7742         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7743         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7744         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7745         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7746         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7747         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7748         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7749         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7750         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7751         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7752         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7753         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7754         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7755         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7756         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7757         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7758         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7759         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7760         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
7761
7762         reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7763         rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7764         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7765
7766         rt2800_rx_filter_calibration(rt2x00dev);
7767
7768         if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7769                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7770
7771         rt2800_led_open_drain_enable(rt2x00dev);
7772         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7773 }
7774
7775 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7776 {
7777         u8 rfcsr;
7778         u32 reg;
7779
7780         rt2800_rf_init_calibration(rt2x00dev, 30);
7781
7782         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7783         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7784         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7785         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7786         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7787         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7788         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7789         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7790         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7791         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7792         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7793         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7794         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7795         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7796         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7797         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7798         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7799         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7800         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7801         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7802         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7803         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7804         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7805         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7806         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7807         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7808         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7809         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7810         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7811         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7812         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
7813
7814         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7815         rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7816         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7817
7818         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7819         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7820         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7821         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7822         msleep(1);
7823         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7824         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7825         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7826         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7827
7828         rt2800_rx_filter_calibration(rt2x00dev);
7829         rt2800_led_open_drain_enable(rt2x00dev);
7830         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7831 }
7832
7833 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7834 {
7835         u8 bbp;
7836         bool txbf_enabled = false; /* FIXME */
7837
7838         bbp = rt2800_bbp_read(rt2x00dev, 105);
7839         if (rt2x00dev->default_ant.rx_chain_num == 1)
7840                 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
7841         else
7842                 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
7843         rt2800_bbp_write(rt2x00dev, 105, bbp);
7844
7845         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7846
7847         rt2800_bbp_write(rt2x00dev, 92, 0x02);
7848         rt2800_bbp_write(rt2x00dev, 82, 0x82);
7849         rt2800_bbp_write(rt2x00dev, 106, 0x05);
7850         rt2800_bbp_write(rt2x00dev, 104, 0x92);
7851         rt2800_bbp_write(rt2x00dev, 88, 0x90);
7852         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7853         rt2800_bbp_write(rt2x00dev, 47, 0x48);
7854         rt2800_bbp_write(rt2x00dev, 120, 0x50);
7855
7856         if (txbf_enabled)
7857                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7858         else
7859                 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7860
7861         /* SNR mapping */
7862         rt2800_bbp_write(rt2x00dev, 142, 6);
7863         rt2800_bbp_write(rt2x00dev, 143, 160);
7864         rt2800_bbp_write(rt2x00dev, 142, 7);
7865         rt2800_bbp_write(rt2x00dev, 143, 161);
7866         rt2800_bbp_write(rt2x00dev, 142, 8);
7867         rt2800_bbp_write(rt2x00dev, 143, 162);
7868
7869         /* ADC/DAC control */
7870         rt2800_bbp_write(rt2x00dev, 31, 0x08);
7871
7872         /* RX AGC energy lower bound in log2 */
7873         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
7874
7875         /* FIXME: BBP 105 owerwrite? */
7876         rt2800_bbp_write(rt2x00dev, 105, 0x04);
7877
7878 }
7879
7880 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
7881 {
7882         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7883         u32 reg;
7884         u8 rfcsr;
7885
7886         /* Disable GPIO #4 and #7 function for LAN PE control */
7887         reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7888         rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
7889         rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
7890         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7891
7892         /* Initialize default register values */
7893         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
7894         rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
7895         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7896         rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
7897         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7898         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7899         rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
7900         rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
7901         rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
7902         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
7903         rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
7904         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7905         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7906         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7907         rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
7908         rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
7909         rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
7910         rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
7911         rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
7912         rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
7913         rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
7914         rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
7915         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
7916         rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
7917         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
7918         rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
7919         rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
7920         rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
7921         rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
7922         rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
7923         rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
7924         rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
7925
7926         /* Initiate calibration */
7927         /* TODO: use rt2800_rf_init_calibration ? */
7928         rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
7929         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
7930         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
7931
7932         rt2800_freq_cal_mode1(rt2x00dev);
7933
7934         rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
7935         rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
7936         rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
7937
7938         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7939         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7940         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7941         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7942         usleep_range(1000, 1500);
7943         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7944         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7945         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7946
7947         /* Set initial values for RX filter calibration */
7948         drv_data->calibration_bw20 = 0x1f;
7949         drv_data->calibration_bw40 = 0x2f;
7950
7951         /* Save BBP 25 & 26 values for later use in channel switching */
7952         drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7953         drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7954
7955         rt2800_led_open_drain_enable(rt2x00dev);
7956         rt2800_normal_mode_setup_3593(rt2x00dev);
7957
7958         rt3593_post_bbp_init(rt2x00dev);
7959
7960         /* TODO: enable stream mode support */
7961 }
7962
7963 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
7964 {
7965         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7966         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7967         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7968         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7969         rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
7970         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7971         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7972         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7973         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7974         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7975         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7976         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7977         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7978         if (rt2800_clk_is_20mhz(rt2x00dev))
7979                 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
7980         else
7981                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7982         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7983         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7984         rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
7985         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7986         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7987         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7988         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7989         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7990         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7991         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7992         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7993         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7994         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7995         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7996         rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
7997         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7998         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7999         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8000         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8001         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8002         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8003         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8004         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8005         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8006         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8007         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8008         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8009         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8010         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8011         rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
8012         rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
8013         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8014         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8015         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8016         rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
8017         rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
8018         rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
8019         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8020         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8021         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8022         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8023         rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
8024         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8025         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8026         rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
8027         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8028         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8029         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8030         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8031 }
8032
8033 static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev)
8034 {
8035         u8 rfcsr;
8036
8037         /* TODO: get the actual ECO value from the SoC */
8038         const unsigned int eco = 5;
8039
8040         rt2800_rf_init_calibration(rt2x00dev, 2);
8041
8042         rt2800_rfcsr_write(rt2x00dev, 0, 0xe0);
8043         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8044         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
8045         rt2800_rfcsr_write(rt2x00dev, 3, 0x20);
8046         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
8047         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
8048         rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
8049         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8050         rt2800_rfcsr_write(rt2x00dev, 8, 0x5b);
8051         rt2800_rfcsr_write(rt2x00dev, 9, 0x08);
8052         rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
8053         rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
8054         rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
8055         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
8056         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8057         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8058         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8059
8060         /* RFCSR 17 will be initialized later based on the
8061          * frequency offset stored in the EEPROM
8062          */
8063
8064         rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
8065         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8066         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8067         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8068         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8069         rt2800_rfcsr_write(rt2x00dev, 23, 0xc0);
8070         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8071         rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8072         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8073         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8074         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8075         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
8076         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8077         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8078         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8079         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8080         rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
8081         rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8082         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8083         rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8084         rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
8085         rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
8086         rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8087         rt2800_rfcsr_write(rt2x00dev, 41, 0x00);
8088         rt2800_rfcsr_write(rt2x00dev, 42, 0x00);
8089         rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8090         rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
8091         rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
8092         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
8093         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8094         rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
8095         rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
8096         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
8097         rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
8098         rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
8099         rt2800_rfcsr_write(rt2x00dev, 53, 0x76);
8100         rt2800_rfcsr_write(rt2x00dev, 54, 0x76);
8101         rt2800_rfcsr_write(rt2x00dev, 55, 0x76);
8102         rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
8103         rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
8104         rt2800_rfcsr_write(rt2x00dev, 58, 0x00);
8105         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
8106         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
8107         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
8108         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8109         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8110
8111         /* TODO: rx filter calibration? */
8112
8113         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
8114
8115         rt2800_bbp_write(rt2x00dev, 163, 0x9d);
8116
8117         rt2800_bbp_write(rt2x00dev, 105, 0x05);
8118
8119         rt2800_bbp_write(rt2x00dev, 179, 0x02);
8120         rt2800_bbp_write(rt2x00dev, 180, 0x00);
8121         rt2800_bbp_write(rt2x00dev, 182, 0x40);
8122         rt2800_bbp_write(rt2x00dev, 180, 0x01);
8123         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
8124
8125         rt2800_bbp_write(rt2x00dev, 179, 0x00);
8126
8127         rt2800_bbp_write(rt2x00dev, 142, 0x04);
8128         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
8129         rt2800_bbp_write(rt2x00dev, 142, 0x06);
8130         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
8131         rt2800_bbp_write(rt2x00dev, 142, 0x07);
8132         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
8133         rt2800_bbp_write(rt2x00dev, 142, 0x08);
8134         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
8135         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
8136
8137         if (eco == 5) {
8138                 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
8139                 rt2800_rfcsr_write(rt2x00dev, 33, 0x32);
8140         }
8141
8142         rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8143         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0);
8144         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
8145         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8146         msleep(1);
8147         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
8148         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8149
8150         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
8151         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
8152         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
8153
8154         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
8155         rfcsr |= 0xc0;
8156         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
8157
8158         rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
8159         rfcsr |= 0x20;
8160         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
8161
8162         rfcsr = rt2800_rfcsr_read(rt2x00dev, 46);
8163         rfcsr |= 0x20;
8164         rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
8165
8166         rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
8167         rfcsr &= ~0xee;
8168         rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
8169 }
8170
8171 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
8172 {
8173         rt2800_rf_init_calibration(rt2x00dev, 2);
8174
8175         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
8176         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8177         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8178         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8179         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8180                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8181         else
8182                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
8183         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8184         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8185         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8186         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8187         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8188         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8189         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8190         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8191         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8192         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8193
8194         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8195         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8196         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8197         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8198         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8199         if (rt2x00_is_usb(rt2x00dev) &&
8200             rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8201                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8202         else
8203                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
8204         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8205         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8206         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8207         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8208
8209         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8210         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8211         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8212         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8213         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8214         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8215         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8216         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8217         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8218         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8219
8220         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8221         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8222         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
8223         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
8224         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8225         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8226         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8227                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8228         else
8229                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
8230         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8231         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8232         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8233
8234         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8235         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8236                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8237         else
8238                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
8239         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
8240         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
8241         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8242                 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
8243         else
8244                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
8245         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
8246         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
8247         rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
8248
8249         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8250         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
8251                 if (rt2x00_is_usb(rt2x00dev))
8252                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8253                 else
8254                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
8255         } else {
8256                 if (rt2x00_is_usb(rt2x00dev))
8257                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
8258                 else
8259                         rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
8260         }
8261         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8262         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8263
8264         rt2800_normal_mode_setup_5xxx(rt2x00dev);
8265
8266         rt2800_led_open_drain_enable(rt2x00dev);
8267 }
8268
8269 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
8270 {
8271         rt2800_rf_init_calibration(rt2x00dev, 2);
8272
8273         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
8274         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8275         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8276         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8277         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8278         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8279         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8280         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8281         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8282         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8283         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8284         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8285         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8286         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
8287         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8288         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
8289         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8290         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
8291         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
8292         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8293         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8294         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8295         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8296         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8297         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8298         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8299         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
8300         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8301         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8302         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8303         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8304         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8305         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
8306         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8307         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
8308         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8309         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8310         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8311         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8312         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8313         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8314         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
8315         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8316         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8317         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
8318         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
8319         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
8320         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
8321         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8322         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8323         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
8324         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8325         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8326         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
8327         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8328         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
8329         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
8330         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8331
8332         rt2800_normal_mode_setup_5xxx(rt2x00dev);
8333
8334         rt2800_led_open_drain_enable(rt2x00dev);
8335 }
8336
8337 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
8338 {
8339         rt2800_rf_init_calibration(rt2x00dev, 30);
8340
8341         rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
8342         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
8343         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8344         rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
8345         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8346         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8347         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8348         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8349         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8350         rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
8351         rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
8352         rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
8353         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8354         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8355         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8356         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8357         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8358         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8359         rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
8360         rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
8361         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8362
8363         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8364         msleep(1);
8365
8366         rt2800_freq_cal_mode1(rt2x00dev);
8367
8368         /* Enable DC filter */
8369         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
8370                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
8371
8372         rt2800_normal_mode_setup_5xxx(rt2x00dev);
8373
8374         if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
8375                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8376
8377         rt2800_led_open_drain_enable(rt2x00dev);
8378 }
8379
8380 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
8381                                        bool set_bw, bool is_ht40)
8382 {
8383         u8 bbp_val;
8384
8385         bbp_val = rt2800_bbp_read(rt2x00dev, 21);
8386         bbp_val |= 0x1;
8387         rt2800_bbp_write(rt2x00dev, 21, bbp_val);
8388         usleep_range(100, 200);
8389
8390         if (set_bw) {
8391                 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
8392                 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
8393                 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
8394                 usleep_range(100, 200);
8395         }
8396
8397         bbp_val = rt2800_bbp_read(rt2x00dev, 21);
8398         bbp_val &= (~0x1);
8399         rt2800_bbp_write(rt2x00dev, 21, bbp_val);
8400         usleep_range(100, 200);
8401 }
8402
8403 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
8404 {
8405         u8 rf_val;
8406
8407         if (btxcal)
8408                 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
8409         else
8410                 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
8411
8412         rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
8413
8414         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8415         rf_val |= 0x80;
8416         rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
8417
8418         if (btxcal) {
8419                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
8420                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
8421                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
8422                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8423                 rf_val &= (~0x3F);
8424                 rf_val |= 0x3F;
8425                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
8426                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8427                 rf_val &= (~0x3F);
8428                 rf_val |= 0x3F;
8429                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
8430                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
8431         } else {
8432                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
8433                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
8434                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
8435                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8436                 rf_val &= (~0x3F);
8437                 rf_val |= 0x34;
8438                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
8439                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8440                 rf_val &= (~0x3F);
8441                 rf_val |= 0x34;
8442                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
8443         }
8444
8445         return 0;
8446 }
8447
8448 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
8449 {
8450         unsigned int cnt;
8451         u8 bbp_val;
8452         char cal_val;
8453
8454         rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
8455
8456         cnt = 0;
8457         do {
8458                 usleep_range(500, 2000);
8459                 bbp_val = rt2800_bbp_read(rt2x00dev, 159);
8460                 if (bbp_val == 0x02 || cnt == 20)
8461                         break;
8462
8463                 cnt++;
8464         } while (cnt < 20);
8465
8466         bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39);
8467         cal_val = bbp_val & 0x7F;
8468         if (cal_val >= 0x40)
8469                 cal_val -= 128;
8470
8471         return cal_val;
8472 }
8473
8474 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
8475                                          bool btxcal)
8476 {
8477         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8478         u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
8479         u8 filter_target;
8480         u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
8481         u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
8482         int loop = 0, is_ht40, cnt;
8483         u8 bbp_val, rf_val;
8484         char cal_r32_init, cal_r32_val, cal_diff;
8485         u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
8486         u8 saverfb5r06, saverfb5r07;
8487         u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
8488         u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
8489         u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
8490         u8 saverfb5r58, saverfb5r59;
8491         u8 savebbp159r0, savebbp159r2, savebbpr23;
8492         u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
8493
8494         /* Save MAC registers */
8495         MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8496         MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8497
8498         /* save BBP registers */
8499         savebbpr23 = rt2800_bbp_read(rt2x00dev, 23);
8500
8501         savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0);
8502         savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8503
8504         /* Save RF registers */
8505         saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8506         saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8507         saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8508         saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8509         saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
8510         saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8511         saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8512         saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
8513         saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8514         saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
8515         saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
8516         saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
8517
8518         saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
8519         saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
8520         saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
8521         saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
8522         saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
8523         saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
8524         saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
8525         saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
8526         saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
8527         saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
8528
8529         saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8530         saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8531
8532         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8533         rf_val |= 0x3;
8534         rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
8535
8536         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8537         rf_val |= 0x1;
8538         rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
8539
8540         cnt = 0;
8541         do {
8542                 usleep_range(500, 2000);
8543                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8544                 if (((rf_val & 0x1) == 0x00) || (cnt == 40))
8545                         break;
8546                 cnt++;
8547         } while (cnt < 40);
8548
8549         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8550         rf_val &= (~0x3);
8551         rf_val |= 0x1;
8552         rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
8553
8554         /* I-3 */
8555         bbp_val = rt2800_bbp_read(rt2x00dev, 23);
8556         bbp_val &= (~0x1F);
8557         bbp_val |= 0x10;
8558         rt2800_bbp_write(rt2x00dev, 23, bbp_val);
8559
8560         do {
8561                 /* I-4,5,6,7,8,9 */
8562                 if (loop == 0) {
8563                         is_ht40 = false;
8564
8565                         if (btxcal)
8566                                 filter_target = tx_filter_target_20m;
8567                         else
8568                                 filter_target = rx_filter_target_20m;
8569                 } else {
8570                         is_ht40 = true;
8571
8572                         if (btxcal)
8573                                 filter_target = tx_filter_target_40m;
8574                         else
8575                                 filter_target = rx_filter_target_40m;
8576                 }
8577
8578                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
8579                 rf_val &= (~0x04);
8580                 if (loop == 1)
8581                         rf_val |= 0x4;
8582
8583                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
8584
8585                 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
8586
8587                 rt2800_rf_lp_config(rt2x00dev, btxcal);
8588                 if (btxcal) {
8589                         tx_agc_fc = 0;
8590                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8591                         rf_val &= (~0x7F);
8592                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
8593                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8594                         rf_val &= (~0x7F);
8595                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
8596                 } else {
8597                         rx_agc_fc = 0;
8598                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8599                         rf_val &= (~0x7F);
8600                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
8601                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8602                         rf_val &= (~0x7F);
8603                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
8604                 }
8605
8606                 usleep_range(1000, 2000);
8607
8608                 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8609                 bbp_val &= (~0x6);
8610                 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
8611
8612                 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
8613
8614                 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
8615
8616                 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8617                 bbp_val |= 0x6;
8618                 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
8619 do_cal:
8620                 if (btxcal) {
8621                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8622                         rf_val &= (~0x7F);
8623                         rf_val |= tx_agc_fc;
8624                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
8625                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8626                         rf_val &= (~0x7F);
8627                         rf_val |= tx_agc_fc;
8628                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
8629                 } else {
8630                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8631                         rf_val &= (~0x7F);
8632                         rf_val |= rx_agc_fc;
8633                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
8634                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8635                         rf_val &= (~0x7F);
8636                         rf_val |= rx_agc_fc;
8637                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
8638                 }
8639
8640                 usleep_range(500, 1000);
8641
8642                 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
8643
8644                 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
8645
8646                 cal_diff = cal_r32_init - cal_r32_val;
8647
8648                 if (btxcal)
8649                         cmm_agc_fc = tx_agc_fc;
8650                 else
8651                         cmm_agc_fc = rx_agc_fc;
8652
8653                 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
8654                     ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
8655                         if (btxcal)
8656                                 tx_agc_fc = 0;
8657                         else
8658                                 rx_agc_fc = 0;
8659                 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
8660                         if (btxcal)
8661                                 tx_agc_fc++;
8662                         else
8663                                 rx_agc_fc++;
8664                         goto do_cal;
8665                 }
8666
8667                 if (btxcal) {
8668                         if (loop == 0)
8669                                 drv_data->tx_calibration_bw20 = tx_agc_fc;
8670                         else
8671                                 drv_data->tx_calibration_bw40 = tx_agc_fc;
8672                 } else {
8673                         if (loop == 0)
8674                                 drv_data->rx_calibration_bw20 = rx_agc_fc;
8675                         else
8676                                 drv_data->rx_calibration_bw40 = rx_agc_fc;
8677                 }
8678
8679                 loop++;
8680         } while (loop <= 1);
8681
8682         rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
8683         rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
8684         rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
8685         rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
8686         rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
8687         rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
8688         rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
8689         rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
8690         rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
8691         rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
8692         rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
8693         rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
8694
8695         rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
8696         rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
8697         rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
8698         rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
8699         rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
8700         rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
8701         rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
8702         rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
8703         rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
8704         rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
8705
8706         rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
8707         rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
8708
8709         rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
8710
8711         rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
8712         rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
8713
8714         bbp_val = rt2800_bbp_read(rt2x00dev, 4);
8715         rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
8716                           2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
8717         rt2800_bbp_write(rt2x00dev, 4, bbp_val);
8718
8719         rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
8720         rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
8721 }
8722
8723 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
8724 {
8725         /* Initialize RF central register to default value */
8726         rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
8727         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8728         rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
8729         rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
8730         rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
8731         rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
8732         rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
8733         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8734         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
8735         rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
8736         rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
8737         rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
8738         rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
8739         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8740         rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
8741         rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
8742         rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
8743         rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
8744         rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
8745         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8746         rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
8747         rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
8748         rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
8749         rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
8750         rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
8751         rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
8752         rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
8753         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8754         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8755         rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
8756         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
8757         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
8758         rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
8759         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8760         rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
8761         rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8762         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8763         rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8764         rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
8765         rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
8766         rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8767         rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
8768         rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
8769         rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8770
8771         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
8772         if (rt2800_clk_is_20mhz(rt2x00dev))
8773                 rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
8774         else
8775                 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8776         rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
8777         rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
8778         rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
8779         rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
8780         rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
8781         rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
8782         rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
8783         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
8784         rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
8785         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8786         rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8787         rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
8788         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8789         rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
8790         rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
8791         rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
8792
8793         rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
8794         rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
8795         rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
8796
8797         /* Initialize RF channel register to default value */
8798         rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
8799         rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
8800         rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
8801         rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
8802         rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
8803         rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
8804         rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
8805         rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
8806         rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
8807         rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
8808         rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
8809         rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8810         rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
8811         rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
8812         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8813         rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
8814         rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
8815         rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
8816         rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
8817         rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8818         rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
8819         rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
8820         rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
8821         rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
8822         rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
8823         rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
8824         rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
8825         rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
8826         rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
8827         rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
8828         rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
8829         rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
8830         rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
8831         rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
8832         rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
8833         rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
8834         rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
8835         rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
8836         rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
8837         rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
8838         rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
8839         rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
8840         rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
8841         rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
8842         rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
8843         rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8844         rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
8845         rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
8846         rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
8847         rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
8848         rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
8849         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
8850         rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
8851         rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
8852         rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
8853         rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
8854         rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
8855         rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
8856         rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
8857         rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
8858
8859         rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
8860
8861         rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
8862         rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
8863         rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
8864         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
8865         rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
8866         rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
8867         rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
8868         rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
8869         rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
8870         rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
8871         rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
8872         rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
8873         rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
8874         rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
8875         rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8876         rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
8877         rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8878         rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
8879         rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
8880         rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
8881         rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
8882         rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
8883         rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
8884         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8885         rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
8886         rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
8887         rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
8888         rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8889         rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
8890         rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
8891
8892         rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
8893         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8894         rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8895         rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
8896         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
8897         rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
8898         rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
8899         rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8900         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
8901
8902         rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
8903         rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
8904         rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
8905         rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
8906         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8907         rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8908
8909         /* Initialize RF channel register for DRQFN */
8910         rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8911         rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
8912         rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
8913         rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
8914         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
8915         rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
8916         rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
8917         rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
8918
8919         /* Initialize RF DC calibration register to default value */
8920         rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
8921         rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
8922         rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
8923         rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
8924         rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
8925         rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8926         rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
8927         rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
8928         rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
8929         rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
8930         rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
8931         rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
8932         rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
8933         rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
8934         rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
8935         rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
8936         rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
8937         rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
8938         rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
8939         rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
8940         rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8941         rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
8942         rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
8943         rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
8944         rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
8945         rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
8946         rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
8947         rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
8948         rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
8949         rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
8950         rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
8951         rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
8952         rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
8953         rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
8954         rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
8955         rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
8956         rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
8957         rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
8958         rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
8959         rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
8960         rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
8961         rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
8962         rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
8963         rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
8964         rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
8965         rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
8966         rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
8967         rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
8968         rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
8969         rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
8970         rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
8971         rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
8972         rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
8973         rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
8974         rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
8975         rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
8976         rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
8977         rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
8978         rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
8979
8980         rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
8981         rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
8982         rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
8983
8984         rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8985         rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
8986
8987         rt2800_bw_filter_calibration(rt2x00dev, true);
8988         rt2800_bw_filter_calibration(rt2x00dev, false);
8989 }
8990
8991 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
8992 {
8993         if (rt2800_is_305x_soc(rt2x00dev)) {
8994                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
8995                 return;
8996         }
8997
8998         switch (rt2x00dev->chip.rt) {
8999         case RT3070:
9000         case RT3071:
9001         case RT3090:
9002                 rt2800_init_rfcsr_30xx(rt2x00dev);
9003                 break;
9004         case RT3290:
9005                 rt2800_init_rfcsr_3290(rt2x00dev);
9006                 break;
9007         case RT3352:
9008                 rt2800_init_rfcsr_3352(rt2x00dev);
9009                 break;
9010         case RT3390:
9011                 rt2800_init_rfcsr_3390(rt2x00dev);
9012                 break;
9013         case RT3883:
9014                 rt2800_init_rfcsr_3883(rt2x00dev);
9015                 break;
9016         case RT3572:
9017                 rt2800_init_rfcsr_3572(rt2x00dev);
9018                 break;
9019         case RT3593:
9020                 rt2800_init_rfcsr_3593(rt2x00dev);
9021                 break;
9022         case RT5350:
9023                 rt2800_init_rfcsr_5350(rt2x00dev);
9024                 break;
9025         case RT5390:
9026                 rt2800_init_rfcsr_5390(rt2x00dev);
9027                 break;
9028         case RT5392:
9029                 rt2800_init_rfcsr_5392(rt2x00dev);
9030                 break;
9031         case RT5592:
9032                 rt2800_init_rfcsr_5592(rt2x00dev);
9033                 break;
9034         case RT6352:
9035                 rt2800_init_rfcsr_6352(rt2x00dev);
9036                 break;
9037         }
9038 }
9039
9040 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
9041 {
9042         u32 reg;
9043         u16 word;
9044
9045         /*
9046          * Initialize MAC registers.
9047          */
9048         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
9049                      rt2800_init_registers(rt2x00dev)))
9050                 return -EIO;
9051
9052         /*
9053          * Wait BBP/RF to wake up.
9054          */
9055         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
9056                 return -EIO;
9057
9058         /*
9059          * Send signal during boot time to initialize firmware.
9060          */
9061         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
9062         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
9063         if (rt2x00_is_usb(rt2x00dev))
9064                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
9065         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
9066         msleep(1);
9067
9068         /*
9069          * Make sure BBP is up and running.
9070          */
9071         if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
9072                 return -EIO;
9073
9074         /*
9075          * Initialize BBP/RF registers.
9076          */
9077         rt2800_init_bbp(rt2x00dev);
9078         rt2800_init_rfcsr(rt2x00dev);
9079
9080         if (rt2x00_is_usb(rt2x00dev) &&
9081             (rt2x00_rt(rt2x00dev, RT3070) ||
9082              rt2x00_rt(rt2x00dev, RT3071) ||
9083              rt2x00_rt(rt2x00dev, RT3572))) {
9084                 udelay(200);
9085                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
9086                 udelay(10);
9087         }
9088
9089         /*
9090          * Enable RX.
9091          */
9092         reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9093         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
9094         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9095         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9096
9097         udelay(50);
9098
9099         reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
9100         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
9101         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
9102         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9103         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
9104
9105         reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9106         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
9107         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9108         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9109
9110         /*
9111          * Initialize LED control
9112          */
9113         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF);
9114         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
9115                            word & 0xff, (word >> 8) & 0xff);
9116
9117         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF);
9118         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
9119                            word & 0xff, (word >> 8) & 0xff);
9120
9121         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY);
9122         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
9123                            word & 0xff, (word >> 8) & 0xff);
9124
9125         return 0;
9126 }
9127 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
9128
9129 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
9130 {
9131         u32 reg;
9132
9133         rt2800_disable_wpdma(rt2x00dev);
9134
9135         /* Wait for DMA, ignore error */
9136         rt2800_wait_wpdma_ready(rt2x00dev);
9137
9138         reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9139         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
9140         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9141         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9142 }
9143 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
9144
9145 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
9146 {
9147         u32 reg;
9148         u16 efuse_ctrl_reg;
9149
9150         if (rt2x00_rt(rt2x00dev, RT3290))
9151                 efuse_ctrl_reg = EFUSE_CTRL_3290;
9152         else
9153                 efuse_ctrl_reg = EFUSE_CTRL;
9154
9155         reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg);
9156         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
9157 }
9158 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
9159
9160 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
9161 {
9162         u32 reg;
9163         u16 efuse_ctrl_reg;
9164         u16 efuse_data0_reg;
9165         u16 efuse_data1_reg;
9166         u16 efuse_data2_reg;
9167         u16 efuse_data3_reg;
9168
9169         if (rt2x00_rt(rt2x00dev, RT3290)) {
9170                 efuse_ctrl_reg = EFUSE_CTRL_3290;
9171                 efuse_data0_reg = EFUSE_DATA0_3290;
9172                 efuse_data1_reg = EFUSE_DATA1_3290;
9173                 efuse_data2_reg = EFUSE_DATA2_3290;
9174                 efuse_data3_reg = EFUSE_DATA3_3290;
9175         } else {
9176                 efuse_ctrl_reg = EFUSE_CTRL;
9177                 efuse_data0_reg = EFUSE_DATA0;
9178                 efuse_data1_reg = EFUSE_DATA1;
9179                 efuse_data2_reg = EFUSE_DATA2;
9180                 efuse_data3_reg = EFUSE_DATA3;
9181         }
9182         mutex_lock(&rt2x00dev->csr_mutex);
9183
9184         reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg);
9185         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
9186         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
9187         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
9188         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
9189
9190         /* Wait until the EEPROM has been loaded */
9191         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
9192         /* Apparently the data is read from end to start */
9193         reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg);
9194         /* The returned value is in CPU order, but eeprom is le */
9195         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
9196         reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg);
9197         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
9198         reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg);
9199         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
9200         reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg);
9201         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
9202
9203         mutex_unlock(&rt2x00dev->csr_mutex);
9204 }
9205
9206 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
9207 {
9208         unsigned int i;
9209
9210         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
9211                 rt2800_efuse_read(rt2x00dev, i);
9212
9213         return 0;
9214 }
9215 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
9216
9217 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
9218 {
9219         u16 word;
9220
9221         if (rt2x00_rt(rt2x00dev, RT3593) ||
9222             rt2x00_rt(rt2x00dev, RT3883))
9223                 return 0;
9224
9225         word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
9226         if ((word & 0x00ff) != 0x00ff)
9227                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
9228
9229         return 0;
9230 }
9231
9232 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
9233 {
9234         u16 word;
9235
9236         if (rt2x00_rt(rt2x00dev, RT3593) ||
9237             rt2x00_rt(rt2x00dev, RT3883))
9238                 return 0;
9239
9240         word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
9241         if ((word & 0x00ff) != 0x00ff)
9242                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
9243
9244         return 0;
9245 }
9246
9247 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
9248 {
9249         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
9250         u16 word;
9251         u8 *mac;
9252         u8 default_lna_gain;
9253         int retval;
9254
9255         /*
9256          * Read the EEPROM.
9257          */
9258         retval = rt2800_read_eeprom(rt2x00dev);
9259         if (retval)
9260                 return retval;
9261
9262         /*
9263          * Start validation of the data that has been read.
9264          */
9265         mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
9266         rt2x00lib_set_mac_address(rt2x00dev, mac);
9267
9268         word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
9269         if (word == 0xffff) {
9270                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
9271                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
9272                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
9273                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
9274                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
9275         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
9276                    rt2x00_rt(rt2x00dev, RT2872)) {
9277                 /*
9278                  * There is a max of 2 RX streams for RT28x0 series
9279                  */
9280                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
9281                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
9282                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
9283         }
9284
9285         word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9286         if (word == 0xffff) {
9287                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
9288                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
9289                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
9290                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
9291                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
9292                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
9293                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
9294                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
9295                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
9296                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
9297                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
9298                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
9299                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
9300                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
9301                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
9302                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
9303                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
9304         }
9305
9306         word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
9307         if ((word & 0x00ff) == 0x00ff) {
9308                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
9309                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
9310                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
9311         }
9312         if ((word & 0xff00) == 0xff00) {
9313                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
9314                                    LED_MODE_TXRX_ACTIVITY);
9315                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
9316                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
9317                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
9318                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
9319                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
9320                 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
9321         }
9322
9323         /*
9324          * During the LNA validation we are going to use
9325          * lna0 as correct value. Note that EEPROM_LNA
9326          * is never validated.
9327          */
9328         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
9329         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
9330
9331         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
9332         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
9333                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
9334         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
9335                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
9336         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
9337
9338         drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
9339
9340         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
9341         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
9342                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
9343         if (!rt2x00_rt(rt2x00dev, RT3593) &&
9344             !rt2x00_rt(rt2x00dev, RT3883)) {
9345                 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
9346                     rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
9347                         rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
9348                                            default_lna_gain);
9349         }
9350         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
9351
9352         drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
9353
9354         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
9355         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
9356                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
9357         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
9358                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
9359         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
9360
9361         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
9362         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
9363                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
9364         if (!rt2x00_rt(rt2x00dev, RT3593) &&
9365             !rt2x00_rt(rt2x00dev, RT3883)) {
9366                 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
9367                     rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
9368                         rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
9369                                            default_lna_gain);
9370         }
9371         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
9372
9373         if (rt2x00_rt(rt2x00dev, RT3593) ||
9374             rt2x00_rt(rt2x00dev, RT3883)) {
9375                 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
9376                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
9377                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
9378                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
9379                                            default_lna_gain);
9380                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
9381                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
9382                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
9383                                            default_lna_gain);
9384                 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
9385         }
9386
9387         return 0;
9388 }
9389
9390 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
9391 {
9392         u16 value;
9393         u16 eeprom;
9394         u16 rf;
9395
9396         /*
9397          * Read EEPROM word for configuration.
9398          */
9399         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
9400
9401         /*
9402          * Identify RF chipset by EEPROM value
9403          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
9404          * RT53xx: defined in "EEPROM_CHIP_ID" field
9405          */
9406         if (rt2x00_rt(rt2x00dev, RT3290) ||
9407             rt2x00_rt(rt2x00dev, RT5390) ||
9408             rt2x00_rt(rt2x00dev, RT5392) ||
9409             rt2x00_rt(rt2x00dev, RT6352))
9410                 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
9411         else if (rt2x00_rt(rt2x00dev, RT3352))
9412                 rf = RF3322;
9413         else if (rt2x00_rt(rt2x00dev, RT3883))
9414                 rf = RF3853;
9415         else if (rt2x00_rt(rt2x00dev, RT5350))
9416                 rf = RF5350;
9417         else
9418                 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
9419
9420         switch (rf) {
9421         case RF2820:
9422         case RF2850:
9423         case RF2720:
9424         case RF2750:
9425         case RF3020:
9426         case RF2020:
9427         case RF3021:
9428         case RF3022:
9429         case RF3052:
9430         case RF3053:
9431         case RF3070:
9432         case RF3290:
9433         case RF3320:
9434         case RF3322:
9435         case RF3853:
9436         case RF5350:
9437         case RF5360:
9438         case RF5362:
9439         case RF5370:
9440         case RF5372:
9441         case RF5390:
9442         case RF5392:
9443         case RF5592:
9444         case RF7620:
9445                 break;
9446         default:
9447                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
9448                            rf);
9449                 return -ENODEV;
9450         }
9451
9452         rt2x00_set_rf(rt2x00dev, rf);
9453
9454         /*
9455          * Identify default antenna configuration.
9456          */
9457         rt2x00dev->default_ant.tx_chain_num =
9458             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
9459         rt2x00dev->default_ant.rx_chain_num =
9460             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
9461
9462         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9463
9464         if (rt2x00_rt(rt2x00dev, RT3070) ||
9465             rt2x00_rt(rt2x00dev, RT3090) ||
9466             rt2x00_rt(rt2x00dev, RT3352) ||
9467             rt2x00_rt(rt2x00dev, RT3390)) {
9468                 value = rt2x00_get_field16(eeprom,
9469                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
9470                 switch (value) {
9471                 case 0:
9472                 case 1:
9473                 case 2:
9474                         rt2x00dev->default_ant.tx = ANTENNA_A;
9475                         rt2x00dev->default_ant.rx = ANTENNA_A;
9476                         break;
9477                 case 3:
9478                         rt2x00dev->default_ant.tx = ANTENNA_A;
9479                         rt2x00dev->default_ant.rx = ANTENNA_B;
9480                         break;
9481                 }
9482         } else {
9483                 rt2x00dev->default_ant.tx = ANTENNA_A;
9484                 rt2x00dev->default_ant.rx = ANTENNA_A;
9485         }
9486
9487         /* These chips have hardware RX antenna diversity */
9488         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
9489             rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
9490                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
9491                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
9492         }
9493
9494         /*
9495          * Determine external LNA informations.
9496          */
9497         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
9498                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
9499         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
9500                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
9501
9502         /*
9503          * Detect if this device has an hardware controlled radio.
9504          */
9505         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
9506                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
9507
9508         /*
9509          * Detect if this device has Bluetooth co-existence.
9510          */
9511         if (!rt2x00_rt(rt2x00dev, RT3352) &&
9512             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
9513                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
9514
9515         /*
9516          * Read frequency offset and RF programming sequence.
9517          */
9518         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
9519         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
9520
9521         /*
9522          * Store led settings, for correct led behaviour.
9523          */
9524 #ifdef CONFIG_RT2X00_LIB_LEDS
9525         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
9526         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
9527         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
9528
9529         rt2x00dev->led_mcu_reg = eeprom;
9530 #endif /* CONFIG_RT2X00_LIB_LEDS */
9531
9532         /*
9533          * Check if support EIRP tx power limit feature.
9534          */
9535         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
9536
9537         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
9538                                         EIRP_MAX_TX_POWER_LIMIT)
9539                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
9540
9541         /*
9542          * Detect if device uses internal or external PA
9543          */
9544         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9545
9546         if (rt2x00_rt(rt2x00dev, RT3352)) {
9547                 if (rt2x00_get_field16(eeprom,
9548                     EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
9549                     __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
9550                               &rt2x00dev->cap_flags);
9551                 if (rt2x00_get_field16(eeprom,
9552                     EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352))
9553                     __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
9554                               &rt2x00dev->cap_flags);
9555         }
9556
9557         return 0;
9558 }
9559
9560 /*
9561  * RF value list for rt28xx
9562  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
9563  */
9564 static const struct rf_channel rf_vals[] = {
9565         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
9566         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
9567         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
9568         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
9569         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
9570         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
9571         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
9572         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
9573         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
9574         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
9575         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
9576         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
9577         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
9578         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
9579
9580         /* 802.11 UNI / HyperLan 2 */
9581         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
9582         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
9583         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
9584         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
9585         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
9586         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
9587         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
9588         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
9589         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
9590         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
9591         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
9592         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
9593
9594         /* 802.11 HyperLan 2 */
9595         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
9596         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
9597         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
9598         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
9599         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
9600         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
9601         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
9602         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
9603         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
9604         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
9605         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
9606         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
9607         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
9608         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
9609         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
9610         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
9611
9612         /* 802.11 UNII */
9613         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
9614         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
9615         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
9616         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
9617         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
9618         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
9619         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
9620         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
9621         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
9622         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
9623         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
9624
9625         /* 802.11 Japan */
9626         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
9627         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
9628         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
9629         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
9630         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
9631         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
9632         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
9633 };
9634
9635 /*
9636  * RF value list for rt3xxx
9637  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
9638  */
9639 static const struct rf_channel rf_vals_3x[] = {
9640         {1,  241, 2, 2 },
9641         {2,  241, 2, 7 },
9642         {3,  242, 2, 2 },
9643         {4,  242, 2, 7 },
9644         {5,  243, 2, 2 },
9645         {6,  243, 2, 7 },
9646         {7,  244, 2, 2 },
9647         {8,  244, 2, 7 },
9648         {9,  245, 2, 2 },
9649         {10, 245, 2, 7 },
9650         {11, 246, 2, 2 },
9651         {12, 246, 2, 7 },
9652         {13, 247, 2, 2 },
9653         {14, 248, 2, 4 },
9654
9655         /* 802.11 UNI / HyperLan 2 */
9656         {36, 0x56, 0, 4},
9657         {38, 0x56, 0, 6},
9658         {40, 0x56, 0, 8},
9659         {44, 0x57, 0, 0},
9660         {46, 0x57, 0, 2},
9661         {48, 0x57, 0, 4},
9662         {52, 0x57, 0, 8},
9663         {54, 0x57, 0, 10},
9664         {56, 0x58, 0, 0},
9665         {60, 0x58, 0, 4},
9666         {62, 0x58, 0, 6},
9667         {64, 0x58, 0, 8},
9668
9669         /* 802.11 HyperLan 2 */
9670         {100, 0x5b, 0, 8},
9671         {102, 0x5b, 0, 10},
9672         {104, 0x5c, 0, 0},
9673         {108, 0x5c, 0, 4},
9674         {110, 0x5c, 0, 6},
9675         {112, 0x5c, 0, 8},
9676         {116, 0x5d, 0, 0},
9677         {118, 0x5d, 0, 2},
9678         {120, 0x5d, 0, 4},
9679         {124, 0x5d, 0, 8},
9680         {126, 0x5d, 0, 10},
9681         {128, 0x5e, 0, 0},
9682         {132, 0x5e, 0, 4},
9683         {134, 0x5e, 0, 6},
9684         {136, 0x5e, 0, 8},
9685         {140, 0x5f, 0, 0},
9686
9687         /* 802.11 UNII */
9688         {149, 0x5f, 0, 9},
9689         {151, 0x5f, 0, 11},
9690         {153, 0x60, 0, 1},
9691         {157, 0x60, 0, 5},
9692         {159, 0x60, 0, 7},
9693         {161, 0x60, 0, 9},
9694         {165, 0x61, 0, 1},
9695         {167, 0x61, 0, 3},
9696         {169, 0x61, 0, 5},
9697         {171, 0x61, 0, 7},
9698         {173, 0x61, 0, 9},
9699 };
9700
9701 /*
9702  * RF value list for rt3xxx with Xtal20MHz
9703  * Supports: 2.4 GHz (all) (RF3322)
9704  */
9705 static const struct rf_channel rf_vals_3x_xtal20[] = {
9706         {1,    0xE2,     2,  0x14},
9707         {2,    0xE3,     2,  0x14},
9708         {3,    0xE4,     2,  0x14},
9709         {4,    0xE5,     2,  0x14},
9710         {5,    0xE6,     2,  0x14},
9711         {6,    0xE7,     2,  0x14},
9712         {7,    0xE8,     2,  0x14},
9713         {8,    0xE9,     2,  0x14},
9714         {9,    0xEA,     2,  0x14},
9715         {10,   0xEB,     2,  0x14},
9716         {11,   0xEC,     2,  0x14},
9717         {12,   0xED,     2,  0x14},
9718         {13,   0xEE,     2,  0x14},
9719         {14,   0xF0,     2,  0x18},
9720 };
9721
9722 static const struct rf_channel rf_vals_3853[] = {
9723         {1,  241, 6, 2},
9724         {2,  241, 6, 7},
9725         {3,  242, 6, 2},
9726         {4,  242, 6, 7},
9727         {5,  243, 6, 2},
9728         {6,  243, 6, 7},
9729         {7,  244, 6, 2},
9730         {8,  244, 6, 7},
9731         {9,  245, 6, 2},
9732         {10, 245, 6, 7},
9733         {11, 246, 6, 2},
9734         {12, 246, 6, 7},
9735         {13, 247, 6, 2},
9736         {14, 248, 6, 4},
9737
9738         {36, 0x56, 8, 4},
9739         {38, 0x56, 8, 6},
9740         {40, 0x56, 8, 8},
9741         {44, 0x57, 8, 0},
9742         {46, 0x57, 8, 2},
9743         {48, 0x57, 8, 4},
9744         {52, 0x57, 8, 8},
9745         {54, 0x57, 8, 10},
9746         {56, 0x58, 8, 0},
9747         {60, 0x58, 8, 4},
9748         {62, 0x58, 8, 6},
9749         {64, 0x58, 8, 8},
9750
9751         {100, 0x5b, 8, 8},
9752         {102, 0x5b, 8, 10},
9753         {104, 0x5c, 8, 0},
9754         {108, 0x5c, 8, 4},
9755         {110, 0x5c, 8, 6},
9756         {112, 0x5c, 8, 8},
9757         {114, 0x5c, 8, 10},
9758         {116, 0x5d, 8, 0},
9759         {118, 0x5d, 8, 2},
9760         {120, 0x5d, 8, 4},
9761         {124, 0x5d, 8, 8},
9762         {126, 0x5d, 8, 10},
9763         {128, 0x5e, 8, 0},
9764         {132, 0x5e, 8, 4},
9765         {134, 0x5e, 8, 6},
9766         {136, 0x5e, 8, 8},
9767         {140, 0x5f, 8, 0},
9768
9769         {149, 0x5f, 8, 9},
9770         {151, 0x5f, 8, 11},
9771         {153, 0x60, 8, 1},
9772         {157, 0x60, 8, 5},
9773         {159, 0x60, 8, 7},
9774         {161, 0x60, 8, 9},
9775         {165, 0x61, 8, 1},
9776         {167, 0x61, 8, 3},
9777         {169, 0x61, 8, 5},
9778         {171, 0x61, 8, 7},
9779         {173, 0x61, 8, 9},
9780 };
9781
9782 static const struct rf_channel rf_vals_5592_xtal20[] = {
9783         /* Channel, N, K, mod, R */
9784         {1, 482, 4, 10, 3},
9785         {2, 483, 4, 10, 3},
9786         {3, 484, 4, 10, 3},
9787         {4, 485, 4, 10, 3},
9788         {5, 486, 4, 10, 3},
9789         {6, 487, 4, 10, 3},
9790         {7, 488, 4, 10, 3},
9791         {8, 489, 4, 10, 3},
9792         {9, 490, 4, 10, 3},
9793         {10, 491, 4, 10, 3},
9794         {11, 492, 4, 10, 3},
9795         {12, 493, 4, 10, 3},
9796         {13, 494, 4, 10, 3},
9797         {14, 496, 8, 10, 3},
9798         {36, 172, 8, 12, 1},
9799         {38, 173, 0, 12, 1},
9800         {40, 173, 4, 12, 1},
9801         {42, 173, 8, 12, 1},
9802         {44, 174, 0, 12, 1},
9803         {46, 174, 4, 12, 1},
9804         {48, 174, 8, 12, 1},
9805         {50, 175, 0, 12, 1},
9806         {52, 175, 4, 12, 1},
9807         {54, 175, 8, 12, 1},
9808         {56, 176, 0, 12, 1},
9809         {58, 176, 4, 12, 1},
9810         {60, 176, 8, 12, 1},
9811         {62, 177, 0, 12, 1},
9812         {64, 177, 4, 12, 1},
9813         {100, 183, 4, 12, 1},
9814         {102, 183, 8, 12, 1},
9815         {104, 184, 0, 12, 1},
9816         {106, 184, 4, 12, 1},
9817         {108, 184, 8, 12, 1},
9818         {110, 185, 0, 12, 1},
9819         {112, 185, 4, 12, 1},
9820         {114, 185, 8, 12, 1},
9821         {116, 186, 0, 12, 1},
9822         {118, 186, 4, 12, 1},
9823         {120, 186, 8, 12, 1},
9824         {122, 187, 0, 12, 1},
9825         {124, 187, 4, 12, 1},
9826         {126, 187, 8, 12, 1},
9827         {128, 188, 0, 12, 1},
9828         {130, 188, 4, 12, 1},
9829         {132, 188, 8, 12, 1},
9830         {134, 189, 0, 12, 1},
9831         {136, 189, 4, 12, 1},
9832         {138, 189, 8, 12, 1},
9833         {140, 190, 0, 12, 1},
9834         {149, 191, 6, 12, 1},
9835         {151, 191, 10, 12, 1},
9836         {153, 192, 2, 12, 1},
9837         {155, 192, 6, 12, 1},
9838         {157, 192, 10, 12, 1},
9839         {159, 193, 2, 12, 1},
9840         {161, 193, 6, 12, 1},
9841         {165, 194, 2, 12, 1},
9842         {184, 164, 0, 12, 1},
9843         {188, 164, 4, 12, 1},
9844         {192, 165, 8, 12, 1},
9845         {196, 166, 0, 12, 1},
9846 };
9847
9848 static const struct rf_channel rf_vals_5592_xtal40[] = {
9849         /* Channel, N, K, mod, R */
9850         {1, 241, 2, 10, 3},
9851         {2, 241, 7, 10, 3},
9852         {3, 242, 2, 10, 3},
9853         {4, 242, 7, 10, 3},
9854         {5, 243, 2, 10, 3},
9855         {6, 243, 7, 10, 3},
9856         {7, 244, 2, 10, 3},
9857         {8, 244, 7, 10, 3},
9858         {9, 245, 2, 10, 3},
9859         {10, 245, 7, 10, 3},
9860         {11, 246, 2, 10, 3},
9861         {12, 246, 7, 10, 3},
9862         {13, 247, 2, 10, 3},
9863         {14, 248, 4, 10, 3},
9864         {36, 86, 4, 12, 1},
9865         {38, 86, 6, 12, 1},
9866         {40, 86, 8, 12, 1},
9867         {42, 86, 10, 12, 1},
9868         {44, 87, 0, 12, 1},
9869         {46, 87, 2, 12, 1},
9870         {48, 87, 4, 12, 1},
9871         {50, 87, 6, 12, 1},
9872         {52, 87, 8, 12, 1},
9873         {54, 87, 10, 12, 1},
9874         {56, 88, 0, 12, 1},
9875         {58, 88, 2, 12, 1},
9876         {60, 88, 4, 12, 1},
9877         {62, 88, 6, 12, 1},
9878         {64, 88, 8, 12, 1},
9879         {100, 91, 8, 12, 1},
9880         {102, 91, 10, 12, 1},
9881         {104, 92, 0, 12, 1},
9882         {106, 92, 2, 12, 1},
9883         {108, 92, 4, 12, 1},
9884         {110, 92, 6, 12, 1},
9885         {112, 92, 8, 12, 1},
9886         {114, 92, 10, 12, 1},
9887         {116, 93, 0, 12, 1},
9888         {118, 93, 2, 12, 1},
9889         {120, 93, 4, 12, 1},
9890         {122, 93, 6, 12, 1},
9891         {124, 93, 8, 12, 1},
9892         {126, 93, 10, 12, 1},
9893         {128, 94, 0, 12, 1},
9894         {130, 94, 2, 12, 1},
9895         {132, 94, 4, 12, 1},
9896         {134, 94, 6, 12, 1},
9897         {136, 94, 8, 12, 1},
9898         {138, 94, 10, 12, 1},
9899         {140, 95, 0, 12, 1},
9900         {149, 95, 9, 12, 1},
9901         {151, 95, 11, 12, 1},
9902         {153, 96, 1, 12, 1},
9903         {155, 96, 3, 12, 1},
9904         {157, 96, 5, 12, 1},
9905         {159, 96, 7, 12, 1},
9906         {161, 96, 9, 12, 1},
9907         {165, 97, 1, 12, 1},
9908         {184, 82, 0, 12, 1},
9909         {188, 82, 4, 12, 1},
9910         {192, 82, 8, 12, 1},
9911         {196, 83, 0, 12, 1},
9912 };
9913
9914 static const struct rf_channel rf_vals_7620[] = {
9915         {1, 0x50, 0x99, 0x99, 1},
9916         {2, 0x50, 0x44, 0x44, 2},
9917         {3, 0x50, 0xEE, 0xEE, 2},
9918         {4, 0x50, 0x99, 0x99, 3},
9919         {5, 0x51, 0x44, 0x44, 0},
9920         {6, 0x51, 0xEE, 0xEE, 0},
9921         {7, 0x51, 0x99, 0x99, 1},
9922         {8, 0x51, 0x44, 0x44, 2},
9923         {9, 0x51, 0xEE, 0xEE, 2},
9924         {10, 0x51, 0x99, 0x99, 3},
9925         {11, 0x52, 0x44, 0x44, 0},
9926         {12, 0x52, 0xEE, 0xEE, 0},
9927         {13, 0x52, 0x99, 0x99, 1},
9928         {14, 0x52, 0x33, 0x33, 3},
9929 };
9930
9931 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
9932 {
9933         struct hw_mode_spec *spec = &rt2x00dev->spec;
9934         struct channel_info *info;
9935         char *default_power1;
9936         char *default_power2;
9937         char *default_power3;
9938         unsigned int i, tx_chains, rx_chains;
9939         u32 reg;
9940
9941         /*
9942          * Disable powersaving as default.
9943          */
9944         rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
9945
9946         /*
9947          * Change default retry settings to values corresponding more closely
9948          * to rate[0].count setting of minstrel rate control algorithm.
9949          */
9950         rt2x00dev->hw->wiphy->retry_short = 2;
9951         rt2x00dev->hw->wiphy->retry_long = 2;
9952
9953         /*
9954          * Initialize all hw fields.
9955          */
9956         ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
9957         ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
9958         ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
9959         ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
9960         ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
9961
9962         /*
9963          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
9964          * unless we are capable of sending the buffered frames out after the
9965          * DTIM transmission using rt2x00lib_beacondone. This will send out
9966          * multicast and broadcast traffic immediately instead of buffering it
9967          * infinitly and thus dropping it after some time.
9968          */
9969         if (!rt2x00_is_usb(rt2x00dev))
9970                 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
9971
9972         /* Set MFP if HW crypto is disabled. */
9973         if (rt2800_hwcrypt_disabled(rt2x00dev))
9974                 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
9975
9976         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
9977         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
9978                                 rt2800_eeprom_addr(rt2x00dev,
9979                                                    EEPROM_MAC_ADDR_0));
9980
9981         /*
9982          * As rt2800 has a global fallback table we cannot specify
9983          * more then one tx rate per frame but since the hw will
9984          * try several rates (based on the fallback table) we should
9985          * initialize max_report_rates to the maximum number of rates
9986          * we are going to try. Otherwise mac80211 will truncate our
9987          * reported tx rates and the rc algortihm will end up with
9988          * incorrect data.
9989          */
9990         rt2x00dev->hw->max_rates = 1;
9991         rt2x00dev->hw->max_report_rates = 7;
9992         rt2x00dev->hw->max_rate_tries = 1;
9993
9994         /*
9995          * Initialize hw_mode information.
9996          */
9997         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
9998
9999         switch (rt2x00dev->chip.rf) {
10000         case RF2720:
10001         case RF2820:
10002                 spec->num_channels = 14;
10003                 spec->channels = rf_vals;
10004                 break;
10005
10006         case RF2750:
10007         case RF2850:
10008                 spec->num_channels = ARRAY_SIZE(rf_vals);
10009                 spec->channels = rf_vals;
10010                 break;
10011
10012         case RF2020:
10013         case RF3020:
10014         case RF3021:
10015         case RF3022:
10016         case RF3070:
10017         case RF3290:
10018         case RF3320:
10019         case RF3322:
10020         case RF5350:
10021         case RF5360:
10022         case RF5362:
10023         case RF5370:
10024         case RF5372:
10025         case RF5390:
10026         case RF5392:
10027                 spec->num_channels = 14;
10028                 if (rt2800_clk_is_20mhz(rt2x00dev))
10029                         spec->channels = rf_vals_3x_xtal20;
10030                 else
10031                         spec->channels = rf_vals_3x;
10032                 break;
10033
10034         case RF7620:
10035                 spec->num_channels = ARRAY_SIZE(rf_vals_7620);
10036                 spec->channels = rf_vals_7620;
10037                 break;
10038
10039         case RF3052:
10040         case RF3053:
10041                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
10042                 spec->channels = rf_vals_3x;
10043                 break;
10044
10045         case RF3853:
10046                 spec->num_channels = ARRAY_SIZE(rf_vals_3853);
10047                 spec->channels = rf_vals_3853;
10048                 break;
10049
10050         case RF5592:
10051                 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
10052                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
10053                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
10054                         spec->channels = rf_vals_5592_xtal40;
10055                 } else {
10056                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
10057                         spec->channels = rf_vals_5592_xtal20;
10058                 }
10059                 break;
10060         }
10061
10062         if (WARN_ON_ONCE(!spec->channels))
10063                 return -ENODEV;
10064
10065         spec->supported_bands = SUPPORT_BAND_2GHZ;
10066         if (spec->num_channels > 14)
10067                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
10068
10069         /*
10070          * Initialize HT information.
10071          */
10072         if (!rt2x00_rf(rt2x00dev, RF2020))
10073                 spec->ht.ht_supported = true;
10074         else
10075                 spec->ht.ht_supported = false;
10076
10077         spec->ht.cap =
10078             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
10079             IEEE80211_HT_CAP_GRN_FLD |
10080             IEEE80211_HT_CAP_SGI_20 |
10081             IEEE80211_HT_CAP_SGI_40;
10082
10083         tx_chains = rt2x00dev->default_ant.tx_chain_num;
10084         rx_chains = rt2x00dev->default_ant.rx_chain_num;
10085
10086         if (tx_chains >= 2)
10087                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
10088
10089         spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
10090
10091         spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
10092         spec->ht.ampdu_density = 4;
10093         spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
10094         if (tx_chains != rx_chains) {
10095                 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
10096                 spec->ht.mcs.tx_params |=
10097                     (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
10098         }
10099
10100         switch (rx_chains) {
10101         case 3:
10102                 spec->ht.mcs.rx_mask[2] = 0xff;
10103                 /* fall through */
10104         case 2:
10105                 spec->ht.mcs.rx_mask[1] = 0xff;
10106                 /* fall through */
10107         case 1:
10108                 spec->ht.mcs.rx_mask[0] = 0xff;
10109                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
10110                 break;
10111         }
10112
10113         /*
10114          * Create channel information array
10115          */
10116         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
10117         if (!info)
10118                 return -ENOMEM;
10119
10120         spec->channels_info = info;
10121
10122         default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
10123         default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
10124
10125         if (rt2x00dev->default_ant.tx_chain_num > 2)
10126                 default_power3 = rt2800_eeprom_addr(rt2x00dev,
10127                                                     EEPROM_EXT_TXPOWER_BG3);
10128         else
10129                 default_power3 = NULL;
10130
10131         for (i = 0; i < 14; i++) {
10132                 info[i].default_power1 = default_power1[i];
10133                 info[i].default_power2 = default_power2[i];
10134                 if (default_power3)
10135                         info[i].default_power3 = default_power3[i];
10136         }
10137
10138         if (spec->num_channels > 14) {
10139                 default_power1 = rt2800_eeprom_addr(rt2x00dev,
10140                                                     EEPROM_TXPOWER_A1);
10141                 default_power2 = rt2800_eeprom_addr(rt2x00dev,
10142                                                     EEPROM_TXPOWER_A2);
10143
10144                 if (rt2x00dev->default_ant.tx_chain_num > 2)
10145                         default_power3 =
10146                                 rt2800_eeprom_addr(rt2x00dev,
10147                                                    EEPROM_EXT_TXPOWER_A3);
10148                 else
10149                         default_power3 = NULL;
10150
10151                 for (i = 14; i < spec->num_channels; i++) {
10152                         info[i].default_power1 = default_power1[i - 14];
10153                         info[i].default_power2 = default_power2[i - 14];
10154                         if (default_power3)
10155                                 info[i].default_power3 = default_power3[i - 14];
10156                 }
10157         }
10158
10159         switch (rt2x00dev->chip.rf) {
10160         case RF2020:
10161         case RF3020:
10162         case RF3021:
10163         case RF3022:
10164         case RF3320:
10165         case RF3052:
10166         case RF3053:
10167         case RF3070:
10168         case RF3290:
10169         case RF3853:
10170         case RF5350:
10171         case RF5360:
10172         case RF5362:
10173         case RF5370:
10174         case RF5372:
10175         case RF5390:
10176         case RF5392:
10177         case RF5592:
10178         case RF7620:
10179                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
10180                 break;
10181         }
10182
10183         return 0;
10184 }
10185
10186 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
10187 {
10188         u32 reg;
10189         u32 rt;
10190         u32 rev;
10191
10192         if (rt2x00_rt(rt2x00dev, RT3290))
10193                 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290);
10194         else
10195                 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
10196
10197         rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
10198         rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
10199
10200         switch (rt) {
10201         case RT2860:
10202         case RT2872:
10203         case RT2883:
10204         case RT3070:
10205         case RT3071:
10206         case RT3090:
10207         case RT3290:
10208         case RT3352:
10209         case RT3390:
10210         case RT3572:
10211         case RT3593:
10212         case RT3883:
10213         case RT5350:
10214         case RT5390:
10215         case RT5392:
10216         case RT5592:
10217                 break;
10218         default:
10219                 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
10220                            rt, rev);
10221                 return -ENODEV;
10222         }
10223
10224         if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
10225                 rt = RT6352;
10226
10227         rt2x00_set_rt(rt2x00dev, rt, rev);
10228
10229         return 0;
10230 }
10231
10232 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
10233 {
10234         int retval;
10235         u32 reg;
10236
10237         retval = rt2800_probe_rt(rt2x00dev);
10238         if (retval)
10239                 return retval;
10240
10241         /*
10242          * Allocate eeprom data.
10243          */
10244         retval = rt2800_validate_eeprom(rt2x00dev);
10245         if (retval)
10246                 return retval;
10247
10248         retval = rt2800_init_eeprom(rt2x00dev);
10249         if (retval)
10250                 return retval;
10251
10252         /*
10253          * Enable rfkill polling by setting GPIO direction of the
10254          * rfkill switch GPIO pin correctly.
10255          */
10256         reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
10257         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
10258         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
10259
10260         /*
10261          * Initialize hw specifications.
10262          */
10263         retval = rt2800_probe_hw_mode(rt2x00dev);
10264         if (retval)
10265                 return retval;
10266
10267         /*
10268          * Set device capabilities.
10269          */
10270         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
10271         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
10272         if (!rt2x00_is_usb(rt2x00dev))
10273                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
10274
10275         /*
10276          * Set device requirements.
10277          */
10278         if (!rt2x00_is_soc(rt2x00dev))
10279                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
10280         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
10281         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
10282         if (!rt2800_hwcrypt_disabled(rt2x00dev))
10283                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
10284         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
10285         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
10286         if (rt2x00_is_usb(rt2x00dev))
10287                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
10288         else {
10289                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
10290                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
10291         }
10292
10293         if (modparam_watchdog) {
10294                 __set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags);
10295                 rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100);
10296         } else {
10297                 rt2x00dev->link.watchdog_disabled = true;
10298         }
10299
10300         /*
10301          * Set the rssi offset.
10302          */
10303         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
10304
10305         return 0;
10306 }
10307 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
10308
10309 /*
10310  * IEEE80211 stack callback functions.
10311  */
10312 void rt2800_get_key_seq(struct ieee80211_hw *hw,
10313                         struct ieee80211_key_conf *key,
10314                         struct ieee80211_key_seq *seq)
10315 {
10316         struct rt2x00_dev *rt2x00dev = hw->priv;
10317         struct mac_iveiv_entry iveiv_entry;
10318         u32 offset;
10319
10320         if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
10321                 return;
10322
10323         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
10324         rt2800_register_multiread(rt2x00dev, offset,
10325                                       &iveiv_entry, sizeof(iveiv_entry));
10326
10327         memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
10328         memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
10329 }
10330 EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
10331
10332 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
10333 {
10334         struct rt2x00_dev *rt2x00dev = hw->priv;
10335         u32 reg;
10336         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
10337
10338         reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
10339         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
10340         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
10341
10342         reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
10343         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
10344         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
10345
10346         reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
10347         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
10348         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
10349
10350         reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
10351         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
10352         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
10353
10354         reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
10355         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
10356         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
10357
10358         reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
10359         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
10360         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
10361
10362         reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
10363         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
10364         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
10365
10366         return 0;
10367 }
10368 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
10369
10370 int rt2800_conf_tx(struct ieee80211_hw *hw,
10371                    struct ieee80211_vif *vif, u16 queue_idx,
10372                    const struct ieee80211_tx_queue_params *params)
10373 {
10374         struct rt2x00_dev *rt2x00dev = hw->priv;
10375         struct data_queue *queue;
10376         struct rt2x00_field32 field;
10377         int retval;
10378         u32 reg;
10379         u32 offset;
10380
10381         /*
10382          * First pass the configuration through rt2x00lib, that will
10383          * update the queue settings and validate the input. After that
10384          * we are free to update the registers based on the value
10385          * in the queue parameter.
10386          */
10387         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
10388         if (retval)
10389                 return retval;
10390
10391         /*
10392          * We only need to perform additional register initialization
10393          * for WMM queues/
10394          */
10395         if (queue_idx >= 4)
10396                 return 0;
10397
10398         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
10399
10400         /* Update WMM TXOP register */
10401         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
10402         field.bit_offset = (queue_idx & 1) * 16;
10403         field.bit_mask = 0xffff << field.bit_offset;
10404
10405         reg = rt2800_register_read(rt2x00dev, offset);
10406         rt2x00_set_field32(&reg, field, queue->txop);
10407         rt2800_register_write(rt2x00dev, offset, reg);
10408
10409         /* Update WMM registers */
10410         field.bit_offset = queue_idx * 4;
10411         field.bit_mask = 0xf << field.bit_offset;
10412
10413         reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG);
10414         rt2x00_set_field32(&reg, field, queue->aifs);
10415         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
10416
10417         reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG);
10418         rt2x00_set_field32(&reg, field, queue->cw_min);
10419         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
10420
10421         reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG);
10422         rt2x00_set_field32(&reg, field, queue->cw_max);
10423         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
10424
10425         /* Update EDCA registers */
10426         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
10427
10428         reg = rt2800_register_read(rt2x00dev, offset);
10429         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
10430         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
10431         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
10432         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
10433         rt2800_register_write(rt2x00dev, offset, reg);
10434
10435         return 0;
10436 }
10437 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
10438
10439 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
10440 {
10441         struct rt2x00_dev *rt2x00dev = hw->priv;
10442         u64 tsf;
10443         u32 reg;
10444
10445         reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1);
10446         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
10447         reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0);
10448         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
10449
10450         return tsf;
10451 }
10452 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
10453
10454 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
10455                         struct ieee80211_ampdu_params *params)
10456 {
10457         struct ieee80211_sta *sta = params->sta;
10458         enum ieee80211_ampdu_mlme_action action = params->action;
10459         u16 tid = params->tid;
10460         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
10461         int ret = 0;
10462
10463         /*
10464          * Don't allow aggregation for stations the hardware isn't aware
10465          * of because tx status reports for frames to an unknown station
10466          * always contain wcid=WCID_END+1 and thus we can't distinguish
10467          * between multiple stations which leads to unwanted situations
10468          * when the hw reorders frames due to aggregation.
10469          */
10470         if (sta_priv->wcid > WCID_END)
10471                 return 1;
10472
10473         switch (action) {
10474         case IEEE80211_AMPDU_RX_START:
10475         case IEEE80211_AMPDU_RX_STOP:
10476                 /*
10477                  * The hw itself takes care of setting up BlockAck mechanisms.
10478                  * So, we only have to allow mac80211 to nagotiate a BlockAck
10479                  * agreement. Once that is done, the hw will BlockAck incoming
10480                  * AMPDUs without further setup.
10481                  */
10482                 break;
10483         case IEEE80211_AMPDU_TX_START:
10484                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
10485                 break;
10486         case IEEE80211_AMPDU_TX_STOP_CONT:
10487         case IEEE80211_AMPDU_TX_STOP_FLUSH:
10488         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
10489                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
10490                 break;
10491         case IEEE80211_AMPDU_TX_OPERATIONAL:
10492                 break;
10493         default:
10494                 rt2x00_warn((struct rt2x00_dev *)hw->priv,
10495                             "Unknown AMPDU action\n");
10496         }
10497
10498         return ret;
10499 }
10500 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
10501
10502 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
10503                       struct survey_info *survey)
10504 {
10505         struct rt2x00_dev *rt2x00dev = hw->priv;
10506         struct ieee80211_conf *conf = &hw->conf;
10507         u32 idle, busy, busy_ext;
10508
10509         if (idx != 0)
10510                 return -ENOENT;
10511
10512         survey->channel = conf->chandef.chan;
10513
10514         idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
10515         busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
10516         busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
10517
10518         if (idle || busy) {
10519                 survey->filled = SURVEY_INFO_TIME |
10520                                  SURVEY_INFO_TIME_BUSY |
10521                                  SURVEY_INFO_TIME_EXT_BUSY;
10522
10523                 survey->time = (idle + busy) / 1000;
10524                 survey->time_busy = busy / 1000;
10525                 survey->time_ext_busy = busy_ext / 1000;
10526         }
10527
10528         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
10529                 survey->filled |= SURVEY_INFO_IN_USE;
10530
10531         return 0;
10532
10533 }
10534 EXPORT_SYMBOL_GPL(rt2800_get_survey);
10535
10536 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
10537 MODULE_VERSION(DRV_VERSION);
10538 MODULE_DESCRIPTION("Ralink RT2800 library");
10539 MODULE_LICENSE("GPL");