2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.10"
31 /* Register definitions */
32 #define MWL8K_HIU_GEN_PTR 0x00000c10
33 #define MWL8K_MODE_STA 0x0000005a
34 #define MWL8K_MODE_AP 0x000000a5
35 #define MWL8K_HIU_INT_CODE 0x00000c14
36 #define MWL8K_FWSTA_READY 0xf0f1f2f4
37 #define MWL8K_FWAP_READY 0xf1f2f4a5
38 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
39 #define MWL8K_HIU_SCRATCH 0x00000c40
41 /* Host->device communications */
42 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
47 #define MWL8K_H2A_INT_DUMMY (1 << 20)
48 #define MWL8K_H2A_INT_RESET (1 << 15)
49 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
50 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
52 /* Device->host communications */
53 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
58 #define MWL8K_A2H_INT_DUMMY (1 << 20)
59 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66 #define MWL8K_A2H_INT_RX_READY (1 << 1)
67 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
69 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
80 #define MWL8K_RX_QUEUES 1
81 #define MWL8K_TX_QUEUES 4
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
91 struct mwl8k_device_info {
95 struct rxd_ops *rxd_ops;
99 struct mwl8k_rx_queue {
102 /* hw receives here */
105 /* refill descs here */
112 DECLARE_PCI_UNMAP_ADDR(dma)
116 struct mwl8k_tx_queue {
117 /* hw transmits here */
120 /* sw appends here */
123 struct ieee80211_tx_queue_stats stats;
124 struct mwl8k_tx_desc *txd;
126 struct sk_buff **skb;
129 /* Pointers to the firmware data and meta information about it. */
130 struct mwl8k_firmware {
131 /* Boot helper code */
132 struct firmware *helper;
135 struct firmware *ucode;
141 struct ieee80211_hw *hw;
143 struct pci_dev *pdev;
145 struct mwl8k_device_info *device_info;
147 struct rxd_ops *rxd_ops;
149 /* firmware files and meta data */
150 struct mwl8k_firmware fw;
152 /* firmware access */
153 struct mutex fw_mutex;
154 struct task_struct *fw_mutex_owner;
156 struct completion *hostcmd_wait;
158 /* lock held over TX and TX reap */
161 /* TX quiesce completion, protected by fw_mutex and tx_lock */
162 struct completion *tx_wait;
164 struct ieee80211_vif *vif;
166 struct ieee80211_channel *current_channel;
168 /* power management status cookie from firmware */
170 dma_addr_t cookie_dma;
177 * Running count of TX packets in flight, to avoid
178 * iterating over the transmit rings each time.
182 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
183 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
186 struct ieee80211_supported_band band;
187 struct ieee80211_channel channels[14];
188 struct ieee80211_rate rates[14];
191 bool radio_short_preamble;
192 bool sniffer_enabled;
195 /* XXX need to convert this to handle multiple interfaces */
197 u8 capture_bssid[ETH_ALEN];
198 struct sk_buff *beacon_skb;
201 * This FJ worker has to be global as it is scheduled from the
202 * RX handler. At this point we don't know which interface it
203 * belongs to until the list of bssids waiting to complete join
206 struct work_struct finalize_join_worker;
208 /* Tasklet to reclaim TX descriptors and buffers after tx */
209 struct tasklet_struct tx_reclaim_task;
212 /* Per interface specific private data */
214 /* backpointer to parent config block */
215 struct mwl8k_priv *priv;
217 /* BSS config of AP or IBSS from mac80211*/
218 struct ieee80211_bss_conf bss_info;
220 /* BSSID of AP or IBSS */
222 u8 mac_addr[ETH_ALEN];
224 /* Index into station database.Returned by update_sta_db call */
227 /* Non AMPDU sequence number assigned by driver */
231 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
233 static const struct ieee80211_channel mwl8k_channels[] = {
234 { .center_freq = 2412, .hw_value = 1, },
235 { .center_freq = 2417, .hw_value = 2, },
236 { .center_freq = 2422, .hw_value = 3, },
237 { .center_freq = 2427, .hw_value = 4, },
238 { .center_freq = 2432, .hw_value = 5, },
239 { .center_freq = 2437, .hw_value = 6, },
240 { .center_freq = 2442, .hw_value = 7, },
241 { .center_freq = 2447, .hw_value = 8, },
242 { .center_freq = 2452, .hw_value = 9, },
243 { .center_freq = 2457, .hw_value = 10, },
244 { .center_freq = 2462, .hw_value = 11, },
247 static const struct ieee80211_rate mwl8k_rates[] = {
248 { .bitrate = 10, .hw_value = 2, },
249 { .bitrate = 20, .hw_value = 4, },
250 { .bitrate = 55, .hw_value = 11, },
251 { .bitrate = 110, .hw_value = 22, },
252 { .bitrate = 220, .hw_value = 44, },
253 { .bitrate = 60, .hw_value = 12, },
254 { .bitrate = 90, .hw_value = 18, },
255 { .bitrate = 120, .hw_value = 24, },
256 { .bitrate = 180, .hw_value = 36, },
257 { .bitrate = 240, .hw_value = 48, },
258 { .bitrate = 360, .hw_value = 72, },
259 { .bitrate = 480, .hw_value = 96, },
260 { .bitrate = 540, .hw_value = 108, },
261 { .bitrate = 720, .hw_value = 144, },
264 static const u8 mwl8k_rateids[12] = {
265 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108,
268 /* Set or get info from Firmware */
269 #define MWL8K_CMD_SET 0x0001
270 #define MWL8K_CMD_GET 0x0000
272 /* Firmware command codes */
273 #define MWL8K_CMD_CODE_DNLD 0x0001
274 #define MWL8K_CMD_GET_HW_SPEC 0x0003
275 #define MWL8K_CMD_SET_HW_SPEC 0x0004
276 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
277 #define MWL8K_CMD_GET_STAT 0x0014
278 #define MWL8K_CMD_RADIO_CONTROL 0x001c
279 #define MWL8K_CMD_RF_TX_POWER 0x001e
280 #define MWL8K_CMD_RF_ANTENNA 0x0020
281 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
282 #define MWL8K_CMD_SET_POST_SCAN 0x0108
283 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
284 #define MWL8K_CMD_SET_AID 0x010d
285 #define MWL8K_CMD_SET_RATE 0x0110
286 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
287 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
288 #define MWL8K_CMD_SET_SLOT 0x0114
289 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
290 #define MWL8K_CMD_SET_WMM_MODE 0x0123
291 #define MWL8K_CMD_MIMO_CONFIG 0x0125
292 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
293 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
294 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
295 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
296 #define MWL8K_CMD_UPDATE_STADB 0x1123
298 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
300 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
301 snprintf(buf, bufsize, "%s", #x);\
304 switch (cmd & ~0x8000) {
305 MWL8K_CMDNAME(CODE_DNLD);
306 MWL8K_CMDNAME(GET_HW_SPEC);
307 MWL8K_CMDNAME(SET_HW_SPEC);
308 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
309 MWL8K_CMDNAME(GET_STAT);
310 MWL8K_CMDNAME(RADIO_CONTROL);
311 MWL8K_CMDNAME(RF_TX_POWER);
312 MWL8K_CMDNAME(RF_ANTENNA);
313 MWL8K_CMDNAME(SET_PRE_SCAN);
314 MWL8K_CMDNAME(SET_POST_SCAN);
315 MWL8K_CMDNAME(SET_RF_CHANNEL);
316 MWL8K_CMDNAME(SET_AID);
317 MWL8K_CMDNAME(SET_RATE);
318 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
319 MWL8K_CMDNAME(RTS_THRESHOLD);
320 MWL8K_CMDNAME(SET_SLOT);
321 MWL8K_CMDNAME(SET_EDCA_PARAMS);
322 MWL8K_CMDNAME(SET_WMM_MODE);
323 MWL8K_CMDNAME(MIMO_CONFIG);
324 MWL8K_CMDNAME(USE_FIXED_RATE);
325 MWL8K_CMDNAME(ENABLE_SNIFFER);
326 MWL8K_CMDNAME(SET_MAC_ADDR);
327 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
328 MWL8K_CMDNAME(UPDATE_STADB);
330 snprintf(buf, bufsize, "0x%x", cmd);
337 /* Hardware and firmware reset */
338 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
340 iowrite32(MWL8K_H2A_INT_RESET,
341 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
342 iowrite32(MWL8K_H2A_INT_RESET,
343 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
347 /* Release fw image */
348 static void mwl8k_release_fw(struct firmware **fw)
352 release_firmware(*fw);
356 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
358 mwl8k_release_fw(&priv->fw.ucode);
359 mwl8k_release_fw(&priv->fw.helper);
362 /* Request fw image */
363 static int mwl8k_request_fw(struct mwl8k_priv *priv,
364 const char *fname, struct firmware **fw)
366 /* release current image */
368 mwl8k_release_fw(fw);
370 return request_firmware((const struct firmware **)fw,
371 fname, &priv->pdev->dev);
374 static int mwl8k_request_firmware(struct mwl8k_priv *priv)
376 struct mwl8k_device_info *di = priv->device_info;
379 if (di->helper_image != NULL) {
380 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
382 printk(KERN_ERR "%s: Error requesting helper "
383 "firmware file %s\n", pci_name(priv->pdev),
389 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
391 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
392 pci_name(priv->pdev), di->fw_image);
393 mwl8k_release_fw(&priv->fw.helper);
400 MODULE_FIRMWARE("mwl8k/helper_8687.fw");
401 MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
403 struct mwl8k_cmd_pkt {
409 } __attribute__((packed));
415 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
417 void __iomem *regs = priv->regs;
421 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
422 if (pci_dma_mapping_error(priv->pdev, dma_addr))
425 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
426 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
427 iowrite32(MWL8K_H2A_INT_DOORBELL,
428 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
429 iowrite32(MWL8K_H2A_INT_DUMMY,
430 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
436 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
437 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
438 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
446 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
448 return loops ? 0 : -ETIMEDOUT;
451 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
452 const u8 *data, size_t length)
454 struct mwl8k_cmd_pkt *cmd;
458 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
462 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
468 int block_size = length > 256 ? 256 : length;
470 memcpy(cmd->payload, data + done, block_size);
471 cmd->length = cpu_to_le16(block_size);
473 rc = mwl8k_send_fw_load_cmd(priv, cmd,
474 sizeof(*cmd) + block_size);
479 length -= block_size;
484 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
492 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
493 const u8 *data, size_t length)
495 unsigned char *buffer;
496 int may_continue, rc = 0;
497 u32 done, prev_block_size;
499 buffer = kmalloc(1024, GFP_KERNEL);
506 while (may_continue > 0) {
509 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
510 if (block_size & 1) {
514 done += prev_block_size;
515 length -= prev_block_size;
518 if (block_size > 1024 || block_size > length) {
528 if (block_size == 0) {
535 prev_block_size = block_size;
536 memcpy(buffer, data + done, block_size);
538 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
543 if (!rc && length != 0)
551 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
553 struct mwl8k_priv *priv = hw->priv;
554 struct firmware *fw = priv->fw.ucode;
555 struct mwl8k_device_info *di = priv->device_info;
559 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
560 struct firmware *helper = priv->fw.helper;
562 if (helper == NULL) {
563 printk(KERN_ERR "%s: helper image needed but none "
564 "given\n", pci_name(priv->pdev));
568 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
570 printk(KERN_ERR "%s: unable to load firmware "
571 "helper image\n", pci_name(priv->pdev));
576 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
578 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
582 printk(KERN_ERR "%s: unable to load firmware image\n",
583 pci_name(priv->pdev));
587 if (di->modes & BIT(NL80211_IFTYPE_AP))
588 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
590 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
597 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
598 if (ready_code == MWL8K_FWAP_READY) {
601 } else if (ready_code == MWL8K_FWSTA_READY) {
610 return loops ? 0 : -ETIMEDOUT;
615 * Defines shared between transmission and reception.
617 /* HT control fields for firmware */
622 } __attribute__((packed));
624 /* Firmware Station database operations */
625 #define MWL8K_STA_DB_ADD_ENTRY 0
626 #define MWL8K_STA_DB_MODIFY_ENTRY 1
627 #define MWL8K_STA_DB_DEL_ENTRY 2
628 #define MWL8K_STA_DB_FLUSH 3
630 /* Peer Entry flags - used to define the type of the peer node */
631 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
633 struct peer_capability_info {
634 /* Peer type - AP vs. STA. */
637 /* Basic 802.11 capabilities from assoc resp. */
640 /* Set if peer supports 802.11n high throughput (HT). */
643 /* Valid if HT is supported. */
645 __u8 extended_ht_caps;
646 struct ewc_ht_info ewc_info;
648 /* Legacy rate table. Intersection of our rates and peer rates. */
649 __u8 legacy_rates[12];
651 /* HT rate table. Intersection of our rates and peer rates. */
655 /* If set, interoperability mode, no proprietary extensions. */
659 __le16 amsdu_enabled;
660 } __attribute__((packed));
662 /* Inline functions to manipulate QoS field in data descriptor. */
663 static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
665 u16 val_mask = 1 << 4;
667 /* End of Service Period Bit 4 */
668 return qos | val_mask;
671 static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
675 u16 qos_mask = ~(val_mask << shift);
677 /* Ack Policy Bit 5-6 */
678 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
681 static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
683 u16 val_mask = 1 << 7;
685 /* AMSDU present Bit 7 */
686 return qos | val_mask;
689 static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
693 u16 qos_mask = ~(val_mask << shift);
695 /* Queue Length Bits 8-15 */
696 return (qos & qos_mask) | ((len & val_mask) << shift);
699 /* DMA header used by firmware and hardware. */
700 struct mwl8k_dma_data {
702 struct ieee80211_hdr wh;
704 } __attribute__((packed));
706 /* Routines to add/remove DMA header from skb. */
707 static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
709 struct mwl8k_dma_data *tr;
712 tr = (struct mwl8k_dma_data *)skb->data;
713 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
715 if (hdrlen != sizeof(tr->wh)) {
716 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
717 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
718 *((__le16 *)(tr->data - 2)) = qos;
720 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
724 if (hdrlen != sizeof(*tr))
725 skb_pull(skb, sizeof(*tr) - hdrlen);
728 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
730 struct ieee80211_hdr *wh;
732 struct mwl8k_dma_data *tr;
735 * Add a firmware DMA header; the firmware requires that we
736 * present a 2-byte payload length followed by a 4-address
737 * header (without QoS field), followed (optionally) by any
738 * WEP/ExtIV header (but only filled in for CCMP).
740 wh = (struct ieee80211_hdr *)skb->data;
742 hdrlen = ieee80211_hdrlen(wh->frame_control);
743 if (hdrlen != sizeof(*tr))
744 skb_push(skb, sizeof(*tr) - hdrlen);
746 if (ieee80211_is_data_qos(wh->frame_control))
749 tr = (struct mwl8k_dma_data *)skb->data;
751 memmove(&tr->wh, wh, hdrlen);
752 if (hdrlen != sizeof(tr->wh))
753 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
756 * Firmware length is the length of the fully formed "802.11
757 * payload". That is, everything except for the 802.11 header.
758 * This includes all crypto material including the MIC.
760 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
765 * Packet reception for 88w8366.
767 struct mwl8k_rxd_8366 {
771 __le32 pkt_phys_addr;
772 __le32 next_rxd_phys_addr;
776 __le32 hw_noise_floor_info;
783 } __attribute__((packed));
785 #define MWL8K_8366_RATE_INFO_MCS_FORMAT 0x80
786 #define MWL8K_8366_RATE_INFO_40MHZ 0x40
787 #define MWL8K_8366_RATE_INFO_RATEID(x) ((x) & 0x3f)
789 #define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80
791 static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr)
793 struct mwl8k_rxd_8366 *rxd = _rxd;
795 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
796 rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST;
799 static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len)
801 struct mwl8k_rxd_8366 *rxd = _rxd;
803 rxd->pkt_len = cpu_to_le16(len);
804 rxd->pkt_phys_addr = cpu_to_le32(addr);
810 mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status,
813 struct mwl8k_rxd_8366 *rxd = _rxd;
815 if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST))
819 memset(status, 0, sizeof(*status));
821 status->signal = -rxd->rssi;
822 status->noise = -rxd->noise_floor;
824 if (rxd->rate & MWL8K_8366_RATE_INFO_MCS_FORMAT) {
825 status->flag |= RX_FLAG_HT;
826 if (rxd->rate & MWL8K_8366_RATE_INFO_40MHZ)
827 status->flag |= RX_FLAG_40MHZ;
828 status->rate_idx = MWL8K_8366_RATE_INFO_RATEID(rxd->rate);
832 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
833 if (mwl8k_rates[i].hw_value == rxd->rate) {
834 status->rate_idx = i;
840 status->band = IEEE80211_BAND_2GHZ;
841 status->freq = ieee80211_channel_to_frequency(rxd->channel);
843 *qos = rxd->qos_control;
845 return le16_to_cpu(rxd->pkt_len);
848 static struct rxd_ops rxd_8366_ops = {
849 .rxd_size = sizeof(struct mwl8k_rxd_8366),
850 .rxd_init = mwl8k_rxd_8366_init,
851 .rxd_refill = mwl8k_rxd_8366_refill,
852 .rxd_process = mwl8k_rxd_8366_process,
856 * Packet reception for 88w8687.
858 struct mwl8k_rxd_8687 {
862 __le32 pkt_phys_addr;
863 __le32 next_rxd_phys_addr;
873 } __attribute__((packed));
875 #define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
876 #define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
877 #define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
878 #define MWL8K_8687_RATE_INFO_40MHZ 0x0004
879 #define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
880 #define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
882 #define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
884 static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
886 struct mwl8k_rxd_8687 *rxd = _rxd;
888 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
889 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
892 static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
894 struct mwl8k_rxd_8687 *rxd = _rxd;
896 rxd->pkt_len = cpu_to_le16(len);
897 rxd->pkt_phys_addr = cpu_to_le32(addr);
903 mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status,
906 struct mwl8k_rxd_8687 *rxd = _rxd;
909 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
913 rate_info = le16_to_cpu(rxd->rate_info);
915 memset(status, 0, sizeof(*status));
917 status->signal = -rxd->rssi;
918 status->noise = -rxd->noise_level;
919 status->qual = rxd->link_quality;
920 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
921 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
923 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
924 status->flag |= RX_FLAG_SHORTPRE;
925 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
926 status->flag |= RX_FLAG_40MHZ;
927 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
928 status->flag |= RX_FLAG_SHORT_GI;
929 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
930 status->flag |= RX_FLAG_HT;
932 status->band = IEEE80211_BAND_2GHZ;
933 status->freq = ieee80211_channel_to_frequency(rxd->channel);
935 *qos = rxd->qos_control;
937 return le16_to_cpu(rxd->pkt_len);
940 static struct rxd_ops rxd_8687_ops = {
941 .rxd_size = sizeof(struct mwl8k_rxd_8687),
942 .rxd_init = mwl8k_rxd_8687_init,
943 .rxd_refill = mwl8k_rxd_8687_refill,
944 .rxd_process = mwl8k_rxd_8687_process,
948 #define MWL8K_RX_DESCS 256
949 #define MWL8K_RX_MAXSZ 3800
951 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
953 struct mwl8k_priv *priv = hw->priv;
954 struct mwl8k_rx_queue *rxq = priv->rxq + index;
962 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
964 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
965 if (rxq->rxd == NULL) {
966 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
967 wiphy_name(hw->wiphy));
970 memset(rxq->rxd, 0, size);
972 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
973 if (rxq->buf == NULL) {
974 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
975 wiphy_name(hw->wiphy));
976 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
979 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
981 for (i = 0; i < MWL8K_RX_DESCS; i++) {
985 dma_addr_t next_dma_addr;
987 desc_size = priv->rxd_ops->rxd_size;
988 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
991 if (nexti == MWL8K_RX_DESCS)
993 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
995 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
1001 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1003 struct mwl8k_priv *priv = hw->priv;
1004 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1008 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
1009 struct sk_buff *skb;
1014 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1018 addr = pci_map_single(priv->pdev, skb->data,
1019 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
1023 if (rxq->tail == MWL8K_RX_DESCS)
1025 rxq->buf[rx].skb = skb;
1026 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
1028 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1029 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
1037 /* Must be called only when the card's reception is completely halted */
1038 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1040 struct mwl8k_priv *priv = hw->priv;
1041 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1044 for (i = 0; i < MWL8K_RX_DESCS; i++) {
1045 if (rxq->buf[i].skb != NULL) {
1046 pci_unmap_single(priv->pdev,
1047 pci_unmap_addr(&rxq->buf[i], dma),
1048 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1049 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
1051 kfree_skb(rxq->buf[i].skb);
1052 rxq->buf[i].skb = NULL;
1059 pci_free_consistent(priv->pdev,
1060 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
1061 rxq->rxd, rxq->rxd_dma);
1067 * Scan a list of BSSIDs to process for finalize join.
1068 * Allows for extension to process multiple BSSIDs.
1071 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1073 return priv->capture_beacon &&
1074 ieee80211_is_beacon(wh->frame_control) &&
1075 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1078 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1079 struct sk_buff *skb)
1081 struct mwl8k_priv *priv = hw->priv;
1083 priv->capture_beacon = false;
1084 memset(priv->capture_bssid, 0, ETH_ALEN);
1087 * Use GFP_ATOMIC as rxq_process is called from
1088 * the primary interrupt handler, memory allocation call
1091 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1092 if (priv->beacon_skb != NULL)
1093 ieee80211_queue_work(hw, &priv->finalize_join_worker);
1096 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1098 struct mwl8k_priv *priv = hw->priv;
1099 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1103 while (rxq->rxd_count && limit--) {
1104 struct sk_buff *skb;
1107 struct ieee80211_rx_status status;
1110 skb = rxq->buf[rxq->head].skb;
1114 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1116 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
1120 rxq->buf[rxq->head].skb = NULL;
1122 pci_unmap_single(priv->pdev,
1123 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1124 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1125 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
1128 if (rxq->head == MWL8K_RX_DESCS)
1133 skb_put(skb, pkt_len);
1134 mwl8k_remove_dma_header(skb, qos);
1137 * Check for a pending join operation. Save a
1138 * copy of the beacon and schedule a tasklet to
1139 * send a FINALIZE_JOIN command to the firmware.
1141 if (mwl8k_capture_bssid(priv, (void *)skb->data))
1142 mwl8k_save_beacon(hw, skb);
1144 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1145 ieee80211_rx_irqsafe(hw, skb);
1155 * Packet transmission.
1158 /* Transmit packet ACK policy */
1159 #define MWL8K_TXD_ACK_POLICY_NORMAL 0
1160 #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1162 #define MWL8K_TXD_STATUS_OK 0x00000001
1163 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1164 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1165 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
1166 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
1168 struct mwl8k_tx_desc {
1173 __le32 pkt_phys_addr;
1175 __u8 dest_MAC_addr[ETH_ALEN];
1176 __le32 next_txd_phys_addr;
1181 } __attribute__((packed));
1183 #define MWL8K_TX_DESCS 128
1185 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1187 struct mwl8k_priv *priv = hw->priv;
1188 struct mwl8k_tx_queue *txq = priv->txq + index;
1192 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1193 txq->stats.limit = MWL8K_TX_DESCS;
1197 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1199 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1200 if (txq->txd == NULL) {
1201 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1202 wiphy_name(hw->wiphy));
1205 memset(txq->txd, 0, size);
1207 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1208 if (txq->skb == NULL) {
1209 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1210 wiphy_name(hw->wiphy));
1211 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1214 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
1216 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1217 struct mwl8k_tx_desc *tx_desc;
1220 tx_desc = txq->txd + i;
1221 nexti = (i + 1) % MWL8K_TX_DESCS;
1223 tx_desc->status = 0;
1224 tx_desc->next_txd_phys_addr =
1225 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1231 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1233 iowrite32(MWL8K_H2A_INT_PPA_READY,
1234 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1235 iowrite32(MWL8K_H2A_INT_DUMMY,
1236 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1237 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1240 struct mwl8k_txq_info {
1249 static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1250 struct mwl8k_txq_info *txinfo)
1252 int count, desc, status;
1253 struct mwl8k_tx_queue *txq;
1254 struct mwl8k_tx_desc *tx_desc;
1257 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1259 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
1260 txq = priv->txq + count;
1261 txinfo[count].len = txq->stats.len;
1262 txinfo[count].head = txq->head;
1263 txinfo[count].tail = txq->tail;
1264 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1265 tx_desc = txq->txd + desc;
1266 status = le32_to_cpu(tx_desc->status);
1268 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1269 txinfo[count].fw_owned++;
1271 txinfo[count].drv_owned++;
1273 if (tx_desc->pkt_len == 0)
1274 txinfo[count].unused++;
1282 * Must be called with priv->fw_mutex held and tx queues stopped.
1284 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1286 struct mwl8k_priv *priv = hw->priv;
1287 DECLARE_COMPLETION_ONSTACK(tx_wait);
1289 unsigned long timeout;
1293 spin_lock_bh(&priv->tx_lock);
1294 count = priv->pending_tx_pkts;
1296 priv->tx_wait = &tx_wait;
1297 spin_unlock_bh(&priv->tx_lock);
1300 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
1304 timeout = wait_for_completion_timeout(&tx_wait,
1305 msecs_to_jiffies(5000));
1309 spin_lock_bh(&priv->tx_lock);
1310 priv->tx_wait = NULL;
1311 newcount = priv->pending_tx_pkts;
1312 mwl8k_scan_tx_ring(priv, txinfo);
1313 spin_unlock_bh(&priv->tx_lock);
1315 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
1316 __func__, __LINE__, count, newcount);
1318 for (index = 0; index < MWL8K_TX_QUEUES; index++)
1319 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1325 txinfo[index].fw_owned,
1326 txinfo[index].drv_owned,
1327 txinfo[index].unused);
1335 #define MWL8K_TXD_SUCCESS(status) \
1336 ((status) & (MWL8K_TXD_STATUS_OK | \
1337 MWL8K_TXD_STATUS_OK_RETRY | \
1338 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1340 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1342 struct mwl8k_priv *priv = hw->priv;
1343 struct mwl8k_tx_queue *txq = priv->txq + index;
1346 while (txq->stats.len > 0) {
1348 struct mwl8k_tx_desc *tx_desc;
1351 struct sk_buff *skb;
1352 struct ieee80211_tx_info *info;
1356 tx_desc = txq->txd + tx;
1358 status = le32_to_cpu(tx_desc->status);
1360 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1364 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1367 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1368 BUG_ON(txq->stats.len == 0);
1370 priv->pending_tx_pkts--;
1372 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1373 size = le16_to_cpu(tx_desc->pkt_len);
1375 txq->skb[tx] = NULL;
1377 BUG_ON(skb == NULL);
1378 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1380 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
1382 /* Mark descriptor as unused */
1383 tx_desc->pkt_phys_addr = 0;
1384 tx_desc->pkt_len = 0;
1386 info = IEEE80211_SKB_CB(skb);
1387 ieee80211_tx_info_clear_status(info);
1388 if (MWL8K_TXD_SUCCESS(status))
1389 info->flags |= IEEE80211_TX_STAT_ACK;
1391 ieee80211_tx_status_irqsafe(hw, skb);
1396 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1397 ieee80211_wake_queue(hw, index);
1400 /* must be called only when the card's transmit is completely halted */
1401 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1403 struct mwl8k_priv *priv = hw->priv;
1404 struct mwl8k_tx_queue *txq = priv->txq + index;
1406 mwl8k_txq_reclaim(hw, index, 1);
1411 pci_free_consistent(priv->pdev,
1412 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1413 txq->txd, txq->txd_dma);
1418 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1420 struct mwl8k_priv *priv = hw->priv;
1421 struct ieee80211_tx_info *tx_info;
1422 struct mwl8k_vif *mwl8k_vif;
1423 struct ieee80211_hdr *wh;
1424 struct mwl8k_tx_queue *txq;
1425 struct mwl8k_tx_desc *tx;
1431 wh = (struct ieee80211_hdr *)skb->data;
1432 if (ieee80211_is_data_qos(wh->frame_control))
1433 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1437 mwl8k_add_dma_header(skb);
1438 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1440 tx_info = IEEE80211_SKB_CB(skb);
1441 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1443 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1444 u16 seqno = mwl8k_vif->seqno;
1446 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1447 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1448 mwl8k_vif->seqno = seqno++ % 4096;
1451 /* Setup firmware control bit fields for each frame type. */
1454 if (ieee80211_is_mgmt(wh->frame_control) ||
1455 ieee80211_is_ctl(wh->frame_control)) {
1457 qos = mwl8k_qos_setbit_eosp(qos);
1458 /* Set Queue size to unspecified */
1459 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1460 } else if (ieee80211_is_data(wh->frame_control)) {
1462 if (is_multicast_ether_addr(wh->addr1))
1463 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1465 /* Send pkt in an aggregate if AMPDU frame. */
1466 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1467 qos = mwl8k_qos_setbit_ack(qos,
1468 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1470 qos = mwl8k_qos_setbit_ack(qos,
1471 MWL8K_TXD_ACK_POLICY_NORMAL);
1473 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1474 qos = mwl8k_qos_setbit_amsdu(qos);
1477 dma = pci_map_single(priv->pdev, skb->data,
1478 skb->len, PCI_DMA_TODEVICE);
1480 if (pci_dma_mapping_error(priv->pdev, dma)) {
1481 printk(KERN_DEBUG "%s: failed to dma map skb, "
1482 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1484 return NETDEV_TX_OK;
1487 spin_lock_bh(&priv->tx_lock);
1489 txq = priv->txq + index;
1491 BUG_ON(txq->skb[txq->tail] != NULL);
1492 txq->skb[txq->tail] = skb;
1494 tx = txq->txd + txq->tail;
1495 tx->data_rate = txdatarate;
1496 tx->tx_priority = index;
1497 tx->qos_control = cpu_to_le16(qos);
1498 tx->pkt_phys_addr = cpu_to_le32(dma);
1499 tx->pkt_len = cpu_to_le16(skb->len);
1501 tx->peer_id = mwl8k_vif->peer_id;
1503 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1507 priv->pending_tx_pkts++;
1510 if (txq->tail == MWL8K_TX_DESCS)
1513 if (txq->head == txq->tail)
1514 ieee80211_stop_queue(hw, index);
1516 mwl8k_tx_start(priv);
1518 spin_unlock_bh(&priv->tx_lock);
1520 return NETDEV_TX_OK;
1527 * We have the following requirements for issuing firmware commands:
1528 * - Some commands require that the packet transmit path is idle when
1529 * the command is issued. (For simplicity, we'll just quiesce the
1530 * transmit path for every command.)
1531 * - There are certain sequences of commands that need to be issued to
1532 * the hardware sequentially, with no other intervening commands.
1534 * This leads to an implementation of a "firmware lock" as a mutex that
1535 * can be taken recursively, and which is taken by both the low-level
1536 * command submission function (mwl8k_post_cmd) as well as any users of
1537 * that function that require issuing of an atomic sequence of commands,
1538 * and quiesces the transmit path whenever it's taken.
1540 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1542 struct mwl8k_priv *priv = hw->priv;
1544 if (priv->fw_mutex_owner != current) {
1547 mutex_lock(&priv->fw_mutex);
1548 ieee80211_stop_queues(hw);
1550 rc = mwl8k_tx_wait_empty(hw);
1552 ieee80211_wake_queues(hw);
1553 mutex_unlock(&priv->fw_mutex);
1558 priv->fw_mutex_owner = current;
1561 priv->fw_mutex_depth++;
1566 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1568 struct mwl8k_priv *priv = hw->priv;
1570 if (!--priv->fw_mutex_depth) {
1571 ieee80211_wake_queues(hw);
1572 priv->fw_mutex_owner = NULL;
1573 mutex_unlock(&priv->fw_mutex);
1579 * Command processing.
1582 /* Timeout firmware commands after 2000ms */
1583 #define MWL8K_CMD_TIMEOUT_MS 2000
1585 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1587 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1588 struct mwl8k_priv *priv = hw->priv;
1589 void __iomem *regs = priv->regs;
1590 dma_addr_t dma_addr;
1591 unsigned int dma_size;
1593 unsigned long timeout = 0;
1596 cmd->result = 0xffff;
1597 dma_size = le16_to_cpu(cmd->length);
1598 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1599 PCI_DMA_BIDIRECTIONAL);
1600 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1603 rc = mwl8k_fw_lock(hw);
1605 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1606 PCI_DMA_BIDIRECTIONAL);
1610 priv->hostcmd_wait = &cmd_wait;
1611 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1612 iowrite32(MWL8K_H2A_INT_DOORBELL,
1613 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1614 iowrite32(MWL8K_H2A_INT_DUMMY,
1615 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1617 timeout = wait_for_completion_timeout(&cmd_wait,
1618 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1620 priv->hostcmd_wait = NULL;
1622 mwl8k_fw_unlock(hw);
1624 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1625 PCI_DMA_BIDIRECTIONAL);
1628 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1629 wiphy_name(hw->wiphy),
1630 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1631 MWL8K_CMD_TIMEOUT_MS);
1634 rc = cmd->result ? -EINVAL : 0;
1636 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1637 wiphy_name(hw->wiphy),
1638 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1639 le16_to_cpu(cmd->result));
1646 * CMD_GET_HW_SPEC (STA version).
1648 struct mwl8k_cmd_get_hw_spec_sta {
1649 struct mwl8k_cmd_pkt header;
1651 __u8 host_interface;
1653 __u8 perm_addr[ETH_ALEN];
1658 __u8 mcs_bitmap[16];
1659 __le32 rx_queue_ptr;
1660 __le32 num_tx_queues;
1661 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1663 __le32 num_tx_desc_per_queue;
1665 } __attribute__((packed));
1667 static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
1669 struct mwl8k_priv *priv = hw->priv;
1670 struct mwl8k_cmd_get_hw_spec_sta *cmd;
1674 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1678 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1679 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1681 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1682 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1683 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1684 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1685 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1686 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1687 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1688 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1690 rc = mwl8k_post_cmd(hw, &cmd->header);
1693 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1694 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1695 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1696 priv->hw_rev = cmd->hw_rev;
1704 * CMD_GET_HW_SPEC (AP version).
1706 struct mwl8k_cmd_get_hw_spec_ap {
1707 struct mwl8k_cmd_pkt header;
1709 __u8 host_interface;
1712 __u8 perm_addr[ETH_ALEN];
1723 } __attribute__((packed));
1725 static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1727 struct mwl8k_priv *priv = hw->priv;
1728 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1731 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1735 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1736 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1738 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1739 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1741 rc = mwl8k_post_cmd(hw, &cmd->header);
1746 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1747 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1748 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1749 priv->hw_rev = cmd->hw_rev;
1751 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1752 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1754 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1755 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1757 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1758 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1760 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1761 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1763 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1764 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1766 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1767 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1777 struct mwl8k_cmd_set_hw_spec {
1778 struct mwl8k_cmd_pkt header;
1780 __u8 host_interface;
1782 __u8 perm_addr[ETH_ALEN];
1787 __le32 rx_queue_ptr;
1788 __le32 num_tx_queues;
1789 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1791 __le32 num_tx_desc_per_queue;
1793 } __attribute__((packed));
1795 #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1797 static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1799 struct mwl8k_priv *priv = hw->priv;
1800 struct mwl8k_cmd_set_hw_spec *cmd;
1804 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1808 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1809 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1811 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1812 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1813 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1814 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1815 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1816 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1817 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1818 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1820 rc = mwl8k_post_cmd(hw, &cmd->header);
1827 * CMD_MAC_MULTICAST_ADR.
1829 struct mwl8k_cmd_mac_multicast_adr {
1830 struct mwl8k_cmd_pkt header;
1833 __u8 addr[0][ETH_ALEN];
1836 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1837 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1838 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1839 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1841 static struct mwl8k_cmd_pkt *
1842 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1843 int mc_count, struct dev_addr_list *mclist)
1845 struct mwl8k_priv *priv = hw->priv;
1846 struct mwl8k_cmd_mac_multicast_adr *cmd;
1849 if (allmulti || mc_count > priv->num_mcaddrs) {
1854 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1856 cmd = kzalloc(size, GFP_ATOMIC);
1860 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1861 cmd->header.length = cpu_to_le16(size);
1862 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1863 MWL8K_ENABLE_RX_BROADCAST);
1866 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1867 } else if (mc_count) {
1870 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1871 cmd->numaddr = cpu_to_le16(mc_count);
1872 for (i = 0; i < mc_count && mclist; i++) {
1873 if (mclist->da_addrlen != ETH_ALEN) {
1877 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1878 mclist = mclist->next;
1882 return &cmd->header;
1886 * CMD_802_11_GET_STAT.
1888 struct mwl8k_cmd_802_11_get_stat {
1889 struct mwl8k_cmd_pkt header;
1891 } __attribute__((packed));
1893 #define MWL8K_STAT_ACK_FAILURE 9
1894 #define MWL8K_STAT_RTS_FAILURE 12
1895 #define MWL8K_STAT_FCS_ERROR 24
1896 #define MWL8K_STAT_RTS_SUCCESS 11
1898 static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1899 struct ieee80211_low_level_stats *stats)
1901 struct mwl8k_cmd_802_11_get_stat *cmd;
1904 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1908 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1909 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1911 rc = mwl8k_post_cmd(hw, &cmd->header);
1913 stats->dot11ACKFailureCount =
1914 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1915 stats->dot11RTSFailureCount =
1916 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1917 stats->dot11FCSErrorCount =
1918 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1919 stats->dot11RTSSuccessCount =
1920 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1928 * CMD_802_11_RADIO_CONTROL.
1930 struct mwl8k_cmd_802_11_radio_control {
1931 struct mwl8k_cmd_pkt header;
1935 } __attribute__((packed));
1938 mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1940 struct mwl8k_priv *priv = hw->priv;
1941 struct mwl8k_cmd_802_11_radio_control *cmd;
1944 if (enable == priv->radio_on && !force)
1947 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1951 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1952 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1953 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1954 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1955 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1957 rc = mwl8k_post_cmd(hw, &cmd->header);
1961 priv->radio_on = enable;
1966 static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1968 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1971 static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1973 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1977 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1979 struct mwl8k_priv *priv;
1981 if (hw == NULL || hw->priv == NULL)
1985 priv->radio_short_preamble = short_preamble;
1987 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
1991 * CMD_802_11_RF_TX_POWER.
1993 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1995 struct mwl8k_cmd_802_11_rf_tx_power {
1996 struct mwl8k_cmd_pkt header;
1998 __le16 support_level;
1999 __le16 current_level;
2001 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
2002 } __attribute__((packed));
2004 static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
2006 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
2009 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2013 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2014 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2015 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2016 cmd->support_level = cpu_to_le16(dBm);
2018 rc = mwl8k_post_cmd(hw, &cmd->header);
2027 struct mwl8k_cmd_rf_antenna {
2028 struct mwl8k_cmd_pkt header;
2031 } __attribute__((packed));
2033 #define MWL8K_RF_ANTENNA_RX 1
2034 #define MWL8K_RF_ANTENNA_TX 2
2037 mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2039 struct mwl8k_cmd_rf_antenna *cmd;
2042 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2046 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2047 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2048 cmd->antenna = cpu_to_le16(antenna);
2049 cmd->mode = cpu_to_le16(mask);
2051 rc = mwl8k_post_cmd(hw, &cmd->header);
2060 struct mwl8k_cmd_set_pre_scan {
2061 struct mwl8k_cmd_pkt header;
2062 } __attribute__((packed));
2064 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2066 struct mwl8k_cmd_set_pre_scan *cmd;
2069 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2073 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2074 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2076 rc = mwl8k_post_cmd(hw, &cmd->header);
2083 * CMD_SET_POST_SCAN.
2085 struct mwl8k_cmd_set_post_scan {
2086 struct mwl8k_cmd_pkt header;
2088 __u8 bssid[ETH_ALEN];
2089 } __attribute__((packed));
2092 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
2094 struct mwl8k_cmd_set_post_scan *cmd;
2097 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2101 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2102 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2104 memcpy(cmd->bssid, mac, ETH_ALEN);
2106 rc = mwl8k_post_cmd(hw, &cmd->header);
2113 * CMD_SET_RF_CHANNEL.
2115 struct mwl8k_cmd_set_rf_channel {
2116 struct mwl8k_cmd_pkt header;
2118 __u8 current_channel;
2119 __le32 channel_flags;
2120 } __attribute__((packed));
2122 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2123 struct ieee80211_channel *channel)
2125 struct mwl8k_cmd_set_rf_channel *cmd;
2128 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2132 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2133 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2134 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2135 cmd->current_channel = channel->hw_value;
2136 if (channel->band == IEEE80211_BAND_2GHZ)
2137 cmd->channel_flags = cpu_to_le32(0x00000081);
2139 cmd->channel_flags = cpu_to_le32(0x00000000);
2141 rc = mwl8k_post_cmd(hw, &cmd->header);
2150 struct mwl8k_cmd_set_slot {
2151 struct mwl8k_cmd_pkt header;
2154 } __attribute__((packed));
2156 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
2158 struct mwl8k_cmd_set_slot *cmd;
2161 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2165 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2166 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2167 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2168 cmd->short_slot = short_slot_time;
2170 rc = mwl8k_post_cmd(hw, &cmd->header);
2179 struct mwl8k_cmd_mimo_config {
2180 struct mwl8k_cmd_pkt header;
2182 __u8 rx_antenna_map;
2183 __u8 tx_antenna_map;
2184 } __attribute__((packed));
2186 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2188 struct mwl8k_cmd_mimo_config *cmd;
2191 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2195 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2196 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2197 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2198 cmd->rx_antenna_map = rx;
2199 cmd->tx_antenna_map = tx;
2201 rc = mwl8k_post_cmd(hw, &cmd->header);
2208 * CMD_ENABLE_SNIFFER.
2210 struct mwl8k_cmd_enable_sniffer {
2211 struct mwl8k_cmd_pkt header;
2213 } __attribute__((packed));
2215 static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2217 struct mwl8k_cmd_enable_sniffer *cmd;
2220 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2224 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2225 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2226 cmd->action = cpu_to_le32(!!enable);
2228 rc = mwl8k_post_cmd(hw, &cmd->header);
2237 struct mwl8k_cmd_set_mac_addr {
2238 struct mwl8k_cmd_pkt header;
2242 __u8 mac_addr[ETH_ALEN];
2244 __u8 mac_addr[ETH_ALEN];
2246 } __attribute__((packed));
2248 static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2250 struct mwl8k_priv *priv = hw->priv;
2251 struct mwl8k_cmd_set_mac_addr *cmd;
2254 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2258 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2259 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2261 cmd->mbss.mac_type = 0;
2262 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2264 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2267 rc = mwl8k_post_cmd(hw, &cmd->header);
2275 * CMD_SET_RATEADAPT_MODE.
2277 struct mwl8k_cmd_set_rate_adapt_mode {
2278 struct mwl8k_cmd_pkt header;
2281 } __attribute__((packed));
2283 static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2285 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2288 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2292 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2293 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2294 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2295 cmd->mode = cpu_to_le16(mode);
2297 rc = mwl8k_post_cmd(hw, &cmd->header);
2306 struct mwl8k_cmd_set_wmm {
2307 struct mwl8k_cmd_pkt header;
2309 } __attribute__((packed));
2311 static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2313 struct mwl8k_priv *priv = hw->priv;
2314 struct mwl8k_cmd_set_wmm *cmd;
2317 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2321 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2322 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2323 cmd->action = cpu_to_le16(!!enable);
2325 rc = mwl8k_post_cmd(hw, &cmd->header);
2329 priv->wmm_enabled = enable;
2335 * CMD_SET_RTS_THRESHOLD.
2337 struct mwl8k_cmd_rts_threshold {
2338 struct mwl8k_cmd_pkt header;
2341 } __attribute__((packed));
2343 static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
2344 u16 action, u16 threshold)
2346 struct mwl8k_cmd_rts_threshold *cmd;
2349 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2353 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2354 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2355 cmd->action = cpu_to_le16(action);
2356 cmd->threshold = cpu_to_le16(threshold);
2358 rc = mwl8k_post_cmd(hw, &cmd->header);
2365 * CMD_SET_EDCA_PARAMS.
2367 struct mwl8k_cmd_set_edca_params {
2368 struct mwl8k_cmd_pkt header;
2370 /* See MWL8K_SET_EDCA_XXX below */
2373 /* TX opportunity in units of 32 us */
2378 /* Log exponent of max contention period: 0...15 */
2381 /* Log exponent of min contention period: 0...15 */
2384 /* Adaptive interframe spacing in units of 32us */
2387 /* TX queue to configure */
2391 /* Log exponent of max contention period: 0...15 */
2394 /* Log exponent of min contention period: 0...15 */
2397 /* Adaptive interframe spacing in units of 32us */
2400 /* TX queue to configure */
2404 } __attribute__((packed));
2406 #define MWL8K_SET_EDCA_CW 0x01
2407 #define MWL8K_SET_EDCA_TXOP 0x02
2408 #define MWL8K_SET_EDCA_AIFS 0x04
2410 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2411 MWL8K_SET_EDCA_TXOP | \
2412 MWL8K_SET_EDCA_AIFS)
2415 mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2416 __u16 cw_min, __u16 cw_max,
2417 __u8 aifs, __u16 txop)
2419 struct mwl8k_priv *priv = hw->priv;
2420 struct mwl8k_cmd_set_edca_params *cmd;
2423 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2428 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2431 qnum ^= !(qnum >> 1);
2433 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2434 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2435 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2436 cmd->txop = cpu_to_le16(txop);
2438 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2439 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2440 cmd->ap.aifs = aifs;
2443 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2444 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2445 cmd->sta.aifs = aifs;
2446 cmd->sta.txq = qnum;
2449 rc = mwl8k_post_cmd(hw, &cmd->header);
2456 * CMD_FINALIZE_JOIN.
2459 /* FJ beacon buffer size is compiled into the firmware. */
2460 #define MWL8K_FJ_BEACON_MAXLEN 128
2462 struct mwl8k_cmd_finalize_join {
2463 struct mwl8k_cmd_pkt header;
2464 __le32 sleep_interval; /* Number of beacon periods to sleep */
2465 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2466 } __attribute__((packed));
2468 static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2469 __u16 framelen, __u16 dtim)
2471 struct mwl8k_cmd_finalize_join *cmd;
2472 struct ieee80211_mgmt *payload = frame;
2480 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2484 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2485 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2486 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2488 hdrlen = ieee80211_hdrlen(payload->frame_control);
2490 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2492 /* XXX TBD Might just have to abort and return an error */
2493 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2494 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2495 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2496 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2498 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2499 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2501 if (payload && payload_len)
2502 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2504 rc = mwl8k_post_cmd(hw, &cmd->header);
2512 struct mwl8k_cmd_update_sta_db {
2513 struct mwl8k_cmd_pkt header;
2515 /* See STADB_ACTION_TYPE */
2518 /* Peer MAC address */
2519 __u8 peer_addr[ETH_ALEN];
2523 /* Peer info - valid during add/update. */
2524 struct peer_capability_info peer_info;
2525 } __attribute__((packed));
2527 static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2528 struct ieee80211_vif *vif, __u32 action)
2530 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2531 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2532 struct mwl8k_cmd_update_sta_db *cmd;
2533 struct peer_capability_info *peer_info;
2536 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2540 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2541 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2543 cmd->action = cpu_to_le32(action);
2544 peer_info = &cmd->peer_info;
2545 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2548 case MWL8K_STA_DB_ADD_ENTRY:
2549 case MWL8K_STA_DB_MODIFY_ENTRY:
2550 /* Build peer_info block */
2551 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2552 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2553 memcpy(peer_info->legacy_rates, mwl8k_rateids,
2554 sizeof(mwl8k_rateids));
2555 peer_info->interop = 1;
2556 peer_info->amsdu_enabled = 0;
2558 rc = mwl8k_post_cmd(hw, &cmd->header);
2560 mv_vif->peer_id = peer_info->station_id;
2564 case MWL8K_STA_DB_DEL_ENTRY:
2565 case MWL8K_STA_DB_FLUSH:
2567 rc = mwl8k_post_cmd(hw, &cmd->header);
2569 mv_vif->peer_id = 0;
2580 #define MWL8K_FRAME_PROT_DISABLED 0x00
2581 #define MWL8K_FRAME_PROT_11G 0x07
2582 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2583 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2585 struct mwl8k_cmd_update_set_aid {
2586 struct mwl8k_cmd_pkt header;
2589 /* AP's MAC address (BSSID) */
2590 __u8 bssid[ETH_ALEN];
2591 __le16 protection_mode;
2592 __u8 supp_rates[14];
2593 } __attribute__((packed));
2595 static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2596 struct ieee80211_vif *vif)
2598 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2599 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2600 struct mwl8k_cmd_update_set_aid *cmd;
2604 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2608 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2609 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2610 cmd->aid = cpu_to_le16(info->aid);
2612 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2614 if (info->use_cts_prot) {
2615 prot_mode = MWL8K_FRAME_PROT_11G;
2617 switch (info->ht_operation_mode &
2618 IEEE80211_HT_OP_MODE_PROTECTION) {
2619 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2620 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2622 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2623 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2626 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2630 cmd->protection_mode = cpu_to_le16(prot_mode);
2632 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2634 rc = mwl8k_post_cmd(hw, &cmd->header);
2643 struct mwl8k_cmd_update_rateset {
2644 struct mwl8k_cmd_pkt header;
2645 __u8 legacy_rates[14];
2647 /* Bitmap for supported MCS codes. */
2650 } __attribute__((packed));
2652 static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2653 struct ieee80211_vif *vif)
2655 struct mwl8k_cmd_update_rateset *cmd;
2658 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2662 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2663 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2664 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2666 rc = mwl8k_post_cmd(hw, &cmd->header);
2673 * CMD_USE_FIXED_RATE.
2675 #define MWL8K_RATE_TABLE_SIZE 8
2676 #define MWL8K_UCAST_RATE 0
2677 #define MWL8K_USE_AUTO_RATE 0x0002
2679 struct mwl8k_rate_entry {
2680 /* Set to 1 if HT rate, 0 if legacy. */
2683 /* Set to 1 to use retry_count field. */
2684 __le32 enable_retry;
2686 /* Specified legacy rate or MCS. */
2689 /* Number of allowed retries. */
2691 } __attribute__((packed));
2693 struct mwl8k_rate_table {
2694 /* 1 to allow specified rate and below */
2695 __le32 allow_rate_drop;
2697 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2698 } __attribute__((packed));
2700 struct mwl8k_cmd_use_fixed_rate {
2701 struct mwl8k_cmd_pkt header;
2703 struct mwl8k_rate_table rate_table;
2705 /* Unicast, Broadcast or Multicast */
2709 } __attribute__((packed));
2711 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2712 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2714 struct mwl8k_cmd_use_fixed_rate *cmd;
2718 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2722 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2723 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2725 cmd->action = cpu_to_le32(action);
2726 cmd->rate_type = cpu_to_le32(rate_type);
2728 if (rate_table != NULL) {
2730 * Copy over each field manually so that endian
2731 * conversion can be done.
2733 cmd->rate_table.allow_rate_drop =
2734 cpu_to_le32(rate_table->allow_rate_drop);
2735 cmd->rate_table.num_rates =
2736 cpu_to_le32(rate_table->num_rates);
2738 for (count = 0; count < rate_table->num_rates; count++) {
2739 struct mwl8k_rate_entry *dst =
2740 &cmd->rate_table.rate_entry[count];
2741 struct mwl8k_rate_entry *src =
2742 &rate_table->rate_entry[count];
2744 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2745 dst->enable_retry = cpu_to_le32(src->enable_retry);
2746 dst->rate = cpu_to_le32(src->rate);
2747 dst->retry_count = cpu_to_le32(src->retry_count);
2751 rc = mwl8k_post_cmd(hw, &cmd->header);
2759 * Interrupt handling.
2761 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2763 struct ieee80211_hw *hw = dev_id;
2764 struct mwl8k_priv *priv = hw->priv;
2767 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2768 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2773 if (status & MWL8K_A2H_INT_TX_DONE)
2774 tasklet_schedule(&priv->tx_reclaim_task);
2776 if (status & MWL8K_A2H_INT_RX_READY) {
2777 while (rxq_process(hw, 0, 1))
2778 rxq_refill(hw, 0, 1);
2781 if (status & MWL8K_A2H_INT_OPC_DONE) {
2782 if (priv->hostcmd_wait != NULL)
2783 complete(priv->hostcmd_wait);
2786 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2787 if (!mutex_is_locked(&priv->fw_mutex) &&
2788 priv->radio_on && priv->pending_tx_pkts)
2789 mwl8k_tx_start(priv);
2797 * Core driver operations.
2799 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2801 struct mwl8k_priv *priv = hw->priv;
2802 int index = skb_get_queue_mapping(skb);
2805 if (priv->current_channel == NULL) {
2806 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2807 "disabled\n", wiphy_name(hw->wiphy));
2809 return NETDEV_TX_OK;
2812 rc = mwl8k_txq_xmit(hw, index, skb);
2817 static int mwl8k_start(struct ieee80211_hw *hw)
2819 struct mwl8k_priv *priv = hw->priv;
2822 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
2823 IRQF_SHARED, MWL8K_NAME, hw);
2825 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2826 wiphy_name(hw->wiphy));
2830 /* Enable tx reclaim tasklet */
2831 tasklet_enable(&priv->tx_reclaim_task);
2833 /* Enable interrupts */
2834 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2836 rc = mwl8k_fw_lock(hw);
2838 rc = mwl8k_cmd_802_11_radio_enable(hw);
2842 rc = mwl8k_enable_sniffer(hw, 0);
2845 rc = mwl8k_cmd_set_pre_scan(hw);
2848 rc = mwl8k_cmd_set_post_scan(hw,
2849 "\x00\x00\x00\x00\x00\x00");
2853 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
2856 rc = mwl8k_set_wmm(hw, 0);
2858 mwl8k_fw_unlock(hw);
2862 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2863 free_irq(priv->pdev->irq, hw);
2864 tasklet_disable(&priv->tx_reclaim_task);
2870 static void mwl8k_stop(struct ieee80211_hw *hw)
2872 struct mwl8k_priv *priv = hw->priv;
2875 mwl8k_cmd_802_11_radio_disable(hw);
2877 ieee80211_stop_queues(hw);
2879 /* Disable interrupts */
2880 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2881 free_irq(priv->pdev->irq, hw);
2883 /* Stop finalize join worker */
2884 cancel_work_sync(&priv->finalize_join_worker);
2885 if (priv->beacon_skb != NULL)
2886 dev_kfree_skb(priv->beacon_skb);
2888 /* Stop tx reclaim tasklet */
2889 tasklet_disable(&priv->tx_reclaim_task);
2891 /* Return all skbs to mac80211 */
2892 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2893 mwl8k_txq_reclaim(hw, i, 1);
2896 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2897 struct ieee80211_if_init_conf *conf)
2899 struct mwl8k_priv *priv = hw->priv;
2900 struct mwl8k_vif *mwl8k_vif;
2903 * We only support one active interface at a time.
2905 if (priv->vif != NULL)
2909 * We only support managed interfaces for now.
2911 if (conf->type != NL80211_IFTYPE_STATION)
2915 * Reject interface creation if sniffer mode is active, as
2916 * STA operation is mutually exclusive with hardware sniffer
2919 if (priv->sniffer_enabled) {
2920 printk(KERN_INFO "%s: unable to create STA "
2921 "interface due to sniffer mode being enabled\n",
2922 wiphy_name(hw->wiphy));
2926 /* Clean out driver private area */
2927 mwl8k_vif = MWL8K_VIF(conf->vif);
2928 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2930 /* Set and save the mac address */
2931 mwl8k_set_mac_addr(hw, conf->mac_addr);
2932 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2934 /* Back pointer to parent config block */
2935 mwl8k_vif->priv = priv;
2937 /* Set Initial sequence number to zero */
2938 mwl8k_vif->seqno = 0;
2940 priv->vif = conf->vif;
2941 priv->current_channel = NULL;
2946 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2947 struct ieee80211_if_init_conf *conf)
2949 struct mwl8k_priv *priv = hw->priv;
2951 if (priv->vif == NULL)
2954 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2959 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2961 struct ieee80211_conf *conf = &hw->conf;
2962 struct mwl8k_priv *priv = hw->priv;
2965 if (conf->flags & IEEE80211_CONF_IDLE) {
2966 mwl8k_cmd_802_11_radio_disable(hw);
2967 priv->current_channel = NULL;
2971 rc = mwl8k_fw_lock(hw);
2975 rc = mwl8k_cmd_802_11_radio_enable(hw);
2979 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2983 priv->current_channel = conf->channel;
2985 if (conf->power_level > 18)
2986 conf->power_level = 18;
2987 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2992 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2994 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2996 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
3000 mwl8k_fw_unlock(hw);
3005 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
3006 struct ieee80211_vif *vif,
3007 struct ieee80211_bss_conf *info,
3010 struct mwl8k_priv *priv = hw->priv;
3011 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3014 if (changed & BSS_CHANGED_BSSID)
3015 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
3017 if ((changed & BSS_CHANGED_ASSOC) == 0)
3020 priv->capture_beacon = false;
3022 rc = mwl8k_fw_lock(hw);
3027 memcpy(&mwl8k_vif->bss_info, info,
3028 sizeof(struct ieee80211_bss_conf));
3031 rc = mwl8k_update_rateset(hw, vif);
3035 /* Turn on rate adaptation */
3036 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
3037 MWL8K_UCAST_RATE, NULL);
3041 /* Set radio preamble */
3042 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
3047 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
3051 /* Update peer rate info */
3052 rc = mwl8k_cmd_update_sta_db(hw, vif,
3053 MWL8K_STA_DB_MODIFY_ENTRY);
3058 rc = mwl8k_cmd_set_aid(hw, vif);
3063 * Finalize the join. Tell rx handler to process
3064 * next beacon from our BSSID.
3066 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
3067 priv->capture_beacon = true;
3069 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
3070 memset(&mwl8k_vif->bss_info, 0,
3071 sizeof(struct ieee80211_bss_conf));
3072 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
3076 mwl8k_fw_unlock(hw);
3079 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3080 int mc_count, struct dev_addr_list *mclist)
3082 struct mwl8k_cmd_pkt *cmd;
3085 * Synthesize and return a command packet that programs the
3086 * hardware multicast address filter. At this point we don't
3087 * know whether FIF_ALLMULTI is being requested, but if it is,
3088 * we'll end up throwing this packet away and creating a new
3089 * one in mwl8k_configure_filter().
3091 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
3093 return (unsigned long)cmd;
3097 mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3098 unsigned int changed_flags,
3099 unsigned int *total_flags)
3101 struct mwl8k_priv *priv = hw->priv;
3104 * Hardware sniffer mode is mutually exclusive with STA
3105 * operation, so refuse to enable sniffer mode if a STA
3106 * interface is active.
3108 if (priv->vif != NULL) {
3109 if (net_ratelimit())
3110 printk(KERN_INFO "%s: not enabling sniffer "
3111 "mode because STA interface is active\n",
3112 wiphy_name(hw->wiphy));
3116 if (!priv->sniffer_enabled) {
3117 if (mwl8k_enable_sniffer(hw, 1))
3119 priv->sniffer_enabled = true;
3122 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3123 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3129 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3130 unsigned int changed_flags,
3131 unsigned int *total_flags,
3134 struct mwl8k_priv *priv = hw->priv;
3135 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3138 * AP firmware doesn't allow fine-grained control over
3139 * the receive filter.
3142 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3148 * Enable hardware sniffer mode if FIF_CONTROL or
3149 * FIF_OTHER_BSS is requested.
3151 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3152 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3157 /* Clear unsupported feature flags */
3158 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3160 if (mwl8k_fw_lock(hw))
3163 if (priv->sniffer_enabled) {
3164 mwl8k_enable_sniffer(hw, 0);
3165 priv->sniffer_enabled = false;
3168 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
3169 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3171 * Disable the BSS filter.
3173 mwl8k_cmd_set_pre_scan(hw);
3178 * Enable the BSS filter.
3180 * If there is an active STA interface, use that
3181 * interface's BSSID, otherwise use a dummy one
3182 * (where the OUI part needs to be nonzero for
3183 * the BSSID to be accepted by POST_SCAN).
3185 bssid = "\x01\x00\x00\x00\x00\x00";
3186 if (priv->vif != NULL)
3187 bssid = MWL8K_VIF(priv->vif)->bssid;
3189 mwl8k_cmd_set_post_scan(hw, bssid);
3194 * If FIF_ALLMULTI is being requested, throw away the command
3195 * packet that ->prepare_multicast() built and replace it with
3196 * a command packet that enables reception of all multicast
3199 if (*total_flags & FIF_ALLMULTI) {
3201 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3205 mwl8k_post_cmd(hw, cmd);
3209 mwl8k_fw_unlock(hw);
3212 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3214 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
3217 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3218 const struct ieee80211_tx_queue_params *params)
3220 struct mwl8k_priv *priv = hw->priv;
3223 rc = mwl8k_fw_lock(hw);
3225 if (!priv->wmm_enabled)
3226 rc = mwl8k_set_wmm(hw, 1);
3229 rc = mwl8k_set_edca_params(hw, queue,
3235 mwl8k_fw_unlock(hw);
3241 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3242 struct ieee80211_tx_queue_stats *stats)
3244 struct mwl8k_priv *priv = hw->priv;
3245 struct mwl8k_tx_queue *txq;
3248 spin_lock_bh(&priv->tx_lock);
3249 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3250 txq = priv->txq + index;
3251 memcpy(&stats[index], &txq->stats,
3252 sizeof(struct ieee80211_tx_queue_stats));
3254 spin_unlock_bh(&priv->tx_lock);
3259 static int mwl8k_get_stats(struct ieee80211_hw *hw,
3260 struct ieee80211_low_level_stats *stats)
3262 return mwl8k_cmd_802_11_get_stat(hw, stats);
3265 static const struct ieee80211_ops mwl8k_ops = {
3267 .start = mwl8k_start,
3269 .add_interface = mwl8k_add_interface,
3270 .remove_interface = mwl8k_remove_interface,
3271 .config = mwl8k_config,
3272 .bss_info_changed = mwl8k_bss_info_changed,
3273 .prepare_multicast = mwl8k_prepare_multicast,
3274 .configure_filter = mwl8k_configure_filter,
3275 .set_rts_threshold = mwl8k_set_rts_threshold,
3276 .conf_tx = mwl8k_conf_tx,
3277 .get_tx_stats = mwl8k_get_tx_stats,
3278 .get_stats = mwl8k_get_stats,
3281 static void mwl8k_tx_reclaim_handler(unsigned long data)
3284 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3285 struct mwl8k_priv *priv = hw->priv;
3287 spin_lock_bh(&priv->tx_lock);
3288 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3289 mwl8k_txq_reclaim(hw, i, 0);
3291 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
3292 complete(priv->tx_wait);
3293 priv->tx_wait = NULL;
3295 spin_unlock_bh(&priv->tx_lock);
3298 static void mwl8k_finalize_join_worker(struct work_struct *work)
3300 struct mwl8k_priv *priv =
3301 container_of(work, struct mwl8k_priv, finalize_join_worker);
3302 struct sk_buff *skb = priv->beacon_skb;
3303 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
3305 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3308 priv->beacon_skb = NULL;
3316 static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3318 .part_name = "88w8687",
3319 .helper_image = "mwl8k/helper_8687.fw",
3320 .fw_image = "mwl8k/fmimage_8687.fw",
3321 .rxd_ops = &rxd_8687_ops,
3322 .modes = BIT(NL80211_IFTYPE_STATION),
3325 .part_name = "88w8366",
3326 .helper_image = "mwl8k/helper_8366.fw",
3327 .fw_image = "mwl8k/fmimage_8366.fw",
3328 .rxd_ops = &rxd_8366_ops,
3333 static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
3334 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3335 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3336 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3339 MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3341 static int __devinit mwl8k_probe(struct pci_dev *pdev,
3342 const struct pci_device_id *id)
3344 static int printed_version = 0;
3345 struct ieee80211_hw *hw;
3346 struct mwl8k_priv *priv;
3350 if (!printed_version) {
3351 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3352 printed_version = 1;
3355 rc = pci_enable_device(pdev);
3357 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3362 rc = pci_request_regions(pdev, MWL8K_NAME);
3364 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3369 pci_set_master(pdev);
3371 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3373 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3381 priv->device_info = &mwl8k_info_tbl[id->driver_data];
3382 priv->rxd_ops = priv->device_info->rxd_ops;
3383 priv->sniffer_enabled = false;
3384 priv->wmm_enabled = false;
3385 priv->pending_tx_pkts = 0;
3387 SET_IEEE80211_DEV(hw, &pdev->dev);
3388 pci_set_drvdata(pdev, hw);
3390 priv->sram = pci_iomap(pdev, 0, 0x10000);
3391 if (priv->sram == NULL) {
3392 printk(KERN_ERR "%s: Cannot map device SRAM\n",
3393 wiphy_name(hw->wiphy));
3398 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3399 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3401 priv->regs = pci_iomap(pdev, 1, 0x10000);
3402 if (priv->regs == NULL) {
3403 priv->regs = pci_iomap(pdev, 2, 0x10000);
3404 if (priv->regs == NULL) {
3405 printk(KERN_ERR "%s: Cannot map device registers\n",
3406 wiphy_name(hw->wiphy));
3411 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3412 priv->band.band = IEEE80211_BAND_2GHZ;
3413 priv->band.channels = priv->channels;
3414 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3415 priv->band.bitrates = priv->rates;
3416 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3417 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3419 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3420 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3423 * Extra headroom is the size of the required DMA header
3424 * minus the size of the smallest 802.11 frame (CTS frame).
3426 hw->extra_tx_headroom =
3427 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3429 hw->channel_change_time = 10;
3431 hw->queues = MWL8K_TX_QUEUES;
3433 hw->wiphy->interface_modes = priv->device_info->modes;
3435 /* Set rssi and noise values to dBm */
3436 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
3437 hw->vif_data_size = sizeof(struct mwl8k_vif);
3440 /* Set default radio state and preamble */
3442 priv->radio_short_preamble = 0;
3444 /* Finalize join worker */
3445 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3447 /* TX reclaim tasklet */
3448 tasklet_init(&priv->tx_reclaim_task,
3449 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3450 tasklet_disable(&priv->tx_reclaim_task);
3452 /* Power management cookie */
3453 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3454 if (priv->cookie == NULL)
3457 rc = mwl8k_rxq_init(hw, 0);
3460 rxq_refill(hw, 0, INT_MAX);
3462 mutex_init(&priv->fw_mutex);
3463 priv->fw_mutex_owner = NULL;
3464 priv->fw_mutex_depth = 0;
3465 priv->hostcmd_wait = NULL;
3467 spin_lock_init(&priv->tx_lock);
3469 priv->tx_wait = NULL;
3471 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3472 rc = mwl8k_txq_init(hw, i);
3474 goto err_free_queues;
3477 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3478 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3479 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3480 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3482 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
3483 IRQF_SHARED, MWL8K_NAME, hw);
3485 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3486 wiphy_name(hw->wiphy));
3487 goto err_free_queues;
3490 /* Reset firmware and hardware */
3491 mwl8k_hw_reset(priv);
3493 /* Ask userland hotplug daemon for the device firmware */
3494 rc = mwl8k_request_firmware(priv);
3496 printk(KERN_ERR "%s: Firmware files not found\n",
3497 wiphy_name(hw->wiphy));
3501 /* Load firmware into hardware */
3502 rc = mwl8k_load_firmware(hw);
3504 printk(KERN_ERR "%s: Cannot start firmware\n",
3505 wiphy_name(hw->wiphy));
3506 goto err_stop_firmware;
3509 /* Reclaim memory once firmware is successfully loaded */
3510 mwl8k_release_firmware(priv);
3513 * Temporarily enable interrupts. Initial firmware host
3514 * commands use interrupts and avoids polling. Disable
3515 * interrupts when done.
3517 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3519 /* Get config data, mac addrs etc */
3521 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3523 rc = mwl8k_cmd_set_hw_spec(hw);
3525 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3528 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3529 wiphy_name(hw->wiphy));
3530 goto err_stop_firmware;
3533 /* Turn radio off */
3534 rc = mwl8k_cmd_802_11_radio_disable(hw);
3536 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3537 goto err_stop_firmware;
3540 /* Clear MAC address */
3541 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3543 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3544 wiphy_name(hw->wiphy));
3545 goto err_stop_firmware;
3548 /* Disable interrupts */
3549 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3550 free_irq(priv->pdev->irq, hw);
3552 rc = ieee80211_register_hw(hw);
3554 printk(KERN_ERR "%s: Cannot register device\n",
3555 wiphy_name(hw->wiphy));
3556 goto err_stop_firmware;
3559 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
3560 wiphy_name(hw->wiphy), priv->device_info->part_name,
3561 priv->hw_rev, hw->wiphy->perm_addr,
3562 priv->ap_fw ? "AP" : "STA",
3563 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3564 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3569 mwl8k_hw_reset(priv);
3570 mwl8k_release_firmware(priv);
3573 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3574 free_irq(priv->pdev->irq, hw);
3577 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3578 mwl8k_txq_deinit(hw, i);
3579 mwl8k_rxq_deinit(hw, 0);
3582 if (priv->cookie != NULL)
3583 pci_free_consistent(priv->pdev, 4,
3584 priv->cookie, priv->cookie_dma);
3586 if (priv->regs != NULL)
3587 pci_iounmap(pdev, priv->regs);
3589 if (priv->sram != NULL)
3590 pci_iounmap(pdev, priv->sram);
3592 pci_set_drvdata(pdev, NULL);
3593 ieee80211_free_hw(hw);
3596 pci_release_regions(pdev);
3597 pci_disable_device(pdev);
3602 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3604 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3607 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3609 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3610 struct mwl8k_priv *priv;
3617 ieee80211_stop_queues(hw);
3619 ieee80211_unregister_hw(hw);
3621 /* Remove tx reclaim tasklet */
3622 tasklet_kill(&priv->tx_reclaim_task);
3625 mwl8k_hw_reset(priv);
3627 /* Return all skbs to mac80211 */
3628 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3629 mwl8k_txq_reclaim(hw, i, 1);
3631 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3632 mwl8k_txq_deinit(hw, i);
3634 mwl8k_rxq_deinit(hw, 0);
3636 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3638 pci_iounmap(pdev, priv->regs);
3639 pci_iounmap(pdev, priv->sram);
3640 pci_set_drvdata(pdev, NULL);
3641 ieee80211_free_hw(hw);
3642 pci_release_regions(pdev);
3643 pci_disable_device(pdev);
3646 static struct pci_driver mwl8k_driver = {
3648 .id_table = mwl8k_pci_id_table,
3649 .probe = mwl8k_probe,
3650 .remove = __devexit_p(mwl8k_remove),
3651 .shutdown = __devexit_p(mwl8k_shutdown),
3654 static int __init mwl8k_init(void)
3656 return pci_register_driver(&mwl8k_driver);
3659 static void __exit mwl8k_exit(void)
3661 pci_unregister_driver(&mwl8k_driver);
3664 module_init(mwl8k_init);
3665 module_exit(mwl8k_exit);
3667 MODULE_DESCRIPTION(MWL8K_DESC);
3668 MODULE_VERSION(MWL8K_VERSION);
3669 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3670 MODULE_LICENSE("GPL");