2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.11"
31 /* Register definitions */
32 #define MWL8K_HIU_GEN_PTR 0x00000c10
33 #define MWL8K_MODE_STA 0x0000005a
34 #define MWL8K_MODE_AP 0x000000a5
35 #define MWL8K_HIU_INT_CODE 0x00000c14
36 #define MWL8K_FWSTA_READY 0xf0f1f2f4
37 #define MWL8K_FWAP_READY 0xf1f2f4a5
38 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
39 #define MWL8K_HIU_SCRATCH 0x00000c40
41 /* Host->device communications */
42 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
47 #define MWL8K_H2A_INT_DUMMY (1 << 20)
48 #define MWL8K_H2A_INT_RESET (1 << 15)
49 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
50 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
52 /* Device->host communications */
53 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
58 #define MWL8K_A2H_INT_DUMMY (1 << 20)
59 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66 #define MWL8K_A2H_INT_RX_READY (1 << 1)
67 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
69 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
80 #define MWL8K_RX_QUEUES 1
81 #define MWL8K_TX_QUEUES 4
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
91 struct mwl8k_device_info {
95 struct rxd_ops *ap_rxd_ops;
98 struct mwl8k_rx_queue {
101 /* hw receives here */
104 /* refill descs here */
111 DECLARE_PCI_UNMAP_ADDR(dma)
115 struct mwl8k_tx_queue {
116 /* hw transmits here */
119 /* sw appends here */
122 struct ieee80211_tx_queue_stats stats;
123 struct mwl8k_tx_desc *txd;
125 struct sk_buff **skb;
129 struct ieee80211_hw *hw;
130 struct pci_dev *pdev;
132 struct mwl8k_device_info *device_info;
138 struct firmware *fw_helper;
139 struct firmware *fw_ucode;
141 /* hardware/firmware parameters */
143 struct rxd_ops *rxd_ops;
145 /* firmware access */
146 struct mutex fw_mutex;
147 struct task_struct *fw_mutex_owner;
149 struct completion *hostcmd_wait;
151 /* lock held over TX and TX reap */
154 /* TX quiesce completion, protected by fw_mutex and tx_lock */
155 struct completion *tx_wait;
157 struct ieee80211_vif *vif;
159 struct ieee80211_channel *current_channel;
161 /* power management status cookie from firmware */
163 dma_addr_t cookie_dma;
170 * Running count of TX packets in flight, to avoid
171 * iterating over the transmit rings each time.
175 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
176 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
179 struct ieee80211_supported_band band;
180 struct ieee80211_channel channels[14];
181 struct ieee80211_rate rates[14];
184 bool radio_short_preamble;
185 bool sniffer_enabled;
188 /* XXX need to convert this to handle multiple interfaces */
190 u8 capture_bssid[ETH_ALEN];
191 struct sk_buff *beacon_skb;
194 * This FJ worker has to be global as it is scheduled from the
195 * RX handler. At this point we don't know which interface it
196 * belongs to until the list of bssids waiting to complete join
199 struct work_struct finalize_join_worker;
201 /* Tasklet to reclaim TX descriptors and buffers after tx */
202 struct tasklet_struct tx_reclaim_task;
205 /* Per interface specific private data */
207 /* Local MAC address. */
208 u8 mac_addr[ETH_ALEN];
213 /* Index into station database. Returned by UPDATE_STADB. */
216 /* Non AMPDU sequence number assigned by driver */
220 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
222 static const struct ieee80211_channel mwl8k_channels[] = {
223 { .center_freq = 2412, .hw_value = 1, },
224 { .center_freq = 2417, .hw_value = 2, },
225 { .center_freq = 2422, .hw_value = 3, },
226 { .center_freq = 2427, .hw_value = 4, },
227 { .center_freq = 2432, .hw_value = 5, },
228 { .center_freq = 2437, .hw_value = 6, },
229 { .center_freq = 2442, .hw_value = 7, },
230 { .center_freq = 2447, .hw_value = 8, },
231 { .center_freq = 2452, .hw_value = 9, },
232 { .center_freq = 2457, .hw_value = 10, },
233 { .center_freq = 2462, .hw_value = 11, },
234 { .center_freq = 2467, .hw_value = 12, },
235 { .center_freq = 2472, .hw_value = 13, },
236 { .center_freq = 2484, .hw_value = 14, },
239 static const struct ieee80211_rate mwl8k_rates[] = {
240 { .bitrate = 10, .hw_value = 2, },
241 { .bitrate = 20, .hw_value = 4, },
242 { .bitrate = 55, .hw_value = 11, },
243 { .bitrate = 110, .hw_value = 22, },
244 { .bitrate = 220, .hw_value = 44, },
245 { .bitrate = 60, .hw_value = 12, },
246 { .bitrate = 90, .hw_value = 18, },
247 { .bitrate = 120, .hw_value = 24, },
248 { .bitrate = 180, .hw_value = 36, },
249 { .bitrate = 240, .hw_value = 48, },
250 { .bitrate = 360, .hw_value = 72, },
251 { .bitrate = 480, .hw_value = 96, },
252 { .bitrate = 540, .hw_value = 108, },
253 { .bitrate = 720, .hw_value = 144, },
256 static const u8 mwl8k_rateids[12] = {
257 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108,
260 /* Set or get info from Firmware */
261 #define MWL8K_CMD_SET 0x0001
262 #define MWL8K_CMD_GET 0x0000
264 /* Firmware command codes */
265 #define MWL8K_CMD_CODE_DNLD 0x0001
266 #define MWL8K_CMD_GET_HW_SPEC 0x0003
267 #define MWL8K_CMD_SET_HW_SPEC 0x0004
268 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
269 #define MWL8K_CMD_GET_STAT 0x0014
270 #define MWL8K_CMD_RADIO_CONTROL 0x001c
271 #define MWL8K_CMD_RF_TX_POWER 0x001e
272 #define MWL8K_CMD_RF_ANTENNA 0x0020
273 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
274 #define MWL8K_CMD_SET_POST_SCAN 0x0108
275 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
276 #define MWL8K_CMD_SET_AID 0x010d
277 #define MWL8K_CMD_SET_RATE 0x0110
278 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
279 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
280 #define MWL8K_CMD_SET_SLOT 0x0114
281 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
282 #define MWL8K_CMD_SET_WMM_MODE 0x0123
283 #define MWL8K_CMD_MIMO_CONFIG 0x0125
284 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
285 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
286 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
287 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
288 #define MWL8K_CMD_UPDATE_STADB 0x1123
290 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
292 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
293 snprintf(buf, bufsize, "%s", #x);\
296 switch (cmd & ~0x8000) {
297 MWL8K_CMDNAME(CODE_DNLD);
298 MWL8K_CMDNAME(GET_HW_SPEC);
299 MWL8K_CMDNAME(SET_HW_SPEC);
300 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
301 MWL8K_CMDNAME(GET_STAT);
302 MWL8K_CMDNAME(RADIO_CONTROL);
303 MWL8K_CMDNAME(RF_TX_POWER);
304 MWL8K_CMDNAME(RF_ANTENNA);
305 MWL8K_CMDNAME(SET_PRE_SCAN);
306 MWL8K_CMDNAME(SET_POST_SCAN);
307 MWL8K_CMDNAME(SET_RF_CHANNEL);
308 MWL8K_CMDNAME(SET_AID);
309 MWL8K_CMDNAME(SET_RATE);
310 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
311 MWL8K_CMDNAME(RTS_THRESHOLD);
312 MWL8K_CMDNAME(SET_SLOT);
313 MWL8K_CMDNAME(SET_EDCA_PARAMS);
314 MWL8K_CMDNAME(SET_WMM_MODE);
315 MWL8K_CMDNAME(MIMO_CONFIG);
316 MWL8K_CMDNAME(USE_FIXED_RATE);
317 MWL8K_CMDNAME(ENABLE_SNIFFER);
318 MWL8K_CMDNAME(SET_MAC_ADDR);
319 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
320 MWL8K_CMDNAME(UPDATE_STADB);
322 snprintf(buf, bufsize, "0x%x", cmd);
329 /* Hardware and firmware reset */
330 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
332 iowrite32(MWL8K_H2A_INT_RESET,
333 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
334 iowrite32(MWL8K_H2A_INT_RESET,
335 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
339 /* Release fw image */
340 static void mwl8k_release_fw(struct firmware **fw)
344 release_firmware(*fw);
348 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
350 mwl8k_release_fw(&priv->fw_ucode);
351 mwl8k_release_fw(&priv->fw_helper);
354 /* Request fw image */
355 static int mwl8k_request_fw(struct mwl8k_priv *priv,
356 const char *fname, struct firmware **fw)
358 /* release current image */
360 mwl8k_release_fw(fw);
362 return request_firmware((const struct firmware **)fw,
363 fname, &priv->pdev->dev);
366 static int mwl8k_request_firmware(struct mwl8k_priv *priv)
368 struct mwl8k_device_info *di = priv->device_info;
371 if (di->helper_image != NULL) {
372 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
374 printk(KERN_ERR "%s: Error requesting helper "
375 "firmware file %s\n", pci_name(priv->pdev),
381 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
383 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
384 pci_name(priv->pdev), di->fw_image);
385 mwl8k_release_fw(&priv->fw_helper);
392 MODULE_FIRMWARE("mwl8k/helper_8687.fw");
393 MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
395 struct mwl8k_cmd_pkt {
401 } __attribute__((packed));
407 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
409 void __iomem *regs = priv->regs;
413 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
414 if (pci_dma_mapping_error(priv->pdev, dma_addr))
417 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
418 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
419 iowrite32(MWL8K_H2A_INT_DOORBELL,
420 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
421 iowrite32(MWL8K_H2A_INT_DUMMY,
422 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
428 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
429 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
430 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
438 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
440 return loops ? 0 : -ETIMEDOUT;
443 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
444 const u8 *data, size_t length)
446 struct mwl8k_cmd_pkt *cmd;
450 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
454 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
460 int block_size = length > 256 ? 256 : length;
462 memcpy(cmd->payload, data + done, block_size);
463 cmd->length = cpu_to_le16(block_size);
465 rc = mwl8k_send_fw_load_cmd(priv, cmd,
466 sizeof(*cmd) + block_size);
471 length -= block_size;
476 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
484 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
485 const u8 *data, size_t length)
487 unsigned char *buffer;
488 int may_continue, rc = 0;
489 u32 done, prev_block_size;
491 buffer = kmalloc(1024, GFP_KERNEL);
498 while (may_continue > 0) {
501 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
502 if (block_size & 1) {
506 done += prev_block_size;
507 length -= prev_block_size;
510 if (block_size > 1024 || block_size > length) {
520 if (block_size == 0) {
527 prev_block_size = block_size;
528 memcpy(buffer, data + done, block_size);
530 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
535 if (!rc && length != 0)
543 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
545 struct mwl8k_priv *priv = hw->priv;
546 struct firmware *fw = priv->fw_ucode;
550 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
551 struct firmware *helper = priv->fw_helper;
553 if (helper == NULL) {
554 printk(KERN_ERR "%s: helper image needed but none "
555 "given\n", pci_name(priv->pdev));
559 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
561 printk(KERN_ERR "%s: unable to load firmware "
562 "helper image\n", pci_name(priv->pdev));
567 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
569 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
573 printk(KERN_ERR "%s: unable to load firmware image\n",
574 pci_name(priv->pdev));
578 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
584 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
585 if (ready_code == MWL8K_FWAP_READY) {
588 } else if (ready_code == MWL8K_FWSTA_READY) {
597 return loops ? 0 : -ETIMEDOUT;
602 * Defines shared between transmission and reception.
604 /* HT control fields for firmware */
609 } __attribute__((packed));
611 /* Firmware Station database operations */
612 #define MWL8K_STA_DB_ADD_ENTRY 0
613 #define MWL8K_STA_DB_MODIFY_ENTRY 1
614 #define MWL8K_STA_DB_DEL_ENTRY 2
615 #define MWL8K_STA_DB_FLUSH 3
617 /* Peer Entry flags - used to define the type of the peer node */
618 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
620 struct peer_capability_info {
621 /* Peer type - AP vs. STA. */
624 /* Basic 802.11 capabilities from assoc resp. */
627 /* Set if peer supports 802.11n high throughput (HT). */
630 /* Valid if HT is supported. */
632 __u8 extended_ht_caps;
633 struct ewc_ht_info ewc_info;
635 /* Legacy rate table. Intersection of our rates and peer rates. */
636 __u8 legacy_rates[12];
638 /* HT rate table. Intersection of our rates and peer rates. */
642 /* If set, interoperability mode, no proprietary extensions. */
646 __le16 amsdu_enabled;
647 } __attribute__((packed));
649 /* DMA header used by firmware and hardware. */
650 struct mwl8k_dma_data {
652 struct ieee80211_hdr wh;
654 } __attribute__((packed));
656 /* Routines to add/remove DMA header from skb. */
657 static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
659 struct mwl8k_dma_data *tr;
662 tr = (struct mwl8k_dma_data *)skb->data;
663 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
665 if (hdrlen != sizeof(tr->wh)) {
666 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
667 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
668 *((__le16 *)(tr->data - 2)) = qos;
670 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
674 if (hdrlen != sizeof(*tr))
675 skb_pull(skb, sizeof(*tr) - hdrlen);
678 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
680 struct ieee80211_hdr *wh;
682 struct mwl8k_dma_data *tr;
685 * Add a firmware DMA header; the firmware requires that we
686 * present a 2-byte payload length followed by a 4-address
687 * header (without QoS field), followed (optionally) by any
688 * WEP/ExtIV header (but only filled in for CCMP).
690 wh = (struct ieee80211_hdr *)skb->data;
692 hdrlen = ieee80211_hdrlen(wh->frame_control);
693 if (hdrlen != sizeof(*tr))
694 skb_push(skb, sizeof(*tr) - hdrlen);
696 if (ieee80211_is_data_qos(wh->frame_control))
699 tr = (struct mwl8k_dma_data *)skb->data;
701 memmove(&tr->wh, wh, hdrlen);
702 if (hdrlen != sizeof(tr->wh))
703 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
706 * Firmware length is the length of the fully formed "802.11
707 * payload". That is, everything except for the 802.11 header.
708 * This includes all crypto material including the MIC.
710 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
715 * Packet reception for 88w8366 AP firmware.
717 struct mwl8k_rxd_8366_ap {
721 __le32 pkt_phys_addr;
722 __le32 next_rxd_phys_addr;
726 __le32 hw_noise_floor_info;
733 } __attribute__((packed));
735 #define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
736 #define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
737 #define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
739 #define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
741 static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
743 struct mwl8k_rxd_8366_ap *rxd = _rxd;
745 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
746 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
749 static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
751 struct mwl8k_rxd_8366_ap *rxd = _rxd;
753 rxd->pkt_len = cpu_to_le16(len);
754 rxd->pkt_phys_addr = cpu_to_le32(addr);
760 mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
763 struct mwl8k_rxd_8366_ap *rxd = _rxd;
765 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
769 memset(status, 0, sizeof(*status));
771 status->signal = -rxd->rssi;
772 status->noise = -rxd->noise_floor;
774 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
775 status->flag |= RX_FLAG_HT;
776 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
777 status->flag |= RX_FLAG_40MHZ;
778 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
782 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
783 if (mwl8k_rates[i].hw_value == rxd->rate) {
784 status->rate_idx = i;
790 status->band = IEEE80211_BAND_2GHZ;
791 status->freq = ieee80211_channel_to_frequency(rxd->channel);
793 *qos = rxd->qos_control;
795 return le16_to_cpu(rxd->pkt_len);
798 static struct rxd_ops rxd_8366_ap_ops = {
799 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
800 .rxd_init = mwl8k_rxd_8366_ap_init,
801 .rxd_refill = mwl8k_rxd_8366_ap_refill,
802 .rxd_process = mwl8k_rxd_8366_ap_process,
806 * Packet reception for STA firmware.
808 struct mwl8k_rxd_sta {
812 __le32 pkt_phys_addr;
813 __le32 next_rxd_phys_addr;
823 } __attribute__((packed));
825 #define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
826 #define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
827 #define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
828 #define MWL8K_STA_RATE_INFO_40MHZ 0x0004
829 #define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
830 #define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
832 #define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
834 static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
836 struct mwl8k_rxd_sta *rxd = _rxd;
838 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
839 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
842 static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
844 struct mwl8k_rxd_sta *rxd = _rxd;
846 rxd->pkt_len = cpu_to_le16(len);
847 rxd->pkt_phys_addr = cpu_to_le32(addr);
853 mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
856 struct mwl8k_rxd_sta *rxd = _rxd;
859 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
863 rate_info = le16_to_cpu(rxd->rate_info);
865 memset(status, 0, sizeof(*status));
867 status->signal = -rxd->rssi;
868 status->noise = -rxd->noise_level;
869 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
870 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
872 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
873 status->flag |= RX_FLAG_SHORTPRE;
874 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
875 status->flag |= RX_FLAG_40MHZ;
876 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
877 status->flag |= RX_FLAG_SHORT_GI;
878 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
879 status->flag |= RX_FLAG_HT;
881 status->band = IEEE80211_BAND_2GHZ;
882 status->freq = ieee80211_channel_to_frequency(rxd->channel);
884 *qos = rxd->qos_control;
886 return le16_to_cpu(rxd->pkt_len);
889 static struct rxd_ops rxd_sta_ops = {
890 .rxd_size = sizeof(struct mwl8k_rxd_sta),
891 .rxd_init = mwl8k_rxd_sta_init,
892 .rxd_refill = mwl8k_rxd_sta_refill,
893 .rxd_process = mwl8k_rxd_sta_process,
897 #define MWL8K_RX_DESCS 256
898 #define MWL8K_RX_MAXSZ 3800
900 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
902 struct mwl8k_priv *priv = hw->priv;
903 struct mwl8k_rx_queue *rxq = priv->rxq + index;
911 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
913 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
914 if (rxq->rxd == NULL) {
915 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
916 wiphy_name(hw->wiphy));
919 memset(rxq->rxd, 0, size);
921 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
922 if (rxq->buf == NULL) {
923 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
924 wiphy_name(hw->wiphy));
925 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
928 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
930 for (i = 0; i < MWL8K_RX_DESCS; i++) {
934 dma_addr_t next_dma_addr;
936 desc_size = priv->rxd_ops->rxd_size;
937 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
940 if (nexti == MWL8K_RX_DESCS)
942 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
944 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
950 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
952 struct mwl8k_priv *priv = hw->priv;
953 struct mwl8k_rx_queue *rxq = priv->rxq + index;
957 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
963 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
967 addr = pci_map_single(priv->pdev, skb->data,
968 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
972 if (rxq->tail == MWL8K_RX_DESCS)
974 rxq->buf[rx].skb = skb;
975 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
977 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
978 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
986 /* Must be called only when the card's reception is completely halted */
987 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
989 struct mwl8k_priv *priv = hw->priv;
990 struct mwl8k_rx_queue *rxq = priv->rxq + index;
993 for (i = 0; i < MWL8K_RX_DESCS; i++) {
994 if (rxq->buf[i].skb != NULL) {
995 pci_unmap_single(priv->pdev,
996 pci_unmap_addr(&rxq->buf[i], dma),
997 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
998 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
1000 kfree_skb(rxq->buf[i].skb);
1001 rxq->buf[i].skb = NULL;
1008 pci_free_consistent(priv->pdev,
1009 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
1010 rxq->rxd, rxq->rxd_dma);
1016 * Scan a list of BSSIDs to process for finalize join.
1017 * Allows for extension to process multiple BSSIDs.
1020 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1022 return priv->capture_beacon &&
1023 ieee80211_is_beacon(wh->frame_control) &&
1024 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1027 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1028 struct sk_buff *skb)
1030 struct mwl8k_priv *priv = hw->priv;
1032 priv->capture_beacon = false;
1033 memset(priv->capture_bssid, 0, ETH_ALEN);
1036 * Use GFP_ATOMIC as rxq_process is called from
1037 * the primary interrupt handler, memory allocation call
1040 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1041 if (priv->beacon_skb != NULL)
1042 ieee80211_queue_work(hw, &priv->finalize_join_worker);
1045 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1047 struct mwl8k_priv *priv = hw->priv;
1048 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1052 while (rxq->rxd_count && limit--) {
1053 struct sk_buff *skb;
1056 struct ieee80211_rx_status status;
1059 skb = rxq->buf[rxq->head].skb;
1063 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1065 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
1069 rxq->buf[rxq->head].skb = NULL;
1071 pci_unmap_single(priv->pdev,
1072 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1073 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1074 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
1077 if (rxq->head == MWL8K_RX_DESCS)
1082 skb_put(skb, pkt_len);
1083 mwl8k_remove_dma_header(skb, qos);
1086 * Check for a pending join operation. Save a
1087 * copy of the beacon and schedule a tasklet to
1088 * send a FINALIZE_JOIN command to the firmware.
1090 if (mwl8k_capture_bssid(priv, (void *)skb->data))
1091 mwl8k_save_beacon(hw, skb);
1093 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1094 ieee80211_rx_irqsafe(hw, skb);
1104 * Packet transmission.
1107 #define MWL8K_TXD_STATUS_OK 0x00000001
1108 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1109 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1110 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
1111 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
1113 #define MWL8K_QOS_QLEN_UNSPEC 0xff00
1114 #define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1115 #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1116 #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1117 #define MWL8K_QOS_EOSP 0x0010
1119 struct mwl8k_tx_desc {
1124 __le32 pkt_phys_addr;
1126 __u8 dest_MAC_addr[ETH_ALEN];
1127 __le32 next_txd_phys_addr;
1132 } __attribute__((packed));
1134 #define MWL8K_TX_DESCS 128
1136 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1138 struct mwl8k_priv *priv = hw->priv;
1139 struct mwl8k_tx_queue *txq = priv->txq + index;
1143 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1144 txq->stats.limit = MWL8K_TX_DESCS;
1148 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1150 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1151 if (txq->txd == NULL) {
1152 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1153 wiphy_name(hw->wiphy));
1156 memset(txq->txd, 0, size);
1158 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1159 if (txq->skb == NULL) {
1160 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1161 wiphy_name(hw->wiphy));
1162 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1165 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
1167 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1168 struct mwl8k_tx_desc *tx_desc;
1171 tx_desc = txq->txd + i;
1172 nexti = (i + 1) % MWL8K_TX_DESCS;
1174 tx_desc->status = 0;
1175 tx_desc->next_txd_phys_addr =
1176 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1182 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1184 iowrite32(MWL8K_H2A_INT_PPA_READY,
1185 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1186 iowrite32(MWL8K_H2A_INT_DUMMY,
1187 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1188 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1191 static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
1193 struct mwl8k_priv *priv = hw->priv;
1196 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1197 struct mwl8k_tx_queue *txq = priv->txq + i;
1203 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1204 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1207 status = le32_to_cpu(tx_desc->status);
1208 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1213 if (tx_desc->pkt_len == 0)
1217 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1218 "fw_owned=%d drv_owned=%d unused=%d\n",
1219 wiphy_name(hw->wiphy), i,
1220 txq->stats.len, txq->head, txq->tail,
1221 fw_owned, drv_owned, unused);
1226 * Must be called with priv->fw_mutex held and tx queues stopped.
1228 #define MWL8K_TX_WAIT_TIMEOUT_MS 1000
1230 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1232 struct mwl8k_priv *priv = hw->priv;
1233 DECLARE_COMPLETION_ONSTACK(tx_wait);
1240 * The TX queues are stopped at this point, so this test
1241 * doesn't need to take ->tx_lock.
1243 if (!priv->pending_tx_pkts)
1249 spin_lock_bh(&priv->tx_lock);
1250 priv->tx_wait = &tx_wait;
1253 unsigned long timeout;
1255 oldcount = priv->pending_tx_pkts;
1257 spin_unlock_bh(&priv->tx_lock);
1258 timeout = wait_for_completion_timeout(&tx_wait,
1259 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
1260 spin_lock_bh(&priv->tx_lock);
1263 WARN_ON(priv->pending_tx_pkts);
1265 printk(KERN_NOTICE "%s: tx rings drained\n",
1266 wiphy_name(hw->wiphy));
1271 if (priv->pending_tx_pkts < oldcount) {
1272 printk(KERN_NOTICE "%s: timeout waiting for tx "
1273 "rings to drain (%d -> %d pkts), retrying\n",
1274 wiphy_name(hw->wiphy), oldcount,
1275 priv->pending_tx_pkts);
1280 priv->tx_wait = NULL;
1282 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1283 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1284 mwl8k_dump_tx_rings(hw);
1288 spin_unlock_bh(&priv->tx_lock);
1293 #define MWL8K_TXD_SUCCESS(status) \
1294 ((status) & (MWL8K_TXD_STATUS_OK | \
1295 MWL8K_TXD_STATUS_OK_RETRY | \
1296 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1298 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1300 struct mwl8k_priv *priv = hw->priv;
1301 struct mwl8k_tx_queue *txq = priv->txq + index;
1304 while (txq->stats.len > 0) {
1306 struct mwl8k_tx_desc *tx_desc;
1309 struct sk_buff *skb;
1310 struct ieee80211_tx_info *info;
1314 tx_desc = txq->txd + tx;
1316 status = le32_to_cpu(tx_desc->status);
1318 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1322 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1325 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1326 BUG_ON(txq->stats.len == 0);
1328 priv->pending_tx_pkts--;
1330 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1331 size = le16_to_cpu(tx_desc->pkt_len);
1333 txq->skb[tx] = NULL;
1335 BUG_ON(skb == NULL);
1336 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1338 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
1340 /* Mark descriptor as unused */
1341 tx_desc->pkt_phys_addr = 0;
1342 tx_desc->pkt_len = 0;
1344 info = IEEE80211_SKB_CB(skb);
1345 ieee80211_tx_info_clear_status(info);
1346 if (MWL8K_TXD_SUCCESS(status))
1347 info->flags |= IEEE80211_TX_STAT_ACK;
1349 ieee80211_tx_status_irqsafe(hw, skb);
1354 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1355 ieee80211_wake_queue(hw, index);
1358 /* must be called only when the card's transmit is completely halted */
1359 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1361 struct mwl8k_priv *priv = hw->priv;
1362 struct mwl8k_tx_queue *txq = priv->txq + index;
1364 mwl8k_txq_reclaim(hw, index, 1);
1369 pci_free_consistent(priv->pdev,
1370 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1371 txq->txd, txq->txd_dma);
1376 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1378 struct mwl8k_priv *priv = hw->priv;
1379 struct ieee80211_tx_info *tx_info;
1380 struct mwl8k_vif *mwl8k_vif;
1381 struct ieee80211_hdr *wh;
1382 struct mwl8k_tx_queue *txq;
1383 struct mwl8k_tx_desc *tx;
1389 wh = (struct ieee80211_hdr *)skb->data;
1390 if (ieee80211_is_data_qos(wh->frame_control))
1391 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1395 mwl8k_add_dma_header(skb);
1396 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1398 tx_info = IEEE80211_SKB_CB(skb);
1399 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1401 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1402 u16 seqno = mwl8k_vif->seqno;
1404 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1405 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1406 mwl8k_vif->seqno = seqno++ % 4096;
1409 /* Setup firmware control bit fields for each frame type. */
1412 if (ieee80211_is_mgmt(wh->frame_control) ||
1413 ieee80211_is_ctl(wh->frame_control)) {
1415 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
1416 } else if (ieee80211_is_data(wh->frame_control)) {
1418 if (is_multicast_ether_addr(wh->addr1))
1419 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1421 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
1422 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1423 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
1425 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
1428 dma = pci_map_single(priv->pdev, skb->data,
1429 skb->len, PCI_DMA_TODEVICE);
1431 if (pci_dma_mapping_error(priv->pdev, dma)) {
1432 printk(KERN_DEBUG "%s: failed to dma map skb, "
1433 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1435 return NETDEV_TX_OK;
1438 spin_lock_bh(&priv->tx_lock);
1440 txq = priv->txq + index;
1442 BUG_ON(txq->skb[txq->tail] != NULL);
1443 txq->skb[txq->tail] = skb;
1445 tx = txq->txd + txq->tail;
1446 tx->data_rate = txdatarate;
1447 tx->tx_priority = index;
1448 tx->qos_control = cpu_to_le16(qos);
1449 tx->pkt_phys_addr = cpu_to_le32(dma);
1450 tx->pkt_len = cpu_to_le16(skb->len);
1452 tx->peer_id = mwl8k_vif->peer_id;
1454 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1458 priv->pending_tx_pkts++;
1461 if (txq->tail == MWL8K_TX_DESCS)
1464 if (txq->head == txq->tail)
1465 ieee80211_stop_queue(hw, index);
1467 mwl8k_tx_start(priv);
1469 spin_unlock_bh(&priv->tx_lock);
1471 return NETDEV_TX_OK;
1478 * We have the following requirements for issuing firmware commands:
1479 * - Some commands require that the packet transmit path is idle when
1480 * the command is issued. (For simplicity, we'll just quiesce the
1481 * transmit path for every command.)
1482 * - There are certain sequences of commands that need to be issued to
1483 * the hardware sequentially, with no other intervening commands.
1485 * This leads to an implementation of a "firmware lock" as a mutex that
1486 * can be taken recursively, and which is taken by both the low-level
1487 * command submission function (mwl8k_post_cmd) as well as any users of
1488 * that function that require issuing of an atomic sequence of commands,
1489 * and quiesces the transmit path whenever it's taken.
1491 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1493 struct mwl8k_priv *priv = hw->priv;
1495 if (priv->fw_mutex_owner != current) {
1498 mutex_lock(&priv->fw_mutex);
1499 ieee80211_stop_queues(hw);
1501 rc = mwl8k_tx_wait_empty(hw);
1503 ieee80211_wake_queues(hw);
1504 mutex_unlock(&priv->fw_mutex);
1509 priv->fw_mutex_owner = current;
1512 priv->fw_mutex_depth++;
1517 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1519 struct mwl8k_priv *priv = hw->priv;
1521 if (!--priv->fw_mutex_depth) {
1522 ieee80211_wake_queues(hw);
1523 priv->fw_mutex_owner = NULL;
1524 mutex_unlock(&priv->fw_mutex);
1530 * Command processing.
1533 /* Timeout firmware commands after 10s */
1534 #define MWL8K_CMD_TIMEOUT_MS 10000
1536 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1538 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1539 struct mwl8k_priv *priv = hw->priv;
1540 void __iomem *regs = priv->regs;
1541 dma_addr_t dma_addr;
1542 unsigned int dma_size;
1544 unsigned long timeout = 0;
1547 cmd->result = 0xffff;
1548 dma_size = le16_to_cpu(cmd->length);
1549 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1550 PCI_DMA_BIDIRECTIONAL);
1551 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1554 rc = mwl8k_fw_lock(hw);
1556 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1557 PCI_DMA_BIDIRECTIONAL);
1561 priv->hostcmd_wait = &cmd_wait;
1562 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1563 iowrite32(MWL8K_H2A_INT_DOORBELL,
1564 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1565 iowrite32(MWL8K_H2A_INT_DUMMY,
1566 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1568 timeout = wait_for_completion_timeout(&cmd_wait,
1569 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1571 priv->hostcmd_wait = NULL;
1573 mwl8k_fw_unlock(hw);
1575 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1576 PCI_DMA_BIDIRECTIONAL);
1579 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1580 wiphy_name(hw->wiphy),
1581 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1582 MWL8K_CMD_TIMEOUT_MS);
1587 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1589 rc = cmd->result ? -EINVAL : 0;
1591 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1592 wiphy_name(hw->wiphy),
1593 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1594 le16_to_cpu(cmd->result));
1596 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1597 wiphy_name(hw->wiphy),
1598 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1606 * CMD_GET_HW_SPEC (STA version).
1608 struct mwl8k_cmd_get_hw_spec_sta {
1609 struct mwl8k_cmd_pkt header;
1611 __u8 host_interface;
1613 __u8 perm_addr[ETH_ALEN];
1618 __u8 mcs_bitmap[16];
1619 __le32 rx_queue_ptr;
1620 __le32 num_tx_queues;
1621 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1623 __le32 num_tx_desc_per_queue;
1625 } __attribute__((packed));
1627 static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
1629 struct mwl8k_priv *priv = hw->priv;
1630 struct mwl8k_cmd_get_hw_spec_sta *cmd;
1634 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1638 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1639 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1641 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1642 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1643 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1644 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1645 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1646 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1647 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1648 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1650 rc = mwl8k_post_cmd(hw, &cmd->header);
1653 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1654 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1655 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1656 priv->hw_rev = cmd->hw_rev;
1664 * CMD_GET_HW_SPEC (AP version).
1666 struct mwl8k_cmd_get_hw_spec_ap {
1667 struct mwl8k_cmd_pkt header;
1669 __u8 host_interface;
1672 __u8 perm_addr[ETH_ALEN];
1683 } __attribute__((packed));
1685 static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1687 struct mwl8k_priv *priv = hw->priv;
1688 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1691 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1695 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1696 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1698 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1699 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1701 rc = mwl8k_post_cmd(hw, &cmd->header);
1706 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1707 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1708 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1709 priv->hw_rev = cmd->hw_rev;
1711 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1712 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1714 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1715 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1717 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1718 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1720 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1721 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1723 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1724 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1726 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1727 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1737 struct mwl8k_cmd_set_hw_spec {
1738 struct mwl8k_cmd_pkt header;
1740 __u8 host_interface;
1742 __u8 perm_addr[ETH_ALEN];
1747 __le32 rx_queue_ptr;
1748 __le32 num_tx_queues;
1749 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1751 __le32 num_tx_desc_per_queue;
1753 } __attribute__((packed));
1755 #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1757 static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1759 struct mwl8k_priv *priv = hw->priv;
1760 struct mwl8k_cmd_set_hw_spec *cmd;
1764 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1768 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1769 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1771 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1772 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1773 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1774 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1775 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1776 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1777 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1778 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1780 rc = mwl8k_post_cmd(hw, &cmd->header);
1787 * CMD_MAC_MULTICAST_ADR.
1789 struct mwl8k_cmd_mac_multicast_adr {
1790 struct mwl8k_cmd_pkt header;
1793 __u8 addr[0][ETH_ALEN];
1796 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1797 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1798 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1799 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1801 static struct mwl8k_cmd_pkt *
1802 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1803 int mc_count, struct dev_addr_list *mclist)
1805 struct mwl8k_priv *priv = hw->priv;
1806 struct mwl8k_cmd_mac_multicast_adr *cmd;
1809 if (allmulti || mc_count > priv->num_mcaddrs) {
1814 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1816 cmd = kzalloc(size, GFP_ATOMIC);
1820 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1821 cmd->header.length = cpu_to_le16(size);
1822 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1823 MWL8K_ENABLE_RX_BROADCAST);
1826 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1827 } else if (mc_count) {
1830 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1831 cmd->numaddr = cpu_to_le16(mc_count);
1832 for (i = 0; i < mc_count && mclist; i++) {
1833 if (mclist->da_addrlen != ETH_ALEN) {
1837 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1838 mclist = mclist->next;
1842 return &cmd->header;
1848 struct mwl8k_cmd_get_stat {
1849 struct mwl8k_cmd_pkt header;
1851 } __attribute__((packed));
1853 #define MWL8K_STAT_ACK_FAILURE 9
1854 #define MWL8K_STAT_RTS_FAILURE 12
1855 #define MWL8K_STAT_FCS_ERROR 24
1856 #define MWL8K_STAT_RTS_SUCCESS 11
1858 static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
1859 struct ieee80211_low_level_stats *stats)
1861 struct mwl8k_cmd_get_stat *cmd;
1864 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1868 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1869 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1871 rc = mwl8k_post_cmd(hw, &cmd->header);
1873 stats->dot11ACKFailureCount =
1874 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1875 stats->dot11RTSFailureCount =
1876 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1877 stats->dot11FCSErrorCount =
1878 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1879 stats->dot11RTSSuccessCount =
1880 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1888 * CMD_RADIO_CONTROL.
1890 struct mwl8k_cmd_radio_control {
1891 struct mwl8k_cmd_pkt header;
1895 } __attribute__((packed));
1898 mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1900 struct mwl8k_priv *priv = hw->priv;
1901 struct mwl8k_cmd_radio_control *cmd;
1904 if (enable == priv->radio_on && !force)
1907 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1911 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1912 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1913 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1914 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1915 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1917 rc = mwl8k_post_cmd(hw, &cmd->header);
1921 priv->radio_on = enable;
1926 static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
1928 return mwl8k_cmd_radio_control(hw, 0, 0);
1931 static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
1933 return mwl8k_cmd_radio_control(hw, 1, 0);
1937 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1939 struct mwl8k_priv *priv = hw->priv;
1941 priv->radio_short_preamble = short_preamble;
1943 return mwl8k_cmd_radio_control(hw, 1, 1);
1949 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1951 struct mwl8k_cmd_rf_tx_power {
1952 struct mwl8k_cmd_pkt header;
1954 __le16 support_level;
1955 __le16 current_level;
1957 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1958 } __attribute__((packed));
1960 static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1962 struct mwl8k_cmd_rf_tx_power *cmd;
1965 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1969 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1970 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1971 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1972 cmd->support_level = cpu_to_le16(dBm);
1974 rc = mwl8k_post_cmd(hw, &cmd->header);
1983 struct mwl8k_cmd_rf_antenna {
1984 struct mwl8k_cmd_pkt header;
1987 } __attribute__((packed));
1989 #define MWL8K_RF_ANTENNA_RX 1
1990 #define MWL8K_RF_ANTENNA_TX 2
1993 mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
1995 struct mwl8k_cmd_rf_antenna *cmd;
1998 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2002 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2003 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2004 cmd->antenna = cpu_to_le16(antenna);
2005 cmd->mode = cpu_to_le16(mask);
2007 rc = mwl8k_post_cmd(hw, &cmd->header);
2016 struct mwl8k_cmd_set_pre_scan {
2017 struct mwl8k_cmd_pkt header;
2018 } __attribute__((packed));
2020 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2022 struct mwl8k_cmd_set_pre_scan *cmd;
2025 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2029 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2030 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2032 rc = mwl8k_post_cmd(hw, &cmd->header);
2039 * CMD_SET_POST_SCAN.
2041 struct mwl8k_cmd_set_post_scan {
2042 struct mwl8k_cmd_pkt header;
2044 __u8 bssid[ETH_ALEN];
2045 } __attribute__((packed));
2048 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
2050 struct mwl8k_cmd_set_post_scan *cmd;
2053 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2057 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2058 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2060 memcpy(cmd->bssid, mac, ETH_ALEN);
2062 rc = mwl8k_post_cmd(hw, &cmd->header);
2069 * CMD_SET_RF_CHANNEL.
2071 struct mwl8k_cmd_set_rf_channel {
2072 struct mwl8k_cmd_pkt header;
2074 __u8 current_channel;
2075 __le32 channel_flags;
2076 } __attribute__((packed));
2078 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2079 struct ieee80211_channel *channel)
2081 struct mwl8k_cmd_set_rf_channel *cmd;
2084 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2088 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2089 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2090 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2091 cmd->current_channel = channel->hw_value;
2092 if (channel->band == IEEE80211_BAND_2GHZ)
2093 cmd->channel_flags = cpu_to_le32(0x00000081);
2095 cmd->channel_flags = cpu_to_le32(0x00000000);
2097 rc = mwl8k_post_cmd(hw, &cmd->header);
2106 #define MWL8K_FRAME_PROT_DISABLED 0x00
2107 #define MWL8K_FRAME_PROT_11G 0x07
2108 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2109 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2111 struct mwl8k_cmd_update_set_aid {
2112 struct mwl8k_cmd_pkt header;
2115 /* AP's MAC address (BSSID) */
2116 __u8 bssid[ETH_ALEN];
2117 __le16 protection_mode;
2118 __u8 supp_rates[14];
2119 } __attribute__((packed));
2122 mwl8k_cmd_set_aid(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2124 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2125 struct mwl8k_cmd_update_set_aid *cmd;
2129 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2133 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2134 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2135 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
2137 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2139 if (vif->bss_conf.use_cts_prot) {
2140 prot_mode = MWL8K_FRAME_PROT_11G;
2142 switch (vif->bss_conf.ht_operation_mode &
2143 IEEE80211_HT_OP_MODE_PROTECTION) {
2144 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2145 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2147 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2148 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2151 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2155 cmd->protection_mode = cpu_to_le16(prot_mode);
2157 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2159 rc = mwl8k_post_cmd(hw, &cmd->header);
2168 struct mwl8k_cmd_set_rate {
2169 struct mwl8k_cmd_pkt header;
2170 __u8 legacy_rates[14];
2172 /* Bitmap for supported MCS codes. */
2175 } __attribute__((packed));
2178 mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2180 struct mwl8k_cmd_set_rate *cmd;
2183 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2187 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2188 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2189 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2191 rc = mwl8k_post_cmd(hw, &cmd->header);
2198 * CMD_FINALIZE_JOIN.
2200 #define MWL8K_FJ_BEACON_MAXLEN 128
2202 struct mwl8k_cmd_finalize_join {
2203 struct mwl8k_cmd_pkt header;
2204 __le32 sleep_interval; /* Number of beacon periods to sleep */
2205 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2206 } __attribute__((packed));
2208 static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2209 int framelen, int dtim)
2211 struct mwl8k_cmd_finalize_join *cmd;
2212 struct ieee80211_mgmt *payload = frame;
2216 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2220 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2221 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2222 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2224 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2225 if (payload_len < 0)
2227 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2228 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2230 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2232 rc = mwl8k_post_cmd(hw, &cmd->header);
2239 * CMD_SET_RTS_THRESHOLD.
2241 struct mwl8k_cmd_set_rts_threshold {
2242 struct mwl8k_cmd_pkt header;
2245 } __attribute__((packed));
2247 static int mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw,
2248 u16 action, u16 threshold)
2250 struct mwl8k_cmd_set_rts_threshold *cmd;
2253 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2257 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2258 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2259 cmd->action = cpu_to_le16(action);
2260 cmd->threshold = cpu_to_le16(threshold);
2262 rc = mwl8k_post_cmd(hw, &cmd->header);
2271 struct mwl8k_cmd_set_slot {
2272 struct mwl8k_cmd_pkt header;
2275 } __attribute__((packed));
2277 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
2279 struct mwl8k_cmd_set_slot *cmd;
2282 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2286 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2287 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2288 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2289 cmd->short_slot = short_slot_time;
2291 rc = mwl8k_post_cmd(hw, &cmd->header);
2298 * CMD_SET_EDCA_PARAMS.
2300 struct mwl8k_cmd_set_edca_params {
2301 struct mwl8k_cmd_pkt header;
2303 /* See MWL8K_SET_EDCA_XXX below */
2306 /* TX opportunity in units of 32 us */
2311 /* Log exponent of max contention period: 0...15 */
2314 /* Log exponent of min contention period: 0...15 */
2317 /* Adaptive interframe spacing in units of 32us */
2320 /* TX queue to configure */
2324 /* Log exponent of max contention period: 0...15 */
2327 /* Log exponent of min contention period: 0...15 */
2330 /* Adaptive interframe spacing in units of 32us */
2333 /* TX queue to configure */
2337 } __attribute__((packed));
2339 #define MWL8K_SET_EDCA_CW 0x01
2340 #define MWL8K_SET_EDCA_TXOP 0x02
2341 #define MWL8K_SET_EDCA_AIFS 0x04
2343 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2344 MWL8K_SET_EDCA_TXOP | \
2345 MWL8K_SET_EDCA_AIFS)
2348 mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2349 __u16 cw_min, __u16 cw_max,
2350 __u8 aifs, __u16 txop)
2352 struct mwl8k_priv *priv = hw->priv;
2353 struct mwl8k_cmd_set_edca_params *cmd;
2356 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2361 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2364 qnum ^= !(qnum >> 1);
2366 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2367 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2368 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2369 cmd->txop = cpu_to_le16(txop);
2371 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2372 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2373 cmd->ap.aifs = aifs;
2376 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2377 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2378 cmd->sta.aifs = aifs;
2379 cmd->sta.txq = qnum;
2382 rc = mwl8k_post_cmd(hw, &cmd->header);
2391 struct mwl8k_cmd_set_wmm_mode {
2392 struct mwl8k_cmd_pkt header;
2394 } __attribute__((packed));
2396 static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
2398 struct mwl8k_priv *priv = hw->priv;
2399 struct mwl8k_cmd_set_wmm_mode *cmd;
2402 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2406 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2407 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2408 cmd->action = cpu_to_le16(!!enable);
2410 rc = mwl8k_post_cmd(hw, &cmd->header);
2414 priv->wmm_enabled = enable;
2422 struct mwl8k_cmd_mimo_config {
2423 struct mwl8k_cmd_pkt header;
2425 __u8 rx_antenna_map;
2426 __u8 tx_antenna_map;
2427 } __attribute__((packed));
2429 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2431 struct mwl8k_cmd_mimo_config *cmd;
2434 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2438 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2439 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2440 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2441 cmd->rx_antenna_map = rx;
2442 cmd->tx_antenna_map = tx;
2444 rc = mwl8k_post_cmd(hw, &cmd->header);
2451 * CMD_USE_FIXED_RATE.
2453 #define MWL8K_RATE_TABLE_SIZE 8
2454 #define MWL8K_UCAST_RATE 0
2455 #define MWL8K_USE_AUTO_RATE 0x0002
2457 struct mwl8k_rate_entry {
2458 /* Set to 1 if HT rate, 0 if legacy. */
2461 /* Set to 1 to use retry_count field. */
2462 __le32 enable_retry;
2464 /* Specified legacy rate or MCS. */
2467 /* Number of allowed retries. */
2469 } __attribute__((packed));
2471 struct mwl8k_rate_table {
2472 /* 1 to allow specified rate and below */
2473 __le32 allow_rate_drop;
2475 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2476 } __attribute__((packed));
2478 struct mwl8k_cmd_use_fixed_rate {
2479 struct mwl8k_cmd_pkt header;
2481 struct mwl8k_rate_table rate_table;
2483 /* Unicast, Broadcast or Multicast */
2487 } __attribute__((packed));
2489 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2490 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2492 struct mwl8k_cmd_use_fixed_rate *cmd;
2496 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2500 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2501 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2503 cmd->action = cpu_to_le32(action);
2504 cmd->rate_type = cpu_to_le32(rate_type);
2506 if (rate_table != NULL) {
2508 * Copy over each field manually so that endian
2509 * conversion can be done.
2511 cmd->rate_table.allow_rate_drop =
2512 cpu_to_le32(rate_table->allow_rate_drop);
2513 cmd->rate_table.num_rates =
2514 cpu_to_le32(rate_table->num_rates);
2516 for (count = 0; count < rate_table->num_rates; count++) {
2517 struct mwl8k_rate_entry *dst =
2518 &cmd->rate_table.rate_entry[count];
2519 struct mwl8k_rate_entry *src =
2520 &rate_table->rate_entry[count];
2522 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2523 dst->enable_retry = cpu_to_le32(src->enable_retry);
2524 dst->rate = cpu_to_le32(src->rate);
2525 dst->retry_count = cpu_to_le32(src->retry_count);
2529 rc = mwl8k_post_cmd(hw, &cmd->header);
2536 * CMD_ENABLE_SNIFFER.
2538 struct mwl8k_cmd_enable_sniffer {
2539 struct mwl8k_cmd_pkt header;
2541 } __attribute__((packed));
2543 static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2545 struct mwl8k_cmd_enable_sniffer *cmd;
2548 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2552 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2553 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2554 cmd->action = cpu_to_le32(!!enable);
2556 rc = mwl8k_post_cmd(hw, &cmd->header);
2565 struct mwl8k_cmd_set_mac_addr {
2566 struct mwl8k_cmd_pkt header;
2570 __u8 mac_addr[ETH_ALEN];
2572 __u8 mac_addr[ETH_ALEN];
2574 } __attribute__((packed));
2576 static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2578 struct mwl8k_priv *priv = hw->priv;
2579 struct mwl8k_cmd_set_mac_addr *cmd;
2582 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2586 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2587 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2589 cmd->mbss.mac_type = 0;
2590 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2592 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2595 rc = mwl8k_post_cmd(hw, &cmd->header);
2602 * CMD_SET_RATEADAPT_MODE.
2604 struct mwl8k_cmd_set_rate_adapt_mode {
2605 struct mwl8k_cmd_pkt header;
2608 } __attribute__((packed));
2610 static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
2612 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2615 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2619 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2620 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2621 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2622 cmd->mode = cpu_to_le16(mode);
2624 rc = mwl8k_post_cmd(hw, &cmd->header);
2633 struct mwl8k_cmd_update_stadb {
2634 struct mwl8k_cmd_pkt header;
2636 /* See STADB_ACTION_TYPE */
2639 /* Peer MAC address */
2640 __u8 peer_addr[ETH_ALEN];
2644 /* Peer info - valid during add/update. */
2645 struct peer_capability_info peer_info;
2646 } __attribute__((packed));
2648 static int mwl8k_cmd_update_stadb(struct ieee80211_hw *hw,
2649 struct ieee80211_vif *vif, __u32 action)
2651 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2652 struct mwl8k_cmd_update_stadb *cmd;
2653 struct peer_capability_info *peer_info;
2656 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2660 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2661 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2663 cmd->action = cpu_to_le32(action);
2664 peer_info = &cmd->peer_info;
2665 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2668 case MWL8K_STA_DB_ADD_ENTRY:
2669 case MWL8K_STA_DB_MODIFY_ENTRY:
2670 /* Build peer_info block */
2671 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2672 peer_info->basic_caps =
2673 cpu_to_le16(vif->bss_conf.assoc_capability);
2674 memcpy(peer_info->legacy_rates, mwl8k_rateids,
2675 sizeof(mwl8k_rateids));
2676 peer_info->interop = 1;
2677 peer_info->amsdu_enabled = 0;
2679 rc = mwl8k_post_cmd(hw, &cmd->header);
2681 mv_vif->peer_id = peer_info->station_id;
2685 case MWL8K_STA_DB_DEL_ENTRY:
2686 case MWL8K_STA_DB_FLUSH:
2688 rc = mwl8k_post_cmd(hw, &cmd->header);
2690 mv_vif->peer_id = 0;
2700 * Interrupt handling.
2702 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2704 struct ieee80211_hw *hw = dev_id;
2705 struct mwl8k_priv *priv = hw->priv;
2708 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2709 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2714 if (status & MWL8K_A2H_INT_TX_DONE)
2715 tasklet_schedule(&priv->tx_reclaim_task);
2717 if (status & MWL8K_A2H_INT_RX_READY) {
2718 while (rxq_process(hw, 0, 1))
2719 rxq_refill(hw, 0, 1);
2722 if (status & MWL8K_A2H_INT_OPC_DONE) {
2723 if (priv->hostcmd_wait != NULL)
2724 complete(priv->hostcmd_wait);
2727 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2728 if (!mutex_is_locked(&priv->fw_mutex) &&
2729 priv->radio_on && priv->pending_tx_pkts)
2730 mwl8k_tx_start(priv);
2738 * Core driver operations.
2740 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2742 struct mwl8k_priv *priv = hw->priv;
2743 int index = skb_get_queue_mapping(skb);
2746 if (priv->current_channel == NULL) {
2747 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2748 "disabled\n", wiphy_name(hw->wiphy));
2750 return NETDEV_TX_OK;
2753 rc = mwl8k_txq_xmit(hw, index, skb);
2758 static int mwl8k_start(struct ieee80211_hw *hw)
2760 struct mwl8k_priv *priv = hw->priv;
2763 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
2764 IRQF_SHARED, MWL8K_NAME, hw);
2766 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2767 wiphy_name(hw->wiphy));
2771 /* Enable tx reclaim tasklet */
2772 tasklet_enable(&priv->tx_reclaim_task);
2774 /* Enable interrupts */
2775 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2777 rc = mwl8k_fw_lock(hw);
2779 rc = mwl8k_cmd_radio_enable(hw);
2783 rc = mwl8k_cmd_enable_sniffer(hw, 0);
2786 rc = mwl8k_cmd_set_pre_scan(hw);
2789 rc = mwl8k_cmd_set_post_scan(hw,
2790 "\x00\x00\x00\x00\x00\x00");
2794 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
2797 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
2799 mwl8k_fw_unlock(hw);
2803 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2804 free_irq(priv->pdev->irq, hw);
2805 tasklet_disable(&priv->tx_reclaim_task);
2811 static void mwl8k_stop(struct ieee80211_hw *hw)
2813 struct mwl8k_priv *priv = hw->priv;
2816 mwl8k_cmd_radio_disable(hw);
2818 ieee80211_stop_queues(hw);
2820 /* Disable interrupts */
2821 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2822 free_irq(priv->pdev->irq, hw);
2824 /* Stop finalize join worker */
2825 cancel_work_sync(&priv->finalize_join_worker);
2826 if (priv->beacon_skb != NULL)
2827 dev_kfree_skb(priv->beacon_skb);
2829 /* Stop tx reclaim tasklet */
2830 tasklet_disable(&priv->tx_reclaim_task);
2832 /* Return all skbs to mac80211 */
2833 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2834 mwl8k_txq_reclaim(hw, i, 1);
2837 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2838 struct ieee80211_vif *vif)
2840 struct mwl8k_priv *priv = hw->priv;
2841 struct mwl8k_vif *mwl8k_vif;
2844 * We only support one active interface at a time.
2846 if (priv->vif != NULL)
2850 * We only support managed interfaces for now.
2852 if (vif->type != NL80211_IFTYPE_STATION)
2856 * Reject interface creation if sniffer mode is active, as
2857 * STA operation is mutually exclusive with hardware sniffer
2860 if (priv->sniffer_enabled) {
2861 printk(KERN_INFO "%s: unable to create STA "
2862 "interface due to sniffer mode being enabled\n",
2863 wiphy_name(hw->wiphy));
2867 /* Clean out driver private area */
2868 mwl8k_vif = MWL8K_VIF(vif);
2869 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2871 /* Set and save the mac address */
2872 mwl8k_cmd_set_mac_addr(hw, vif->addr);
2873 memcpy(mwl8k_vif->mac_addr, vif->addr, ETH_ALEN);
2875 /* Set Initial sequence number to zero */
2876 mwl8k_vif->seqno = 0;
2879 priv->current_channel = NULL;
2884 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2885 struct ieee80211_vif *vif)
2887 struct mwl8k_priv *priv = hw->priv;
2889 if (priv->vif == NULL)
2892 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2897 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2899 struct ieee80211_conf *conf = &hw->conf;
2900 struct mwl8k_priv *priv = hw->priv;
2903 if (conf->flags & IEEE80211_CONF_IDLE) {
2904 mwl8k_cmd_radio_disable(hw);
2905 priv->current_channel = NULL;
2909 rc = mwl8k_fw_lock(hw);
2913 rc = mwl8k_cmd_radio_enable(hw);
2917 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2921 priv->current_channel = conf->channel;
2923 if (conf->power_level > 18)
2924 conf->power_level = 18;
2925 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
2930 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2932 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2934 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
2938 mwl8k_fw_unlock(hw);
2943 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2944 struct ieee80211_vif *vif,
2945 struct ieee80211_bss_conf *info,
2948 struct mwl8k_priv *priv = hw->priv;
2949 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2952 if ((changed & BSS_CHANGED_ASSOC) == 0)
2955 priv->capture_beacon = false;
2957 rc = mwl8k_fw_lock(hw);
2961 if (vif->bss_conf.assoc) {
2962 memcpy(mwl8k_vif->bssid, vif->bss_conf.bssid, ETH_ALEN);
2965 rc = mwl8k_cmd_set_rate(hw, vif);
2969 /* Turn on rate adaptation */
2970 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2971 MWL8K_UCAST_RATE, NULL);
2975 /* Set radio preamble */
2976 rc = mwl8k_set_radio_preamble(hw,
2977 vif->bss_conf.use_short_preamble);
2982 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
2986 /* Update peer rate info */
2987 rc = mwl8k_cmd_update_stadb(hw, vif,
2988 MWL8K_STA_DB_MODIFY_ENTRY);
2993 rc = mwl8k_cmd_set_aid(hw, vif);
2998 * Finalize the join. Tell rx handler to process
2999 * next beacon from our BSSID.
3001 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
3002 priv->capture_beacon = true;
3004 rc = mwl8k_cmd_update_stadb(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
3005 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
3009 mwl8k_fw_unlock(hw);
3012 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3013 int mc_count, struct dev_addr_list *mclist)
3015 struct mwl8k_cmd_pkt *cmd;
3018 * Synthesize and return a command packet that programs the
3019 * hardware multicast address filter. At this point we don't
3020 * know whether FIF_ALLMULTI is being requested, but if it is,
3021 * we'll end up throwing this packet away and creating a new
3022 * one in mwl8k_configure_filter().
3024 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
3026 return (unsigned long)cmd;
3030 mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3031 unsigned int changed_flags,
3032 unsigned int *total_flags)
3034 struct mwl8k_priv *priv = hw->priv;
3037 * Hardware sniffer mode is mutually exclusive with STA
3038 * operation, so refuse to enable sniffer mode if a STA
3039 * interface is active.
3041 if (priv->vif != NULL) {
3042 if (net_ratelimit())
3043 printk(KERN_INFO "%s: not enabling sniffer "
3044 "mode because STA interface is active\n",
3045 wiphy_name(hw->wiphy));
3049 if (!priv->sniffer_enabled) {
3050 if (mwl8k_cmd_enable_sniffer(hw, 1))
3052 priv->sniffer_enabled = true;
3055 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3056 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3062 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3063 unsigned int changed_flags,
3064 unsigned int *total_flags,
3067 struct mwl8k_priv *priv = hw->priv;
3068 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3071 * AP firmware doesn't allow fine-grained control over
3072 * the receive filter.
3075 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3081 * Enable hardware sniffer mode if FIF_CONTROL or
3082 * FIF_OTHER_BSS is requested.
3084 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3085 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3090 /* Clear unsupported feature flags */
3091 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3093 if (mwl8k_fw_lock(hw))
3096 if (priv->sniffer_enabled) {
3097 mwl8k_cmd_enable_sniffer(hw, 0);
3098 priv->sniffer_enabled = false;
3101 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
3102 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3104 * Disable the BSS filter.
3106 mwl8k_cmd_set_pre_scan(hw);
3111 * Enable the BSS filter.
3113 * If there is an active STA interface, use that
3114 * interface's BSSID, otherwise use a dummy one
3115 * (where the OUI part needs to be nonzero for
3116 * the BSSID to be accepted by POST_SCAN).
3118 bssid = "\x01\x00\x00\x00\x00\x00";
3119 if (priv->vif != NULL)
3120 bssid = MWL8K_VIF(priv->vif)->bssid;
3122 mwl8k_cmd_set_post_scan(hw, bssid);
3127 * If FIF_ALLMULTI is being requested, throw away the command
3128 * packet that ->prepare_multicast() built and replace it with
3129 * a command packet that enables reception of all multicast
3132 if (*total_flags & FIF_ALLMULTI) {
3134 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3138 mwl8k_post_cmd(hw, cmd);
3142 mwl8k_fw_unlock(hw);
3145 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3147 return mwl8k_cmd_set_rts_threshold(hw, MWL8K_CMD_SET, value);
3150 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3151 const struct ieee80211_tx_queue_params *params)
3153 struct mwl8k_priv *priv = hw->priv;
3156 rc = mwl8k_fw_lock(hw);
3158 if (!priv->wmm_enabled)
3159 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
3162 rc = mwl8k_cmd_set_edca_params(hw, queue,
3168 mwl8k_fw_unlock(hw);
3174 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3175 struct ieee80211_tx_queue_stats *stats)
3177 struct mwl8k_priv *priv = hw->priv;
3178 struct mwl8k_tx_queue *txq;
3181 spin_lock_bh(&priv->tx_lock);
3182 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3183 txq = priv->txq + index;
3184 memcpy(&stats[index], &txq->stats,
3185 sizeof(struct ieee80211_tx_queue_stats));
3187 spin_unlock_bh(&priv->tx_lock);
3192 static int mwl8k_get_stats(struct ieee80211_hw *hw,
3193 struct ieee80211_low_level_stats *stats)
3195 return mwl8k_cmd_get_stat(hw, stats);
3198 static const struct ieee80211_ops mwl8k_ops = {
3200 .start = mwl8k_start,
3202 .add_interface = mwl8k_add_interface,
3203 .remove_interface = mwl8k_remove_interface,
3204 .config = mwl8k_config,
3205 .bss_info_changed = mwl8k_bss_info_changed,
3206 .prepare_multicast = mwl8k_prepare_multicast,
3207 .configure_filter = mwl8k_configure_filter,
3208 .set_rts_threshold = mwl8k_set_rts_threshold,
3209 .conf_tx = mwl8k_conf_tx,
3210 .get_tx_stats = mwl8k_get_tx_stats,
3211 .get_stats = mwl8k_get_stats,
3214 static void mwl8k_tx_reclaim_handler(unsigned long data)
3217 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3218 struct mwl8k_priv *priv = hw->priv;
3220 spin_lock_bh(&priv->tx_lock);
3221 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3222 mwl8k_txq_reclaim(hw, i, 0);
3224 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
3225 complete(priv->tx_wait);
3226 priv->tx_wait = NULL;
3228 spin_unlock_bh(&priv->tx_lock);
3231 static void mwl8k_finalize_join_worker(struct work_struct *work)
3233 struct mwl8k_priv *priv =
3234 container_of(work, struct mwl8k_priv, finalize_join_worker);
3235 struct sk_buff *skb = priv->beacon_skb;
3237 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
3238 priv->vif->bss_conf.dtim_period);
3241 priv->beacon_skb = NULL;
3249 static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3251 .part_name = "88w8687",
3252 .helper_image = "mwl8k/helper_8687.fw",
3253 .fw_image = "mwl8k/fmimage_8687.fw",
3256 .part_name = "88w8366",
3257 .helper_image = "mwl8k/helper_8366.fw",
3258 .fw_image = "mwl8k/fmimage_8366.fw",
3259 .ap_rxd_ops = &rxd_8366_ap_ops,
3263 static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
3264 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3265 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3266 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3269 MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3271 static int __devinit mwl8k_probe(struct pci_dev *pdev,
3272 const struct pci_device_id *id)
3274 static int printed_version = 0;
3275 struct ieee80211_hw *hw;
3276 struct mwl8k_priv *priv;
3280 if (!printed_version) {
3281 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3282 printed_version = 1;
3286 rc = pci_enable_device(pdev);
3288 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3293 rc = pci_request_regions(pdev, MWL8K_NAME);
3295 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3297 goto err_disable_device;
3300 pci_set_master(pdev);
3303 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3305 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3310 SET_IEEE80211_DEV(hw, &pdev->dev);
3311 pci_set_drvdata(pdev, hw);
3316 priv->device_info = &mwl8k_info_tbl[id->driver_data];
3319 priv->sram = pci_iomap(pdev, 0, 0x10000);
3320 if (priv->sram == NULL) {
3321 printk(KERN_ERR "%s: Cannot map device SRAM\n",
3322 wiphy_name(hw->wiphy));
3327 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3328 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3330 priv->regs = pci_iomap(pdev, 1, 0x10000);
3331 if (priv->regs == NULL) {
3332 priv->regs = pci_iomap(pdev, 2, 0x10000);
3333 if (priv->regs == NULL) {
3334 printk(KERN_ERR "%s: Cannot map device registers\n",
3335 wiphy_name(hw->wiphy));
3341 /* Reset firmware and hardware */
3342 mwl8k_hw_reset(priv);
3344 /* Ask userland hotplug daemon for the device firmware */
3345 rc = mwl8k_request_firmware(priv);
3347 printk(KERN_ERR "%s: Firmware files not found\n",
3348 wiphy_name(hw->wiphy));
3349 goto err_stop_firmware;
3352 /* Load firmware into hardware */
3353 rc = mwl8k_load_firmware(hw);
3355 printk(KERN_ERR "%s: Cannot start firmware\n",
3356 wiphy_name(hw->wiphy));
3357 goto err_stop_firmware;
3360 /* Reclaim memory once firmware is successfully loaded */
3361 mwl8k_release_firmware(priv);
3365 priv->rxd_ops = priv->device_info->ap_rxd_ops;
3366 if (priv->rxd_ops == NULL) {
3367 printk(KERN_ERR "%s: Driver does not have AP "
3368 "firmware image support for this hardware\n",
3369 wiphy_name(hw->wiphy));
3370 goto err_stop_firmware;
3373 priv->rxd_ops = &rxd_sta_ops;
3376 priv->sniffer_enabled = false;
3377 priv->wmm_enabled = false;
3378 priv->pending_tx_pkts = 0;
3381 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3382 priv->band.band = IEEE80211_BAND_2GHZ;
3383 priv->band.channels = priv->channels;
3384 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3385 priv->band.bitrates = priv->rates;
3386 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3387 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3389 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3390 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3393 * Extra headroom is the size of the required DMA header
3394 * minus the size of the smallest 802.11 frame (CTS frame).
3396 hw->extra_tx_headroom =
3397 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3399 hw->channel_change_time = 10;
3401 hw->queues = MWL8K_TX_QUEUES;
3403 /* Set rssi and noise values to dBm */
3404 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
3405 hw->vif_data_size = sizeof(struct mwl8k_vif);
3408 /* Set default radio state and preamble */
3410 priv->radio_short_preamble = 0;
3412 /* Finalize join worker */
3413 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3415 /* TX reclaim tasklet */
3416 tasklet_init(&priv->tx_reclaim_task,
3417 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3418 tasklet_disable(&priv->tx_reclaim_task);
3420 /* Power management cookie */
3421 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3422 if (priv->cookie == NULL)
3423 goto err_stop_firmware;
3425 rc = mwl8k_rxq_init(hw, 0);
3427 goto err_free_cookie;
3428 rxq_refill(hw, 0, INT_MAX);
3430 mutex_init(&priv->fw_mutex);
3431 priv->fw_mutex_owner = NULL;
3432 priv->fw_mutex_depth = 0;
3433 priv->hostcmd_wait = NULL;
3435 spin_lock_init(&priv->tx_lock);
3437 priv->tx_wait = NULL;
3439 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3440 rc = mwl8k_txq_init(hw, i);
3442 goto err_free_queues;
3445 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3446 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3447 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3448 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3450 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
3451 IRQF_SHARED, MWL8K_NAME, hw);
3453 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3454 wiphy_name(hw->wiphy));
3455 goto err_free_queues;
3459 * Temporarily enable interrupts. Initial firmware host
3460 * commands use interrupts and avoids polling. Disable
3461 * interrupts when done.
3463 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3465 /* Get config data, mac addrs etc */
3467 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3469 rc = mwl8k_cmd_set_hw_spec(hw);
3471 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3473 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
3476 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3477 wiphy_name(hw->wiphy));
3481 /* Turn radio off */
3482 rc = mwl8k_cmd_radio_disable(hw);
3484 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3488 /* Clear MAC address */
3489 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3491 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3492 wiphy_name(hw->wiphy));
3496 /* Disable interrupts */
3497 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3498 free_irq(priv->pdev->irq, hw);
3500 rc = ieee80211_register_hw(hw);
3502 printk(KERN_ERR "%s: Cannot register device\n",
3503 wiphy_name(hw->wiphy));
3507 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
3508 wiphy_name(hw->wiphy), priv->device_info->part_name,
3509 priv->hw_rev, hw->wiphy->perm_addr,
3510 priv->ap_fw ? "AP" : "STA",
3511 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3512 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3517 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3518 free_irq(priv->pdev->irq, hw);
3521 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3522 mwl8k_txq_deinit(hw, i);
3523 mwl8k_rxq_deinit(hw, 0);
3526 if (priv->cookie != NULL)
3527 pci_free_consistent(priv->pdev, 4,
3528 priv->cookie, priv->cookie_dma);
3531 mwl8k_hw_reset(priv);
3532 mwl8k_release_firmware(priv);
3535 if (priv->regs != NULL)
3536 pci_iounmap(pdev, priv->regs);
3538 if (priv->sram != NULL)
3539 pci_iounmap(pdev, priv->sram);
3541 pci_set_drvdata(pdev, NULL);
3542 ieee80211_free_hw(hw);
3545 pci_release_regions(pdev);
3548 pci_disable_device(pdev);
3553 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3555 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3558 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3560 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3561 struct mwl8k_priv *priv;
3568 ieee80211_stop_queues(hw);
3570 ieee80211_unregister_hw(hw);
3572 /* Remove tx reclaim tasklet */
3573 tasklet_kill(&priv->tx_reclaim_task);
3576 mwl8k_hw_reset(priv);
3578 /* Return all skbs to mac80211 */
3579 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3580 mwl8k_txq_reclaim(hw, i, 1);
3582 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3583 mwl8k_txq_deinit(hw, i);
3585 mwl8k_rxq_deinit(hw, 0);
3587 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3589 pci_iounmap(pdev, priv->regs);
3590 pci_iounmap(pdev, priv->sram);
3591 pci_set_drvdata(pdev, NULL);
3592 ieee80211_free_hw(hw);
3593 pci_release_regions(pdev);
3594 pci_disable_device(pdev);
3597 static struct pci_driver mwl8k_driver = {
3599 .id_table = mwl8k_pci_id_table,
3600 .probe = mwl8k_probe,
3601 .remove = __devexit_p(mwl8k_remove),
3602 .shutdown = __devexit_p(mwl8k_shutdown),
3605 static int __init mwl8k_init(void)
3607 return pci_register_driver(&mwl8k_driver);
3610 static void __exit mwl8k_exit(void)
3612 pci_unregister_driver(&mwl8k_driver);
3615 module_init(mwl8k_init);
3616 module_exit(mwl8k_exit);
3618 MODULE_DESCRIPTION(MWL8K_DESC);
3619 MODULE_VERSION(MWL8K_VERSION);
3620 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3621 MODULE_LICENSE("GPL");