drivers/net/wireless/mediatek/mt76/dma.c

   1 // SPDX-License-Identifier: ISC
   2 /*
   3  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
   4  */
   5
   6 #include <linux/dma-mapping.h>
   7 #include "mt76.h"
   8 #include "dma.h"
   9
  10 #if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED)
  11
  12 #define Q_READ(_dev, _q, _field) ({                                     \
  13         u32 _offset = offsetof(struct mt76_queue_regs, _field);         \
  14         u32 _val;                                                       \
  15         if ((_q)->flags & MT_QFLAG_WED)                                 \
  16                 _val = mtk_wed_device_reg_read(&(_dev)->mmio.wed,       \
  17                                                ((_q)->wed_regs +        \
  18                                                 _offset));              \
  19         else                                                            \
  20                 _val = readl(&(_q)->regs->_field);                      \
  21         _val;                                                           \
  22 })
  23
  24 #define Q_WRITE(_dev, _q, _field, _val) do {                            \
  25         u32 _offset = offsetof(struct mt76_queue_regs, _field);         \
  26         if ((_q)->flags & MT_QFLAG_WED)                                 \
  27                 mtk_wed_device_reg_write(&(_dev)->mmio.wed,             \
  28                                          ((_q)->wed_regs + _offset),    \
  29                                          _val);                         \
  30         else                                                            \
  31                 writel(_val, &(_q)->regs->_field);                      \
  32 } while (0)
  33
  34 #else
  35
  36 #define Q_READ(_dev, _q, _field)        readl(&(_q)->regs->_field)
  37 #define Q_WRITE(_dev, _q, _field, _val) writel(_val, &(_q)->regs->_field)
  38
  39 #endif
  40
  41 static struct mt76_txwi_cache *
  42 mt76_alloc_txwi(struct mt76_dev *dev)
  43 {
  44         struct mt76_txwi_cache *t;
  45         dma_addr_t addr;
  46         u8 *txwi;
  47         int size;
  48
  49         size = L1_CACHE_ALIGN(dev->drv->txwi_size + sizeof(*t));
  50         txwi = kzalloc(size, GFP_ATOMIC);
  51         if (!txwi)
  52                 return NULL;
  53
  54         addr = dma_map_single(dev->dma_dev, txwi, dev->drv->txwi_size,
  55                               DMA_TO_DEVICE);
  56         t = (struct mt76_txwi_cache *)(txwi + dev->drv->txwi_size);
  57         t->dma_addr = addr;
  58
  59         return t;
  60 }
  61
  62 static struct mt76_txwi_cache *
  63 mt76_alloc_rxwi(struct mt76_dev *dev)
  64 {
  65         struct mt76_txwi_cache *t;
  66
  67         t = kzalloc(L1_CACHE_ALIGN(sizeof(*t)), GFP_ATOMIC);
  68         if (!t)
  69                 return NULL;
  70
  71         t->ptr = NULL;
  72         return t;
  73 }
  74
  75 static struct mt76_txwi_cache *
  76 __mt76_get_txwi(struct mt76_dev *dev)
  77 {
  78         struct mt76_txwi_cache *t = NULL;
  79
  80         spin_lock(&dev->lock);
  81         if (!list_empty(&dev->txwi_cache)) {
  82                 t = list_first_entry(&dev->txwi_cache, struct mt76_txwi_cache,
  83                                      list);
  84                 list_del(&t->list);
  85         }
  86         spin_unlock(&dev->lock);
  87
  88         return t;
  89 }
  90
  91 static struct mt76_txwi_cache *
  92 __mt76_get_rxwi(struct mt76_dev *dev)
  93 {
  94         struct mt76_txwi_cache *t = NULL;
  95
  96         spin_lock(&dev->wed_lock);
  97         if (!list_empty(&dev->rxwi_cache)) {
  98                 t = list_first_entry(&dev->rxwi_cache, struct mt76_txwi_cache,
  99                                      list);
 100                 list_del(&t->list);
 101         }
 102         spin_unlock(&dev->wed_lock);
 103
 104         return t;
 105 }
 106
 107 static struct mt76_txwi_cache *
 108 mt76_get_txwi(struct mt76_dev *dev)
 109 {
 110         struct mt76_txwi_cache *t = __mt76_get_txwi(dev);
 111
 112         if (t)
 113                 return t;
 114
 115         return mt76_alloc_txwi(dev);
 116 }
 117
 118 struct mt76_txwi_cache *
 119 mt76_get_rxwi(struct mt76_dev *dev)
 120 {
 121         struct mt76_txwi_cache *t = __mt76_get_rxwi(dev);
 122
 123         if (t)
 124                 return t;
 125
 126         return mt76_alloc_rxwi(dev);
 127 }
 128 EXPORT_SYMBOL_GPL(mt76_get_rxwi);
 129
 130 void
 131 mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
 132 {
 133         if (!t)
 134                 return;
 135
 136         spin_lock(&dev->lock);
 137         list_add(&t->list, &dev->txwi_cache);
 138         spin_unlock(&dev->lock);
 139 }
 140 EXPORT_SYMBOL_GPL(mt76_put_txwi);
 141
 142 void
 143 mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
 144 {
 145         if (!t)
 146                 return;
 147
 148         spin_lock(&dev->wed_lock);
 149         list_add(&t->list, &dev->rxwi_cache);
 150         spin_unlock(&dev->wed_lock);
 151 }
 152 EXPORT_SYMBOL_GPL(mt76_put_rxwi);
 153
 154 static void
 155 mt76_free_pending_txwi(struct mt76_dev *dev)
 156 {
 157         struct mt76_txwi_cache *t;
 158
 159         local_bh_disable();
 160         while ((t = __mt76_get_txwi(dev)) != NULL) {
 161                 dma_unmap_single(dev->dma_dev, t->dma_addr, dev->drv->txwi_size,
 162                                  DMA_TO_DEVICE);
 163                 kfree(mt76_get_txwi_ptr(dev, t));
 164         }
 165         local_bh_enable();
 166 }
 167
 168 static void
 169 mt76_free_pending_rxwi(struct mt76_dev *dev)
 170 {
 171         struct mt76_txwi_cache *t;
 172
 173         local_bh_disable();
 174         while ((t = __mt76_get_rxwi(dev)) != NULL) {
 175                 if (t->ptr)
 176                         skb_free_frag(t->ptr);
 177                 kfree(t);
 178         }
 179         local_bh_enable();
 180 }
 181
 182 static void
 183 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
 184 {
 185         Q_WRITE(dev, q, desc_base, q->desc_dma);
 186         Q_WRITE(dev, q, ring_size, q->ndesc);
 187         q->head = Q_READ(dev, q, dma_idx);
 188         q->tail = q->head;
 189 }
 190
 191 static void
 192 mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
 193 {
 194         int i;
 195
 196         if (!q || !q->ndesc)
 197                 return;
 198
 199         /* clear descriptors */
 200         for (i = 0; i < q->ndesc; i++)
 201                 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE);
 202
 203         Q_WRITE(dev, q, cpu_idx, 0);
 204         Q_WRITE(dev, q, dma_idx, 0);
 205         mt76_dma_sync_idx(dev, q);
 206 }
 207
 208 static int
 209 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
 210                  struct mt76_queue_buf *buf, int nbufs, u32 info,
 211                  struct sk_buff *skb, void *txwi)
 212 {
 213         struct mt76_queue_entry *entry;
 214         struct mt76_desc *desc;
 215         int i, idx = -1;
 216         u32 ctrl, next;
 217
 218         for (i = 0; i < nbufs; i += 2, buf += 2) {
 219                 u32 buf0 = buf[0].addr, buf1 = 0;
 220
 221                 idx = q->head;
 222                 next = (q->head + 1) % q->ndesc;
 223
 224                 desc = &q->desc[idx];
 225                 entry = &q->entry[idx];
 226
 227                 if ((q->flags & MT_QFLAG_WED) &&
 228                     FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX) {
 229                         struct mt76_txwi_cache *t = txwi;
 230                         int rx_token;
 231
 232                         if (!t)
 233                                 return -ENOMEM;
 234
 235                         rx_token = mt76_rx_token_consume(dev, (void *)skb, t,
 236                                                          buf[0].addr);
 237                         if (rx_token < 0)
 238                                 return -ENOMEM;
 239
 240                         buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token);
 241                         ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len) |
 242                                MT_DMA_CTL_TO_HOST;
 243                 } else {
 244                         if (txwi) {
 245                                 q->entry[next].txwi = DMA_DUMMY_DATA;
 246                                 q->entry[next].skip_buf0 = true;
 247                         }
 248
 249                         if (buf[0].skip_unmap)
 250                                 entry->skip_buf0 = true;
 251                         entry->skip_buf1 = i == nbufs - 1;
 252
 253                         entry->dma_addr[0] = buf[0].addr;
 254                         entry->dma_len[0] = buf[0].len;
 255
 256                         ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
 257                         if (i < nbufs - 1) {
 258                                 entry->dma_addr[1] = buf[1].addr;
 259                                 entry->dma_len[1] = buf[1].len;
 260                                 buf1 = buf[1].addr;
 261                                 ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
 262                                 if (buf[1].skip_unmap)
 263                                         entry->skip_buf1 = true;
 264                         }
 265
 266                         if (i == nbufs - 1)
 267                                 ctrl |= MT_DMA_CTL_LAST_SEC0;
 268                         else if (i == nbufs - 2)
 269                                 ctrl |= MT_DMA_CTL_LAST_SEC1;
 270                 }
 271
 272                 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
 273                 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
 274                 WRITE_ONCE(desc->info, cpu_to_le32(info));
 275                 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl));
 276
 277                 q->head = next;
 278                 q->queued++;
 279         }
 280
 281         q->entry[idx].txwi = txwi;
 282         q->entry[idx].skb = skb;
 283         q->entry[idx].wcid = 0xffff;
 284
 285         return idx;
 286 }
 287
 288 static void
 289 mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx,
 290                         struct mt76_queue_entry *prev_e)
 291 {
 292         struct mt76_queue_entry *e = &q->entry[idx];
 293
 294         if (!e->skip_buf0)
 295                 dma_unmap_single(dev->dma_dev, e->dma_addr[0], e->dma_len[0],
 296                                  DMA_TO_DEVICE);
 297
 298         if (!e->skip_buf1)
 299                 dma_unmap_single(dev->dma_dev, e->dma_addr[1], e->dma_len[1],
 300                                  DMA_TO_DEVICE);
 301
 302         if (e->txwi == DMA_DUMMY_DATA)
 303                 e->txwi = NULL;
 304
 305         if (e->skb == DMA_DUMMY_DATA)
 306                 e->skb = NULL;
 307
 308         *prev_e = *e;
 309         memset(e, 0, sizeof(*e));
 310 }
 311
 312 static void
 313 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q)
 314 {
 315         wmb();
 316         Q_WRITE(dev, q, cpu_idx, q->head);
 317 }
 318
 319 static void
 320 mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
 321 {
 322         struct mt76_queue_entry entry;
 323         int last;
 324
 325         if (!q || !q->ndesc)
 326                 return;
 327
 328         spin_lock_bh(&q->cleanup_lock);
 329         if (flush)
 330                 last = -1;
 331         else
 332                 last = Q_READ(dev, q, dma_idx);
 333
 334         while (q->queued > 0 && q->tail != last) {
 335                 mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry);
 336                 mt76_queue_tx_complete(dev, q, &entry);
 337
 338                 if (entry.txwi) {
 339                         if (!(dev->drv->drv_flags & MT_DRV_TXWI_NO_FREE))
 340                                 mt76_put_txwi(dev, entry.txwi);
 341                 }
 342
 343                 if (!flush && q->tail == last)
 344                         last = Q_READ(dev, q, dma_idx);
 345         }
 346         spin_unlock_bh(&q->cleanup_lock);
 347
 348         if (flush) {
 349                 spin_lock_bh(&q->lock);
 350                 mt76_dma_sync_idx(dev, q);
 351                 mt76_dma_kick_queue(dev, q);
 352                 spin_unlock_bh(&q->lock);
 353         }
 354
 355         if (!q->queued)
 356                 wake_up(&dev->tx_wait);
 357 }
 358
 359 static void *
 360 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
 361                  int *len, u32 *info, bool *more, bool *drop)
 362 {
 363         struct mt76_queue_entry *e = &q->entry[idx];
 364         struct mt76_desc *desc = &q->desc[idx];
 365         void *buf;
 366
 367         if (len) {
 368                 u32 ctrl = le32_to_cpu(READ_ONCE(desc->ctrl));
 369                 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctrl);
 370                 *more = !(ctrl & MT_DMA_CTL_LAST_SEC0);
 371         }
 372
 373         if (info)
 374                 *info = le32_to_cpu(desc->info);
 375
 376         if ((q->flags & MT_QFLAG_WED) &&
 377             FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX) {
 378                 u32 token = FIELD_GET(MT_DMA_CTL_TOKEN,
 379                                       le32_to_cpu(desc->buf1));
 380                 struct mt76_txwi_cache *t = mt76_rx_token_release(dev, token);
 381
 382                 if (!t)
 383                         return NULL;
 384
 385                 dma_unmap_single(dev->dma_dev, t->dma_addr,
 386                                  SKB_WITH_OVERHEAD(q->buf_size),
 387                                  DMA_FROM_DEVICE);
 388
 389                 buf = t->ptr;
 390                 t->dma_addr = 0;
 391                 t->ptr = NULL;
 392
 393                 mt76_put_rxwi(dev, t);
 394
 395                 if (drop) {
 396                         u32 ctrl = le32_to_cpu(READ_ONCE(desc->ctrl));
 397
 398                         *drop = !!(ctrl & (MT_DMA_CTL_TO_HOST_A |
 399                                            MT_DMA_CTL_DROP));
 400                 }
 401         } else {
 402                 buf = e->buf;
 403                 e->buf = NULL;
 404                 dma_unmap_single(dev->dma_dev, e->dma_addr[0],
 405                                  SKB_WITH_OVERHEAD(q->buf_size),
 406                                  DMA_FROM_DEVICE);
 407         }
 408
 409         return buf;
 410 }
 411
 412 static void *
 413 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
 414                  int *len, u32 *info, bool *more, bool *drop)
 415 {
 416         int idx = q->tail;
 417
 418         *more = false;
 419         if (!q->queued)
 420                 return NULL;
 421
 422         if (flush)
 423                 q->desc[idx].ctrl |= cpu_to_le32(MT_DMA_CTL_DMA_DONE);
 424         else if (!(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE)))
 425                 return NULL;
 426
 427         q->tail = (q->tail + 1) % q->ndesc;
 428         q->queued--;
 429
 430         return mt76_dma_get_buf(dev, q, idx, len, info, more, drop);
 431 }
 432
 433 static int
 434 mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q,
 435                           struct sk_buff *skb, u32 tx_info)
 436 {
 437         struct mt76_queue_buf buf = {};
 438         dma_addr_t addr;
 439
 440         if (q->queued + 1 >= q->ndesc - 1)
 441                 goto error;
 442
 443         addr = dma_map_single(dev->dma_dev, skb->data, skb->len,
 444                               DMA_TO_DEVICE);
 445         if (unlikely(dma_mapping_error(dev->dma_dev, addr)))
 446                 goto error;
 447
 448         buf.addr = addr;
 449         buf.len = skb->len;
 450
 451         spin_lock_bh(&q->lock);
 452         mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
 453         mt76_dma_kick_queue(dev, q);
 454         spin_unlock_bh(&q->lock);
 455
 456         return 0;
 457
 458 error:
 459         dev_kfree_skb(skb);
 460         return -ENOMEM;
 461 }
 462
 463 static int
 464 mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
 465                       enum mt76_txq_id qid, struct sk_buff *skb,
 466                       struct mt76_wcid *wcid, struct ieee80211_sta *sta)
 467 {
 468         struct ieee80211_tx_status status = {
 469                 .sta = sta,
 470         };
 471         struct mt76_tx_info tx_info = {
 472                 .skb = skb,
 473         };
 474         struct ieee80211_hw *hw;
 475         int len, n = 0, ret = -ENOMEM;
 476         struct mt76_txwi_cache *t;
 477         struct sk_buff *iter;
 478         dma_addr_t addr;
 479         u8 *txwi;
 480
 481         t = mt76_get_txwi(dev);
 482         if (!t)
 483                 goto free_skb;
 484
 485         txwi = mt76_get_txwi_ptr(dev, t);
 486
 487         skb->prev = skb->next = NULL;
 488         if (dev->drv->drv_flags & MT_DRV_TX_ALIGNED4_SKBS)
 489                 mt76_insert_hdr_pad(skb);
 490
 491         len = skb_headlen(skb);
 492         addr = dma_map_single(dev->dma_dev, skb->data, len, DMA_TO_DEVICE);
 493         if (unlikely(dma_mapping_error(dev->dma_dev, addr)))
 494                 goto free;
 495
 496         tx_info.buf[n].addr = t->dma_addr;
 497         tx_info.buf[n++].len = dev->drv->txwi_size;
 498         tx_info.buf[n].addr = addr;
 499         tx_info.buf[n++].len = len;
 500
 501         skb_walk_frags(skb, iter) {
 502                 if (n == ARRAY_SIZE(tx_info.buf))
 503                         goto unmap;
 504
 505                 addr = dma_map_single(dev->dma_dev, iter->data, iter->len,
 506                                       DMA_TO_DEVICE);
 507                 if (unlikely(dma_mapping_error(dev->dma_dev, addr)))
 508                         goto unmap;
 509
 510                 tx_info.buf[n].addr = addr;
 511                 tx_info.buf[n++].len = iter->len;
 512         }
 513         tx_info.nbuf = n;
 514
 515         if (q->queued + (tx_info.nbuf + 1) / 2 >= q->ndesc - 1) {
 516                 ret = -ENOMEM;
 517                 goto unmap;
 518         }
 519
 520         dma_sync_single_for_cpu(dev->dma_dev, t->dma_addr, dev->drv->txwi_size,
 521                                 DMA_TO_DEVICE);
 522         ret = dev->drv->tx_prepare_skb(dev, txwi, qid, wcid, sta, &tx_info);
 523         dma_sync_single_for_device(dev->dma_dev, t->dma_addr, dev->drv->txwi_size,
 524                                    DMA_TO_DEVICE);
 525         if (ret < 0)
 526                 goto unmap;
 527
 528         return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf,
 529                                 tx_info.info, tx_info.skb, t);
 530
 531 unmap:
 532         for (n--; n > 0; n--)
 533                 dma_unmap_single(dev->dma_dev, tx_info.buf[n].addr,
 534                                  tx_info.buf[n].len, DMA_TO_DEVICE);
 535
 536 free:
 537 #ifdef CONFIG_NL80211_TESTMODE
 538         /* fix tx_done accounting on queue overflow */
 539         if (mt76_is_testmode_skb(dev, skb, &hw)) {
 540                 struct mt76_phy *phy = hw->priv;
 541
 542                 if (tx_info.skb == phy->test.tx_skb)
 543                         phy->test.tx_done--;
 544         }
 545 #endif
 546
 547         mt76_put_txwi(dev, t);
 548
 549 free_skb:
 550         status.skb = tx_info.skb;
 551         hw = mt76_tx_status_get_hw(dev, tx_info.skb);
 552         ieee80211_tx_status_ext(hw, &status);
 553
 554         return ret;
 555 }
 556
 557 static int
 558 mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
 559 {
 560         int len = SKB_WITH_OVERHEAD(q->buf_size);
 561         int frames = 0, offset = q->buf_offset;
 562         dma_addr_t addr;
 563
 564         if (!q->ndesc)
 565                 return 0;
 566
 567         spin_lock_bh(&q->lock);
 568
 569         while (q->queued < q->ndesc - 1) {
 570                 struct mt76_txwi_cache *t = NULL;
 571                 struct mt76_queue_buf qbuf;
 572                 void *buf = NULL;
 573
 574                 if ((q->flags & MT_QFLAG_WED) &&
 575                     FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX) {
 576                         t = mt76_get_rxwi(dev);
 577                         if (!t)
 578                                 break;
 579                 }
 580
 581                 buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
 582                 if (!buf)
 583                         break;
 584
 585                 addr = dma_map_single(dev->dma_dev, buf, len, DMA_FROM_DEVICE);
 586                 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) {
 587                         skb_free_frag(buf);
 588                         break;
 589                 }
 590
 591                 qbuf.addr = addr + offset;
 592                 qbuf.len = len - offset;
 593                 qbuf.skip_unmap = false;
 594                 if (mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, t) < 0) {
 595                         dma_unmap_single(dev->dma_dev, addr, len,
 596                                          DMA_FROM_DEVICE);
 597                         skb_free_frag(buf);
 598                         break;
 599                 }
 600                 frames++;
 601         }
 602
 603         if (frames)
 604                 mt76_dma_kick_queue(dev, q);
 605
 606         spin_unlock_bh(&q->lock);
 607
 608         return frames;
 609 }
 610
 611 static int
 612 mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q)
 613 {
 614 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
 615         struct mtk_wed_device *wed = &dev->mmio.wed;
 616         int ret, type, ring;
 617         u8 flags = q->flags;
 618
 619         if (!mtk_wed_device_active(wed))
 620                 q->flags &= ~MT_QFLAG_WED;
 621
 622         if (!(q->flags & MT_QFLAG_WED))
 623                 return 0;
 624
 625         type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
 626         ring = FIELD_GET(MT_QFLAG_WED_RING, q->flags);
 627
 628         switch (type) {
 629         case MT76_WED_Q_TX:
 630                 ret = mtk_wed_device_tx_ring_setup(wed, ring, q->regs, false);
 631                 if (!ret)
 632                         q->wed_regs = wed->tx_ring[ring].reg_base;
 633                 break;
 634         case MT76_WED_Q_TXFREE:
 635                 /* WED txfree queue needs ring to be initialized before setup */
 636                 q->flags = 0;
 637                 mt76_dma_queue_reset(dev, q);
 638                 mt76_dma_rx_fill(dev, q);
 639                 q->flags = flags;
 640
 641                 ret = mtk_wed_device_txfree_ring_setup(wed, q->regs);
 642                 if (!ret)
 643                         q->wed_regs = wed->txfree_ring.reg_base;
 644                 break;
 645         case MT76_WED_Q_RX:
 646                 ret = mtk_wed_device_rx_ring_setup(wed, ring, q->regs, false);
 647                 if (!ret)
 648                         q->wed_regs = wed->rx_ring[ring].reg_base;
 649                 break;
 650         default:
 651                 ret = -EINVAL;
 652         }
 653
 654         return ret;
 655 #else
 656         return 0;
 657 #endif
 658 }
 659
 660 static int
 661 mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
 662                      int idx, int n_desc, int bufsize,
 663                      u32 ring_base)
 664 {
 665         int ret, size;
 666
 667         spin_lock_init(&q->lock);
 668         spin_lock_init(&q->cleanup_lock);
 669
 670         q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE;
 671         q->ndesc = n_desc;
 672         q->buf_size = bufsize;
 673         q->hw_idx = idx;
 674
 675         size = q->ndesc * sizeof(struct mt76_desc);
 676         q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL);
 677         if (!q->desc)
 678                 return -ENOMEM;
 679
 680         size = q->ndesc * sizeof(*q->entry);
 681         q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL);
 682         if (!q->entry)
 683                 return -ENOMEM;
 684
 685         ret = mt76_dma_wed_setup(dev, q);
 686         if (ret)
 687                 return ret;
 688
 689         if (q->flags != MT_WED_Q_TXFREE)
 690                 mt76_dma_queue_reset(dev, q);
 691
 692         return 0;
 693 }
 694
 695 static void
 696 mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
 697 {
 698         struct page *page;
 699         void *buf;
 700         bool more;
 701
 702         if (!q->ndesc)
 703                 return;
 704
 705         spin_lock_bh(&q->lock);
 706         do {
 707                 buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more, NULL);
 708                 if (!buf)
 709                         break;
 710
 711                 skb_free_frag(buf);
 712         } while (1);
 713         spin_unlock_bh(&q->lock);
 714
 715         if (!q->rx_page.va)
 716                 return;
 717
 718         page = virt_to_page(q->rx_page.va);
 719         __page_frag_cache_drain(page, q->rx_page.pagecnt_bias);
 720         memset(&q->rx_page, 0, sizeof(q->rx_page));
 721 }
 722
 723 static void
 724 mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
 725 {
 726         struct mt76_queue *q = &dev->q_rx[qid];
 727         int i;
 728
 729         if (!q->ndesc)
 730                 return;
 731
 732         for (i = 0; i < q->ndesc; i++)
 733                 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE);
 734
 735         mt76_dma_rx_cleanup(dev, q);
 736         mt76_dma_sync_idx(dev, q);
 737         mt76_dma_rx_fill(dev, q);
 738
 739         if (!q->rx_head)
 740                 return;
 741
 742         dev_kfree_skb(q->rx_head);
 743         q->rx_head = NULL;
 744 }
 745
 746 static void
 747 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
 748                   int len, bool more, u32 info)
 749 {
 750         struct sk_buff *skb = q->rx_head;
 751         struct skb_shared_info *shinfo = skb_shinfo(skb);
 752         int nr_frags = shinfo->nr_frags;
 753
 754         if (nr_frags < ARRAY_SIZE(shinfo->frags)) {
 755                 struct page *page = virt_to_head_page(data);
 756                 int offset = data - page_address(page) + q->buf_offset;
 757
 758                 skb_add_rx_frag(skb, nr_frags, page, offset, len, q->buf_size);
 759         } else {
 760                 skb_free_frag(data);
 761         }
 762
 763         if (more)
 764                 return;
 765
 766         q->rx_head = NULL;
 767         if (nr_frags < ARRAY_SIZE(shinfo->frags))
 768                 dev->drv->rx_skb(dev, q - dev->q_rx, skb, &info);
 769         else
 770                 dev_kfree_skb(skb);
 771 }
 772
 773 static int
 774 mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
 775 {
 776         int len, data_len, done = 0, dma_idx;
 777         struct sk_buff *skb;
 778         unsigned char *data;
 779         bool check_ddone = false;
 780         bool more;
 781
 782         if (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) &&
 783             q->flags == MT_WED_Q_TXFREE) {
 784                 dma_idx = Q_READ(dev, q, dma_idx);
 785                 check_ddone = true;
 786         }
 787
 788         while (done < budget) {
 789                 bool drop = false;
 790                 u32 info;
 791
 792                 if (check_ddone) {
 793                         if (q->tail == dma_idx)
 794                                 dma_idx = Q_READ(dev, q, dma_idx);
 795
 796                         if (q->tail == dma_idx)
 797                                 break;
 798                 }
 799
 800                 data = mt76_dma_dequeue(dev, q, false, &len, &info, &more,
 801                                         &drop);
 802                 if (!data)
 803                         break;
 804
 805                 if (drop)
 806                         goto free_frag;
 807
 808                 if (q->rx_head)
 809                         data_len = q->buf_size;
 810                 else
 811                         data_len = SKB_WITH_OVERHEAD(q->buf_size);
 812
 813                 if (data_len < len + q->buf_offset) {
 814                         dev_kfree_skb(q->rx_head);
 815                         q->rx_head = NULL;
 816                         goto free_frag;
 817                 }
 818
 819                 if (q->rx_head) {
 820                         mt76_add_fragment(dev, q, data, len, more, info);
 821                         continue;
 822                 }
 823
 824                 if (!more && dev->drv->rx_check &&
 825                     !(dev->drv->rx_check(dev, data, len)))
 826                         goto free_frag;
 827
 828                 skb = build_skb(data, q->buf_size);
 829                 if (!skb)
 830                         goto free_frag;
 831
 832                 skb_reserve(skb, q->buf_offset);
 833
 834                 *(u32 *)skb->cb = info;
 835
 836                 __skb_put(skb, len);
 837                 done++;
 838
 839                 if (more) {
 840                         q->rx_head = skb;
 841                         continue;
 842                 }
 843
 844                 dev->drv->rx_skb(dev, q - dev->q_rx, skb, &info);
 845                 continue;
 846
 847 free_frag:
 848                 skb_free_frag(data);
 849         }
 850
 851         mt76_dma_rx_fill(dev, q);
 852         return done;
 853 }
 854
 855 int mt76_dma_rx_poll(struct napi_struct *napi, int budget)
 856 {
 857         struct mt76_dev *dev;
 858         int qid, done = 0, cur;
 859
 860         dev = container_of(napi->dev, struct mt76_dev, napi_dev);
 861         qid = napi - dev->napi;
 862
 863         rcu_read_lock();
 864
 865         do {
 866                 cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done);
 867                 mt76_rx_poll_complete(dev, qid, napi);
 868                 done += cur;
 869         } while (cur && done < budget);
 870
 871         rcu_read_unlock();
 872
 873         if (done < budget && napi_complete(napi))
 874                 dev->drv->rx_poll_complete(dev, qid);
 875
 876         return done;
 877 }
 878 EXPORT_SYMBOL_GPL(mt76_dma_rx_poll);
 879
 880 static int
 881 mt76_dma_init(struct mt76_dev *dev,
 882               int (*poll)(struct napi_struct *napi, int budget))
 883 {
 884         int i;
 885
 886         init_dummy_netdev(&dev->napi_dev);
 887         init_dummy_netdev(&dev->tx_napi_dev);
 888         snprintf(dev->napi_dev.name, sizeof(dev->napi_dev.name), "%s",
 889                  wiphy_name(dev->hw->wiphy));
 890         dev->napi_dev.threaded = 1;
 891
 892         mt76_for_each_q_rx(dev, i) {
 893                 netif_napi_add(&dev->napi_dev, &dev->napi[i], poll);
 894                 mt76_dma_rx_fill(dev, &dev->q_rx[i]);
 895                 napi_enable(&dev->napi[i]);
 896         }
 897
 898         return 0;
 899 }
 900
 901 static const struct mt76_queue_ops mt76_dma_ops = {
 902         .init = mt76_dma_init,
 903         .alloc = mt76_dma_alloc_queue,
 904         .reset_q = mt76_dma_queue_reset,
 905         .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw,
 906         .tx_queue_skb = mt76_dma_tx_queue_skb,
 907         .tx_cleanup = mt76_dma_tx_cleanup,
 908         .rx_cleanup = mt76_dma_rx_cleanup,
 909         .rx_reset = mt76_dma_rx_reset,
 910         .kick = mt76_dma_kick_queue,
 911 };
 912
 913 void mt76_dma_attach(struct mt76_dev *dev)
 914 {
 915         dev->queue_ops = &mt76_dma_ops;
 916 }
 917 EXPORT_SYMBOL_GPL(mt76_dma_attach);
 918
 919 void mt76_dma_cleanup(struct mt76_dev *dev)
 920 {
 921         int i;
 922
 923         mt76_worker_disable(&dev->tx_worker);
 924         netif_napi_del(&dev->tx_napi);
 925
 926         for (i = 0; i < ARRAY_SIZE(dev->phys); i++) {
 927                 struct mt76_phy *phy = dev->phys[i];
 928                 int j;
 929
 930                 if (!phy)
 931                         continue;
 932
 933                 for (j = 0; j < ARRAY_SIZE(phy->q_tx); j++)
 934                         mt76_dma_tx_cleanup(dev, phy->q_tx[j], true);
 935         }
 936
 937         for (i = 0; i < ARRAY_SIZE(dev->q_mcu); i++)
 938                 mt76_dma_tx_cleanup(dev, dev->q_mcu[i], true);
 939
 940         mt76_for_each_q_rx(dev, i) {
 941                 struct mt76_queue *q = &dev->q_rx[i];
 942
 943                 netif_napi_del(&dev->napi[i]);
 944                 if (FIELD_GET(MT_QFLAG_WED_TYPE, q->flags))
 945                         mt76_dma_rx_cleanup(dev, q);
 946         }
 947
 948         mt76_free_pending_txwi(dev);
 949         mt76_free_pending_rxwi(dev);
 950
 951         if (mtk_wed_device_active(&dev->mmio.wed))
 952                 mtk_wed_device_detach(&dev->mmio.wed);
 953 }
 954 EXPORT_SYMBOL_GPL(mt76_dma_cleanup);