1 /******************************************************************************
3 * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
33 #include "iwl-debug.h"
37 #include "iwl-op-mode.h"
39 /* FIXME: need to abstract out TX command (once we know what it looks like) */
40 #include "dvm/commands.h"
42 #define IWL_TX_CRC_SIZE 4
43 #define IWL_TX_DELIMITER_SIZE 4
45 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
50 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
51 * of buffer descriptors, each of which points to one or more data buffers for
52 * the device to read from or fill. Driver and device exchange status of each
53 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
54 * entries in each circular buffer, to protect against confusing empty and full
57 * The device reads or writes the data in the queues via the device's several
58 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
60 * For Tx queue, there are low mark and high mark limits. If, after queuing
61 * the packet for Tx, free space become < low mark, Tx queue stopped. When
62 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
65 ***************************************************/
66 static int iwl_queue_space(const struct iwl_queue *q)
68 int s = q->read_ptr - q->write_ptr;
70 if (q->read_ptr > q->write_ptr)
75 /* keep some reserve to not confuse empty and full situations */
83 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
85 static int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
88 q->n_window = slots_num;
91 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
92 * and iwl_queue_dec_wrap are broken. */
93 if (WARN_ON(!is_power_of_2(count)))
96 /* slots_num must be power-of-two size, otherwise
97 * get_cmd_index is broken. */
98 if (WARN_ON(!is_power_of_2(slots_num)))
101 q->low_mark = q->n_window / 4;
105 q->high_mark = q->n_window / 8;
106 if (q->high_mark < 2)
115 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
116 struct iwl_dma_ptr *ptr, size_t size)
118 if (WARN_ON(ptr->addr))
121 ptr->addr = dma_alloc_coherent(trans->dev, size,
122 &ptr->dma, GFP_KERNEL);
129 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
130 struct iwl_dma_ptr *ptr)
132 if (unlikely(!ptr->addr))
135 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
136 memset(ptr, 0, sizeof(*ptr));
139 static void iwl_pcie_txq_stuck_timer(unsigned long data)
141 struct iwl_txq *txq = (void *)data;
142 struct iwl_queue *q = &txq->q;
143 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
144 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
145 u32 scd_sram_addr = trans_pcie->scd_base_addr +
146 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
150 spin_lock(&txq->lock);
151 /* check if triggered erroneously */
152 if (txq->q.read_ptr == txq->q.write_ptr) {
153 spin_unlock(&txq->lock);
156 spin_unlock(&txq->lock);
158 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
159 jiffies_to_msecs(trans_pcie->wd_timeout));
160 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
161 txq->q.read_ptr, txq->q.write_ptr);
163 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
165 iwl_print_hex_error(trans, buf, sizeof(buf));
167 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
168 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
169 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
171 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
172 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
173 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
174 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
176 iwl_trans_read_mem32(trans,
177 trans_pcie->scd_base_addr +
178 SCD_TRANS_TBL_OFFSET_QUEUE(i));
181 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
183 tbl_dw = tbl_dw & 0x0000FFFF;
186 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
187 i, active ? "" : "in", fifo, tbl_dw,
189 SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
190 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
193 for (i = q->read_ptr; i != q->write_ptr;
194 i = iwl_queue_inc_wrap(i, q->n_bd)) {
195 struct iwl_tx_cmd *tx_cmd =
196 (struct iwl_tx_cmd *)txq->entries[i].cmd->payload;
197 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
198 get_unaligned_le32(&tx_cmd->scratch));
201 iwl_op_mode_nic_error(trans->op_mode);
205 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
207 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
208 struct iwl_txq *txq, u16 byte_cnt)
210 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
211 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
212 int write_ptr = txq->q.write_ptr;
213 int txq_id = txq->q.id;
216 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
218 struct iwl_tx_cmd *tx_cmd =
219 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
221 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
223 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
225 sta_id = tx_cmd->sta_id;
226 sec_ctl = tx_cmd->sec_ctl;
228 switch (sec_ctl & TX_CMD_SEC_MSK) {
232 case TX_CMD_SEC_TKIP:
236 len += WEP_IV_LEN + WEP_ICV_LEN;
240 if (trans_pcie->bc_table_dword)
241 len = DIV_ROUND_UP(len, 4);
243 bc_ent = cpu_to_le16(len | (sta_id << 12));
245 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
247 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
249 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
252 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
255 struct iwl_trans_pcie *trans_pcie =
256 IWL_TRANS_GET_PCIE_TRANS(trans);
257 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
258 int txq_id = txq->q.id;
259 int read_ptr = txq->q.read_ptr;
262 struct iwl_tx_cmd *tx_cmd =
263 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
265 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
267 if (txq_id != trans_pcie->cmd_queue)
268 sta_id = tx_cmd->sta_id;
270 bc_ent = cpu_to_le16(1 | (sta_id << 12));
271 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
273 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
275 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
279 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
281 void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq)
284 int txq_id = txq->q.id;
286 if (txq->need_update == 0)
289 if (trans->cfg->base_params->shadow_reg_enable) {
290 /* shadow register enabled */
291 iwl_write32(trans, HBUS_TARG_WRPTR,
292 txq->q.write_ptr | (txq_id << 8));
294 struct iwl_trans_pcie *trans_pcie =
295 IWL_TRANS_GET_PCIE_TRANS(trans);
296 /* if we're trying to save power */
297 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
298 /* wake up nic if it's powered down ...
299 * uCode will wake up, and interrupt us again, so next
300 * time we'll skip this part. */
301 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
303 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
304 IWL_DEBUG_INFO(trans,
305 "Tx queue %d requesting wakeup,"
306 " GP1 = 0x%x\n", txq_id, reg);
307 iwl_set_bit(trans, CSR_GP_CNTRL,
308 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
312 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id,
315 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
316 txq->q.write_ptr | (txq_id << 8));
319 * else not in power-save mode,
320 * uCode will never sleep when we're
321 * trying to tx (during RFKILL, we're not trying to tx).
324 iwl_write32(trans, HBUS_TARG_WRPTR,
325 txq->q.write_ptr | (txq_id << 8));
327 txq->need_update = 0;
330 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
332 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
334 dma_addr_t addr = get_unaligned_le32(&tb->lo);
335 if (sizeof(dma_addr_t) > sizeof(u32))
337 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
342 static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
344 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
346 return le16_to_cpu(tb->hi_n_len) >> 4;
349 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
350 dma_addr_t addr, u16 len)
352 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
353 u16 hi_n_len = len << 4;
355 put_unaligned_le32(addr, &tb->lo);
356 if (sizeof(dma_addr_t) > sizeof(u32))
357 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
359 tb->hi_n_len = cpu_to_le16(hi_n_len);
361 tfd->num_tbs = idx + 1;
364 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
366 return tfd->num_tbs & 0x1f;
369 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
370 struct iwl_cmd_meta *meta, struct iwl_tfd *tfd,
371 enum dma_data_direction dma_dir)
376 /* Sanity check on number of chunks */
377 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
379 if (num_tbs >= IWL_NUM_OF_TBS) {
380 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
381 /* @todo issue fatal error, it is quite serious situation */
387 dma_unmap_single(trans->dev,
388 dma_unmap_addr(meta, mapping),
389 dma_unmap_len(meta, len),
392 /* Unmap chunks, if any. */
393 for (i = 1; i < num_tbs; i++)
394 dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i),
395 iwl_pcie_tfd_tb_get_len(tfd, i), dma_dir);
401 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
402 * @trans - transport private data
404 * @dma_dir - the direction of the DMA mapping
406 * Does NOT advance any TFD circular buffer read/write indexes
407 * Does NOT free the TFD itself (which is within circular buffer)
409 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
410 enum dma_data_direction dma_dir)
412 struct iwl_tfd *tfd_tmp = txq->tfds;
414 /* rd_ptr is bounded by n_bd and idx is bounded by n_window */
415 int rd_ptr = txq->q.read_ptr;
416 int idx = get_cmd_index(&txq->q, rd_ptr);
418 lockdep_assert_held(&txq->lock);
420 /* We have only q->n_window txq->entries, but we use q->n_bd tfds */
421 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr],
428 skb = txq->entries[idx].skb;
430 /* Can be called from irqs-disabled context
431 * If skb is not NULL, it means that the whole queue is being
432 * freed and that the queue is not empty - free the skb
435 iwl_op_mode_free_skb(trans->op_mode, skb);
436 txq->entries[idx].skb = NULL;
441 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
442 dma_addr_t addr, u16 len, u8 reset)
445 struct iwl_tfd *tfd, *tfd_tmp;
450 tfd = &tfd_tmp[q->write_ptr];
453 memset(tfd, 0, sizeof(*tfd));
455 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
457 /* Each TFD can point to a maximum 20 Tx buffers */
458 if (num_tbs >= IWL_NUM_OF_TBS) {
459 IWL_ERR(trans, "Error can not send more than %d chunks\n",
464 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
467 if (unlikely(addr & ~IWL_TX_DMA_MASK))
468 IWL_ERR(trans, "Unaligned address = %llx\n",
469 (unsigned long long)addr);
471 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
476 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
477 struct iwl_txq *txq, int slots_num,
480 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
481 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
484 if (WARN_ON(txq->entries || txq->tfds))
487 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
489 txq->trans_pcie = trans_pcie;
491 txq->q.n_window = slots_num;
493 txq->entries = kcalloc(slots_num,
494 sizeof(struct iwl_pcie_txq_entry),
500 if (txq_id == trans_pcie->cmd_queue)
501 for (i = 0; i < slots_num; i++) {
502 txq->entries[i].cmd =
503 kmalloc(sizeof(struct iwl_device_cmd),
505 if (!txq->entries[i].cmd)
509 /* Circular buffer of transmit frame descriptors (TFDs),
510 * shared with device */
511 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
512 &txq->q.dma_addr, GFP_KERNEL);
514 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
521 if (txq->entries && txq_id == trans_pcie->cmd_queue)
522 for (i = 0; i < slots_num; i++)
523 kfree(txq->entries[i].cmd);
531 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
532 int slots_num, u32 txq_id)
536 txq->need_update = 0;
538 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
539 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
540 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
542 /* Initialize queue's high/low-water marks, and head/tail indexes */
543 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
548 spin_lock_init(&txq->lock);
551 * Tell nic where to find circular buffer of Tx Frame Descriptors for
552 * given Tx queue, and enable the DMA channel used for that queue.
553 * Circular buffer (TFD queue in DRAM) physical base address */
554 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
555 txq->q.dma_addr >> 8);
561 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
563 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
565 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
566 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
567 struct iwl_queue *q = &txq->q;
568 enum dma_data_direction dma_dir;
573 /* In the command queue, all the TBs are mapped as BIDI
574 * so unmap them as such.
576 if (txq_id == trans_pcie->cmd_queue)
577 dma_dir = DMA_BIDIRECTIONAL;
579 dma_dir = DMA_TO_DEVICE;
581 spin_lock_bh(&txq->lock);
582 while (q->write_ptr != q->read_ptr) {
583 iwl_pcie_txq_free_tfd(trans, txq, dma_dir);
584 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
586 spin_unlock_bh(&txq->lock);
590 * iwl_pcie_txq_free - Deallocate DMA queue.
591 * @txq: Transmit queue to deallocate.
593 * Empty queue by removing and destroying all BD's.
595 * 0-fill, but do not free "txq" descriptor structure.
597 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
599 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
600 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
601 struct device *dev = trans->dev;
607 iwl_pcie_txq_unmap(trans, txq_id);
609 /* De-alloc array of command/tx buffers */
610 if (txq_id == trans_pcie->cmd_queue)
611 for (i = 0; i < txq->q.n_window; i++) {
612 kfree(txq->entries[i].cmd);
613 kfree(txq->entries[i].copy_cmd);
614 kfree(txq->entries[i].free_buf);
617 /* De-alloc circular buffer of TFDs */
619 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
620 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
627 del_timer_sync(&txq->stuck_timer);
629 /* 0-fill queue descriptor structure */
630 memset(txq, 0, sizeof(*txq));
634 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
636 static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask)
638 struct iwl_trans_pcie __maybe_unused *trans_pcie =
639 IWL_TRANS_GET_PCIE_TRANS(trans);
641 iwl_write_prph(trans, SCD_TXFACT, mask);
644 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
646 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
647 int nq = trans->cfg->base_params->num_of_queues;
650 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
651 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
653 /* make sure all queue are not stopped/used */
654 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
655 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
657 trans_pcie->scd_base_addr =
658 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
660 WARN_ON(scd_base_addr != 0 &&
661 scd_base_addr != trans_pcie->scd_base_addr);
663 /* reset context data, TX status and translation data */
664 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
665 SCD_CONTEXT_MEM_LOWER_BOUND,
668 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
669 trans_pcie->scd_bc_tbls.dma >> 10);
671 /* The chain extension of the SCD doesn't work well. This feature is
672 * enabled by default by the HW, so we need to disable it manually.
674 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
676 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
677 trans_pcie->cmd_fifo);
679 /* Activate all Tx DMA/FIFO channels */
680 iwl_pcie_txq_set_sched(trans, IWL_MASK(0, 7));
682 /* Enable DMA channel */
683 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
684 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
685 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
686 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
688 /* Update FH chicken bits */
689 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
690 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
691 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
693 /* Enable L1-Active */
694 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
695 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
698 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
700 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
703 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
705 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
707 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
708 txq->q.dma_addr >> 8);
709 iwl_pcie_txq_unmap(trans, txq_id);
711 txq->q.write_ptr = 0;
714 /* Tell NIC where to find the "keep warm" buffer */
715 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
716 trans_pcie->kw.dma >> 4);
718 iwl_pcie_tx_start(trans, trans_pcie->scd_base_addr);
722 * iwl_pcie_tx_stop - Stop all Tx DMA channels
724 int iwl_pcie_tx_stop(struct iwl_trans *trans)
726 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
730 /* Turn off all Tx DMA fifos */
731 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
733 iwl_pcie_txq_set_sched(trans, 0);
735 /* Stop each Tx DMA channel, and wait for it to be idle */
736 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
737 iwl_write_direct32(trans,
738 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
739 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
740 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
743 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
745 iwl_read_direct32(trans,
746 FH_TSSR_TX_STATUS_REG));
748 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
750 if (!trans_pcie->txq) {
752 "Stopping tx queues that aren't allocated...\n");
756 /* Unmap DMA from host system and free skb's */
757 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
759 iwl_pcie_txq_unmap(trans, txq_id);
765 * iwl_trans_tx_free - Free TXQ Context
767 * Destroy all TX DMA queues and structures
769 void iwl_pcie_tx_free(struct iwl_trans *trans)
772 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
775 if (trans_pcie->txq) {
777 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
778 iwl_pcie_txq_free(trans, txq_id);
781 kfree(trans_pcie->txq);
782 trans_pcie->txq = NULL;
784 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
786 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
790 * iwl_pcie_tx_alloc - allocate TX context
791 * Allocate all Tx DMA structures and initialize them
793 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
796 int txq_id, slots_num;
797 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
799 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
800 sizeof(struct iwlagn_scd_bc_tbl);
802 /*It is not allowed to alloc twice, so warn when this happens.
803 * We cannot rely on the previous allocation, so free and fail */
804 if (WARN_ON(trans_pcie->txq)) {
809 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
812 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
816 /* Alloc keep-warm buffer */
817 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
819 IWL_ERR(trans, "Keep Warm allocation failed\n");
823 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
824 sizeof(struct iwl_txq), GFP_KERNEL);
825 if (!trans_pcie->txq) {
826 IWL_ERR(trans, "Not enough memory for txq\n");
831 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
832 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
834 slots_num = (txq_id == trans_pcie->cmd_queue) ?
835 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
836 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
839 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
847 iwl_pcie_tx_free(trans);
851 int iwl_pcie_tx_init(struct iwl_trans *trans)
853 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
855 int txq_id, slots_num;
859 if (!trans_pcie->txq) {
860 ret = iwl_pcie_tx_alloc(trans);
866 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
868 /* Turn off all Tx DMA fifos */
869 iwl_write_prph(trans, SCD_TXFACT, 0);
871 /* Tell NIC where to find the "keep warm" buffer */
872 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
873 trans_pcie->kw.dma >> 4);
875 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
877 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
878 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
880 slots_num = (txq_id == trans_pcie->cmd_queue) ?
881 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
882 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
885 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
892 /*Upon error, free only if we allocated something */
894 iwl_pcie_tx_free(trans);
898 static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie,
901 if (!trans_pcie->wd_timeout)
905 * if empty delete timer, otherwise move timer forward
906 * since we're making progress on this queue
908 if (txq->q.read_ptr == txq->q.write_ptr)
909 del_timer(&txq->stuck_timer);
911 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
914 /* Frees buffers until index _not_ inclusive */
915 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
916 struct sk_buff_head *skbs)
918 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
919 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
920 /* n_bd is usually 256 => n_bd - 1 = 0xff */
921 int tfd_num = ssn & (txq->q.n_bd - 1);
922 struct iwl_queue *q = &txq->q;
925 /* This function is not meant to release cmd queue*/
926 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
929 spin_lock_bh(&txq->lock);
931 if (txq->q.read_ptr == tfd_num)
934 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
935 txq_id, txq->q.read_ptr, tfd_num, ssn);
937 /*Since we free until index _not_ inclusive, the one before index is
938 * the last we will free. This one must be used */
939 last_to_free = iwl_queue_dec_wrap(tfd_num, q->n_bd);
941 if (!iwl_queue_used(q, last_to_free)) {
943 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
944 __func__, txq_id, last_to_free, q->n_bd,
945 q->write_ptr, q->read_ptr);
949 if (WARN_ON(!skb_queue_empty(skbs)))
953 q->read_ptr != tfd_num;
954 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
956 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
959 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
961 txq->entries[txq->q.read_ptr].skb = NULL;
963 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
965 iwl_pcie_txq_free_tfd(trans, txq, DMA_TO_DEVICE);
968 iwl_pcie_txq_progress(trans_pcie, txq);
970 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
971 iwl_wake_queue(trans, txq);
973 spin_unlock_bh(&txq->lock);
977 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
979 * When FW advances 'R' index, all entries between old and new 'R' index
980 * need to be reclaimed. As result, some free space forms. If there is
981 * enough free space (> low mark), wake the stack that feeds us.
983 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
985 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
986 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
987 struct iwl_queue *q = &txq->q;
990 lockdep_assert_held(&txq->lock);
992 if ((idx >= q->n_bd) || (!iwl_queue_used(q, idx))) {
994 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
995 __func__, txq_id, idx, q->n_bd,
996 q->write_ptr, q->read_ptr);
1000 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1001 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1004 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1005 idx, q->write_ptr, q->read_ptr);
1006 iwl_op_mode_nic_error(trans->op_mode);
1010 iwl_pcie_txq_progress(trans_pcie, txq);
1013 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1016 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1021 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1023 tbl_dw_addr = trans_pcie->scd_base_addr +
1024 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1026 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1029 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1031 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1033 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1038 static inline void iwl_pcie_txq_set_inactive(struct iwl_trans *trans,
1041 /* Simply stop the queue, but don't change any configuration;
1042 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1043 iwl_write_prph(trans,
1044 SCD_QUEUE_STATUS_BITS(txq_id),
1045 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1046 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1049 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
1050 int sta_id, int tid, int frame_limit, u16 ssn)
1052 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1054 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1055 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1057 /* Stop this Tx queue before configuring it */
1058 iwl_pcie_txq_set_inactive(trans, txq_id);
1060 /* Set this queue as a chain-building queue unless it is CMD queue */
1061 if (txq_id != trans_pcie->cmd_queue)
1062 iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));
1064 /* If this queue is mapped to a certain station: it is an AGG queue */
1065 if (sta_id != IWL_INVALID_STATION) {
1066 u16 ra_tid = BUILD_RAxTID(sta_id, tid);
1068 /* Map receiver-address / traffic-ID to this queue */
1069 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1071 /* enable aggregations for the queue */
1072 iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
1075 * disable aggregations for the queue, this will also make the
1076 * ra_tid mapping configuration irrelevant since it is now a
1079 iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
1082 /* Place first TFD at index corresponding to start sequence number.
1083 * Assumes that ssn_idx is valid (!= 0xFFF) */
1084 trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
1085 trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
1087 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1088 (ssn & 0xff) | (txq_id << 8));
1089 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1091 /* Set up Tx window size and frame limit for this queue */
1092 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1093 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1094 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1095 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1096 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1097 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1098 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1099 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1101 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1102 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1103 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1104 (fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1105 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1106 SCD_QUEUE_STTS_REG_MSK);
1107 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n",
1108 txq_id, fifo, ssn & 0xff);
1111 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id)
1113 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1114 u32 stts_addr = trans_pcie->scd_base_addr +
1115 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1116 static const u32 zero_val[4] = {};
1118 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1119 WARN_ONCE(1, "queue %d not used", txq_id);
1123 iwl_pcie_txq_set_inactive(trans, txq_id);
1125 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1126 ARRAY_SIZE(zero_val));
1128 iwl_pcie_txq_unmap(trans, txq_id);
1130 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1133 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1136 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1137 * @priv: device private data point
1138 * @cmd: a point to the ucode command structure
1140 * The function returns < 0 values to indicate the operation is
1141 * failed. On success, it turns the index (> 0) of command in the
1144 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1145 struct iwl_host_cmd *cmd)
1147 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1148 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1149 struct iwl_queue *q = &txq->q;
1150 struct iwl_device_cmd *out_cmd;
1151 struct iwl_cmd_meta *out_meta;
1152 void *dup_buf = NULL;
1153 dma_addr_t phys_addr;
1155 u16 copy_size, cmd_size;
1156 bool had_nocopy = false;
1160 copy_size = sizeof(out_cmd->hdr);
1161 cmd_size = sizeof(out_cmd->hdr);
1163 /* need one for the header if the first is NOCOPY */
1164 BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
1166 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
1169 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1171 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1175 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1177 * This is also a chunk that isn't copied
1178 * to the static buffer so set had_nocopy.
1182 /* only allowed once */
1183 if (WARN_ON(dup_buf)) {
1188 dup_buf = kmemdup(cmd->data[i], cmd->len[i],
1193 /* NOCOPY must not be followed by normal! */
1194 if (WARN_ON(had_nocopy)) {
1198 copy_size += cmd->len[i];
1200 cmd_size += cmd->len[i];
1204 * If any of the command structures end up being larger than
1205 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1206 * allocated into separate TFDs, then we will need to
1207 * increase the size of the buffers.
1209 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1210 "Command %s (%#x) is too large (%d bytes)\n",
1211 get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) {
1216 spin_lock_bh(&txq->lock);
1218 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1219 spin_unlock_bh(&txq->lock);
1221 IWL_ERR(trans, "No space in command queue\n");
1222 iwl_op_mode_cmd_queue_full(trans->op_mode);
1227 idx = get_cmd_index(q, q->write_ptr);
1228 out_cmd = txq->entries[idx].cmd;
1229 out_meta = &txq->entries[idx].meta;
1231 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1232 if (cmd->flags & CMD_WANT_SKB)
1233 out_meta->source = cmd;
1235 /* set up the header */
1237 out_cmd->hdr.cmd = cmd->id;
1238 out_cmd->hdr.flags = 0;
1239 out_cmd->hdr.sequence =
1240 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1241 INDEX_TO_SEQ(q->write_ptr));
1243 /* and copy the data that needs to be copied */
1244 cmd_pos = offsetof(struct iwl_device_cmd, payload);
1245 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
1248 if (cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1251 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], cmd->len[i]);
1252 cmd_pos += cmd->len[i];
1255 WARN_ON_ONCE(txq->entries[idx].copy_cmd);
1258 * since out_cmd will be the source address of the FH, it will write
1259 * the retry count there. So when the user needs to receivce the HCMD
1260 * that corresponds to the response in the response handler, it needs
1261 * to set CMD_WANT_HCMD.
1263 if (cmd->flags & CMD_WANT_HCMD) {
1264 txq->entries[idx].copy_cmd =
1265 kmemdup(out_cmd, cmd_pos, GFP_ATOMIC);
1266 if (unlikely(!txq->entries[idx].copy_cmd)) {
1273 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1274 get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
1275 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1276 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1278 phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size,
1280 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1285 dma_unmap_addr_set(out_meta, mapping, phys_addr);
1286 dma_unmap_len_set(out_meta, len, copy_size);
1288 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, copy_size, 1);
1290 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
1291 const void *data = cmd->data[i];
1295 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1298 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1300 phys_addr = dma_map_single(trans->dev, (void *)data,
1301 cmd->len[i], DMA_BIDIRECTIONAL);
1302 if (dma_mapping_error(trans->dev, phys_addr)) {
1303 iwl_pcie_tfd_unmap(trans, out_meta,
1304 &txq->tfds[q->write_ptr],
1310 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmd->len[i], 0);
1313 out_meta->flags = cmd->flags;
1314 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1315 kfree(txq->entries[idx].free_buf);
1316 txq->entries[idx].free_buf = dup_buf;
1318 txq->need_update = 1;
1320 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size,
1321 &out_cmd->hdr, copy_size);
1323 /* start timer if queue currently empty */
1324 if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
1325 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1327 /* Increment and update queue's write index */
1328 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1329 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1332 spin_unlock_bh(&txq->lock);
1340 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1341 * @rxb: Rx buffer to reclaim
1342 * @handler_status: return value of the handler of the command
1343 * (put in setup_rx_handlers)
1345 * If an Rx buffer has an async callback associated with it the callback
1346 * will be executed. The attached skb (if present) will only be freed
1347 * if the callback returns 1
1349 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1350 struct iwl_rx_cmd_buffer *rxb, int handler_status)
1352 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1353 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1354 int txq_id = SEQ_TO_QUEUE(sequence);
1355 int index = SEQ_TO_INDEX(sequence);
1357 struct iwl_device_cmd *cmd;
1358 struct iwl_cmd_meta *meta;
1359 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1360 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1362 /* If a Tx command is being handled and it isn't in the actual
1363 * command queue then there a command routing bug has been introduced
1364 * in the queue management code. */
1365 if (WARN(txq_id != trans_pcie->cmd_queue,
1366 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1367 txq_id, trans_pcie->cmd_queue, sequence,
1368 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1369 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1370 iwl_print_hex_error(trans, pkt, 32);
1374 spin_lock_bh(&txq->lock);
1376 cmd_index = get_cmd_index(&txq->q, index);
1377 cmd = txq->entries[cmd_index].cmd;
1378 meta = &txq->entries[cmd_index].meta;
1380 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index], DMA_BIDIRECTIONAL);
1382 /* Input error checking is done when commands are added to queue. */
1383 if (meta->flags & CMD_WANT_SKB) {
1384 struct page *p = rxb_steal_page(rxb);
1386 meta->source->resp_pkt = pkt;
1387 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1388 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1389 meta->source->handler_status = handler_status;
1392 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1394 if (!(meta->flags & CMD_ASYNC)) {
1395 if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
1397 "HCMD_ACTIVE already clear for command %s\n",
1398 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1400 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1401 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1402 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1403 wake_up(&trans_pcie->wait_command_queue);
1408 spin_unlock_bh(&txq->lock);
1411 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1413 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1414 struct iwl_host_cmd *cmd)
1416 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1419 /* An asynchronous command can not expect an SKB to be set. */
1420 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1423 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1426 "Error sending %s: enqueue_hcmd failed: %d\n",
1427 get_cmd_string(trans_pcie, cmd->id), ret);
1433 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1434 struct iwl_host_cmd *cmd)
1436 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1440 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1441 get_cmd_string(trans_pcie, cmd->id));
1443 if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE,
1444 &trans_pcie->status))) {
1445 IWL_ERR(trans, "Command %s: a command is already active!\n",
1446 get_cmd_string(trans_pcie, cmd->id));
1450 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1451 get_cmd_string(trans_pcie, cmd->id));
1453 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1456 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1458 "Error sending %s: enqueue_hcmd failed: %d\n",
1459 get_cmd_string(trans_pcie, cmd->id), ret);
1463 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1464 !test_bit(STATUS_HCMD_ACTIVE,
1465 &trans_pcie->status),
1466 HOST_COMPLETE_TIMEOUT);
1468 if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
1469 struct iwl_txq *txq =
1470 &trans_pcie->txq[trans_pcie->cmd_queue];
1471 struct iwl_queue *q = &txq->q;
1474 "Error sending %s: time out after %dms.\n",
1475 get_cmd_string(trans_pcie, cmd->id),
1476 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1479 "Current CMD queue read_ptr %d write_ptr %d\n",
1480 q->read_ptr, q->write_ptr);
1482 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1483 IWL_DEBUG_INFO(trans,
1484 "Clearing HCMD_ACTIVE for command %s\n",
1485 get_cmd_string(trans_pcie, cmd->id));
1491 if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) {
1492 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1493 get_cmd_string(trans_pcie, cmd->id));
1498 if (test_bit(STATUS_RFKILL, &trans_pcie->status)) {
1499 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1504 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1505 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1506 get_cmd_string(trans_pcie, cmd->id));
1514 if (cmd->flags & CMD_WANT_SKB) {
1516 * Cancel the CMD_WANT_SKB flag for the cmd in the
1517 * TX cmd queue. Otherwise in case the cmd comes
1518 * in later, it will possibly set an invalid
1519 * address (cmd->meta.source).
1521 trans_pcie->txq[trans_pcie->cmd_queue].
1522 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1525 if (cmd->resp_pkt) {
1527 cmd->resp_pkt = NULL;
1533 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1535 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1537 if (test_bit(STATUS_FW_ERROR, &trans_pcie->status))
1540 if (test_bit(STATUS_RFKILL, &trans_pcie->status))
1543 if (cmd->flags & CMD_ASYNC)
1544 return iwl_pcie_send_hcmd_async(trans, cmd);
1546 /* We still can fail on RFKILL that can be asserted while we wait */
1547 return iwl_pcie_send_hcmd_sync(trans, cmd);
1550 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1551 struct iwl_device_cmd *dev_cmd, int txq_id)
1553 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1554 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1555 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1556 struct iwl_cmd_meta *out_meta;
1557 struct iwl_txq *txq;
1558 struct iwl_queue *q;
1559 dma_addr_t phys_addr = 0;
1560 dma_addr_t txcmd_phys;
1561 dma_addr_t scratch_phys;
1562 u16 len, firstlen, secondlen;
1563 u8 wait_write_ptr = 0;
1564 __le16 fc = hdr->frame_control;
1565 u8 hdr_len = ieee80211_hdrlen(fc);
1566 u16 __maybe_unused wifi_seq;
1568 txq = &trans_pcie->txq[txq_id];
1571 if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1576 spin_lock(&txq->lock);
1578 /* In AGG mode, the index in the ring must correspond to the WiFi
1579 * sequence number. This is a HW requirements to help the SCD to parse
1581 * Check here that the packets are in the right place on the ring.
1583 #ifdef CONFIG_IWLWIFI_DEBUG
1584 wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1585 WARN_ONCE((iwl_read_prph(trans, SCD_AGGR_SEL) & BIT(txq_id)) &&
1586 ((wifi_seq & 0xff) != q->write_ptr),
1587 "Q: %d WiFi Seq %d tfdNum %d",
1588 txq_id, wifi_seq, q->write_ptr);
1591 /* Set up driver data for this TFD */
1592 txq->entries[q->write_ptr].skb = skb;
1593 txq->entries[q->write_ptr].cmd = dev_cmd;
1595 dev_cmd->hdr.cmd = REPLY_TX;
1596 dev_cmd->hdr.sequence =
1597 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1598 INDEX_TO_SEQ(q->write_ptr)));
1600 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1601 out_meta = &txq->entries[q->write_ptr].meta;
1604 * Use the first empty entry in this queue's command buffer array
1605 * to contain the Tx command and MAC header concatenated together
1606 * (payload data will be in another buffer).
1607 * Size of this varies, due to varying MAC header length.
1608 * If end is not dword aligned, we'll have 2 extra bytes at the end
1609 * of the MAC header (device reads on dword boundaries).
1610 * We'll tell device about this padding later.
1612 len = sizeof(struct iwl_tx_cmd) +
1613 sizeof(struct iwl_cmd_header) + hdr_len;
1614 firstlen = (len + 3) & ~3;
1616 /* Tell NIC about any 2-byte padding after MAC header */
1617 if (firstlen != len)
1618 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1620 /* Physical address of this Tx command's header (not MAC header!),
1621 * within command buffer array. */
1622 txcmd_phys = dma_map_single(trans->dev,
1623 &dev_cmd->hdr, firstlen,
1625 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1627 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1628 dma_unmap_len_set(out_meta, len, firstlen);
1630 if (!ieee80211_has_morefrags(fc)) {
1631 txq->need_update = 1;
1634 txq->need_update = 0;
1637 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1638 * if any (802.11 null frames have no payload). */
1639 secondlen = skb->len - hdr_len;
1640 if (secondlen > 0) {
1641 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1642 secondlen, DMA_TO_DEVICE);
1643 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1644 dma_unmap_single(trans->dev,
1645 dma_unmap_addr(out_meta, mapping),
1646 dma_unmap_len(out_meta, len),
1652 /* Attach buffers to TFD */
1653 iwl_pcie_txq_build_tfd(trans, txq, txcmd_phys, firstlen, 1);
1655 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, secondlen, 0);
1657 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1658 offsetof(struct iwl_tx_cmd, scratch);
1660 /* take back ownership of DMA buffer to enable update */
1661 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1663 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1664 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1666 /* Set up entry for this TFD in Tx byte-count array */
1667 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1669 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1672 trace_iwlwifi_dev_tx(trans->dev, skb,
1673 &txq->tfds[txq->q.write_ptr],
1674 sizeof(struct iwl_tfd),
1675 &dev_cmd->hdr, firstlen,
1676 skb->data + hdr_len, secondlen);
1677 trace_iwlwifi_dev_tx_data(trans->dev, skb,
1678 skb->data + hdr_len, secondlen);
1680 /* start timer if queue currently empty */
1681 if (txq->need_update && q->read_ptr == q->write_ptr &&
1682 trans_pcie->wd_timeout)
1683 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1685 /* Tell device the write index *just past* this latest filled TFD */
1686 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1687 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1690 * At this point the frame is "transmitted" successfully
1691 * and we will get a TX status notification eventually,
1692 * regardless of the value of ret. "ret" only indicates
1693 * whether or not we should update the write pointer.
1695 if (iwl_queue_space(q) < q->high_mark) {
1696 if (wait_write_ptr) {
1697 txq->need_update = 1;
1698 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1700 iwl_stop_queue(trans, txq);
1703 spin_unlock(&txq->lock);
1706 spin_unlock(&txq->lock);