drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
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   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
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  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  20  * along with this program; if not, write to the Free Software
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  44  *    the documentation and/or other materials provided with the
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
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  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-agn-hw.h"
  76 #include "internal.h"
  77
  78 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
  79 {
  80         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
  81                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
  82                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  83                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
  84         else
  85                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
  86                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  87                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
  88 }
  89
  90 /* PCI registers */
  91 #define PCI_CFG_RETRY_TIMEOUT   0x041
  92
  93 static void iwl_pcie_apm_config(struct iwl_trans *trans)
  94 {
  95         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  96         u16 lctl;
  97
  98         /*
  99          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 100          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 101          * If so (likely), disable L0S, so device moves directly L0->L1;
 102          *    costs negligible amount of power savings.
 103          * If not (unlikely), enable L0S, so there is at least some
 104          *    power savings, even without L1.
 105          */
 106         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 107         if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
 108                 /* L1-ASPM enabled; disable(!) L0S */
 109                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 110                 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
 111         } else {
 112                 /* L1-ASPM disabled; enable(!) L0S */
 113                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 114                 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
 115         }
 116         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 117 }
 118
 119 /*
 120  * Start up NIC's basic functionality after it has been reset
 121  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 122  * NOTE:  This does not load uCode nor start the embedded processor
 123  */
 124 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 125 {
 126         int ret = 0;
 127         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 128
 129         /*
 130          * Use "set_bit" below rather than "write", to preserve any hardware
 131          * bits already set by default after reset.
 132          */
 133
 134         /* Disable L0S exit timer (platform NMI Work/Around) */
 135         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 136                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 137
 138         /*
 139          * Disable L0s without affecting L1;
 140          *  don't wait for ICH L0s (ICH bug W/A)
 141          */
 142         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 143                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 144
 145         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 146         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 147
 148         /*
 149          * Enable HAP INTA (interrupt from management bus) to
 150          * wake device's PCI Express link L1a -> L0s
 151          */
 152         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 153                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 154
 155         iwl_pcie_apm_config(trans);
 156
 157         /* Configure analog phase-lock-loop before activating to D0A */
 158         if (trans->cfg->base_params->pll_cfg_val)
 159                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 160                             trans->cfg->base_params->pll_cfg_val);
 161
 162         /*
 163          * Set "initialization complete" bit to move adapter from
 164          * D0U* --> D0A* (powered-up active) state.
 165          */
 166         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 167
 168         /*
 169          * Wait for clock stabilization; once stabilized, access to
 170          * device-internal resources is supported, e.g. iwl_write_prph()
 171          * and accesses to uCode SRAM.
 172          */
 173         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 174                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 175                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 176         if (ret < 0) {
 177                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 178                 goto out;
 179         }
 180
 181         if (trans->cfg->host_interrupt_operation_mode) {
 182                 /*
 183                  * This is a bit of an abuse - This is needed for 7260 / 3160
 184                  * only check host_interrupt_operation_mode even if this is
 185                  * not related to host_interrupt_operation_mode.
 186                  *
 187                  * Enable the oscillator to count wake up time for L1 exit. This
 188                  * consumes slightly more power (100uA) - but allows to be sure
 189                  * that we wake up from L1 on time.
 190                  *
 191                  * This looks weird: read twice the same register, discard the
 192                  * value, set a bit, and yet again, read that same register
 193                  * just to discard the value. But that's the way the hardware
 194                  * seems to like it.
 195                  */
 196                 iwl_read_prph(trans, OSC_CLK);
 197                 iwl_read_prph(trans, OSC_CLK);
 198                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 199                 iwl_read_prph(trans, OSC_CLK);
 200                 iwl_read_prph(trans, OSC_CLK);
 201         }
 202
 203         /*
 204          * Enable DMA clock and wait for it to stabilize.
 205          *
 206          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 207          * do not disable clocks.  This preserves any hardware bits already
 208          * set by default in "CLK_CTRL_REG" after reset.
 209          */
 210         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 211         udelay(20);
 212
 213         /* Disable L1-Active */
 214         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 215                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 216
 217         /* Clear the interrupt in APMG if the NIC is in RFKILL */
 218         iwl_write_prph(trans, APMG_RTC_INT_STT_REG, APMG_RTC_INT_STT_RFKILL);
 219
 220         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 221
 222 out:
 223         return ret;
 224 }
 225
 226 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 227 {
 228         int ret = 0;
 229
 230         /* stop device's busmaster DMA activity */
 231         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 232
 233         ret = iwl_poll_bit(trans, CSR_RESET,
 234                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 235                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 236         if (ret)
 237                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 238
 239         IWL_DEBUG_INFO(trans, "stop master\n");
 240
 241         return ret;
 242 }
 243
 244 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
 245 {
 246         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 247
 248         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 249
 250         /* Stop device's DMA activity */
 251         iwl_pcie_apm_stop_master(trans);
 252
 253         /* Reset the entire device */
 254         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 255
 256         udelay(10);
 257
 258         /*
 259          * Clear "initialization complete" bit to move adapter from
 260          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 261          */
 262         iwl_clear_bit(trans, CSR_GP_CNTRL,
 263                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 264 }
 265
 266 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 267 {
 268         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 269
 270         /* nic_init */
 271         spin_lock(&trans_pcie->irq_lock);
 272         iwl_pcie_apm_init(trans);
 273
 274         spin_unlock(&trans_pcie->irq_lock);
 275
 276         iwl_pcie_set_pwr(trans, false);
 277
 278         iwl_op_mode_nic_config(trans->op_mode);
 279
 280         /* Allocate the RX queue, or reset if it is already allocated */
 281         iwl_pcie_rx_init(trans);
 282
 283         /* Allocate or reset and init all Tx and Command queues */
 284         if (iwl_pcie_tx_init(trans))
 285                 return -ENOMEM;
 286
 287         if (trans->cfg->base_params->shadow_reg_enable) {
 288                 /* enable shadow regs in HW */
 289                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 290                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 291         }
 292
 293         return 0;
 294 }
 295
 296 #define HW_READY_TIMEOUT (50)
 297
 298 /* Note: returns poll_bit return value, which is >= 0 if success */
 299 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 300 {
 301         int ret;
 302
 303         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 304                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 305
 306         /* See if we got it */
 307         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 308                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 309                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 310                            HW_READY_TIMEOUT);
 311
 312         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 313         return ret;
 314 }
 315
 316 /* Note: returns standard 0/-ERROR code */
 317 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 318 {
 319         int ret;
 320         int t = 0;
 321
 322         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 323
 324         ret = iwl_pcie_set_hw_ready(trans);
 325         /* If the card is ready, exit 0 */
 326         if (ret >= 0)
 327                 return 0;
 328
 329         /* If HW is not ready, prepare the conditions to check again */
 330         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 331                     CSR_HW_IF_CONFIG_REG_PREPARE);
 332
 333         do {
 334                 ret = iwl_pcie_set_hw_ready(trans);
 335                 if (ret >= 0)
 336                         return 0;
 337
 338                 usleep_range(200, 1000);
 339                 t += 200;
 340         } while (t < 150000);
 341
 342         return ret;
 343 }
 344
 345 /*
 346  * ucode
 347  */
 348 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 349                                    dma_addr_t phy_addr, u32 byte_cnt)
 350 {
 351         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 352         int ret;
 353
 354         trans_pcie->ucode_write_complete = false;
 355
 356         iwl_write_direct32(trans,
 357                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 358                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 359
 360         iwl_write_direct32(trans,
 361                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 362                            dst_addr);
 363
 364         iwl_write_direct32(trans,
 365                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 366                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 367
 368         iwl_write_direct32(trans,
 369                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 370                            (iwl_get_dma_hi_addr(phy_addr)
 371                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 372
 373         iwl_write_direct32(trans,
 374                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 375                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 376                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 377                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 378
 379         iwl_write_direct32(trans,
 380                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 381                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 382                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 383                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 384
 385         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 386                                  trans_pcie->ucode_write_complete, 5 * HZ);
 387         if (!ret) {
 388                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 389                 return -ETIMEDOUT;
 390         }
 391
 392         return 0;
 393 }
 394
 395 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 396                             const struct fw_desc *section)
 397 {
 398         u8 *v_addr;
 399         dma_addr_t p_addr;
 400         u32 offset, chunk_sz = section->len;
 401         int ret = 0;
 402
 403         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 404                      section_num);
 405
 406         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 407                                     GFP_KERNEL | __GFP_NOWARN);
 408         if (!v_addr) {
 409                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 410                 chunk_sz = PAGE_SIZE;
 411                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 412                                             &p_addr, GFP_KERNEL);
 413                 if (!v_addr)
 414                         return -ENOMEM;
 415         }
 416
 417         for (offset = 0; offset < section->len; offset += chunk_sz) {
 418                 u32 copy_size;
 419
 420                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 421
 422                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 423                 ret = iwl_pcie_load_firmware_chunk(trans,
 424                                                    section->offset + offset,
 425                                                    p_addr, copy_size);
 426                 if (ret) {
 427                         IWL_ERR(trans,
 428                                 "Could not load the [%d] uCode section\n",
 429                                 section_num);
 430                         break;
 431                 }
 432         }
 433
 434         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 435         return ret;
 436 }
 437
 438 static int iwl_pcie_secure_set(struct iwl_trans *trans, int cpu)
 439 {
 440         int shift_param;
 441         u32 address;
 442         int ret = 0;
 443
 444         if (cpu == 1) {
 445                 shift_param = 0;
 446                 address = CSR_SECURE_BOOT_CPU1_STATUS_ADDR;
 447         } else {
 448                 shift_param = 16;
 449                 address = CSR_SECURE_BOOT_CPU2_STATUS_ADDR;
 450         }
 451
 452         /* set CPU to started */
 453         iwl_trans_set_bits_mask(trans,
 454                                 CSR_UCODE_LOAD_STATUS_ADDR,
 455                                 CSR_CPU_STATUS_LOADING_STARTED << shift_param,
 456                                 1);
 457
 458         /* set last complete descriptor number */
 459         iwl_trans_set_bits_mask(trans,
 460                                 CSR_UCODE_LOAD_STATUS_ADDR,
 461                                 CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED
 462                                 << shift_param,
 463                                 1);
 464
 465         /* set last loaded block */
 466         iwl_trans_set_bits_mask(trans,
 467                                 CSR_UCODE_LOAD_STATUS_ADDR,
 468                                 CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK
 469                                 << shift_param,
 470                                 1);
 471
 472         /* image loading complete */
 473         iwl_trans_set_bits_mask(trans,
 474                                 CSR_UCODE_LOAD_STATUS_ADDR,
 475                                 CSR_CPU_STATUS_LOADING_COMPLETED
 476                                 << shift_param,
 477                                 1);
 478
 479         /* set FH_TCSR_0_REG  */
 480         iwl_trans_set_bits_mask(trans, FH_TCSR_0_REG0, 0x00400000, 1);
 481
 482         /* verify image verification started  */
 483         ret = iwl_poll_bit(trans, address,
 484                            CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS,
 485                            CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS,
 486                            CSR_SECURE_TIME_OUT);
 487         if (ret < 0) {
 488                 IWL_ERR(trans, "secure boot process didn't start\n");
 489                 return ret;
 490         }
 491
 492         /* wait for image verification to complete  */
 493         ret = iwl_poll_bit(trans, address,
 494                            CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED,
 495                            CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED,
 496                            CSR_SECURE_TIME_OUT);
 497
 498         if (ret < 0) {
 499                 IWL_ERR(trans, "Time out on secure boot process\n");
 500                 return ret;
 501         }
 502
 503         return 0;
 504 }
 505
 506 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 507                                 const struct fw_img *image)
 508 {
 509         int i, ret = 0;
 510
 511         IWL_DEBUG_FW(trans,
 512                      "working with %s image\n",
 513                      image->is_secure ? "Secured" : "Non Secured");
 514         IWL_DEBUG_FW(trans,
 515                      "working with %s CPU\n",
 516                      image->is_dual_cpus ? "Dual" : "Single");
 517
 518         /* configure the ucode to be ready to get the secured image */
 519         if (image->is_secure) {
 520                 /* set secure boot inspector addresses */
 521                 iwl_write32(trans, CSR_SECURE_INSPECTOR_CODE_ADDR, 0);
 522                 iwl_write32(trans, CSR_SECURE_INSPECTOR_DATA_ADDR, 0);
 523
 524                 /* release CPU1 reset if secure inspector image burned in OTP */
 525                 iwl_write32(trans, CSR_RESET, 0);
 526         }
 527
 528         /* load to FW the binary sections of CPU1 */
 529         IWL_DEBUG_INFO(trans, "Loading CPU1\n");
 530         for (i = 0;
 531              i < IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU;
 532              i++) {
 533                 if (!image->sec[i].data)
 534                         break;
 535                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 536                 if (ret)
 537                         return ret;
 538         }
 539
 540         /* configure the ucode to start secure process on CPU1 */
 541         if (image->is_secure) {
 542                 /* config CPU1 to start secure protocol */
 543                 ret = iwl_pcie_secure_set(trans, 1);
 544                 if (ret)
 545                         return ret;
 546         } else {
 547                 /* Remove all resets to allow NIC to operate */
 548                 iwl_write32(trans, CSR_RESET, 0);
 549         }
 550
 551         if (image->is_dual_cpus) {
 552                 /* load to FW the binary sections of CPU2 */
 553                 IWL_DEBUG_INFO(trans, "working w/ DUAL CPUs - Loading CPU2\n");
 554                 for (i = IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU;
 555                         i < IWL_UCODE_SECTION_MAX; i++) {
 556                         if (!image->sec[i].data)
 557                                 break;
 558                         ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 559                         if (ret)
 560                                 return ret;
 561                 }
 562
 563                 if (image->is_secure) {
 564                         /* set CPU2 for secure protocol */
 565                         ret = iwl_pcie_secure_set(trans, 2);
 566                         if (ret)
 567                                 return ret;
 568                 }
 569         }
 570
 571         return 0;
 572 }
 573
 574 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 575                                    const struct fw_img *fw, bool run_in_rfkill)
 576 {
 577         int ret;
 578         bool hw_rfkill;
 579
 580         /* This may fail if AMT took ownership of the device */
 581         if (iwl_pcie_prepare_card_hw(trans)) {
 582                 IWL_WARN(trans, "Exit HW not ready\n");
 583                 return -EIO;
 584         }
 585
 586         iwl_enable_rfkill_int(trans);
 587
 588         /* If platform's RF_KILL switch is NOT set to KILL */
 589         hw_rfkill = iwl_is_rfkill_set(trans);
 590         if (hw_rfkill)
 591                 set_bit(STATUS_RFKILL, &trans->status);
 592         else
 593                 clear_bit(STATUS_RFKILL, &trans->status);
 594         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 595         if (hw_rfkill && !run_in_rfkill)
 596                 return -ERFKILL;
 597
 598         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 599
 600         ret = iwl_pcie_nic_init(trans);
 601         if (ret) {
 602                 IWL_ERR(trans, "Unable to init nic\n");
 603                 return ret;
 604         }
 605
 606         /* make sure rfkill handshake bits are cleared */
 607         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 608         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 609                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 610
 611         /* clear (again), then enable host interrupts */
 612         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 613         iwl_enable_interrupts(trans);
 614
 615         /* really make sure rfkill handshake bits are cleared */
 616         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 617         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 618
 619         /* Load the given image to the HW */
 620         return iwl_pcie_load_given_ucode(trans, fw);
 621 }
 622
 623 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 624 {
 625         iwl_pcie_reset_ict(trans);
 626         iwl_pcie_tx_start(trans, scd_addr);
 627 }
 628
 629 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 630 {
 631         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 632         bool hw_rfkill, was_hw_rfkill;
 633
 634         was_hw_rfkill = iwl_is_rfkill_set(trans);
 635
 636         /* tell the device to stop sending interrupts */
 637         spin_lock(&trans_pcie->irq_lock);
 638         iwl_disable_interrupts(trans);
 639         spin_unlock(&trans_pcie->irq_lock);
 640
 641         /* device going down, Stop using ICT table */
 642         iwl_pcie_disable_ict(trans);
 643
 644         /*
 645          * If a HW restart happens during firmware loading,
 646          * then the firmware loading might call this function
 647          * and later it might be called again due to the
 648          * restart. So don't process again if the device is
 649          * already dead.
 650          */
 651         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
 652                 iwl_pcie_tx_stop(trans);
 653                 iwl_pcie_rx_stop(trans);
 654
 655                 /* Power-down device's busmaster DMA clocks */
 656                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
 657                                APMG_CLK_VAL_DMA_CLK_RQT);
 658                 udelay(5);
 659         }
 660
 661         /* Make sure (redundant) we've released our request to stay awake */
 662         iwl_clear_bit(trans, CSR_GP_CNTRL,
 663                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 664
 665         /* Stop the device, and put it in low power state */
 666         iwl_pcie_apm_stop(trans);
 667
 668         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
 669          * Clean again the interrupt here
 670          */
 671         spin_lock(&trans_pcie->irq_lock);
 672         iwl_disable_interrupts(trans);
 673         spin_unlock(&trans_pcie->irq_lock);
 674
 675         /* stop and reset the on-board processor */
 676         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
 677
 678         /* clear all status bits */
 679         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
 680         clear_bit(STATUS_INT_ENABLED, &trans->status);
 681         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 682         clear_bit(STATUS_TPOWER_PMI, &trans->status);
 683         clear_bit(STATUS_RFKILL, &trans->status);
 684
 685         /*
 686          * Even if we stop the HW, we still want the RF kill
 687          * interrupt
 688          */
 689         iwl_enable_rfkill_int(trans);
 690
 691         /*
 692          * Check again since the RF kill state may have changed while
 693          * all the interrupts were disabled, in this case we couldn't
 694          * receive the RF kill interrupt and update the state in the
 695          * op_mode.
 696          * Don't call the op_mode if the rkfill state hasn't changed.
 697          * This allows the op_mode to call stop_device from the rfkill
 698          * notification without endless recursion. Under very rare
 699          * circumstances, we might have a small recursion if the rfkill
 700          * state changed exactly now while we were called from stop_device.
 701          * This is very unlikely but can happen and is supported.
 702          */
 703         hw_rfkill = iwl_is_rfkill_set(trans);
 704         if (hw_rfkill)
 705                 set_bit(STATUS_RFKILL, &trans->status);
 706         else
 707                 clear_bit(STATUS_RFKILL, &trans->status);
 708         if (hw_rfkill != was_hw_rfkill)
 709                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 710 }
 711
 712 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
 713 {
 714         iwl_disable_interrupts(trans);
 715
 716         /*
 717          * in testing mode, the host stays awake and the
 718          * hardware won't be reset (not even partially)
 719          */
 720         if (test)
 721                 return;
 722
 723         iwl_pcie_disable_ict(trans);
 724
 725         iwl_clear_bit(trans, CSR_GP_CNTRL,
 726                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 727         iwl_clear_bit(trans, CSR_GP_CNTRL,
 728                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 729
 730         /*
 731          * reset TX queues -- some of their registers reset during S3
 732          * so if we don't reset everything here the D3 image would try
 733          * to execute some invalid memory upon resume
 734          */
 735         iwl_trans_pcie_tx_reset(trans);
 736
 737         iwl_pcie_set_pwr(trans, true);
 738 }
 739
 740 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
 741                                     enum iwl_d3_status *status,
 742                                     bool test)
 743 {
 744         u32 val;
 745         int ret;
 746
 747         if (test) {
 748                 iwl_enable_interrupts(trans);
 749                 *status = IWL_D3_STATUS_ALIVE;
 750                 return 0;
 751         }
 752
 753         iwl_pcie_set_pwr(trans, false);
 754
 755         val = iwl_read32(trans, CSR_RESET);
 756         if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
 757                 *status = IWL_D3_STATUS_RESET;
 758                 return 0;
 759         }
 760
 761         /*
 762          * Also enables interrupts - none will happen as the device doesn't
 763          * know we're waking it up, only when the opmode actually tells it
 764          * after this call.
 765          */
 766         iwl_pcie_reset_ict(trans);
 767
 768         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 769         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 770
 771         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 772                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 773                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 774                            25000);
 775         if (ret) {
 776                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
 777                 return ret;
 778         }
 779
 780         iwl_trans_pcie_tx_reset(trans);
 781
 782         ret = iwl_pcie_rx_init(trans);
 783         if (ret) {
 784                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
 785                 return ret;
 786         }
 787
 788         *status = IWL_D3_STATUS_ALIVE;
 789         return 0;
 790 }
 791
 792 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
 793 {
 794         bool hw_rfkill;
 795         int err;
 796
 797         err = iwl_pcie_prepare_card_hw(trans);
 798         if (err) {
 799                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
 800                 return err;
 801         }
 802
 803         /* Reset the entire device */
 804         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 805
 806         usleep_range(10, 15);
 807
 808         iwl_pcie_apm_init(trans);
 809
 810         /* From now on, the op_mode will be kept updated about RF kill state */
 811         iwl_enable_rfkill_int(trans);
 812
 813         hw_rfkill = iwl_is_rfkill_set(trans);
 814         if (hw_rfkill)
 815                 set_bit(STATUS_RFKILL, &trans->status);
 816         else
 817                 clear_bit(STATUS_RFKILL, &trans->status);
 818         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 819
 820         return 0;
 821 }
 822
 823 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
 824 {
 825         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 826
 827         /* disable interrupts - don't enable HW RF kill interrupt */
 828         spin_lock(&trans_pcie->irq_lock);
 829         iwl_disable_interrupts(trans);
 830         spin_unlock(&trans_pcie->irq_lock);
 831
 832         iwl_pcie_apm_stop(trans);
 833
 834         spin_lock(&trans_pcie->irq_lock);
 835         iwl_disable_interrupts(trans);
 836         spin_unlock(&trans_pcie->irq_lock);
 837
 838         iwl_pcie_disable_ict(trans);
 839 }
 840
 841 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
 842 {
 843         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 844 }
 845
 846 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
 847 {
 848         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 849 }
 850
 851 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
 852 {
 853         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 854 }
 855
 856 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
 857 {
 858         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
 859                                ((reg & 0x000FFFFF) | (3 << 24)));
 860         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
 861 }
 862
 863 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
 864                                       u32 val)
 865 {
 866         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
 867                                ((addr & 0x000FFFFF) | (3 << 24)));
 868         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
 869 }
 870
 871 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
 872                                      const struct iwl_trans_config *trans_cfg)
 873 {
 874         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 875
 876         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
 877         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
 878         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
 879                 trans_pcie->n_no_reclaim_cmds = 0;
 880         else
 881                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
 882         if (trans_pcie->n_no_reclaim_cmds)
 883                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
 884                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
 885
 886         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
 887         if (trans_pcie->rx_buf_size_8k)
 888                 trans_pcie->rx_page_order = get_order(8 * 1024);
 889         else
 890                 trans_pcie->rx_page_order = get_order(4 * 1024);
 891
 892         trans_pcie->wd_timeout =
 893                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
 894
 895         trans_pcie->command_names = trans_cfg->command_names;
 896         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
 897 }
 898
 899 void iwl_trans_pcie_free(struct iwl_trans *trans)
 900 {
 901         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 902
 903         synchronize_irq(trans_pcie->pci_dev->irq);
 904
 905         iwl_pcie_tx_free(trans);
 906         iwl_pcie_rx_free(trans);
 907
 908         free_irq(trans_pcie->pci_dev->irq, trans);
 909         iwl_pcie_free_ict(trans);
 910
 911         pci_disable_msi(trans_pcie->pci_dev);
 912         iounmap(trans_pcie->hw_base);
 913         pci_release_regions(trans_pcie->pci_dev);
 914         pci_disable_device(trans_pcie->pci_dev);
 915         kmem_cache_destroy(trans->dev_cmd_pool);
 916
 917         kfree(trans);
 918 }
 919
 920 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
 921 {
 922         if (state)
 923                 set_bit(STATUS_TPOWER_PMI, &trans->status);
 924         else
 925                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
 926 }
 927
 928 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
 929                                                 unsigned long *flags)
 930 {
 931         int ret;
 932         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 933
 934         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
 935
 936         if (trans_pcie->cmd_in_flight)
 937                 goto out;
 938
 939         /* this bit wakes up the NIC */
 940         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 941                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 942
 943         /*
 944          * These bits say the device is running, and should keep running for
 945          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
 946          * but they do not indicate that embedded SRAM is restored yet;
 947          * 3945 and 4965 have volatile SRAM, and must save/restore contents
 948          * to/from host DRAM when sleeping/waking for power-saving.
 949          * Each direction takes approximately 1/4 millisecond; with this
 950          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
 951          * series of register accesses are expected (e.g. reading Event Log),
 952          * to keep device from sleeping.
 953          *
 954          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
 955          * SRAM is okay/restored.  We don't check that here because this call
 956          * is just for hardware register access; but GP1 MAC_SLEEP check is a
 957          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
 958          *
 959          * 5000 series and later (including 1000 series) have non-volatile SRAM,
 960          * and do not save/restore SRAM when power cycling.
 961          */
 962         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 963                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
 964                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
 965                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
 966         if (unlikely(ret < 0)) {
 967                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
 968                 if (!silent) {
 969                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
 970                         WARN_ONCE(1,
 971                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
 972                                   val);
 973                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
 974                         return false;
 975                 }
 976         }
 977
 978 out:
 979         /*
 980          * Fool sparse by faking we release the lock - sparse will
 981          * track nic_access anyway.
 982          */
 983         __release(&trans_pcie->reg_lock);
 984         return true;
 985 }
 986
 987 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
 988                                               unsigned long *flags)
 989 {
 990         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 991
 992         lockdep_assert_held(&trans_pcie->reg_lock);
 993
 994         /*
 995          * Fool sparse by faking we acquiring the lock - sparse will
 996          * track nic_access anyway.
 997          */
 998         __acquire(&trans_pcie->reg_lock);
 999
1000         if (trans_pcie->cmd_in_flight)
1001                 goto out;
1002
1003         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1004                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1005         /*
1006          * Above we read the CSR_GP_CNTRL register, which will flush
1007          * any previous writes, but we need the write that clears the
1008          * MAC_ACCESS_REQ bit to be performed before any other writes
1009          * scheduled on different CPUs (after we drop reg_lock).
1010          */
1011         mmiowb();
1012 out:
1013         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1014 }
1015
1016 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1017                                    void *buf, int dwords)
1018 {
1019         unsigned long flags;
1020         int offs, ret = 0;
1021         u32 *vals = buf;
1022
1023         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1024                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1025                 for (offs = 0; offs < dwords; offs++)
1026                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1027                 iwl_trans_release_nic_access(trans, &flags);
1028         } else {
1029                 ret = -EBUSY;
1030         }
1031         return ret;
1032 }
1033
1034 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1035                                     const void *buf, int dwords)
1036 {
1037         unsigned long flags;
1038         int offs, ret = 0;
1039         const u32 *vals = buf;
1040
1041         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1042                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1043                 for (offs = 0; offs < dwords; offs++)
1044                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1045                                     vals ? vals[offs] : 0);
1046                 iwl_trans_release_nic_access(trans, &flags);
1047         } else {
1048                 ret = -EBUSY;
1049         }
1050         return ret;
1051 }
1052
1053 #define IWL_FLUSH_WAIT_MS       2000
1054
1055 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
1056 {
1057         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1058         struct iwl_txq *txq;
1059         struct iwl_queue *q;
1060         int cnt;
1061         unsigned long now = jiffies;
1062         u32 scd_sram_addr;
1063         u8 buf[16];
1064         int ret = 0;
1065
1066         /* waiting for all the tx frames complete might take a while */
1067         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1068                 if (cnt == trans_pcie->cmd_queue)
1069                         continue;
1070                 txq = &trans_pcie->txq[cnt];
1071                 q = &txq->q;
1072                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1073                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1074                         msleep(1);
1075
1076                 if (q->read_ptr != q->write_ptr) {
1077                         IWL_ERR(trans,
1078                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1079                         ret = -ETIMEDOUT;
1080                         break;
1081                 }
1082         }
1083
1084         if (!ret)
1085                 return 0;
1086
1087         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1088                 txq->q.read_ptr, txq->q.write_ptr);
1089
1090         scd_sram_addr = trans_pcie->scd_base_addr +
1091                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1092         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1093
1094         iwl_print_hex_error(trans, buf, sizeof(buf));
1095
1096         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1097                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1098                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1099
1100         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1101                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1102                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1103                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1104                 u32 tbl_dw =
1105                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1106                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1107
1108                 if (cnt & 0x1)
1109                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1110                 else
1111                         tbl_dw = tbl_dw & 0x0000FFFF;
1112
1113                 IWL_ERR(trans,
1114                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1115                         cnt, active ? "" : "in", fifo, tbl_dw,
1116                         iwl_read_prph(trans,
1117                                       SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
1118                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1119         }
1120
1121         return ret;
1122 }
1123
1124 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1125                                          u32 mask, u32 value)
1126 {
1127         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1128         unsigned long flags;
1129
1130         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1131         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1132         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1133 }
1134
1135 static const char *get_csr_string(int cmd)
1136 {
1137 #define IWL_CMD(x) case x: return #x
1138         switch (cmd) {
1139         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1140         IWL_CMD(CSR_INT_COALESCING);
1141         IWL_CMD(CSR_INT);
1142         IWL_CMD(CSR_INT_MASK);
1143         IWL_CMD(CSR_FH_INT_STATUS);
1144         IWL_CMD(CSR_GPIO_IN);
1145         IWL_CMD(CSR_RESET);
1146         IWL_CMD(CSR_GP_CNTRL);
1147         IWL_CMD(CSR_HW_REV);
1148         IWL_CMD(CSR_EEPROM_REG);
1149         IWL_CMD(CSR_EEPROM_GP);
1150         IWL_CMD(CSR_OTP_GP_REG);
1151         IWL_CMD(CSR_GIO_REG);
1152         IWL_CMD(CSR_GP_UCODE_REG);
1153         IWL_CMD(CSR_GP_DRIVER_REG);
1154         IWL_CMD(CSR_UCODE_DRV_GP1);
1155         IWL_CMD(CSR_UCODE_DRV_GP2);
1156         IWL_CMD(CSR_LED_REG);
1157         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1158         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1159         IWL_CMD(CSR_ANA_PLL_CFG);
1160         IWL_CMD(CSR_HW_REV_WA_REG);
1161         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1162         default:
1163                 return "UNKNOWN";
1164         }
1165 #undef IWL_CMD
1166 }
1167
1168 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1169 {
1170         int i;
1171         static const u32 csr_tbl[] = {
1172                 CSR_HW_IF_CONFIG_REG,
1173                 CSR_INT_COALESCING,
1174                 CSR_INT,
1175                 CSR_INT_MASK,
1176                 CSR_FH_INT_STATUS,
1177                 CSR_GPIO_IN,
1178                 CSR_RESET,
1179                 CSR_GP_CNTRL,
1180                 CSR_HW_REV,
1181                 CSR_EEPROM_REG,
1182                 CSR_EEPROM_GP,
1183                 CSR_OTP_GP_REG,
1184                 CSR_GIO_REG,
1185                 CSR_GP_UCODE_REG,
1186                 CSR_GP_DRIVER_REG,
1187                 CSR_UCODE_DRV_GP1,
1188                 CSR_UCODE_DRV_GP2,
1189                 CSR_LED_REG,
1190                 CSR_DRAM_INT_TBL_REG,
1191                 CSR_GIO_CHICKEN_BITS,
1192                 CSR_ANA_PLL_CFG,
1193                 CSR_HW_REV_WA_REG,
1194                 CSR_DBG_HPET_MEM_REG
1195         };
1196         IWL_ERR(trans, "CSR values:\n");
1197         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1198                 "CSR_INT_PERIODIC_REG)\n");
1199         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1200                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1201                         get_csr_string(csr_tbl[i]),
1202                         iwl_read32(trans, csr_tbl[i]));
1203         }
1204 }
1205
1206 #ifdef CONFIG_IWLWIFI_DEBUGFS
1207 /* create and remove of files */
1208 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1209         if (!debugfs_create_file(#name, mode, parent, trans,            \
1210                                  &iwl_dbgfs_##name##_ops))              \
1211                 goto err;                                               \
1212 } while (0)
1213
1214 /* file operation */
1215 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1216 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1217         .read = iwl_dbgfs_##name##_read,                                \
1218         .open = simple_open,                                            \
1219         .llseek = generic_file_llseek,                                  \
1220 };
1221
1222 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1223 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1224         .write = iwl_dbgfs_##name##_write,                              \
1225         .open = simple_open,                                            \
1226         .llseek = generic_file_llseek,                                  \
1227 };
1228
1229 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1230 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1231         .write = iwl_dbgfs_##name##_write,                              \
1232         .read = iwl_dbgfs_##name##_read,                                \
1233         .open = simple_open,                                            \
1234         .llseek = generic_file_llseek,                                  \
1235 };
1236
1237 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1238                                        char __user *user_buf,
1239                                        size_t count, loff_t *ppos)
1240 {
1241         struct iwl_trans *trans = file->private_data;
1242         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1243         struct iwl_txq *txq;
1244         struct iwl_queue *q;
1245         char *buf;
1246         int pos = 0;
1247         int cnt;
1248         int ret;
1249         size_t bufsz;
1250
1251         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1252
1253         if (!trans_pcie->txq)
1254                 return -EAGAIN;
1255
1256         buf = kzalloc(bufsz, GFP_KERNEL);
1257         if (!buf)
1258                 return -ENOMEM;
1259
1260         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1261                 txq = &trans_pcie->txq[cnt];
1262                 q = &txq->q;
1263                 pos += scnprintf(buf + pos, bufsz - pos,
1264                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1265                                 cnt, q->read_ptr, q->write_ptr,
1266                                 !!test_bit(cnt, trans_pcie->queue_used),
1267                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1268         }
1269         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1270         kfree(buf);
1271         return ret;
1272 }
1273
1274 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1275                                        char __user *user_buf,
1276                                        size_t count, loff_t *ppos)
1277 {
1278         struct iwl_trans *trans = file->private_data;
1279         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1280         struct iwl_rxq *rxq = &trans_pcie->rxq;
1281         char buf[256];
1282         int pos = 0;
1283         const size_t bufsz = sizeof(buf);
1284
1285         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1286                                                 rxq->read);
1287         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1288                                                 rxq->write);
1289         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1290                                                 rxq->free_count);
1291         if (rxq->rb_stts) {
1292                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1293                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1294         } else {
1295                 pos += scnprintf(buf + pos, bufsz - pos,
1296                                         "closed_rb_num: Not Allocated\n");
1297         }
1298         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1299 }
1300
1301 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1302                                         char __user *user_buf,
1303                                         size_t count, loff_t *ppos)
1304 {
1305         struct iwl_trans *trans = file->private_data;
1306         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1307         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1308
1309         int pos = 0;
1310         char *buf;
1311         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1312         ssize_t ret;
1313
1314         buf = kzalloc(bufsz, GFP_KERNEL);
1315         if (!buf)
1316                 return -ENOMEM;
1317
1318         pos += scnprintf(buf + pos, bufsz - pos,
1319                         "Interrupt Statistics Report:\n");
1320
1321         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1322                 isr_stats->hw);
1323         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1324                 isr_stats->sw);
1325         if (isr_stats->sw || isr_stats->hw) {
1326                 pos += scnprintf(buf + pos, bufsz - pos,
1327                         "\tLast Restarting Code:  0x%X\n",
1328                         isr_stats->err_code);
1329         }
1330 #ifdef CONFIG_IWLWIFI_DEBUG
1331         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1332                 isr_stats->sch);
1333         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1334                 isr_stats->alive);
1335 #endif
1336         pos += scnprintf(buf + pos, bufsz - pos,
1337                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1338
1339         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1340                 isr_stats->ctkill);
1341
1342         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1343                 isr_stats->wakeup);
1344
1345         pos += scnprintf(buf + pos, bufsz - pos,
1346                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1347
1348         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1349                 isr_stats->tx);
1350
1351         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1352                 isr_stats->unhandled);
1353
1354         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1355         kfree(buf);
1356         return ret;
1357 }
1358
1359 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1360                                          const char __user *user_buf,
1361                                          size_t count, loff_t *ppos)
1362 {
1363         struct iwl_trans *trans = file->private_data;
1364         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1365         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1366
1367         char buf[8];
1368         int buf_size;
1369         u32 reset_flag;
1370
1371         memset(buf, 0, sizeof(buf));
1372         buf_size = min(count, sizeof(buf) -  1);
1373         if (copy_from_user(buf, user_buf, buf_size))
1374                 return -EFAULT;
1375         if (sscanf(buf, "%x", &reset_flag) != 1)
1376                 return -EFAULT;
1377         if (reset_flag == 0)
1378                 memset(isr_stats, 0, sizeof(*isr_stats));
1379
1380         return count;
1381 }
1382
1383 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1384                                    const char __user *user_buf,
1385                                    size_t count, loff_t *ppos)
1386 {
1387         struct iwl_trans *trans = file->private_data;
1388         char buf[8];
1389         int buf_size;
1390         int csr;
1391
1392         memset(buf, 0, sizeof(buf));
1393         buf_size = min(count, sizeof(buf) -  1);
1394         if (copy_from_user(buf, user_buf, buf_size))
1395                 return -EFAULT;
1396         if (sscanf(buf, "%d", &csr) != 1)
1397                 return -EFAULT;
1398
1399         iwl_pcie_dump_csr(trans);
1400
1401         return count;
1402 }
1403
1404 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1405                                      char __user *user_buf,
1406                                      size_t count, loff_t *ppos)
1407 {
1408         struct iwl_trans *trans = file->private_data;
1409         char *buf = NULL;
1410         int pos = 0;
1411         ssize_t ret = -EFAULT;
1412
1413         ret = pos = iwl_dump_fh(trans, &buf);
1414         if (buf) {
1415                 ret = simple_read_from_buffer(user_buf,
1416                                               count, ppos, buf, pos);
1417                 kfree(buf);
1418         }
1419
1420         return ret;
1421 }
1422
1423 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1424 DEBUGFS_READ_FILE_OPS(fh_reg);
1425 DEBUGFS_READ_FILE_OPS(rx_queue);
1426 DEBUGFS_READ_FILE_OPS(tx_queue);
1427 DEBUGFS_WRITE_FILE_OPS(csr);
1428
1429 /*
1430  * Create the debugfs files and directories
1431  *
1432  */
1433 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1434                                          struct dentry *dir)
1435 {
1436         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1437         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1438         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1439         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1440         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1441         return 0;
1442
1443 err:
1444         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1445         return -ENOMEM;
1446 }
1447 #else
1448 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1449                                          struct dentry *dir)
1450 {
1451         return 0;
1452 }
1453 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1454
1455 static const struct iwl_trans_ops trans_ops_pcie = {
1456         .start_hw = iwl_trans_pcie_start_hw,
1457         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
1458         .fw_alive = iwl_trans_pcie_fw_alive,
1459         .start_fw = iwl_trans_pcie_start_fw,
1460         .stop_device = iwl_trans_pcie_stop_device,
1461
1462         .d3_suspend = iwl_trans_pcie_d3_suspend,
1463         .d3_resume = iwl_trans_pcie_d3_resume,
1464
1465         .send_cmd = iwl_trans_pcie_send_hcmd,
1466
1467         .tx = iwl_trans_pcie_tx,
1468         .reclaim = iwl_trans_pcie_reclaim,
1469
1470         .txq_disable = iwl_trans_pcie_txq_disable,
1471         .txq_enable = iwl_trans_pcie_txq_enable,
1472
1473         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1474
1475         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1476
1477         .write8 = iwl_trans_pcie_write8,
1478         .write32 = iwl_trans_pcie_write32,
1479         .read32 = iwl_trans_pcie_read32,
1480         .read_prph = iwl_trans_pcie_read_prph,
1481         .write_prph = iwl_trans_pcie_write_prph,
1482         .read_mem = iwl_trans_pcie_read_mem,
1483         .write_mem = iwl_trans_pcie_write_mem,
1484         .configure = iwl_trans_pcie_configure,
1485         .set_pmi = iwl_trans_pcie_set_pmi,
1486         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1487         .release_nic_access = iwl_trans_pcie_release_nic_access,
1488         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
1489 };
1490
1491 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1492                                        const struct pci_device_id *ent,
1493                                        const struct iwl_cfg *cfg)
1494 {
1495         struct iwl_trans_pcie *trans_pcie;
1496         struct iwl_trans *trans;
1497         u16 pci_cmd;
1498         int err;
1499
1500         trans = kzalloc(sizeof(struct iwl_trans) +
1501                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1502         if (!trans) {
1503                 err = -ENOMEM;
1504                 goto out;
1505         }
1506
1507         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1508
1509         trans->ops = &trans_ops_pcie;
1510         trans->cfg = cfg;
1511         trans_lockdep_init(trans);
1512         trans_pcie->trans = trans;
1513         spin_lock_init(&trans_pcie->irq_lock);
1514         spin_lock_init(&trans_pcie->reg_lock);
1515         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1516
1517         err = pci_enable_device(pdev);
1518         if (err)
1519                 goto out_no_pci;
1520
1521         if (!cfg->base_params->pcie_l1_allowed) {
1522                 /*
1523                  * W/A - seems to solve weird behavior. We need to remove this
1524                  * if we don't want to stay in L1 all the time. This wastes a
1525                  * lot of power.
1526                  */
1527                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
1528                                        PCIE_LINK_STATE_L1 |
1529                                        PCIE_LINK_STATE_CLKPM);
1530         }
1531
1532         pci_set_master(pdev);
1533
1534         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1535         if (!err)
1536                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1537         if (err) {
1538                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1539                 if (!err)
1540                         err = pci_set_consistent_dma_mask(pdev,
1541                                                           DMA_BIT_MASK(32));
1542                 /* both attempts failed: */
1543                 if (err) {
1544                         dev_err(&pdev->dev, "No suitable DMA available\n");
1545                         goto out_pci_disable_device;
1546                 }
1547         }
1548
1549         err = pci_request_regions(pdev, DRV_NAME);
1550         if (err) {
1551                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1552                 goto out_pci_disable_device;
1553         }
1554
1555         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1556         if (!trans_pcie->hw_base) {
1557                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1558                 err = -ENODEV;
1559                 goto out_pci_release_regions;
1560         }
1561
1562         /* We disable the RETRY_TIMEOUT register (0x41) to keep
1563          * PCI Tx retries from interfering with C3 CPU state */
1564         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1565
1566         err = pci_enable_msi(pdev);
1567         if (err) {
1568                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1569                 /* enable rfkill interrupt: hw bug w/a */
1570                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1571                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1572                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1573                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1574                 }
1575         }
1576
1577         trans->dev = &pdev->dev;
1578         trans_pcie->pci_dev = pdev;
1579         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1580         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1581         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1582                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1583
1584         /* Initialize the wait queue for commands */
1585         init_waitqueue_head(&trans_pcie->wait_command_queue);
1586
1587         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1588                  "iwl_cmd_pool:%s", dev_name(trans->dev));
1589
1590         trans->dev_cmd_headroom = 0;
1591         trans->dev_cmd_pool =
1592                 kmem_cache_create(trans->dev_cmd_pool_name,
1593                                   sizeof(struct iwl_device_cmd)
1594                                   + trans->dev_cmd_headroom,
1595                                   sizeof(void *),
1596                                   SLAB_HWCACHE_ALIGN,
1597                                   NULL);
1598
1599         if (!trans->dev_cmd_pool) {
1600                 err = -ENOMEM;
1601                 goto out_pci_disable_msi;
1602         }
1603
1604         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1605
1606         if (iwl_pcie_alloc_ict(trans))
1607                 goto out_free_cmd_pool;
1608
1609         err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
1610                                    iwl_pcie_irq_handler,
1611                                    IRQF_SHARED, DRV_NAME, trans);
1612         if (err) {
1613                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1614                 goto out_free_ict;
1615         }
1616
1617         return trans;
1618
1619 out_free_ict:
1620         iwl_pcie_free_ict(trans);
1621 out_free_cmd_pool:
1622         kmem_cache_destroy(trans->dev_cmd_pool);
1623 out_pci_disable_msi:
1624         pci_disable_msi(pdev);
1625 out_pci_release_regions:
1626         pci_release_regions(pdev);
1627 out_pci_disable_device:
1628         pci_disable_device(pdev);
1629 out_no_pci:
1630         kfree(trans);
1631 out:
1632         return ERR_PTR(err);
1633 }