drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
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   4  * redistributing this file, you may do so under either license.
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   6  * GPL LICENSE SUMMARY
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  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
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  20  * along with this program; if not, write to the Free Software
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  44  *    the documentation and/or other materials provided with the
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
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  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-agn-hw.h"
  76 #include "internal.h"
  77
  78 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
  79 {
  80         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
  81                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
  82                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  83                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
  84         else
  85                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
  86                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  87                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
  88 }
  89
  90 /* PCI registers */
  91 #define PCI_CFG_RETRY_TIMEOUT   0x041
  92
  93 static void iwl_pcie_apm_config(struct iwl_trans *trans)
  94 {
  95         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  96         u16 lctl;
  97
  98         /*
  99          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 100          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 101          * If so (likely), disable L0S, so device moves directly L0->L1;
 102          *    costs negligible amount of power savings.
 103          * If not (unlikely), enable L0S, so there is at least some
 104          *    power savings, even without L1.
 105          */
 106         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 107         if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
 108                 /* L1-ASPM enabled; disable(!) L0S */
 109                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 110                 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
 111         } else {
 112                 /* L1-ASPM disabled; enable(!) L0S */
 113                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 114                 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
 115         }
 116         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 117 }
 118
 119 /*
 120  * Start up NIC's basic functionality after it has been reset
 121  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 122  * NOTE:  This does not load uCode nor start the embedded processor
 123  */
 124 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 125 {
 126         int ret = 0;
 127         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 128
 129         /*
 130          * Use "set_bit" below rather than "write", to preserve any hardware
 131          * bits already set by default after reset.
 132          */
 133
 134         /* Disable L0S exit timer (platform NMI Work/Around) */
 135         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 136                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 137
 138         /*
 139          * Disable L0s without affecting L1;
 140          *  don't wait for ICH L0s (ICH bug W/A)
 141          */
 142         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 143                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 144
 145         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 146         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 147
 148         /*
 149          * Enable HAP INTA (interrupt from management bus) to
 150          * wake device's PCI Express link L1a -> L0s
 151          */
 152         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 153                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 154
 155         iwl_pcie_apm_config(trans);
 156
 157         /* Configure analog phase-lock-loop before activating to D0A */
 158         if (trans->cfg->base_params->pll_cfg_val)
 159                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 160                             trans->cfg->base_params->pll_cfg_val);
 161
 162         /*
 163          * Set "initialization complete" bit to move adapter from
 164          * D0U* --> D0A* (powered-up active) state.
 165          */
 166         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 167
 168         /*
 169          * Wait for clock stabilization; once stabilized, access to
 170          * device-internal resources is supported, e.g. iwl_write_prph()
 171          * and accesses to uCode SRAM.
 172          */
 173         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 174                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 175                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 176         if (ret < 0) {
 177                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 178                 goto out;
 179         }
 180
 181         if (trans->cfg->host_interrupt_operation_mode) {
 182                 /*
 183                  * This is a bit of an abuse - This is needed for 7260 / 3160
 184                  * only check host_interrupt_operation_mode even if this is
 185                  * not related to host_interrupt_operation_mode.
 186                  *
 187                  * Enable the oscillator to count wake up time for L1 exit. This
 188                  * consumes slightly more power (100uA) - but allows to be sure
 189                  * that we wake up from L1 on time.
 190                  *
 191                  * This looks weird: read twice the same register, discard the
 192                  * value, set a bit, and yet again, read that same register
 193                  * just to discard the value. But that's the way the hardware
 194                  * seems to like it.
 195                  */
 196                 iwl_read_prph(trans, OSC_CLK);
 197                 iwl_read_prph(trans, OSC_CLK);
 198                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 199                 iwl_read_prph(trans, OSC_CLK);
 200                 iwl_read_prph(trans, OSC_CLK);
 201         }
 202
 203         /*
 204          * Enable DMA clock and wait for it to stabilize.
 205          *
 206          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 207          * do not disable clocks.  This preserves any hardware bits already
 208          * set by default in "CLK_CTRL_REG" after reset.
 209          */
 210         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 211         udelay(20);
 212
 213         /* Disable L1-Active */
 214         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 215                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 216
 217         /* Clear the interrupt in APMG if the NIC is in RFKILL */
 218         iwl_write_prph(trans, APMG_RTC_INT_STT_REG, APMG_RTC_INT_STT_RFKILL);
 219
 220         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 221
 222 out:
 223         return ret;
 224 }
 225
 226 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 227 {
 228         int ret = 0;
 229
 230         /* stop device's busmaster DMA activity */
 231         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 232
 233         ret = iwl_poll_bit(trans, CSR_RESET,
 234                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 235                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 236         if (ret)
 237                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 238
 239         IWL_DEBUG_INFO(trans, "stop master\n");
 240
 241         return ret;
 242 }
 243
 244 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
 245 {
 246         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 247
 248         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 249
 250         /* Stop device's DMA activity */
 251         iwl_pcie_apm_stop_master(trans);
 252
 253         /* Reset the entire device */
 254         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 255
 256         udelay(10);
 257
 258         /*
 259          * Clear "initialization complete" bit to move adapter from
 260          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 261          */
 262         iwl_clear_bit(trans, CSR_GP_CNTRL,
 263                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 264 }
 265
 266 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 267 {
 268         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 269
 270         /* nic_init */
 271         spin_lock(&trans_pcie->irq_lock);
 272         iwl_pcie_apm_init(trans);
 273
 274         spin_unlock(&trans_pcie->irq_lock);
 275
 276         iwl_pcie_set_pwr(trans, false);
 277
 278         iwl_op_mode_nic_config(trans->op_mode);
 279
 280         /* Allocate the RX queue, or reset if it is already allocated */
 281         iwl_pcie_rx_init(trans);
 282
 283         /* Allocate or reset and init all Tx and Command queues */
 284         if (iwl_pcie_tx_init(trans))
 285                 return -ENOMEM;
 286
 287         if (trans->cfg->base_params->shadow_reg_enable) {
 288                 /* enable shadow regs in HW */
 289                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 290                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 291         }
 292
 293         return 0;
 294 }
 295
 296 #define HW_READY_TIMEOUT (50)
 297
 298 /* Note: returns poll_bit return value, which is >= 0 if success */
 299 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 300 {
 301         int ret;
 302
 303         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 304                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 305
 306         /* See if we got it */
 307         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 308                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 309                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 310                            HW_READY_TIMEOUT);
 311
 312         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 313         return ret;
 314 }
 315
 316 /* Note: returns standard 0/-ERROR code */
 317 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 318 {
 319         int ret;
 320         int t = 0;
 321         int iter;
 322
 323         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 324
 325         ret = iwl_pcie_set_hw_ready(trans);
 326         /* If the card is ready, exit 0 */
 327         if (ret >= 0)
 328                 return 0;
 329
 330         for (iter = 0; iter < 10; iter++) {
 331                 /* If HW is not ready, prepare the conditions to check again */
 332                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 333                             CSR_HW_IF_CONFIG_REG_PREPARE);
 334
 335                 do {
 336                         ret = iwl_pcie_set_hw_ready(trans);
 337                         if (ret >= 0)
 338                                 return 0;
 339
 340                         usleep_range(200, 1000);
 341                         t += 200;
 342                 } while (t < 150000);
 343                 msleep(25);
 344         }
 345
 346         IWL_DEBUG_INFO(trans, "got NIC after %d iterations\n", iter);
 347
 348         return ret;
 349 }
 350
 351 /*
 352  * ucode
 353  */
 354 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 355                                    dma_addr_t phy_addr, u32 byte_cnt)
 356 {
 357         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 358         int ret;
 359
 360         trans_pcie->ucode_write_complete = false;
 361
 362         iwl_write_direct32(trans,
 363                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 364                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 365
 366         iwl_write_direct32(trans,
 367                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 368                            dst_addr);
 369
 370         iwl_write_direct32(trans,
 371                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 372                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 373
 374         iwl_write_direct32(trans,
 375                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 376                            (iwl_get_dma_hi_addr(phy_addr)
 377                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 378
 379         iwl_write_direct32(trans,
 380                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 381                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 382                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 383                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 384
 385         iwl_write_direct32(trans,
 386                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 387                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 388                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 389                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 390
 391         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 392                                  trans_pcie->ucode_write_complete, 5 * HZ);
 393         if (!ret) {
 394                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 395                 return -ETIMEDOUT;
 396         }
 397
 398         return 0;
 399 }
 400
 401 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 402                             const struct fw_desc *section)
 403 {
 404         u8 *v_addr;
 405         dma_addr_t p_addr;
 406         u32 offset, chunk_sz = section->len;
 407         int ret = 0;
 408
 409         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 410                      section_num);
 411
 412         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 413                                     GFP_KERNEL | __GFP_NOWARN);
 414         if (!v_addr) {
 415                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 416                 chunk_sz = PAGE_SIZE;
 417                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 418                                             &p_addr, GFP_KERNEL);
 419                 if (!v_addr)
 420                         return -ENOMEM;
 421         }
 422
 423         for (offset = 0; offset < section->len; offset += chunk_sz) {
 424                 u32 copy_size;
 425
 426                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 427
 428                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 429                 ret = iwl_pcie_load_firmware_chunk(trans,
 430                                                    section->offset + offset,
 431                                                    p_addr, copy_size);
 432                 if (ret) {
 433                         IWL_ERR(trans,
 434                                 "Could not load the [%d] uCode section\n",
 435                                 section_num);
 436                         break;
 437                 }
 438         }
 439
 440         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 441         return ret;
 442 }
 443
 444 static int iwl_pcie_secure_set(struct iwl_trans *trans, int cpu)
 445 {
 446         int shift_param;
 447         u32 address;
 448         int ret = 0;
 449
 450         if (cpu == 1) {
 451                 shift_param = 0;
 452                 address = CSR_SECURE_BOOT_CPU1_STATUS_ADDR;
 453         } else {
 454                 shift_param = 16;
 455                 address = CSR_SECURE_BOOT_CPU2_STATUS_ADDR;
 456         }
 457
 458         /* set CPU to started */
 459         iwl_trans_set_bits_mask(trans,
 460                                 CSR_UCODE_LOAD_STATUS_ADDR,
 461                                 CSR_CPU_STATUS_LOADING_STARTED << shift_param,
 462                                 1);
 463
 464         /* set last complete descriptor number */
 465         iwl_trans_set_bits_mask(trans,
 466                                 CSR_UCODE_LOAD_STATUS_ADDR,
 467                                 CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED
 468                                 << shift_param,
 469                                 1);
 470
 471         /* set last loaded block */
 472         iwl_trans_set_bits_mask(trans,
 473                                 CSR_UCODE_LOAD_STATUS_ADDR,
 474                                 CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK
 475                                 << shift_param,
 476                                 1);
 477
 478         /* image loading complete */
 479         iwl_trans_set_bits_mask(trans,
 480                                 CSR_UCODE_LOAD_STATUS_ADDR,
 481                                 CSR_CPU_STATUS_LOADING_COMPLETED
 482                                 << shift_param,
 483                                 1);
 484
 485         /* set FH_TCSR_0_REG  */
 486         iwl_trans_set_bits_mask(trans, FH_TCSR_0_REG0, 0x00400000, 1);
 487
 488         /* verify image verification started  */
 489         ret = iwl_poll_bit(trans, address,
 490                            CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS,
 491                            CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS,
 492                            CSR_SECURE_TIME_OUT);
 493         if (ret < 0) {
 494                 IWL_ERR(trans, "secure boot process didn't start\n");
 495                 return ret;
 496         }
 497
 498         /* wait for image verification to complete  */
 499         ret = iwl_poll_bit(trans, address,
 500                            CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED,
 501                            CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED,
 502                            CSR_SECURE_TIME_OUT);
 503
 504         if (ret < 0) {
 505                 IWL_ERR(trans, "Time out on secure boot process\n");
 506                 return ret;
 507         }
 508
 509         return 0;
 510 }
 511
 512 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 513                                 const struct fw_img *image)
 514 {
 515         int i, ret = 0;
 516
 517         IWL_DEBUG_FW(trans,
 518                      "working with %s image\n",
 519                      image->is_secure ? "Secured" : "Non Secured");
 520         IWL_DEBUG_FW(trans,
 521                      "working with %s CPU\n",
 522                      image->is_dual_cpus ? "Dual" : "Single");
 523
 524         /* configure the ucode to be ready to get the secured image */
 525         if (image->is_secure) {
 526                 /* set secure boot inspector addresses */
 527                 iwl_write32(trans, CSR_SECURE_INSPECTOR_CODE_ADDR, 0);
 528                 iwl_write32(trans, CSR_SECURE_INSPECTOR_DATA_ADDR, 0);
 529
 530                 /* release CPU1 reset if secure inspector image burned in OTP */
 531                 iwl_write32(trans, CSR_RESET, 0);
 532         }
 533
 534         /* load to FW the binary sections of CPU1 */
 535         IWL_DEBUG_INFO(trans, "Loading CPU1\n");
 536         for (i = 0;
 537              i < IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU;
 538              i++) {
 539                 if (!image->sec[i].data)
 540                         break;
 541                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 542                 if (ret)
 543                         return ret;
 544         }
 545
 546         /* configure the ucode to start secure process on CPU1 */
 547         if (image->is_secure) {
 548                 /* config CPU1 to start secure protocol */
 549                 ret = iwl_pcie_secure_set(trans, 1);
 550                 if (ret)
 551                         return ret;
 552         } else {
 553                 /* Remove all resets to allow NIC to operate */
 554                 iwl_write32(trans, CSR_RESET, 0);
 555         }
 556
 557         if (image->is_dual_cpus) {
 558                 /* load to FW the binary sections of CPU2 */
 559                 IWL_DEBUG_INFO(trans, "working w/ DUAL CPUs - Loading CPU2\n");
 560                 for (i = IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU;
 561                         i < IWL_UCODE_SECTION_MAX; i++) {
 562                         if (!image->sec[i].data)
 563                                 break;
 564                         ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 565                         if (ret)
 566                                 return ret;
 567                 }
 568
 569                 if (image->is_secure) {
 570                         /* set CPU2 for secure protocol */
 571                         ret = iwl_pcie_secure_set(trans, 2);
 572                         if (ret)
 573                                 return ret;
 574                 }
 575         }
 576
 577         return 0;
 578 }
 579
 580 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 581                                    const struct fw_img *fw, bool run_in_rfkill)
 582 {
 583         int ret;
 584         bool hw_rfkill;
 585
 586         /* This may fail if AMT took ownership of the device */
 587         if (iwl_pcie_prepare_card_hw(trans)) {
 588                 IWL_WARN(trans, "Exit HW not ready\n");
 589                 return -EIO;
 590         }
 591
 592         iwl_enable_rfkill_int(trans);
 593
 594         /* If platform's RF_KILL switch is NOT set to KILL */
 595         hw_rfkill = iwl_is_rfkill_set(trans);
 596         if (hw_rfkill)
 597                 set_bit(STATUS_RFKILL, &trans->status);
 598         else
 599                 clear_bit(STATUS_RFKILL, &trans->status);
 600         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 601         if (hw_rfkill && !run_in_rfkill)
 602                 return -ERFKILL;
 603
 604         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 605
 606         ret = iwl_pcie_nic_init(trans);
 607         if (ret) {
 608                 IWL_ERR(trans, "Unable to init nic\n");
 609                 return ret;
 610         }
 611
 612         /* make sure rfkill handshake bits are cleared */
 613         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 614         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 615                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 616
 617         /* clear (again), then enable host interrupts */
 618         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 619         iwl_enable_interrupts(trans);
 620
 621         /* really make sure rfkill handshake bits are cleared */
 622         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 623         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 624
 625         /* Load the given image to the HW */
 626         return iwl_pcie_load_given_ucode(trans, fw);
 627 }
 628
 629 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 630 {
 631         iwl_pcie_reset_ict(trans);
 632         iwl_pcie_tx_start(trans, scd_addr);
 633 }
 634
 635 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 636 {
 637         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 638         bool hw_rfkill, was_hw_rfkill;
 639
 640         was_hw_rfkill = iwl_is_rfkill_set(trans);
 641
 642         /* tell the device to stop sending interrupts */
 643         spin_lock(&trans_pcie->irq_lock);
 644         iwl_disable_interrupts(trans);
 645         spin_unlock(&trans_pcie->irq_lock);
 646
 647         /* device going down, Stop using ICT table */
 648         iwl_pcie_disable_ict(trans);
 649
 650         /*
 651          * If a HW restart happens during firmware loading,
 652          * then the firmware loading might call this function
 653          * and later it might be called again due to the
 654          * restart. So don't process again if the device is
 655          * already dead.
 656          */
 657         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
 658                 iwl_pcie_tx_stop(trans);
 659                 iwl_pcie_rx_stop(trans);
 660
 661                 /* Power-down device's busmaster DMA clocks */
 662                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
 663                                APMG_CLK_VAL_DMA_CLK_RQT);
 664                 udelay(5);
 665         }
 666
 667         /* Make sure (redundant) we've released our request to stay awake */
 668         iwl_clear_bit(trans, CSR_GP_CNTRL,
 669                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 670
 671         /* Stop the device, and put it in low power state */
 672         iwl_pcie_apm_stop(trans);
 673
 674         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
 675          * Clean again the interrupt here
 676          */
 677         spin_lock(&trans_pcie->irq_lock);
 678         iwl_disable_interrupts(trans);
 679         spin_unlock(&trans_pcie->irq_lock);
 680
 681         /* stop and reset the on-board processor */
 682         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
 683
 684         /* clear all status bits */
 685         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
 686         clear_bit(STATUS_INT_ENABLED, &trans->status);
 687         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 688         clear_bit(STATUS_TPOWER_PMI, &trans->status);
 689         clear_bit(STATUS_RFKILL, &trans->status);
 690
 691         /*
 692          * Even if we stop the HW, we still want the RF kill
 693          * interrupt
 694          */
 695         iwl_enable_rfkill_int(trans);
 696
 697         /*
 698          * Check again since the RF kill state may have changed while
 699          * all the interrupts were disabled, in this case we couldn't
 700          * receive the RF kill interrupt and update the state in the
 701          * op_mode.
 702          * Don't call the op_mode if the rkfill state hasn't changed.
 703          * This allows the op_mode to call stop_device from the rfkill
 704          * notification without endless recursion. Under very rare
 705          * circumstances, we might have a small recursion if the rfkill
 706          * state changed exactly now while we were called from stop_device.
 707          * This is very unlikely but can happen and is supported.
 708          */
 709         hw_rfkill = iwl_is_rfkill_set(trans);
 710         if (hw_rfkill)
 711                 set_bit(STATUS_RFKILL, &trans->status);
 712         else
 713                 clear_bit(STATUS_RFKILL, &trans->status);
 714         if (hw_rfkill != was_hw_rfkill)
 715                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 716 }
 717
 718 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
 719 {
 720         iwl_disable_interrupts(trans);
 721
 722         /*
 723          * in testing mode, the host stays awake and the
 724          * hardware won't be reset (not even partially)
 725          */
 726         if (test)
 727                 return;
 728
 729         iwl_pcie_disable_ict(trans);
 730
 731         iwl_clear_bit(trans, CSR_GP_CNTRL,
 732                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 733         iwl_clear_bit(trans, CSR_GP_CNTRL,
 734                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 735
 736         /*
 737          * reset TX queues -- some of their registers reset during S3
 738          * so if we don't reset everything here the D3 image would try
 739          * to execute some invalid memory upon resume
 740          */
 741         iwl_trans_pcie_tx_reset(trans);
 742
 743         iwl_pcie_set_pwr(trans, true);
 744 }
 745
 746 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
 747                                     enum iwl_d3_status *status,
 748                                     bool test)
 749 {
 750         u32 val;
 751         int ret;
 752
 753         if (test) {
 754                 iwl_enable_interrupts(trans);
 755                 *status = IWL_D3_STATUS_ALIVE;
 756                 return 0;
 757         }
 758
 759         iwl_pcie_set_pwr(trans, false);
 760
 761         val = iwl_read32(trans, CSR_RESET);
 762         if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
 763                 *status = IWL_D3_STATUS_RESET;
 764                 return 0;
 765         }
 766
 767         /*
 768          * Also enables interrupts - none will happen as the device doesn't
 769          * know we're waking it up, only when the opmode actually tells it
 770          * after this call.
 771          */
 772         iwl_pcie_reset_ict(trans);
 773
 774         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 775         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 776
 777         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 778                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 779                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 780                            25000);
 781         if (ret) {
 782                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
 783                 return ret;
 784         }
 785
 786         iwl_trans_pcie_tx_reset(trans);
 787
 788         ret = iwl_pcie_rx_init(trans);
 789         if (ret) {
 790                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
 791                 return ret;
 792         }
 793
 794         *status = IWL_D3_STATUS_ALIVE;
 795         return 0;
 796 }
 797
 798 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
 799 {
 800         bool hw_rfkill;
 801         int err;
 802
 803         err = iwl_pcie_prepare_card_hw(trans);
 804         if (err) {
 805                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
 806                 return err;
 807         }
 808
 809         /* Reset the entire device */
 810         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 811
 812         usleep_range(10, 15);
 813
 814         iwl_pcie_apm_init(trans);
 815
 816         /* From now on, the op_mode will be kept updated about RF kill state */
 817         iwl_enable_rfkill_int(trans);
 818
 819         hw_rfkill = iwl_is_rfkill_set(trans);
 820         if (hw_rfkill)
 821                 set_bit(STATUS_RFKILL, &trans->status);
 822         else
 823                 clear_bit(STATUS_RFKILL, &trans->status);
 824         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 825
 826         return 0;
 827 }
 828
 829 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
 830 {
 831         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 832
 833         /* disable interrupts - don't enable HW RF kill interrupt */
 834         spin_lock(&trans_pcie->irq_lock);
 835         iwl_disable_interrupts(trans);
 836         spin_unlock(&trans_pcie->irq_lock);
 837
 838         iwl_pcie_apm_stop(trans);
 839
 840         spin_lock(&trans_pcie->irq_lock);
 841         iwl_disable_interrupts(trans);
 842         spin_unlock(&trans_pcie->irq_lock);
 843
 844         iwl_pcie_disable_ict(trans);
 845 }
 846
 847 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
 848 {
 849         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 850 }
 851
 852 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
 853 {
 854         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 855 }
 856
 857 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
 858 {
 859         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 860 }
 861
 862 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
 863 {
 864         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
 865                                ((reg & 0x000FFFFF) | (3 << 24)));
 866         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
 867 }
 868
 869 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
 870                                       u32 val)
 871 {
 872         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
 873                                ((addr & 0x000FFFFF) | (3 << 24)));
 874         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
 875 }
 876
 877 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
 878                                      const struct iwl_trans_config *trans_cfg)
 879 {
 880         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 881
 882         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
 883         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
 884         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
 885                 trans_pcie->n_no_reclaim_cmds = 0;
 886         else
 887                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
 888         if (trans_pcie->n_no_reclaim_cmds)
 889                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
 890                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
 891
 892         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
 893         if (trans_pcie->rx_buf_size_8k)
 894                 trans_pcie->rx_page_order = get_order(8 * 1024);
 895         else
 896                 trans_pcie->rx_page_order = get_order(4 * 1024);
 897
 898         trans_pcie->wd_timeout =
 899                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
 900
 901         trans_pcie->command_names = trans_cfg->command_names;
 902         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
 903 }
 904
 905 void iwl_trans_pcie_free(struct iwl_trans *trans)
 906 {
 907         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 908
 909         synchronize_irq(trans_pcie->pci_dev->irq);
 910
 911         iwl_pcie_tx_free(trans);
 912         iwl_pcie_rx_free(trans);
 913
 914         free_irq(trans_pcie->pci_dev->irq, trans);
 915         iwl_pcie_free_ict(trans);
 916
 917         pci_disable_msi(trans_pcie->pci_dev);
 918         iounmap(trans_pcie->hw_base);
 919         pci_release_regions(trans_pcie->pci_dev);
 920         pci_disable_device(trans_pcie->pci_dev);
 921         kmem_cache_destroy(trans->dev_cmd_pool);
 922
 923         kfree(trans);
 924 }
 925
 926 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
 927 {
 928         if (state)
 929                 set_bit(STATUS_TPOWER_PMI, &trans->status);
 930         else
 931                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
 932 }
 933
 934 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
 935                                                 unsigned long *flags)
 936 {
 937         int ret;
 938         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 939
 940         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
 941
 942         if (trans_pcie->cmd_in_flight)
 943                 goto out;
 944
 945         /* this bit wakes up the NIC */
 946         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 947                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 948
 949         /*
 950          * These bits say the device is running, and should keep running for
 951          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
 952          * but they do not indicate that embedded SRAM is restored yet;
 953          * 3945 and 4965 have volatile SRAM, and must save/restore contents
 954          * to/from host DRAM when sleeping/waking for power-saving.
 955          * Each direction takes approximately 1/4 millisecond; with this
 956          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
 957          * series of register accesses are expected (e.g. reading Event Log),
 958          * to keep device from sleeping.
 959          *
 960          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
 961          * SRAM is okay/restored.  We don't check that here because this call
 962          * is just for hardware register access; but GP1 MAC_SLEEP check is a
 963          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
 964          *
 965          * 5000 series and later (including 1000 series) have non-volatile SRAM,
 966          * and do not save/restore SRAM when power cycling.
 967          */
 968         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 969                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
 970                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
 971                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
 972         if (unlikely(ret < 0)) {
 973                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
 974                 if (!silent) {
 975                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
 976                         WARN_ONCE(1,
 977                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
 978                                   val);
 979                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
 980                         return false;
 981                 }
 982         }
 983
 984 out:
 985         /*
 986          * Fool sparse by faking we release the lock - sparse will
 987          * track nic_access anyway.
 988          */
 989         __release(&trans_pcie->reg_lock);
 990         return true;
 991 }
 992
 993 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
 994                                               unsigned long *flags)
 995 {
 996         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 997
 998         lockdep_assert_held(&trans_pcie->reg_lock);
 999
1000         /*
1001          * Fool sparse by faking we acquiring the lock - sparse will
1002          * track nic_access anyway.
1003          */
1004         __acquire(&trans_pcie->reg_lock);
1005
1006         if (trans_pcie->cmd_in_flight)
1007                 goto out;
1008
1009         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1010                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1011         /*
1012          * Above we read the CSR_GP_CNTRL register, which will flush
1013          * any previous writes, but we need the write that clears the
1014          * MAC_ACCESS_REQ bit to be performed before any other writes
1015          * scheduled on different CPUs (after we drop reg_lock).
1016          */
1017         mmiowb();
1018 out:
1019         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1020 }
1021
1022 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1023                                    void *buf, int dwords)
1024 {
1025         unsigned long flags;
1026         int offs, ret = 0;
1027         u32 *vals = buf;
1028
1029         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1030                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1031                 for (offs = 0; offs < dwords; offs++)
1032                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1033                 iwl_trans_release_nic_access(trans, &flags);
1034         } else {
1035                 ret = -EBUSY;
1036         }
1037         return ret;
1038 }
1039
1040 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1041                                     const void *buf, int dwords)
1042 {
1043         unsigned long flags;
1044         int offs, ret = 0;
1045         const u32 *vals = buf;
1046
1047         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1048                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1049                 for (offs = 0; offs < dwords; offs++)
1050                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1051                                     vals ? vals[offs] : 0);
1052                 iwl_trans_release_nic_access(trans, &flags);
1053         } else {
1054                 ret = -EBUSY;
1055         }
1056         return ret;
1057 }
1058
1059 #define IWL_FLUSH_WAIT_MS       2000
1060
1061 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
1062 {
1063         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1064         struct iwl_txq *txq;
1065         struct iwl_queue *q;
1066         int cnt;
1067         unsigned long now = jiffies;
1068         u32 scd_sram_addr;
1069         u8 buf[16];
1070         int ret = 0;
1071
1072         /* waiting for all the tx frames complete might take a while */
1073         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1074                 if (cnt == trans_pcie->cmd_queue)
1075                         continue;
1076                 txq = &trans_pcie->txq[cnt];
1077                 q = &txq->q;
1078                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1079                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1080                         msleep(1);
1081
1082                 if (q->read_ptr != q->write_ptr) {
1083                         IWL_ERR(trans,
1084                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1085                         ret = -ETIMEDOUT;
1086                         break;
1087                 }
1088         }
1089
1090         if (!ret)
1091                 return 0;
1092
1093         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1094                 txq->q.read_ptr, txq->q.write_ptr);
1095
1096         scd_sram_addr = trans_pcie->scd_base_addr +
1097                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1098         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1099
1100         iwl_print_hex_error(trans, buf, sizeof(buf));
1101
1102         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1103                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1104                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1105
1106         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1107                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1108                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1109                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1110                 u32 tbl_dw =
1111                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1112                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1113
1114                 if (cnt & 0x1)
1115                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1116                 else
1117                         tbl_dw = tbl_dw & 0x0000FFFF;
1118
1119                 IWL_ERR(trans,
1120                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1121                         cnt, active ? "" : "in", fifo, tbl_dw,
1122                         iwl_read_prph(trans,
1123                                       SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
1124                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1125         }
1126
1127         return ret;
1128 }
1129
1130 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1131                                          u32 mask, u32 value)
1132 {
1133         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1134         unsigned long flags;
1135
1136         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1137         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1138         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1139 }
1140
1141 static const char *get_csr_string(int cmd)
1142 {
1143 #define IWL_CMD(x) case x: return #x
1144         switch (cmd) {
1145         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1146         IWL_CMD(CSR_INT_COALESCING);
1147         IWL_CMD(CSR_INT);
1148         IWL_CMD(CSR_INT_MASK);
1149         IWL_CMD(CSR_FH_INT_STATUS);
1150         IWL_CMD(CSR_GPIO_IN);
1151         IWL_CMD(CSR_RESET);
1152         IWL_CMD(CSR_GP_CNTRL);
1153         IWL_CMD(CSR_HW_REV);
1154         IWL_CMD(CSR_EEPROM_REG);
1155         IWL_CMD(CSR_EEPROM_GP);
1156         IWL_CMD(CSR_OTP_GP_REG);
1157         IWL_CMD(CSR_GIO_REG);
1158         IWL_CMD(CSR_GP_UCODE_REG);
1159         IWL_CMD(CSR_GP_DRIVER_REG);
1160         IWL_CMD(CSR_UCODE_DRV_GP1);
1161         IWL_CMD(CSR_UCODE_DRV_GP2);
1162         IWL_CMD(CSR_LED_REG);
1163         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1164         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1165         IWL_CMD(CSR_ANA_PLL_CFG);
1166         IWL_CMD(CSR_HW_REV_WA_REG);
1167         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1168         default:
1169                 return "UNKNOWN";
1170         }
1171 #undef IWL_CMD
1172 }
1173
1174 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1175 {
1176         int i;
1177         static const u32 csr_tbl[] = {
1178                 CSR_HW_IF_CONFIG_REG,
1179                 CSR_INT_COALESCING,
1180                 CSR_INT,
1181                 CSR_INT_MASK,
1182                 CSR_FH_INT_STATUS,
1183                 CSR_GPIO_IN,
1184                 CSR_RESET,
1185                 CSR_GP_CNTRL,
1186                 CSR_HW_REV,
1187                 CSR_EEPROM_REG,
1188                 CSR_EEPROM_GP,
1189                 CSR_OTP_GP_REG,
1190                 CSR_GIO_REG,
1191                 CSR_GP_UCODE_REG,
1192                 CSR_GP_DRIVER_REG,
1193                 CSR_UCODE_DRV_GP1,
1194                 CSR_UCODE_DRV_GP2,
1195                 CSR_LED_REG,
1196                 CSR_DRAM_INT_TBL_REG,
1197                 CSR_GIO_CHICKEN_BITS,
1198                 CSR_ANA_PLL_CFG,
1199                 CSR_HW_REV_WA_REG,
1200                 CSR_DBG_HPET_MEM_REG
1201         };
1202         IWL_ERR(trans, "CSR values:\n");
1203         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1204                 "CSR_INT_PERIODIC_REG)\n");
1205         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1206                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1207                         get_csr_string(csr_tbl[i]),
1208                         iwl_read32(trans, csr_tbl[i]));
1209         }
1210 }
1211
1212 #ifdef CONFIG_IWLWIFI_DEBUGFS
1213 /* create and remove of files */
1214 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1215         if (!debugfs_create_file(#name, mode, parent, trans,            \
1216                                  &iwl_dbgfs_##name##_ops))              \
1217                 goto err;                                               \
1218 } while (0)
1219
1220 /* file operation */
1221 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1222 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1223         .read = iwl_dbgfs_##name##_read,                                \
1224         .open = simple_open,                                            \
1225         .llseek = generic_file_llseek,                                  \
1226 };
1227
1228 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1229 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1230         .write = iwl_dbgfs_##name##_write,                              \
1231         .open = simple_open,                                            \
1232         .llseek = generic_file_llseek,                                  \
1233 };
1234
1235 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1236 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1237         .write = iwl_dbgfs_##name##_write,                              \
1238         .read = iwl_dbgfs_##name##_read,                                \
1239         .open = simple_open,                                            \
1240         .llseek = generic_file_llseek,                                  \
1241 };
1242
1243 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1244                                        char __user *user_buf,
1245                                        size_t count, loff_t *ppos)
1246 {
1247         struct iwl_trans *trans = file->private_data;
1248         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1249         struct iwl_txq *txq;
1250         struct iwl_queue *q;
1251         char *buf;
1252         int pos = 0;
1253         int cnt;
1254         int ret;
1255         size_t bufsz;
1256
1257         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1258
1259         if (!trans_pcie->txq)
1260                 return -EAGAIN;
1261
1262         buf = kzalloc(bufsz, GFP_KERNEL);
1263         if (!buf)
1264                 return -ENOMEM;
1265
1266         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1267                 txq = &trans_pcie->txq[cnt];
1268                 q = &txq->q;
1269                 pos += scnprintf(buf + pos, bufsz - pos,
1270                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1271                                 cnt, q->read_ptr, q->write_ptr,
1272                                 !!test_bit(cnt, trans_pcie->queue_used),
1273                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1274         }
1275         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1276         kfree(buf);
1277         return ret;
1278 }
1279
1280 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1281                                        char __user *user_buf,
1282                                        size_t count, loff_t *ppos)
1283 {
1284         struct iwl_trans *trans = file->private_data;
1285         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1286         struct iwl_rxq *rxq = &trans_pcie->rxq;
1287         char buf[256];
1288         int pos = 0;
1289         const size_t bufsz = sizeof(buf);
1290
1291         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1292                                                 rxq->read);
1293         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1294                                                 rxq->write);
1295         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1296                                                 rxq->free_count);
1297         if (rxq->rb_stts) {
1298                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1299                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1300         } else {
1301                 pos += scnprintf(buf + pos, bufsz - pos,
1302                                         "closed_rb_num: Not Allocated\n");
1303         }
1304         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1305 }
1306
1307 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1308                                         char __user *user_buf,
1309                                         size_t count, loff_t *ppos)
1310 {
1311         struct iwl_trans *trans = file->private_data;
1312         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1313         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1314
1315         int pos = 0;
1316         char *buf;
1317         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1318         ssize_t ret;
1319
1320         buf = kzalloc(bufsz, GFP_KERNEL);
1321         if (!buf)
1322                 return -ENOMEM;
1323
1324         pos += scnprintf(buf + pos, bufsz - pos,
1325                         "Interrupt Statistics Report:\n");
1326
1327         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1328                 isr_stats->hw);
1329         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1330                 isr_stats->sw);
1331         if (isr_stats->sw || isr_stats->hw) {
1332                 pos += scnprintf(buf + pos, bufsz - pos,
1333                         "\tLast Restarting Code:  0x%X\n",
1334                         isr_stats->err_code);
1335         }
1336 #ifdef CONFIG_IWLWIFI_DEBUG
1337         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1338                 isr_stats->sch);
1339         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1340                 isr_stats->alive);
1341 #endif
1342         pos += scnprintf(buf + pos, bufsz - pos,
1343                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1344
1345         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1346                 isr_stats->ctkill);
1347
1348         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1349                 isr_stats->wakeup);
1350
1351         pos += scnprintf(buf + pos, bufsz - pos,
1352                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1353
1354         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1355                 isr_stats->tx);
1356
1357         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1358                 isr_stats->unhandled);
1359
1360         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1361         kfree(buf);
1362         return ret;
1363 }
1364
1365 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1366                                          const char __user *user_buf,
1367                                          size_t count, loff_t *ppos)
1368 {
1369         struct iwl_trans *trans = file->private_data;
1370         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1371         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1372
1373         char buf[8];
1374         int buf_size;
1375         u32 reset_flag;
1376
1377         memset(buf, 0, sizeof(buf));
1378         buf_size = min(count, sizeof(buf) -  1);
1379         if (copy_from_user(buf, user_buf, buf_size))
1380                 return -EFAULT;
1381         if (sscanf(buf, "%x", &reset_flag) != 1)
1382                 return -EFAULT;
1383         if (reset_flag == 0)
1384                 memset(isr_stats, 0, sizeof(*isr_stats));
1385
1386         return count;
1387 }
1388
1389 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1390                                    const char __user *user_buf,
1391                                    size_t count, loff_t *ppos)
1392 {
1393         struct iwl_trans *trans = file->private_data;
1394         char buf[8];
1395         int buf_size;
1396         int csr;
1397
1398         memset(buf, 0, sizeof(buf));
1399         buf_size = min(count, sizeof(buf) -  1);
1400         if (copy_from_user(buf, user_buf, buf_size))
1401                 return -EFAULT;
1402         if (sscanf(buf, "%d", &csr) != 1)
1403                 return -EFAULT;
1404
1405         iwl_pcie_dump_csr(trans);
1406
1407         return count;
1408 }
1409
1410 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1411                                      char __user *user_buf,
1412                                      size_t count, loff_t *ppos)
1413 {
1414         struct iwl_trans *trans = file->private_data;
1415         char *buf = NULL;
1416         int pos = 0;
1417         ssize_t ret = -EFAULT;
1418
1419         ret = pos = iwl_dump_fh(trans, &buf);
1420         if (buf) {
1421                 ret = simple_read_from_buffer(user_buf,
1422                                               count, ppos, buf, pos);
1423                 kfree(buf);
1424         }
1425
1426         return ret;
1427 }
1428
1429 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1430 DEBUGFS_READ_FILE_OPS(fh_reg);
1431 DEBUGFS_READ_FILE_OPS(rx_queue);
1432 DEBUGFS_READ_FILE_OPS(tx_queue);
1433 DEBUGFS_WRITE_FILE_OPS(csr);
1434
1435 /*
1436  * Create the debugfs files and directories
1437  *
1438  */
1439 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1440                                          struct dentry *dir)
1441 {
1442         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1443         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1444         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1445         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1446         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1447         return 0;
1448
1449 err:
1450         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1451         return -ENOMEM;
1452 }
1453 #else
1454 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1455                                          struct dentry *dir)
1456 {
1457         return 0;
1458 }
1459 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1460
1461 static const struct iwl_trans_ops trans_ops_pcie = {
1462         .start_hw = iwl_trans_pcie_start_hw,
1463         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
1464         .fw_alive = iwl_trans_pcie_fw_alive,
1465         .start_fw = iwl_trans_pcie_start_fw,
1466         .stop_device = iwl_trans_pcie_stop_device,
1467
1468         .d3_suspend = iwl_trans_pcie_d3_suspend,
1469         .d3_resume = iwl_trans_pcie_d3_resume,
1470
1471         .send_cmd = iwl_trans_pcie_send_hcmd,
1472
1473         .tx = iwl_trans_pcie_tx,
1474         .reclaim = iwl_trans_pcie_reclaim,
1475
1476         .txq_disable = iwl_trans_pcie_txq_disable,
1477         .txq_enable = iwl_trans_pcie_txq_enable,
1478
1479         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1480
1481         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1482
1483         .write8 = iwl_trans_pcie_write8,
1484         .write32 = iwl_trans_pcie_write32,
1485         .read32 = iwl_trans_pcie_read32,
1486         .read_prph = iwl_trans_pcie_read_prph,
1487         .write_prph = iwl_trans_pcie_write_prph,
1488         .read_mem = iwl_trans_pcie_read_mem,
1489         .write_mem = iwl_trans_pcie_write_mem,
1490         .configure = iwl_trans_pcie_configure,
1491         .set_pmi = iwl_trans_pcie_set_pmi,
1492         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1493         .release_nic_access = iwl_trans_pcie_release_nic_access,
1494         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
1495 };
1496
1497 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1498                                        const struct pci_device_id *ent,
1499                                        const struct iwl_cfg *cfg)
1500 {
1501         struct iwl_trans_pcie *trans_pcie;
1502         struct iwl_trans *trans;
1503         u16 pci_cmd;
1504         int err;
1505
1506         trans = kzalloc(sizeof(struct iwl_trans) +
1507                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1508         if (!trans) {
1509                 err = -ENOMEM;
1510                 goto out;
1511         }
1512
1513         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1514
1515         trans->ops = &trans_ops_pcie;
1516         trans->cfg = cfg;
1517         trans_lockdep_init(trans);
1518         trans_pcie->trans = trans;
1519         spin_lock_init(&trans_pcie->irq_lock);
1520         spin_lock_init(&trans_pcie->reg_lock);
1521         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1522
1523         err = pci_enable_device(pdev);
1524         if (err)
1525                 goto out_no_pci;
1526
1527         if (!cfg->base_params->pcie_l1_allowed) {
1528                 /*
1529                  * W/A - seems to solve weird behavior. We need to remove this
1530                  * if we don't want to stay in L1 all the time. This wastes a
1531                  * lot of power.
1532                  */
1533                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
1534                                        PCIE_LINK_STATE_L1 |
1535                                        PCIE_LINK_STATE_CLKPM);
1536         }
1537
1538         pci_set_master(pdev);
1539
1540         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1541         if (!err)
1542                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1543         if (err) {
1544                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1545                 if (!err)
1546                         err = pci_set_consistent_dma_mask(pdev,
1547                                                           DMA_BIT_MASK(32));
1548                 /* both attempts failed: */
1549                 if (err) {
1550                         dev_err(&pdev->dev, "No suitable DMA available\n");
1551                         goto out_pci_disable_device;
1552                 }
1553         }
1554
1555         err = pci_request_regions(pdev, DRV_NAME);
1556         if (err) {
1557                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1558                 goto out_pci_disable_device;
1559         }
1560
1561         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1562         if (!trans_pcie->hw_base) {
1563                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1564                 err = -ENODEV;
1565                 goto out_pci_release_regions;
1566         }
1567
1568         /* We disable the RETRY_TIMEOUT register (0x41) to keep
1569          * PCI Tx retries from interfering with C3 CPU state */
1570         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1571
1572         trans->dev = &pdev->dev;
1573         trans_pcie->pci_dev = pdev;
1574         iwl_disable_interrupts(trans);
1575
1576         err = pci_enable_msi(pdev);
1577         if (err) {
1578                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1579                 /* enable rfkill interrupt: hw bug w/a */
1580                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1581                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1582                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1583                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1584                 }
1585         }
1586
1587         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1588         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1589         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1590                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1591
1592         /* Initialize the wait queue for commands */
1593         init_waitqueue_head(&trans_pcie->wait_command_queue);
1594
1595         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1596                  "iwl_cmd_pool:%s", dev_name(trans->dev));
1597
1598         trans->dev_cmd_headroom = 0;
1599         trans->dev_cmd_pool =
1600                 kmem_cache_create(trans->dev_cmd_pool_name,
1601                                   sizeof(struct iwl_device_cmd)
1602                                   + trans->dev_cmd_headroom,
1603                                   sizeof(void *),
1604                                   SLAB_HWCACHE_ALIGN,
1605                                   NULL);
1606
1607         if (!trans->dev_cmd_pool) {
1608                 err = -ENOMEM;
1609                 goto out_pci_disable_msi;
1610         }
1611
1612         if (iwl_pcie_alloc_ict(trans))
1613                 goto out_free_cmd_pool;
1614
1615         err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
1616                                    iwl_pcie_irq_handler,
1617                                    IRQF_SHARED, DRV_NAME, trans);
1618         if (err) {
1619                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1620                 goto out_free_ict;
1621         }
1622
1623         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1624
1625         return trans;
1626
1627 out_free_ict:
1628         iwl_pcie_free_ict(trans);
1629 out_free_cmd_pool:
1630         kmem_cache_destroy(trans->dev_cmd_pool);
1631 out_pci_disable_msi:
1632         pci_disable_msi(pdev);
1633 out_pci_release_regions:
1634         pci_release_regions(pdev);
1635 out_pci_disable_device:
1636         pci_disable_device(pdev);
1637 out_no_pci:
1638         kfree(trans);
1639 out:
1640         return ERR_PTR(err);
1641 }