drivers/net/wireless/iwlwifi/pcie/rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 #include "iwl-prph.h"
  34 #include "iwl-io.h"
  35 #include "internal.h"
  36 #include "iwl-op-mode.h"
  37
  38 /******************************************************************************
  39  *
  40  * RX path functions
  41  *
  42  ******************************************************************************/
  43
  44 /*
  45  * Rx theory of operation
  46  *
  47  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  48  * each of which point to Receive Buffers to be filled by the NIC.  These get
  49  * used not only for Rx frames, but for any command response or notification
  50  * from the NIC.  The driver and NIC manage the Rx buffers by means
  51  * of indexes into the circular buffer.
  52  *
  53  * Rx Queue Indexes
  54  * The host/firmware share two index registers for managing the Rx buffers.
  55  *
  56  * The READ index maps to the first position that the firmware may be writing
  57  * to -- the driver can read up to (but not including) this position and get
  58  * good data.
  59  * The READ index is managed by the firmware once the card is enabled.
  60  *
  61  * The WRITE index maps to the last position the driver has read from -- the
  62  * position preceding WRITE is the last slot the firmware can place a packet.
  63  *
  64  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  65  * WRITE = READ.
  66  *
  67  * During initialization, the host sets up the READ queue position to the first
  68  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  69  *
  70  * When the firmware places a packet in a buffer, it will advance the READ index
  71  * and fire the RX interrupt.  The driver can then query the READ index and
  72  * process as many packets as possible, moving the WRITE index forward as it
  73  * resets the Rx queue buffers with new memory.
  74  *
  75  * The management in the driver is as follows:
  76  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  77  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  78  *   to replenish the iwl->rxq->rx_free.
  79  * + In iwl_pcie_rx_replenish (scheduled) if 'processed' != 'read' then the
  80  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  81  *   'processed' and 'read' driver indexes as well)
  82  * + A received packet is processed and handed to the kernel network stack,
  83  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  84  * + The Host/Firmware iwl->rxq is replenished at irq thread time from the
  85  *   rx_free list. If there are no allocated buffers in iwl->rxq->rx_free,
  86  *   the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
  87  *   If there were enough free buffers and RX_STALLED is set it is cleared.
  88  *
  89  *
  90  * Driver sequence:
  91  *
  92  * iwl_rxq_alloc()            Allocates rx_free
  93  * iwl_pcie_rx_replenish()    Replenishes rx_free list from rx_used, and calls
  94  *                            iwl_pcie_rxq_restock
  95  * iwl_pcie_rxq_restock()     Moves available buffers from rx_free into Rx
  96  *                            queue, updates firmware pointers, and updates
  97  *                            the WRITE index.  If insufficient rx_free buffers
  98  *                            are available, schedules iwl_pcie_rx_replenish
  99  *
 100  * -- enable interrupts --
 101  * ISR - iwl_rx()             Detach iwl_rx_mem_buffers from pool up to the
 102  *                            READ INDEX, detaching the SKB from the pool.
 103  *                            Moves the packet buffer from queue to rx_used.
 104  *                            Calls iwl_pcie_rxq_restock to refill any empty
 105  *                            slots.
 106  * ...
 107  *
 108  */
 109
 110 /*
 111  * iwl_rxq_space - Return number of free slots available in queue.
 112  */
 113 static int iwl_rxq_space(const struct iwl_rxq *rxq)
 114 {
 115         /* Make sure RX_QUEUE_SIZE is a power of 2 */
 116         BUILD_BUG_ON(RX_QUEUE_SIZE & (RX_QUEUE_SIZE - 1));
 117
 118         /*
 119          * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
 120          * between empty and completely full queues.
 121          * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
 122          * defined for negative dividends.
 123          */
 124         return (rxq->read - rxq->write - 1) & (RX_QUEUE_SIZE - 1);
 125 }
 126
 127 /*
 128  * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 129  */
 130 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 131 {
 132         return cpu_to_le32((u32)(dma_addr >> 8));
 133 }
 134
 135 /*
 136  * iwl_pcie_rx_stop - stops the Rx DMA
 137  */
 138 int iwl_pcie_rx_stop(struct iwl_trans *trans)
 139 {
 140         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 141         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 142                                    FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 143 }
 144
 145 /*
 146  * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
 147  */
 148 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
 149                                     struct iwl_rxq *rxq)
 150 {
 151         u32 reg;
 152
 153         spin_lock(&rxq->lock);
 154
 155         if (rxq->need_update == 0)
 156                 goto exit_unlock;
 157
 158         if (trans->cfg->base_params->shadow_reg_enable) {
 159                 /* shadow register enabled */
 160                 /* Device expects a multiple of 8 */
 161                 rxq->write_actual = (rxq->write & ~0x7);
 162                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
 163         } else {
 164                 /* If power-saving is in use, make sure device is awake */
 165                 if (test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 166                         reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 167
 168                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 169                                 IWL_DEBUG_INFO(trans,
 170                                         "Rx queue requesting wakeup,"
 171                                         " GP1 = 0x%x\n", reg);
 172                                 iwl_set_bit(trans, CSR_GP_CNTRL,
 173                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 174                                 goto exit_unlock;
 175                         }
 176
 177                         rxq->write_actual = (rxq->write & ~0x7);
 178                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 179                                            rxq->write_actual);
 180
 181                 /* Else device is assumed to be awake */
 182                 } else {
 183                         /* Device expects a multiple of 8 */
 184                         rxq->write_actual = (rxq->write & ~0x7);
 185                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 186                                            rxq->write_actual);
 187                 }
 188         }
 189         rxq->need_update = 0;
 190
 191  exit_unlock:
 192         spin_unlock(&rxq->lock);
 193 }
 194
 195 /*
 196  * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
 197  *
 198  * If there are slots in the RX queue that need to be restocked,
 199  * and we have free pre-allocated buffers, fill the ranks as much
 200  * as we can, pulling from rx_free.
 201  *
 202  * This moves the 'write' index forward to catch up with 'processed', and
 203  * also updates the memory address in the firmware to reference the new
 204  * target buffer.
 205  */
 206 static void iwl_pcie_rxq_restock(struct iwl_trans *trans)
 207 {
 208         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 209         struct iwl_rxq *rxq = &trans_pcie->rxq;
 210         struct iwl_rx_mem_buffer *rxb;
 211
 212         /*
 213          * If the device isn't enabled - not need to try to add buffers...
 214          * This can happen when we stop the device and still have an interrupt
 215          * pending. We stop the APM before we sync the interrupts because we
 216          * have to (see comment there). On the other hand, since the APM is
 217          * stopped, we cannot access the HW (in particular not prph).
 218          * So don't try to restock if the APM has been already stopped.
 219          */
 220         if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 221                 return;
 222
 223         spin_lock(&rxq->lock);
 224         while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
 225                 /* The overwritten rxb must be a used one */
 226                 rxb = rxq->queue[rxq->write];
 227                 BUG_ON(rxb && rxb->page);
 228
 229                 /* Get next free Rx buffer, remove from free list */
 230                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 231                                        list);
 232                 list_del(&rxb->list);
 233
 234                 /* Point to Rx buffer via next RBD in circular buffer */
 235                 rxq->bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
 236                 rxq->queue[rxq->write] = rxb;
 237                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 238                 rxq->free_count--;
 239         }
 240         spin_unlock(&rxq->lock);
 241         /* If the pre-allocated buffer pool is dropping low, schedule to
 242          * refill it */
 243         if (rxq->free_count <= RX_LOW_WATERMARK)
 244                 schedule_work(&trans_pcie->rx_replenish);
 245
 246         /* If we've added more space for the firmware to place data, tell it.
 247          * Increment device's write pointer in multiples of 8. */
 248         if (rxq->write_actual != (rxq->write & ~0x7)) {
 249                 spin_lock(&rxq->lock);
 250                 rxq->need_update = 1;
 251                 spin_unlock(&rxq->lock);
 252                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 253         }
 254 }
 255
 256 /*
 257  * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
 258  *
 259  * A used RBD is an Rx buffer that has been given to the stack. To use it again
 260  * a page must be allocated and the RBD must point to the page. This function
 261  * doesn't change the HW pointer but handles the list of pages that is used by
 262  * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
 263  * allocated buffers.
 264  */
 265 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority)
 266 {
 267         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 268         struct iwl_rxq *rxq = &trans_pcie->rxq;
 269         struct iwl_rx_mem_buffer *rxb;
 270         struct page *page;
 271         gfp_t gfp_mask = priority;
 272
 273         while (1) {
 274                 spin_lock(&rxq->lock);
 275                 if (list_empty(&rxq->rx_used)) {
 276                         spin_unlock(&rxq->lock);
 277                         return;
 278                 }
 279                 spin_unlock(&rxq->lock);
 280
 281                 if (rxq->free_count > RX_LOW_WATERMARK)
 282                         gfp_mask |= __GFP_NOWARN;
 283
 284                 if (trans_pcie->rx_page_order > 0)
 285                         gfp_mask |= __GFP_COMP;
 286
 287                 /* Alloc a new receive buffer */
 288                 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
 289                 if (!page) {
 290                         if (net_ratelimit())
 291                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 292                                            "order: %d\n",
 293                                            trans_pcie->rx_page_order);
 294
 295                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 296                             net_ratelimit())
 297                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 298                                          "Only %u free buffers remaining.\n",
 299                                          priority == GFP_ATOMIC ?
 300                                          "GFP_ATOMIC" : "GFP_KERNEL",
 301                                          rxq->free_count);
 302                         /* We don't reschedule replenish work here -- we will
 303                          * call the restock method and if it still needs
 304                          * more buffers it will schedule replenish */
 305                         return;
 306                 }
 307
 308                 spin_lock(&rxq->lock);
 309
 310                 if (list_empty(&rxq->rx_used)) {
 311                         spin_unlock(&rxq->lock);
 312                         __free_pages(page, trans_pcie->rx_page_order);
 313                         return;
 314                 }
 315                 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
 316                                        list);
 317                 list_del(&rxb->list);
 318                 spin_unlock(&rxq->lock);
 319
 320                 BUG_ON(rxb->page);
 321                 rxb->page = page;
 322                 /* Get physical address of the RB */
 323                 rxb->page_dma =
 324                         dma_map_page(trans->dev, page, 0,
 325                                      PAGE_SIZE << trans_pcie->rx_page_order,
 326                                      DMA_FROM_DEVICE);
 327                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 328                         rxb->page = NULL;
 329                         spin_lock(&rxq->lock);
 330                         list_add(&rxb->list, &rxq->rx_used);
 331                         spin_unlock(&rxq->lock);
 332                         __free_pages(page, trans_pcie->rx_page_order);
 333                         return;
 334                 }
 335                 /* dma address must be no more than 36 bits */
 336                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 337                 /* and also 256 byte aligned! */
 338                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 339
 340                 spin_lock(&rxq->lock);
 341
 342                 list_add_tail(&rxb->list, &rxq->rx_free);
 343                 rxq->free_count++;
 344
 345                 spin_unlock(&rxq->lock);
 346         }
 347 }
 348
 349 static void iwl_pcie_rxq_free_rbs(struct iwl_trans *trans)
 350 {
 351         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 352         struct iwl_rxq *rxq = &trans_pcie->rxq;
 353         int i;
 354
 355         lockdep_assert_held(&rxq->lock);
 356
 357         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 358                 if (!rxq->pool[i].page)
 359                         continue;
 360                 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 361                                PAGE_SIZE << trans_pcie->rx_page_order,
 362                                DMA_FROM_DEVICE);
 363                 __free_pages(rxq->pool[i].page, trans_pcie->rx_page_order);
 364                 rxq->pool[i].page = NULL;
 365         }
 366 }
 367
 368 /*
 369  * iwl_pcie_rx_replenish - Move all used buffers from rx_used to rx_free
 370  *
 371  * When moving to rx_free an page is allocated for the slot.
 372  *
 373  * Also restock the Rx queue via iwl_pcie_rxq_restock.
 374  * This is called as a scheduled work item (except for during initialization)
 375  */
 376 static void iwl_pcie_rx_replenish(struct iwl_trans *trans)
 377 {
 378         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 379
 380         iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL);
 381
 382         spin_lock(&trans_pcie->irq_lock);
 383         iwl_pcie_rxq_restock(trans);
 384         spin_unlock(&trans_pcie->irq_lock);
 385 }
 386
 387 static void iwl_pcie_rx_replenish_now(struct iwl_trans *trans)
 388 {
 389         iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC);
 390
 391         iwl_pcie_rxq_restock(trans);
 392 }
 393
 394 static void iwl_pcie_rx_replenish_work(struct work_struct *data)
 395 {
 396         struct iwl_trans_pcie *trans_pcie =
 397             container_of(data, struct iwl_trans_pcie, rx_replenish);
 398
 399         iwl_pcie_rx_replenish(trans_pcie->trans);
 400 }
 401
 402 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
 403 {
 404         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 405         struct iwl_rxq *rxq = &trans_pcie->rxq;
 406         struct device *dev = trans->dev;
 407
 408         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
 409
 410         spin_lock_init(&rxq->lock);
 411
 412         if (WARN_ON(rxq->bd || rxq->rb_stts))
 413                 return -EINVAL;
 414
 415         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
 416         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 417                                       &rxq->bd_dma, GFP_KERNEL);
 418         if (!rxq->bd)
 419                 goto err_bd;
 420
 421         /*Allocate the driver's pointer to receive buffer status */
 422         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 423                                            &rxq->rb_stts_dma, GFP_KERNEL);
 424         if (!rxq->rb_stts)
 425                 goto err_rb_stts;
 426
 427         return 0;
 428
 429 err_rb_stts:
 430         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 431                           rxq->bd, rxq->bd_dma);
 432         rxq->bd_dma = 0;
 433         rxq->bd = NULL;
 434 err_bd:
 435         return -ENOMEM;
 436 }
 437
 438 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
 439 {
 440         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 441         u32 rb_size;
 442         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 443
 444         if (trans_pcie->rx_buf_size_8k)
 445                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 446         else
 447                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 448
 449         /* Stop Rx DMA */
 450         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 451         /* reset and flush pointers */
 452         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
 453         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
 454         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
 455
 456         /* Reset driver's Rx queue write index */
 457         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 458
 459         /* Tell device where to find RBD circular buffer in DRAM */
 460         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 461                            (u32)(rxq->bd_dma >> 8));
 462
 463         /* Tell device where in DRAM to update its Rx status */
 464         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 465                            rxq->rb_stts_dma >> 4);
 466
 467         /* Enable Rx DMA
 468          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 469          *      the credit mechanism in 5000 HW RX FIFO
 470          * Direct rx interrupts to hosts
 471          * Rx buffer size 4 or 8k
 472          * RB timeout 0x10
 473          * 256 RBDs
 474          */
 475         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 476                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 477                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 478                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 479                            rb_size|
 480                            (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 481                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 482
 483         /* Set interrupt coalescing timer to default (2048 usecs) */
 484         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 485
 486         /* W/A for interrupt coalescing bug in 7260 and 3160 */
 487         if (trans->cfg->host_interrupt_operation_mode)
 488                 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
 489 }
 490
 491 static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
 492 {
 493         int i;
 494
 495         lockdep_assert_held(&rxq->lock);
 496
 497         INIT_LIST_HEAD(&rxq->rx_free);
 498         INIT_LIST_HEAD(&rxq->rx_used);
 499         rxq->free_count = 0;
 500
 501         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
 502                 list_add(&rxq->pool[i].list, &rxq->rx_used);
 503 }
 504
 505 int iwl_pcie_rx_init(struct iwl_trans *trans)
 506 {
 507         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 508         struct iwl_rxq *rxq = &trans_pcie->rxq;
 509         int i, err;
 510
 511         if (!rxq->bd) {
 512                 err = iwl_pcie_rx_alloc(trans);
 513                 if (err)
 514                         return err;
 515         }
 516
 517         spin_lock(&rxq->lock);
 518
 519         INIT_WORK(&trans_pcie->rx_replenish, iwl_pcie_rx_replenish_work);
 520
 521         /* free all first - we might be reconfigured for a different size */
 522         iwl_pcie_rxq_free_rbs(trans);
 523         iwl_pcie_rx_init_rxb_lists(rxq);
 524
 525         for (i = 0; i < RX_QUEUE_SIZE; i++)
 526                 rxq->queue[i] = NULL;
 527
 528         /* Set us so that we have processed and used all buffers, but have
 529          * not restocked the Rx queue with fresh buffers */
 530         rxq->read = rxq->write = 0;
 531         rxq->write_actual = 0;
 532         memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
 533         spin_unlock(&rxq->lock);
 534
 535         iwl_pcie_rx_replenish(trans);
 536
 537         iwl_pcie_rx_hw_init(trans, rxq);
 538
 539         spin_lock(&trans_pcie->irq_lock);
 540         rxq->need_update = 1;
 541         iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 542         spin_unlock(&trans_pcie->irq_lock);
 543
 544         return 0;
 545 }
 546
 547 void iwl_pcie_rx_free(struct iwl_trans *trans)
 548 {
 549         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 550         struct iwl_rxq *rxq = &trans_pcie->rxq;
 551
 552         /*if rxq->bd is NULL, it means that nothing has been allocated,
 553          * exit now */
 554         if (!rxq->bd) {
 555                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 556                 return;
 557         }
 558
 559         cancel_work_sync(&trans_pcie->rx_replenish);
 560
 561         spin_lock(&rxq->lock);
 562         iwl_pcie_rxq_free_rbs(trans);
 563         spin_unlock(&rxq->lock);
 564
 565         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 566                           rxq->bd, rxq->bd_dma);
 567         rxq->bd_dma = 0;
 568         rxq->bd = NULL;
 569
 570         if (rxq->rb_stts)
 571                 dma_free_coherent(trans->dev,
 572                                   sizeof(struct iwl_rb_status),
 573                                   rxq->rb_stts, rxq->rb_stts_dma);
 574         else
 575                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 576         rxq->rb_stts_dma = 0;
 577         rxq->rb_stts = NULL;
 578 }
 579
 580 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
 581                                 struct iwl_rx_mem_buffer *rxb)
 582 {
 583         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 584         struct iwl_rxq *rxq = &trans_pcie->rxq;
 585         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
 586         bool page_stolen = false;
 587         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
 588         u32 offset = 0;
 589
 590         if (WARN_ON(!rxb))
 591                 return;
 592
 593         dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
 594
 595         while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
 596                 struct iwl_rx_packet *pkt;
 597                 struct iwl_device_cmd *cmd;
 598                 u16 sequence;
 599                 bool reclaim;
 600                 int index, cmd_index, err, len;
 601                 struct iwl_rx_cmd_buffer rxcb = {
 602                         ._offset = offset,
 603                         ._rx_page_order = trans_pcie->rx_page_order,
 604                         ._page = rxb->page,
 605                         ._page_stolen = false,
 606                         .truesize = max_len,
 607                 };
 608
 609                 pkt = rxb_addr(&rxcb);
 610
 611                 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID))
 612                         break;
 613
 614                 IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n",
 615                         rxcb._offset, get_cmd_string(trans_pcie, pkt->hdr.cmd),
 616                         pkt->hdr.cmd);
 617
 618                 len = iwl_rx_packet_len(pkt);
 619                 len += sizeof(u32); /* account for status word */
 620                 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
 621                 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
 622
 623                 /* Reclaim a command buffer only if this packet is a response
 624                  *   to a (driver-originated) command.
 625                  * If the packet (e.g. Rx frame) originated from uCode,
 626                  *   there is no command buffer to reclaim.
 627                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 628                  *   but apparently a few don't get set; catch them here. */
 629                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
 630                 if (reclaim) {
 631                         int i;
 632
 633                         for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
 634                                 if (trans_pcie->no_reclaim_cmds[i] ==
 635                                                         pkt->hdr.cmd) {
 636                                         reclaim = false;
 637                                         break;
 638                                 }
 639                         }
 640                 }
 641
 642                 sequence = le16_to_cpu(pkt->hdr.sequence);
 643                 index = SEQ_TO_INDEX(sequence);
 644                 cmd_index = get_cmd_index(&txq->q, index);
 645
 646                 if (reclaim)
 647                         cmd = txq->entries[cmd_index].cmd;
 648                 else
 649                         cmd = NULL;
 650
 651                 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
 652
 653                 if (reclaim) {
 654                         kfree(txq->entries[cmd_index].free_buf);
 655                         txq->entries[cmd_index].free_buf = NULL;
 656                 }
 657
 658                 /*
 659                  * After here, we should always check rxcb._page_stolen,
 660                  * if it is true then one of the handlers took the page.
 661                  */
 662
 663                 if (reclaim) {
 664                         /* Invoke any callbacks, transfer the buffer to caller,
 665                          * and fire off the (possibly) blocking
 666                          * iwl_trans_send_cmd()
 667                          * as we reclaim the driver command queue */
 668                         if (!rxcb._page_stolen)
 669                                 iwl_pcie_hcmd_complete(trans, &rxcb, err);
 670                         else
 671                                 IWL_WARN(trans, "Claim null rxb?\n");
 672                 }
 673
 674                 page_stolen |= rxcb._page_stolen;
 675                 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
 676         }
 677
 678         /* page was stolen from us -- free our reference */
 679         if (page_stolen) {
 680                 __free_pages(rxb->page, trans_pcie->rx_page_order);
 681                 rxb->page = NULL;
 682         }
 683
 684         /* Reuse the page if possible. For notification packets and
 685          * SKBs that fail to Rx correctly, add them back into the
 686          * rx_free list for reuse later. */
 687         spin_lock(&rxq->lock);
 688         if (rxb->page != NULL) {
 689                 rxb->page_dma =
 690                         dma_map_page(trans->dev, rxb->page, 0,
 691                                      PAGE_SIZE << trans_pcie->rx_page_order,
 692                                      DMA_FROM_DEVICE);
 693                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 694                         /*
 695                          * free the page(s) as well to not break
 696                          * the invariant that the items on the used
 697                          * list have no page(s)
 698                          */
 699                         __free_pages(rxb->page, trans_pcie->rx_page_order);
 700                         rxb->page = NULL;
 701                         list_add_tail(&rxb->list, &rxq->rx_used);
 702                 } else {
 703                         list_add_tail(&rxb->list, &rxq->rx_free);
 704                         rxq->free_count++;
 705                 }
 706         } else
 707                 list_add_tail(&rxb->list, &rxq->rx_used);
 708         spin_unlock(&rxq->lock);
 709 }
 710
 711 /*
 712  * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
 713  */
 714 static void iwl_pcie_rx_handle(struct iwl_trans *trans)
 715 {
 716         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 717         struct iwl_rxq *rxq = &trans_pcie->rxq;
 718         u32 r, i;
 719         u8 fill_rx = 0;
 720         u32 count = 8;
 721         int total_empty;
 722
 723         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 724          * buffer that the driver may process (last buffer filled by ucode). */
 725         r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
 726         i = rxq->read;
 727
 728         /* Rx interrupt, but nothing sent from uCode */
 729         if (i == r)
 730                 IWL_DEBUG_RX(trans, "HW = SW = %d\n", r);
 731
 732         /* calculate total frames need to be restock after handling RX */
 733         total_empty = r - rxq->write_actual;
 734         if (total_empty < 0)
 735                 total_empty += RX_QUEUE_SIZE;
 736
 737         if (total_empty > (RX_QUEUE_SIZE / 2))
 738                 fill_rx = 1;
 739
 740         while (i != r) {
 741                 struct iwl_rx_mem_buffer *rxb;
 742
 743                 rxb = rxq->queue[i];
 744                 rxq->queue[i] = NULL;
 745
 746                 IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n",
 747                              r, i, rxb);
 748                 iwl_pcie_rx_handle_rb(trans, rxb);
 749
 750                 i = (i + 1) & RX_QUEUE_MASK;
 751                 /* If there are a lot of unused frames,
 752                  * restock the Rx queue so ucode wont assert. */
 753                 if (fill_rx) {
 754                         count++;
 755                         if (count >= 8) {
 756                                 rxq->read = i;
 757                                 iwl_pcie_rx_replenish_now(trans);
 758                                 count = 0;
 759                         }
 760                 }
 761         }
 762
 763         /* Backtrack one entry */
 764         rxq->read = i;
 765         if (fill_rx)
 766                 iwl_pcie_rx_replenish_now(trans);
 767         else
 768                 iwl_pcie_rxq_restock(trans);
 769 }
 770
 771 /*
 772  * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
 773  */
 774 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
 775 {
 776         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 777
 778         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 779         if (trans->cfg->internal_wimax_coex &&
 780             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
 781                              APMS_CLK_VAL_MRB_FUNC_MODE) ||
 782              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
 783                             APMG_PS_CTRL_VAL_RESET_REQ))) {
 784                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
 785                 iwl_op_mode_wimax_active(trans->op_mode);
 786                 wake_up(&trans_pcie->wait_command_queue);
 787                 return;
 788         }
 789
 790         iwl_pcie_dump_csr(trans);
 791         iwl_dump_fh(trans, NULL);
 792
 793         local_bh_disable();
 794         /* The STATUS_FW_ERROR bit is set in this function. This must happen
 795          * before we wake up the command caller, to ensure a proper cleanup. */
 796         iwl_trans_fw_error(trans);
 797         local_bh_enable();
 798
 799         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
 800         wake_up(&trans_pcie->wait_command_queue);
 801 }
 802
 803 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)
 804 {
 805         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 806         u32 inta;
 807
 808         lockdep_assert_held(&trans_pcie->irq_lock);
 809
 810         trace_iwlwifi_dev_irq(trans->dev);
 811
 812         /* Discover which interrupts are active/pending */
 813         inta = iwl_read32(trans, CSR_INT);
 814
 815         /* the thread will service interrupts and re-enable them */
 816         return inta;
 817 }
 818
 819 /* a device (PCI-E) page is 4096 bytes long */
 820 #define ICT_SHIFT       12
 821 #define ICT_SIZE        (1 << ICT_SHIFT)
 822 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
 823
 824 /* interrupt handler using ict table, with this interrupt driver will
 825  * stop using INTA register to get device's interrupt, reading this register
 826  * is expensive, device will write interrupts in ICT dram table, increment
 827  * index then will fire interrupt to driver, driver will OR all ICT table
 828  * entries from current index up to table entry with 0 value. the result is
 829  * the interrupt we need to service, driver will set the entries back to 0 and
 830  * set index.
 831  */
 832 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans)
 833 {
 834         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 835         u32 inta;
 836         u32 val = 0;
 837         u32 read;
 838
 839         trace_iwlwifi_dev_irq(trans->dev);
 840
 841         /* Ignore interrupt if there's nothing in NIC to service.
 842          * This may be due to IRQ shared with another device,
 843          * or due to sporadic interrupts thrown from our NIC. */
 844         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
 845         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
 846         if (!read)
 847                 return 0;
 848
 849         /*
 850          * Collect all entries up to the first 0, starting from ict_index;
 851          * note we already read at ict_index.
 852          */
 853         do {
 854                 val |= read;
 855                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
 856                                 trans_pcie->ict_index, read);
 857                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
 858                 trans_pcie->ict_index =
 859                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
 860
 861                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
 862                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
 863                                            read);
 864         } while (read);
 865
 866         /* We should not get this value, just ignore it. */
 867         if (val == 0xffffffff)
 868                 val = 0;
 869
 870         /*
 871          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
 872          * (bit 15 before shifting it to 31) to clear when using interrupt
 873          * coalescing. fortunately, bits 18 and 19 stay set when this happens
 874          * so we use them to decide on the real state of the Rx bit.
 875          * In order words, bit 15 is set if bit 18 or bit 19 are set.
 876          */
 877         if (val & 0xC0000)
 878                 val |= 0x8000;
 879
 880         inta = (0xff & val) | ((0xff00 & val) << 16);
 881         return inta;
 882 }
 883
 884 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
 885 {
 886         struct iwl_trans *trans = dev_id;
 887         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 888         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 889         u32 inta = 0;
 890         u32 handled = 0;
 891         u32 i;
 892
 893         lock_map_acquire(&trans->sync_cmd_lockdep_map);
 894
 895         spin_lock(&trans_pcie->irq_lock);
 896
 897         /* dram interrupt table not set yet,
 898          * use legacy interrupt.
 899          */
 900         if (likely(trans_pcie->use_ict))
 901                 inta = iwl_pcie_int_cause_ict(trans);
 902         else
 903                 inta = iwl_pcie_int_cause_non_ict(trans);
 904
 905         if (iwl_have_debug_level(IWL_DL_ISR)) {
 906                 IWL_DEBUG_ISR(trans,
 907                               "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
 908                               inta, trans_pcie->inta_mask,
 909                               iwl_read32(trans, CSR_INT_MASK),
 910                               iwl_read32(trans, CSR_FH_INT_STATUS));
 911                 if (inta & (~trans_pcie->inta_mask))
 912                         IWL_DEBUG_ISR(trans,
 913                                       "We got a masked interrupt (0x%08x)\n",
 914                                       inta & (~trans_pcie->inta_mask));
 915         }
 916
 917         inta &= trans_pcie->inta_mask;
 918
 919         /*
 920          * Ignore interrupt if there's nothing in NIC to service.
 921          * This may be due to IRQ shared with another device,
 922          * or due to sporadic interrupts thrown from our NIC.
 923          */
 924         if (unlikely(!inta)) {
 925                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
 926                 /*
 927                  * Re-enable interrupts here since we don't
 928                  * have anything to service
 929                  */
 930                 if (test_bit(STATUS_INT_ENABLED, &trans->status))
 931                         iwl_enable_interrupts(trans);
 932                 spin_unlock(&trans_pcie->irq_lock);
 933                 lock_map_release(&trans->sync_cmd_lockdep_map);
 934                 return IRQ_NONE;
 935         }
 936
 937         if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
 938                 /*
 939                  * Hardware disappeared. It might have
 940                  * already raised an interrupt.
 941                  */
 942                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
 943                 spin_unlock(&trans_pcie->irq_lock);
 944                 goto out;
 945         }
 946
 947         /* Ack/clear/reset pending uCode interrupts.
 948          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 949          */
 950         /* There is a hardware bug in the interrupt mask function that some
 951          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 952          * they are disabled in the CSR_INT_MASK register. Furthermore the
 953          * ICT interrupt handling mechanism has another bug that might cause
 954          * these unmasked interrupts fail to be detected. We workaround the
 955          * hardware bugs here by ACKing all the possible interrupts so that
 956          * interrupt coalescing can still be achieved.
 957          */
 958         iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
 959
 960         if (iwl_have_debug_level(IWL_DL_ISR))
 961                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
 962                               inta, iwl_read32(trans, CSR_INT_MASK));
 963
 964         spin_unlock(&trans_pcie->irq_lock);
 965
 966         /* Now service all interrupt bits discovered above. */
 967         if (inta & CSR_INT_BIT_HW_ERR) {
 968                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 969
 970                 /* Tell the device to stop sending interrupts */
 971                 iwl_disable_interrupts(trans);
 972
 973                 isr_stats->hw++;
 974                 iwl_pcie_irq_handle_error(trans);
 975
 976                 handled |= CSR_INT_BIT_HW_ERR;
 977
 978                 goto out;
 979         }
 980
 981         if (iwl_have_debug_level(IWL_DL_ISR)) {
 982                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 983                 if (inta & CSR_INT_BIT_SCD) {
 984                         IWL_DEBUG_ISR(trans,
 985                                       "Scheduler finished to transmit the frame/frames.\n");
 986                         isr_stats->sch++;
 987                 }
 988
 989                 /* Alive notification via Rx interrupt will do the real work */
 990                 if (inta & CSR_INT_BIT_ALIVE) {
 991                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
 992                         isr_stats->alive++;
 993                 }
 994         }
 995
 996         /* Safely ignore these bits for debug checks below */
 997         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 998
 999         /* HW RF KILL switch toggled */
1000         if (inta & CSR_INT_BIT_RF_KILL) {
1001                 bool hw_rfkill;
1002
1003                 hw_rfkill = iwl_is_rfkill_set(trans);
1004                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1005                          hw_rfkill ? "disable radio" : "enable radio");
1006
1007                 isr_stats->rfkill++;
1008
1009                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1010                 if (hw_rfkill) {
1011                         set_bit(STATUS_RFKILL, &trans->status);
1012                         if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE,
1013                                                &trans->status))
1014                                 IWL_DEBUG_RF_KILL(trans,
1015                                                   "Rfkill while SYNC HCMD in flight\n");
1016                         wake_up(&trans_pcie->wait_command_queue);
1017                 } else {
1018                         clear_bit(STATUS_RFKILL, &trans->status);
1019                 }
1020
1021                 handled |= CSR_INT_BIT_RF_KILL;
1022         }
1023
1024         /* Chip got too hot and stopped itself */
1025         if (inta & CSR_INT_BIT_CT_KILL) {
1026                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1027                 isr_stats->ctkill++;
1028                 handled |= CSR_INT_BIT_CT_KILL;
1029         }
1030
1031         /* Error detected by uCode */
1032         if (inta & CSR_INT_BIT_SW_ERR) {
1033                 IWL_ERR(trans, "Microcode SW error detected. "
1034                         " Restarting 0x%X.\n", inta);
1035                 isr_stats->sw++;
1036                 iwl_pcie_irq_handle_error(trans);
1037                 handled |= CSR_INT_BIT_SW_ERR;
1038         }
1039
1040         /* uCode wakes up after power-down sleep */
1041         if (inta & CSR_INT_BIT_WAKEUP) {
1042                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1043                 iwl_pcie_rxq_inc_wr_ptr(trans, &trans_pcie->rxq);
1044                 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++)
1045                         iwl_pcie_txq_inc_wr_ptr(trans, &trans_pcie->txq[i]);
1046
1047                 isr_stats->wakeup++;
1048
1049                 handled |= CSR_INT_BIT_WAKEUP;
1050         }
1051
1052         /* All uCode command responses, including Tx command responses,
1053          * Rx "responses" (frame-received notification), and other
1054          * notifications from uCode come through here*/
1055         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1056                     CSR_INT_BIT_RX_PERIODIC)) {
1057                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1058                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1059                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1060                         iwl_write32(trans, CSR_FH_INT_STATUS,
1061                                         CSR_FH_INT_RX_MASK);
1062                 }
1063                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1064                         handled |= CSR_INT_BIT_RX_PERIODIC;
1065                         iwl_write32(trans,
1066                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1067                 }
1068                 /* Sending RX interrupt require many steps to be done in the
1069                  * the device:
1070                  * 1- write interrupt to current index in ICT table.
1071                  * 2- dma RX frame.
1072                  * 3- update RX shared data to indicate last write index.
1073                  * 4- send interrupt.
1074                  * This could lead to RX race, driver could receive RX interrupt
1075                  * but the shared data changes does not reflect this;
1076                  * periodic interrupt will detect any dangling Rx activity.
1077                  */
1078
1079                 /* Disable periodic interrupt; we use it as just a one-shot. */
1080                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1081                             CSR_INT_PERIODIC_DIS);
1082
1083                 iwl_pcie_rx_handle(trans);
1084
1085                 /*
1086                  * Enable periodic interrupt in 8 msec only if we received
1087                  * real RX interrupt (instead of just periodic int), to catch
1088                  * any dangling Rx interrupt.  If it was just the periodic
1089                  * interrupt, there was no dangling Rx activity, and no need
1090                  * to extend the periodic interrupt; one-shot is enough.
1091                  */
1092                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1093                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
1094                                    CSR_INT_PERIODIC_ENA);
1095
1096                 isr_stats->rx++;
1097         }
1098
1099         /* This "Tx" DMA channel is used only for loading uCode */
1100         if (inta & CSR_INT_BIT_FH_TX) {
1101                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1102                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1103                 isr_stats->tx++;
1104                 handled |= CSR_INT_BIT_FH_TX;
1105                 /* Wake up uCode load routine, now that load is complete */
1106                 trans_pcie->ucode_write_complete = true;
1107                 wake_up(&trans_pcie->ucode_write_waitq);
1108         }
1109
1110         if (inta & ~handled) {
1111                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1112                 isr_stats->unhandled++;
1113         }
1114
1115         if (inta & ~(trans_pcie->inta_mask)) {
1116                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1117                          inta & ~trans_pcie->inta_mask);
1118         }
1119
1120         /* Re-enable all interrupts */
1121         /* only Re-enable if disabled by irq */
1122         if (test_bit(STATUS_INT_ENABLED, &trans->status))
1123                 iwl_enable_interrupts(trans);
1124         /* Re-enable RF_KILL if it occurred */
1125         else if (handled & CSR_INT_BIT_RF_KILL)
1126                 iwl_enable_rfkill_int(trans);
1127
1128 out:
1129         lock_map_release(&trans->sync_cmd_lockdep_map);
1130         return IRQ_HANDLED;
1131 }
1132
1133 /******************************************************************************
1134  *
1135  * ICT functions
1136  *
1137  ******************************************************************************/
1138
1139 /* Free dram table */
1140 void iwl_pcie_free_ict(struct iwl_trans *trans)
1141 {
1142         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1143
1144         if (trans_pcie->ict_tbl) {
1145                 dma_free_coherent(trans->dev, ICT_SIZE,
1146                                   trans_pcie->ict_tbl,
1147                                   trans_pcie->ict_tbl_dma);
1148                 trans_pcie->ict_tbl = NULL;
1149                 trans_pcie->ict_tbl_dma = 0;
1150         }
1151 }
1152
1153 /*
1154  * allocate dram shared table, it is an aligned memory
1155  * block of ICT_SIZE.
1156  * also reset all data related to ICT table interrupt.
1157  */
1158 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
1159 {
1160         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1161
1162         trans_pcie->ict_tbl =
1163                 dma_zalloc_coherent(trans->dev, ICT_SIZE,
1164                                    &trans_pcie->ict_tbl_dma,
1165                                    GFP_KERNEL);
1166         if (!trans_pcie->ict_tbl)
1167                 return -ENOMEM;
1168
1169         /* just an API sanity check ... it is guaranteed to be aligned */
1170         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1171                 iwl_pcie_free_ict(trans);
1172                 return -EINVAL;
1173         }
1174
1175         IWL_DEBUG_ISR(trans, "ict dma addr %Lx ict vir addr %p\n",
1176                       (unsigned long long)trans_pcie->ict_tbl_dma,
1177                       trans_pcie->ict_tbl);
1178
1179         return 0;
1180 }
1181
1182 /* Device is going up inform it about using ICT interrupt table,
1183  * also we need to tell the driver to start using ICT interrupt.
1184  */
1185 void iwl_pcie_reset_ict(struct iwl_trans *trans)
1186 {
1187         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1188         u32 val;
1189
1190         if (!trans_pcie->ict_tbl)
1191                 return;
1192
1193         spin_lock(&trans_pcie->irq_lock);
1194         iwl_disable_interrupts(trans);
1195
1196         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1197
1198         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1199
1200         val |= CSR_DRAM_INT_TBL_ENABLE;
1201         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1202
1203         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1204
1205         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1206         trans_pcie->use_ict = true;
1207         trans_pcie->ict_index = 0;
1208         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1209         iwl_enable_interrupts(trans);
1210         spin_unlock(&trans_pcie->irq_lock);
1211 }
1212
1213 /* Device is going down disable ict interrupt usage */
1214 void iwl_pcie_disable_ict(struct iwl_trans *trans)
1215 {
1216         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1217
1218         spin_lock(&trans_pcie->irq_lock);
1219         trans_pcie->use_ict = false;
1220         spin_unlock(&trans_pcie->irq_lock);
1221 }
1222
1223 irqreturn_t iwl_pcie_isr(int irq, void *data)
1224 {
1225         struct iwl_trans *trans = data;
1226
1227         if (!trans)
1228                 return IRQ_NONE;
1229
1230         /* Disable (but don't clear!) interrupts here to avoid
1231          * back-to-back ISRs and sporadic interrupts from our NIC.
1232          * If we have something to service, the tasklet will re-enable ints.
1233          * If we *don't* have something, we'll re-enable before leaving here.
1234          */
1235         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1236
1237         return IRQ_WAKE_THREAD;
1238 }