drivers/net/wireless/iwlwifi/pcie/rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 #include "iwl-prph.h"
  34 #include "iwl-io.h"
  35 #include "internal.h"
  36 #include "iwl-op-mode.h"
  37
  38 /******************************************************************************
  39  *
  40  * RX path functions
  41  *
  42  ******************************************************************************/
  43
  44 /*
  45  * Rx theory of operation
  46  *
  47  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  48  * each of which point to Receive Buffers to be filled by the NIC.  These get
  49  * used not only for Rx frames, but for any command response or notification
  50  * from the NIC.  The driver and NIC manage the Rx buffers by means
  51  * of indexes into the circular buffer.
  52  *
  53  * Rx Queue Indexes
  54  * The host/firmware share two index registers for managing the Rx buffers.
  55  *
  56  * The READ index maps to the first position that the firmware may be writing
  57  * to -- the driver can read up to (but not including) this position and get
  58  * good data.
  59  * The READ index is managed by the firmware once the card is enabled.
  60  *
  61  * The WRITE index maps to the last position the driver has read from -- the
  62  * position preceding WRITE is the last slot the firmware can place a packet.
  63  *
  64  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  65  * WRITE = READ.
  66  *
  67  * During initialization, the host sets up the READ queue position to the first
  68  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  69  *
  70  * When the firmware places a packet in a buffer, it will advance the READ index
  71  * and fire the RX interrupt.  The driver can then query the READ index and
  72  * process as many packets as possible, moving the WRITE index forward as it
  73  * resets the Rx queue buffers with new memory.
  74  *
  75  * The management in the driver is as follows:
  76  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  77  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  78  *   to replenish the iwl->rxq->rx_free.
  79  * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  80  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  81  *   'processed' and 'read' driver indexes as well)
  82  * + A received packet is processed and handed to the kernel network stack,
  83  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  84  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  85  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  86  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
  87  *   were enough free buffers and RX_STALLED is set it is cleared.
  88  *
  89  *
  90  * Driver sequence:
  91  *
  92  * iwl_rx_queue_alloc()   Allocates rx_free
  93  * iwl_rx_replenish()     Replenishes rx_free list from rx_used, and calls
  94  *                            iwl_rx_queue_restock
  95  * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  96  *                            queue, updates firmware pointers, and updates
  97  *                            the WRITE index.  If insufficient rx_free buffers
  98  *                            are available, schedules iwl_rx_replenish
  99  *
 100  * -- enable interrupts --
 101  * ISR - iwl_rx()         Detach iwl_rx_mem_buffers from pool up to the
 102  *                            READ INDEX, detaching the SKB from the pool.
 103  *                            Moves the packet buffer from queue to rx_used.
 104  *                            Calls iwl_rx_queue_restock to refill any empty
 105  *                            slots.
 106  * ...
 107  *
 108  */
 109
 110 /**
 111  * iwl_rx_queue_space - Return number of free slots available in queue.
 112  */
 113 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
 114 {
 115         int s = q->read - q->write;
 116         if (s <= 0)
 117                 s += RX_QUEUE_SIZE;
 118         /* keep some buffer to not confuse full and empty queue */
 119         s -= 2;
 120         if (s < 0)
 121                 s = 0;
 122         return s;
 123 }
 124
 125 /**
 126  * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
 127  */
 128 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
 129                                    struct iwl_rx_queue *q)
 130 {
 131         unsigned long flags;
 132         u32 reg;
 133
 134         spin_lock_irqsave(&q->lock, flags);
 135
 136         if (q->need_update == 0)
 137                 goto exit_unlock;
 138
 139         if (trans->cfg->base_params->shadow_reg_enable) {
 140                 /* shadow register enabled */
 141                 /* Device expects a multiple of 8 */
 142                 q->write_actual = (q->write & ~0x7);
 143                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
 144         } else {
 145                 struct iwl_trans_pcie *trans_pcie =
 146                         IWL_TRANS_GET_PCIE_TRANS(trans);
 147
 148                 /* If power-saving is in use, make sure device is awake */
 149                 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
 150                         reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 151
 152                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 153                                 IWL_DEBUG_INFO(trans,
 154                                         "Rx queue requesting wakeup,"
 155                                         " GP1 = 0x%x\n", reg);
 156                                 iwl_set_bit(trans, CSR_GP_CNTRL,
 157                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 158                                 goto exit_unlock;
 159                         }
 160
 161                         q->write_actual = (q->write & ~0x7);
 162                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 163                                         q->write_actual);
 164
 165                 /* Else device is assumed to be awake */
 166                 } else {
 167                         /* Device expects a multiple of 8 */
 168                         q->write_actual = (q->write & ~0x7);
 169                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 170                                 q->write_actual);
 171                 }
 172         }
 173         q->need_update = 0;
 174
 175  exit_unlock:
 176         spin_unlock_irqrestore(&q->lock, flags);
 177 }
 178
 179 /**
 180  * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 181  */
 182 static inline __le32 iwl_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 183 {
 184         return cpu_to_le32((u32)(dma_addr >> 8));
 185 }
 186
 187 /**
 188  * iwl_rx_queue_restock - refill RX queue from pre-allocated pool
 189  *
 190  * If there are slots in the RX queue that need to be restocked,
 191  * and we have free pre-allocated buffers, fill the ranks as much
 192  * as we can, pulling from rx_free.
 193  *
 194  * This moves the 'write' index forward to catch up with 'processed', and
 195  * also updates the memory address in the firmware to reference the new
 196  * target buffer.
 197  */
 198 static void iwl_rx_queue_restock(struct iwl_trans *trans)
 199 {
 200         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 201         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 202         struct list_head *element;
 203         struct iwl_rx_mem_buffer *rxb;
 204         unsigned long flags;
 205
 206         spin_lock_irqsave(&rxq->lock, flags);
 207         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 208                 /* The overwritten rxb must be a used one */
 209                 rxb = rxq->queue[rxq->write];
 210                 BUG_ON(rxb && rxb->page);
 211
 212                 /* Get next free Rx buffer, remove from free list */
 213                 element = rxq->rx_free.next;
 214                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 215                 list_del(element);
 216
 217                 /* Point to Rx buffer via next RBD in circular buffer */
 218                 rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(rxb->page_dma);
 219                 rxq->queue[rxq->write] = rxb;
 220                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 221                 rxq->free_count--;
 222         }
 223         spin_unlock_irqrestore(&rxq->lock, flags);
 224         /* If the pre-allocated buffer pool is dropping low, schedule to
 225          * refill it */
 226         if (rxq->free_count <= RX_LOW_WATERMARK)
 227                 schedule_work(&trans_pcie->rx_replenish);
 228
 229         /* If we've added more space for the firmware to place data, tell it.
 230          * Increment device's write pointer in multiples of 8. */
 231         if (rxq->write_actual != (rxq->write & ~0x7)) {
 232                 spin_lock_irqsave(&rxq->lock, flags);
 233                 rxq->need_update = 1;
 234                 spin_unlock_irqrestore(&rxq->lock, flags);
 235                 iwl_rx_queue_update_write_ptr(trans, rxq);
 236         }
 237 }
 238
 239 /*
 240  * iwl_rx_allocate - allocate a page for each used RBD
 241  *
 242  * A used RBD is an Rx buffer that has been given to the stack. To use it again
 243  * a page must be allocated and the RBD must point to the page. This function
 244  * doesn't change the HW pointer but handles the list of pages that is used by
 245  * iwl_rx_queue_restock. The latter function will update the HW to use the newly
 246  * allocated buffers.
 247  */
 248 static void iwl_rx_allocate(struct iwl_trans *trans, gfp_t priority)
 249 {
 250         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 251         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 252         struct list_head *element;
 253         struct iwl_rx_mem_buffer *rxb;
 254         struct page *page;
 255         unsigned long flags;
 256         gfp_t gfp_mask = priority;
 257
 258         while (1) {
 259                 spin_lock_irqsave(&rxq->lock, flags);
 260                 if (list_empty(&rxq->rx_used)) {
 261                         spin_unlock_irqrestore(&rxq->lock, flags);
 262                         return;
 263                 }
 264                 spin_unlock_irqrestore(&rxq->lock, flags);
 265
 266                 if (rxq->free_count > RX_LOW_WATERMARK)
 267                         gfp_mask |= __GFP_NOWARN;
 268
 269                 if (trans_pcie->rx_page_order > 0)
 270                         gfp_mask |= __GFP_COMP;
 271
 272                 /* Alloc a new receive buffer */
 273                 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
 274                 if (!page) {
 275                         if (net_ratelimit())
 276                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 277                                            "order: %d\n",
 278                                            trans_pcie->rx_page_order);
 279
 280                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 281                             net_ratelimit())
 282                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 283                                          "Only %u free buffers remaining.\n",
 284                                          priority == GFP_ATOMIC ?
 285                                          "GFP_ATOMIC" : "GFP_KERNEL",
 286                                          rxq->free_count);
 287                         /* We don't reschedule replenish work here -- we will
 288                          * call the restock method and if it still needs
 289                          * more buffers it will schedule replenish */
 290                         return;
 291                 }
 292
 293                 spin_lock_irqsave(&rxq->lock, flags);
 294
 295                 if (list_empty(&rxq->rx_used)) {
 296                         spin_unlock_irqrestore(&rxq->lock, flags);
 297                         __free_pages(page, trans_pcie->rx_page_order);
 298                         return;
 299                 }
 300                 element = rxq->rx_used.next;
 301                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 302                 list_del(element);
 303
 304                 spin_unlock_irqrestore(&rxq->lock, flags);
 305
 306                 BUG_ON(rxb->page);
 307                 rxb->page = page;
 308                 /* Get physical address of the RB */
 309                 rxb->page_dma =
 310                         dma_map_page(trans->dev, page, 0,
 311                                      PAGE_SIZE << trans_pcie->rx_page_order,
 312                                      DMA_FROM_DEVICE);
 313                 /* dma address must be no more than 36 bits */
 314                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 315                 /* and also 256 byte aligned! */
 316                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 317
 318                 spin_lock_irqsave(&rxq->lock, flags);
 319
 320                 list_add_tail(&rxb->list, &rxq->rx_free);
 321                 rxq->free_count++;
 322
 323                 spin_unlock_irqrestore(&rxq->lock, flags);
 324         }
 325 }
 326
 327 /*
 328  * iwl_rx_replenish - Move all used buffers from rx_used to rx_free
 329  *
 330  * When moving to rx_free an page is allocated for the slot.
 331  *
 332  * Also restock the Rx queue via iwl_rx_queue_restock.
 333  * This is called as a scheduled work item (except for during initialization)
 334  */
 335 void iwl_rx_replenish(struct iwl_trans *trans)
 336 {
 337         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 338         unsigned long flags;
 339
 340         iwl_rx_allocate(trans, GFP_KERNEL);
 341
 342         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 343         iwl_rx_queue_restock(trans);
 344         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 345 }
 346
 347 static void iwl_rx_replenish_now(struct iwl_trans *trans)
 348 {
 349         iwl_rx_allocate(trans, GFP_ATOMIC);
 350
 351         iwl_rx_queue_restock(trans);
 352 }
 353
 354 void iwl_bg_rx_replenish(struct work_struct *data)
 355 {
 356         struct iwl_trans_pcie *trans_pcie =
 357             container_of(data, struct iwl_trans_pcie, rx_replenish);
 358
 359         iwl_rx_replenish(trans_pcie->trans);
 360 }
 361
 362 static void iwl_rx_handle_rxbuf(struct iwl_trans *trans,
 363                                 struct iwl_rx_mem_buffer *rxb)
 364 {
 365         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 366         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 367         struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
 368         unsigned long flags;
 369         bool page_stolen = false;
 370         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
 371         u32 offset = 0;
 372
 373         if (WARN_ON(!rxb))
 374                 return;
 375
 376         dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
 377
 378         while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
 379                 struct iwl_rx_packet *pkt;
 380                 struct iwl_device_cmd *cmd;
 381                 u16 sequence;
 382                 bool reclaim;
 383                 int index, cmd_index, err, len;
 384                 struct iwl_rx_cmd_buffer rxcb = {
 385                         ._offset = offset,
 386                         ._page = rxb->page,
 387                         ._page_stolen = false,
 388                         .truesize = max_len,
 389                 };
 390
 391                 pkt = rxb_addr(&rxcb);
 392
 393                 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID))
 394                         break;
 395
 396                 IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n",
 397                         rxcb._offset,
 398                         trans_pcie_get_cmd_string(trans_pcie, pkt->hdr.cmd),
 399                         pkt->hdr.cmd);
 400
 401                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 402                 len += sizeof(u32); /* account for status word */
 403                 trace_iwlwifi_dev_rx(trans->dev, pkt, len);
 404
 405                 /* Reclaim a command buffer only if this packet is a response
 406                  *   to a (driver-originated) command.
 407                  * If the packet (e.g. Rx frame) originated from uCode,
 408                  *   there is no command buffer to reclaim.
 409                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 410                  *   but apparently a few don't get set; catch them here. */
 411                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
 412                 if (reclaim) {
 413                         int i;
 414
 415                         for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
 416                                 if (trans_pcie->no_reclaim_cmds[i] ==
 417                                                         pkt->hdr.cmd) {
 418                                         reclaim = false;
 419                                         break;
 420                                 }
 421                         }
 422                 }
 423
 424                 sequence = le16_to_cpu(pkt->hdr.sequence);
 425                 index = SEQ_TO_INDEX(sequence);
 426                 cmd_index = get_cmd_index(&txq->q, index);
 427
 428                 if (reclaim) {
 429                         struct iwl_pcie_tx_queue_entry *ent;
 430                         ent = &txq->entries[cmd_index];
 431                         cmd = ent->copy_cmd;
 432                         WARN_ON_ONCE(!cmd && ent->meta.flags & CMD_WANT_HCMD);
 433                 } else {
 434                         cmd = NULL;
 435                 }
 436
 437                 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
 438
 439                 if (reclaim) {
 440                         /* The original command isn't needed any more */
 441                         kfree(txq->entries[cmd_index].copy_cmd);
 442                         txq->entries[cmd_index].copy_cmd = NULL;
 443                 }
 444
 445                 /*
 446                  * After here, we should always check rxcb._page_stolen,
 447                  * if it is true then one of the handlers took the page.
 448                  */
 449
 450                 if (reclaim) {
 451                         /* Invoke any callbacks, transfer the buffer to caller,
 452                          * and fire off the (possibly) blocking
 453                          * iwl_trans_send_cmd()
 454                          * as we reclaim the driver command queue */
 455                         if (!rxcb._page_stolen)
 456                                 iwl_tx_cmd_complete(trans, &rxcb, err);
 457                         else
 458                                 IWL_WARN(trans, "Claim null rxb?\n");
 459                 }
 460
 461                 page_stolen |= rxcb._page_stolen;
 462                 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
 463         }
 464
 465         /* page was stolen from us -- free our reference */
 466         if (page_stolen) {
 467                 __free_pages(rxb->page, trans_pcie->rx_page_order);
 468                 rxb->page = NULL;
 469         }
 470
 471         /* Reuse the page if possible. For notification packets and
 472          * SKBs that fail to Rx correctly, add them back into the
 473          * rx_free list for reuse later. */
 474         spin_lock_irqsave(&rxq->lock, flags);
 475         if (rxb->page != NULL) {
 476                 rxb->page_dma =
 477                         dma_map_page(trans->dev, rxb->page, 0,
 478                                      PAGE_SIZE << trans_pcie->rx_page_order,
 479                                      DMA_FROM_DEVICE);
 480                 list_add_tail(&rxb->list, &rxq->rx_free);
 481                 rxq->free_count++;
 482         } else
 483                 list_add_tail(&rxb->list, &rxq->rx_used);
 484         spin_unlock_irqrestore(&rxq->lock, flags);
 485 }
 486
 487 /**
 488  * iwl_rx_handle - Main entry function for receiving responses from uCode
 489  *
 490  * Uses the priv->rx_handlers callback function array to invoke
 491  * the appropriate handlers, including command responses,
 492  * frame-received notifications, and other notifications.
 493  */
 494 static void iwl_rx_handle(struct iwl_trans *trans)
 495 {
 496         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 497         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 498         u32 r, i;
 499         u8 fill_rx = 0;
 500         u32 count = 8;
 501         int total_empty;
 502
 503         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 504          * buffer that the driver may process (last buffer filled by ucode). */
 505         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 506         i = rxq->read;
 507
 508         /* Rx interrupt, but nothing sent from uCode */
 509         if (i == r)
 510                 IWL_DEBUG_RX(trans, "HW = SW = %d\n", r);
 511
 512         /* calculate total frames need to be restock after handling RX */
 513         total_empty = r - rxq->write_actual;
 514         if (total_empty < 0)
 515                 total_empty += RX_QUEUE_SIZE;
 516
 517         if (total_empty > (RX_QUEUE_SIZE / 2))
 518                 fill_rx = 1;
 519
 520         while (i != r) {
 521                 struct iwl_rx_mem_buffer *rxb;
 522
 523                 rxb = rxq->queue[i];
 524                 rxq->queue[i] = NULL;
 525
 526                 IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n",
 527                              r, i, rxb);
 528                 iwl_rx_handle_rxbuf(trans, rxb);
 529
 530                 i = (i + 1) & RX_QUEUE_MASK;
 531                 /* If there are a lot of unused frames,
 532                  * restock the Rx queue so ucode wont assert. */
 533                 if (fill_rx) {
 534                         count++;
 535                         if (count >= 8) {
 536                                 rxq->read = i;
 537                                 iwl_rx_replenish_now(trans);
 538                                 count = 0;
 539                         }
 540                 }
 541         }
 542
 543         /* Backtrack one entry */
 544         rxq->read = i;
 545         if (fill_rx)
 546                 iwl_rx_replenish_now(trans);
 547         else
 548                 iwl_rx_queue_restock(trans);
 549 }
 550
 551 /**
 552  * iwl_irq_handle_error - called for HW or SW error interrupt from card
 553  */
 554 static void iwl_irq_handle_error(struct iwl_trans *trans)
 555 {
 556         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 557         if (trans->cfg->internal_wimax_coex &&
 558             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
 559                              APMS_CLK_VAL_MRB_FUNC_MODE) ||
 560              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
 561                             APMG_PS_CTRL_VAL_RESET_REQ))) {
 562                 struct iwl_trans_pcie *trans_pcie =
 563                         IWL_TRANS_GET_PCIE_TRANS(trans);
 564
 565                 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 566                 iwl_op_mode_wimax_active(trans->op_mode);
 567                 wake_up(&trans->wait_command_queue);
 568                 return;
 569         }
 570
 571         iwl_dump_csr(trans);
 572         iwl_dump_fh(trans, NULL, false);
 573
 574         iwl_op_mode_nic_error(trans->op_mode);
 575 }
 576
 577 /* tasklet for iwlagn interrupt */
 578 void iwl_irq_tasklet(struct iwl_trans *trans)
 579 {
 580         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 581         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 582         u32 inta = 0;
 583         u32 handled = 0;
 584         unsigned long flags;
 585         u32 i;
 586 #ifdef CONFIG_IWLWIFI_DEBUG
 587         u32 inta_mask;
 588 #endif
 589
 590         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 591
 592         /* Ack/clear/reset pending uCode interrupts.
 593          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 594          */
 595         /* There is a hardware bug in the interrupt mask function that some
 596          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 597          * they are disabled in the CSR_INT_MASK register. Furthermore the
 598          * ICT interrupt handling mechanism has another bug that might cause
 599          * these unmasked interrupts fail to be detected. We workaround the
 600          * hardware bugs here by ACKing all the possible interrupts so that
 601          * interrupt coalescing can still be achieved.
 602          */
 603         iwl_write32(trans, CSR_INT,
 604                     trans_pcie->inta | ~trans_pcie->inta_mask);
 605
 606         inta = trans_pcie->inta;
 607
 608 #ifdef CONFIG_IWLWIFI_DEBUG
 609         if (iwl_have_debug_level(IWL_DL_ISR)) {
 610                 /* just for debug */
 611                 inta_mask = iwl_read32(trans, CSR_INT_MASK);
 612                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
 613                               inta, inta_mask);
 614         }
 615 #endif
 616
 617         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 618         trans_pcie->inta = 0;
 619
 620         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 621
 622         /* Now service all interrupt bits discovered above. */
 623         if (inta & CSR_INT_BIT_HW_ERR) {
 624                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 625
 626                 /* Tell the device to stop sending interrupts */
 627                 iwl_disable_interrupts(trans);
 628
 629                 isr_stats->hw++;
 630                 iwl_irq_handle_error(trans);
 631
 632                 handled |= CSR_INT_BIT_HW_ERR;
 633
 634                 return;
 635         }
 636
 637 #ifdef CONFIG_IWLWIFI_DEBUG
 638         if (iwl_have_debug_level(IWL_DL_ISR)) {
 639                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 640                 if (inta & CSR_INT_BIT_SCD) {
 641                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
 642                                       "the frame/frames.\n");
 643                         isr_stats->sch++;
 644                 }
 645
 646                 /* Alive notification via Rx interrupt will do the real work */
 647                 if (inta & CSR_INT_BIT_ALIVE) {
 648                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
 649                         isr_stats->alive++;
 650                 }
 651         }
 652 #endif
 653         /* Safely ignore these bits for debug checks below */
 654         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 655
 656         /* HW RF KILL switch toggled */
 657         if (inta & CSR_INT_BIT_RF_KILL) {
 658                 bool hw_rfkill;
 659
 660                 hw_rfkill = iwl_is_rfkill_set(trans);
 661                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
 662                          hw_rfkill ? "disable radio" : "enable radio");
 663
 664                 isr_stats->rfkill++;
 665
 666                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 667
 668                 handled |= CSR_INT_BIT_RF_KILL;
 669         }
 670
 671         /* Chip got too hot and stopped itself */
 672         if (inta & CSR_INT_BIT_CT_KILL) {
 673                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
 674                 isr_stats->ctkill++;
 675                 handled |= CSR_INT_BIT_CT_KILL;
 676         }
 677
 678         /* Error detected by uCode */
 679         if (inta & CSR_INT_BIT_SW_ERR) {
 680                 IWL_ERR(trans, "Microcode SW error detected. "
 681                         " Restarting 0x%X.\n", inta);
 682                 isr_stats->sw++;
 683                 iwl_irq_handle_error(trans);
 684                 handled |= CSR_INT_BIT_SW_ERR;
 685         }
 686
 687         /* uCode wakes up after power-down sleep */
 688         if (inta & CSR_INT_BIT_WAKEUP) {
 689                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
 690                 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
 691                 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++)
 692                         iwl_txq_update_write_ptr(trans,
 693                                                  &trans_pcie->txq[i]);
 694
 695                 isr_stats->wakeup++;
 696
 697                 handled |= CSR_INT_BIT_WAKEUP;
 698         }
 699
 700         /* All uCode command responses, including Tx command responses,
 701          * Rx "responses" (frame-received notification), and other
 702          * notifications from uCode come through here*/
 703         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
 704                     CSR_INT_BIT_RX_PERIODIC)) {
 705                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
 706                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
 707                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
 708                         iwl_write32(trans, CSR_FH_INT_STATUS,
 709                                         CSR_FH_INT_RX_MASK);
 710                 }
 711                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
 712                         handled |= CSR_INT_BIT_RX_PERIODIC;
 713                         iwl_write32(trans,
 714                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
 715                 }
 716                 /* Sending RX interrupt require many steps to be done in the
 717                  * the device:
 718                  * 1- write interrupt to current index in ICT table.
 719                  * 2- dma RX frame.
 720                  * 3- update RX shared data to indicate last write index.
 721                  * 4- send interrupt.
 722                  * This could lead to RX race, driver could receive RX interrupt
 723                  * but the shared data changes does not reflect this;
 724                  * periodic interrupt will detect any dangling Rx activity.
 725                  */
 726
 727                 /* Disable periodic interrupt; we use it as just a one-shot. */
 728                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
 729                             CSR_INT_PERIODIC_DIS);
 730
 731                 iwl_rx_handle(trans);
 732
 733                 /*
 734                  * Enable periodic interrupt in 8 msec only if we received
 735                  * real RX interrupt (instead of just periodic int), to catch
 736                  * any dangling Rx interrupt.  If it was just the periodic
 737                  * interrupt, there was no dangling Rx activity, and no need
 738                  * to extend the periodic interrupt; one-shot is enough.
 739                  */
 740                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
 741                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
 742                                    CSR_INT_PERIODIC_ENA);
 743
 744                 isr_stats->rx++;
 745         }
 746
 747         /* This "Tx" DMA channel is used only for loading uCode */
 748         if (inta & CSR_INT_BIT_FH_TX) {
 749                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
 750                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
 751                 isr_stats->tx++;
 752                 handled |= CSR_INT_BIT_FH_TX;
 753                 /* Wake up uCode load routine, now that load is complete */
 754                 trans_pcie->ucode_write_complete = true;
 755                 wake_up(&trans_pcie->ucode_write_waitq);
 756         }
 757
 758         if (inta & ~handled) {
 759                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
 760                 isr_stats->unhandled++;
 761         }
 762
 763         if (inta & ~(trans_pcie->inta_mask)) {
 764                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
 765                          inta & ~trans_pcie->inta_mask);
 766         }
 767
 768         /* Re-enable all interrupts */
 769         /* only Re-enable if disabled by irq */
 770         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status))
 771                 iwl_enable_interrupts(trans);
 772         /* Re-enable RF_KILL if it occurred */
 773         else if (handled & CSR_INT_BIT_RF_KILL)
 774                 iwl_enable_rfkill_int(trans);
 775 }
 776
 777 /******************************************************************************
 778  *
 779  * ICT functions
 780  *
 781  ******************************************************************************/
 782
 783 /* a device (PCI-E) page is 4096 bytes long */
 784 #define ICT_SHIFT       12
 785 #define ICT_SIZE        (1 << ICT_SHIFT)
 786 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
 787
 788 /* Free dram table */
 789 void iwl_free_isr_ict(struct iwl_trans *trans)
 790 {
 791         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 792
 793         if (trans_pcie->ict_tbl) {
 794                 dma_free_coherent(trans->dev, ICT_SIZE,
 795                                   trans_pcie->ict_tbl,
 796                                   trans_pcie->ict_tbl_dma);
 797                 trans_pcie->ict_tbl = NULL;
 798                 trans_pcie->ict_tbl_dma = 0;
 799         }
 800 }
 801
 802
 803 /*
 804  * allocate dram shared table, it is an aligned memory
 805  * block of ICT_SIZE.
 806  * also reset all data related to ICT table interrupt.
 807  */
 808 int iwl_alloc_isr_ict(struct iwl_trans *trans)
 809 {
 810         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 811
 812         trans_pcie->ict_tbl =
 813                 dma_alloc_coherent(trans->dev, ICT_SIZE,
 814                                    &trans_pcie->ict_tbl_dma,
 815                                    GFP_KERNEL);
 816         if (!trans_pcie->ict_tbl)
 817                 return -ENOMEM;
 818
 819         /* just an API sanity check ... it is guaranteed to be aligned */
 820         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
 821                 iwl_free_isr_ict(trans);
 822                 return -EINVAL;
 823         }
 824
 825         IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
 826                       (unsigned long long)trans_pcie->ict_tbl_dma);
 827
 828         IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
 829
 830         /* reset table and index to all 0 */
 831         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
 832         trans_pcie->ict_index = 0;
 833
 834         /* add periodic RX interrupt */
 835         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
 836         return 0;
 837 }
 838
 839 /* Device is going up inform it about using ICT interrupt table,
 840  * also we need to tell the driver to start using ICT interrupt.
 841  */
 842 void iwl_reset_ict(struct iwl_trans *trans)
 843 {
 844         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 845         u32 val;
 846         unsigned long flags;
 847
 848         if (!trans_pcie->ict_tbl)
 849                 return;
 850
 851         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 852         iwl_disable_interrupts(trans);
 853
 854         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
 855
 856         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
 857
 858         val |= CSR_DRAM_INT_TBL_ENABLE;
 859         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
 860
 861         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
 862
 863         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
 864         trans_pcie->use_ict = true;
 865         trans_pcie->ict_index = 0;
 866         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
 867         iwl_enable_interrupts(trans);
 868         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 869 }
 870
 871 /* Device is going down disable ict interrupt usage */
 872 void iwl_disable_ict(struct iwl_trans *trans)
 873 {
 874         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 875         unsigned long flags;
 876
 877         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 878         trans_pcie->use_ict = false;
 879         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 880 }
 881
 882 /* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
 883 static irqreturn_t iwl_isr(int irq, void *data)
 884 {
 885         struct iwl_trans *trans = data;
 886         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 887         u32 inta, inta_mask;
 888 #ifdef CONFIG_IWLWIFI_DEBUG
 889         u32 inta_fh;
 890 #endif
 891
 892         lockdep_assert_held(&trans_pcie->irq_lock);
 893
 894         trace_iwlwifi_dev_irq(trans->dev);
 895
 896         /* Disable (but don't clear!) interrupts here to avoid
 897          *    back-to-back ISRs and sporadic interrupts from our NIC.
 898          * If we have something to service, the tasklet will re-enable ints.
 899          * If we *don't* have something, we'll re-enable before leaving here. */
 900         inta_mask = iwl_read32(trans, CSR_INT_MASK);  /* just for debug */
 901         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
 902
 903         /* Discover which interrupts are active/pending */
 904         inta = iwl_read32(trans, CSR_INT);
 905
 906         /* Ignore interrupt if there's nothing in NIC to service.
 907          * This may be due to IRQ shared with another device,
 908          * or due to sporadic interrupts thrown from our NIC. */
 909         if (!inta) {
 910                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
 911                 goto none;
 912         }
 913
 914         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
 915                 /* Hardware disappeared. It might have already raised
 916                  * an interrupt */
 917                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
 918                 return IRQ_HANDLED;
 919         }
 920
 921 #ifdef CONFIG_IWLWIFI_DEBUG
 922         if (iwl_have_debug_level(IWL_DL_ISR)) {
 923                 inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS);
 924                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
 925                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
 926         }
 927 #endif
 928
 929         trans_pcie->inta |= inta;
 930         /* iwl_irq_tasklet() will service interrupts and re-enable them */
 931         if (likely(inta))
 932                 tasklet_schedule(&trans_pcie->irq_tasklet);
 933         else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
 934                  !trans_pcie->inta)
 935                 iwl_enable_interrupts(trans);
 936
 937 none:
 938         /* re-enable interrupts here since we don't have anything to service. */
 939         /* only Re-enable if disabled by irq  and no schedules tasklet. */
 940         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
 941             !trans_pcie->inta)
 942                 iwl_enable_interrupts(trans);
 943
 944         return IRQ_NONE;
 945 }
 946
 947 /* interrupt handler using ict table, with this interrupt driver will
 948  * stop using INTA register to get device's interrupt, reading this register
 949  * is expensive, device will write interrupts in ICT dram table, increment
 950  * index then will fire interrupt to driver, driver will OR all ICT table
 951  * entries from current index up to table entry with 0 value. the result is
 952  * the interrupt we need to service, driver will set the entries back to 0 and
 953  * set index.
 954  */
 955 irqreturn_t iwl_isr_ict(int irq, void *data)
 956 {
 957         struct iwl_trans *trans = data;
 958         struct iwl_trans_pcie *trans_pcie;
 959         u32 inta, inta_mask;
 960         u32 val = 0;
 961         u32 read;
 962         unsigned long flags;
 963
 964         if (!trans)
 965                 return IRQ_NONE;
 966
 967         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 968
 969         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 970
 971         /* dram interrupt table not set yet,
 972          * use legacy interrupt.
 973          */
 974         if (unlikely(!trans_pcie->use_ict)) {
 975                 irqreturn_t ret = iwl_isr(irq, data);
 976                 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 977                 return ret;
 978         }
 979
 980         trace_iwlwifi_dev_irq(trans->dev);
 981
 982
 983         /* Disable (but don't clear!) interrupts here to avoid
 984          * back-to-back ISRs and sporadic interrupts from our NIC.
 985          * If we have something to service, the tasklet will re-enable ints.
 986          * If we *don't* have something, we'll re-enable before leaving here.
 987          */
 988         inta_mask = iwl_read32(trans, CSR_INT_MASK);  /* just for debug */
 989         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
 990
 991
 992         /* Ignore interrupt if there's nothing in NIC to service.
 993          * This may be due to IRQ shared with another device,
 994          * or due to sporadic interrupts thrown from our NIC. */
 995         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
 996         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
 997         if (!read) {
 998                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
 999                 goto none;
1000         }
1001
1002         /*
1003          * Collect all entries up to the first 0, starting from ict_index;
1004          * note we already read at ict_index.
1005          */
1006         do {
1007                 val |= read;
1008                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1009                                 trans_pcie->ict_index, read);
1010                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1011                 trans_pcie->ict_index =
1012                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1013
1014                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1015                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1016                                            read);
1017         } while (read);
1018
1019         /* We should not get this value, just ignore it. */
1020         if (val == 0xffffffff)
1021                 val = 0;
1022
1023         /*
1024          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1025          * (bit 15 before shifting it to 31) to clear when using interrupt
1026          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1027          * so we use them to decide on the real state of the Rx bit.
1028          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1029          */
1030         if (val & 0xC0000)
1031                 val |= 0x8000;
1032
1033         inta = (0xff & val) | ((0xff00 & val) << 16);
1034         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1035                       inta, inta_mask, val);
1036
1037         inta &= trans_pcie->inta_mask;
1038         trans_pcie->inta |= inta;
1039
1040         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1041         if (likely(inta))
1042                 tasklet_schedule(&trans_pcie->irq_tasklet);
1043         else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1044                  !trans_pcie->inta) {
1045                 /* Allow interrupt if was disabled by this handler and
1046                  * no tasklet was schedules, We should not enable interrupt,
1047                  * tasklet will enable it.
1048                  */
1049                 iwl_enable_interrupts(trans);
1050         }
1051
1052         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1053         return IRQ_HANDLED;
1054
1055  none:
1056         /* re-enable interrupts here since we don't have anything to service.
1057          * only Re-enable if disabled by irq.
1058          */
1059         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1060             !trans_pcie->inta)
1061                 iwl_enable_interrupts(trans);
1062
1063         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1064         return IRQ_NONE;
1065 }