drivers/net/wireless/iwlwifi/pcie/rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 #include "iwl-prph.h"
  34 #include "iwl-io.h"
  35 #include "internal.h"
  36 #include "iwl-op-mode.h"
  37
  38 /******************************************************************************
  39  *
  40  * RX path functions
  41  *
  42  ******************************************************************************/
  43
  44 /*
  45  * Rx theory of operation
  46  *
  47  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  48  * each of which point to Receive Buffers to be filled by the NIC.  These get
  49  * used not only for Rx frames, but for any command response or notification
  50  * from the NIC.  The driver and NIC manage the Rx buffers by means
  51  * of indexes into the circular buffer.
  52  *
  53  * Rx Queue Indexes
  54  * The host/firmware share two index registers for managing the Rx buffers.
  55  *
  56  * The READ index maps to the first position that the firmware may be writing
  57  * to -- the driver can read up to (but not including) this position and get
  58  * good data.
  59  * The READ index is managed by the firmware once the card is enabled.
  60  *
  61  * The WRITE index maps to the last position the driver has read from -- the
  62  * position preceding WRITE is the last slot the firmware can place a packet.
  63  *
  64  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  65  * WRITE = READ.
  66  *
  67  * During initialization, the host sets up the READ queue position to the first
  68  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  69  *
  70  * When the firmware places a packet in a buffer, it will advance the READ index
  71  * and fire the RX interrupt.  The driver can then query the READ index and
  72  * process as many packets as possible, moving the WRITE index forward as it
  73  * resets the Rx queue buffers with new memory.
  74  *
  75  * The management in the driver is as follows:
  76  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  77  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  78  *   to replenish the iwl->rxq->rx_free.
  79  * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  80  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  81  *   'processed' and 'read' driver indexes as well)
  82  * + A received packet is processed and handed to the kernel network stack,
  83  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  84  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  85  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  86  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
  87  *   were enough free buffers and RX_STALLED is set it is cleared.
  88  *
  89  *
  90  * Driver sequence:
  91  *
  92  * iwl_rx_queue_alloc()   Allocates rx_free
  93  * iwl_rx_replenish()     Replenishes rx_free list from rx_used, and calls
  94  *                            iwl_rx_queue_restock
  95  * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  96  *                            queue, updates firmware pointers, and updates
  97  *                            the WRITE index.  If insufficient rx_free buffers
  98  *                            are available, schedules iwl_rx_replenish
  99  *
 100  * -- enable interrupts --
 101  * ISR - iwl_rx()         Detach iwl_rx_mem_buffers from pool up to the
 102  *                            READ INDEX, detaching the SKB from the pool.
 103  *                            Moves the packet buffer from queue to rx_used.
 104  *                            Calls iwl_rx_queue_restock to refill any empty
 105  *                            slots.
 106  * ...
 107  *
 108  */
 109
 110 /**
 111  * iwl_rx_queue_space - Return number of free slots available in queue.
 112  */
 113 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
 114 {
 115         int s = q->read - q->write;
 116         if (s <= 0)
 117                 s += RX_QUEUE_SIZE;
 118         /* keep some buffer to not confuse full and empty queue */
 119         s -= 2;
 120         if (s < 0)
 121                 s = 0;
 122         return s;
 123 }
 124
 125 /**
 126  * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
 127  */
 128 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
 129                                    struct iwl_rx_queue *q)
 130 {
 131         unsigned long flags;
 132         u32 reg;
 133
 134         spin_lock_irqsave(&q->lock, flags);
 135
 136         if (q->need_update == 0)
 137                 goto exit_unlock;
 138
 139         if (trans->cfg->base_params->shadow_reg_enable) {
 140                 /* shadow register enabled */
 141                 /* Device expects a multiple of 8 */
 142                 q->write_actual = (q->write & ~0x7);
 143                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
 144         } else {
 145                 struct iwl_trans_pcie *trans_pcie =
 146                         IWL_TRANS_GET_PCIE_TRANS(trans);
 147
 148                 /* If power-saving is in use, make sure device is awake */
 149                 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
 150                         reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 151
 152                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 153                                 IWL_DEBUG_INFO(trans,
 154                                         "Rx queue requesting wakeup,"
 155                                         " GP1 = 0x%x\n", reg);
 156                                 iwl_set_bit(trans, CSR_GP_CNTRL,
 157                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 158                                 goto exit_unlock;
 159                         }
 160
 161                         q->write_actual = (q->write & ~0x7);
 162                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 163                                         q->write_actual);
 164
 165                 /* Else device is assumed to be awake */
 166                 } else {
 167                         /* Device expects a multiple of 8 */
 168                         q->write_actual = (q->write & ~0x7);
 169                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 170                                 q->write_actual);
 171                 }
 172         }
 173         q->need_update = 0;
 174
 175  exit_unlock:
 176         spin_unlock_irqrestore(&q->lock, flags);
 177 }
 178
 179 /**
 180  * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 181  */
 182 static inline __le32 iwl_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 183 {
 184         return cpu_to_le32((u32)(dma_addr >> 8));
 185 }
 186
 187 /**
 188  * iwl_rx_queue_restock - refill RX queue from pre-allocated pool
 189  *
 190  * If there are slots in the RX queue that need to be restocked,
 191  * and we have free pre-allocated buffers, fill the ranks as much
 192  * as we can, pulling from rx_free.
 193  *
 194  * This moves the 'write' index forward to catch up with 'processed', and
 195  * also updates the memory address in the firmware to reference the new
 196  * target buffer.
 197  */
 198 static void iwl_rx_queue_restock(struct iwl_trans *trans)
 199 {
 200         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 201         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 202         struct list_head *element;
 203         struct iwl_rx_mem_buffer *rxb;
 204         unsigned long flags;
 205
 206         /*
 207          * If the device isn't enabled - not need to try to add buffers...
 208          * This can happen when we stop the device and still have an interrupt
 209          * pending. We stop the APM before we sync the interrupts / tasklets
 210          * because we have to (see comment there). On the other hand, since
 211          * the APM is stopped, we cannot access the HW (in particular not prph).
 212          * So don't try to restock if the APM has been already stopped.
 213          */
 214         if (!test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status))
 215                 return;
 216
 217         spin_lock_irqsave(&rxq->lock, flags);
 218         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 219                 /* The overwritten rxb must be a used one */
 220                 rxb = rxq->queue[rxq->write];
 221                 BUG_ON(rxb && rxb->page);
 222
 223                 /* Get next free Rx buffer, remove from free list */
 224                 element = rxq->rx_free.next;
 225                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 226                 list_del(element);
 227
 228                 /* Point to Rx buffer via next RBD in circular buffer */
 229                 rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(rxb->page_dma);
 230                 rxq->queue[rxq->write] = rxb;
 231                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 232                 rxq->free_count--;
 233         }
 234         spin_unlock_irqrestore(&rxq->lock, flags);
 235         /* If the pre-allocated buffer pool is dropping low, schedule to
 236          * refill it */
 237         if (rxq->free_count <= RX_LOW_WATERMARK)
 238                 schedule_work(&trans_pcie->rx_replenish);
 239
 240         /* If we've added more space for the firmware to place data, tell it.
 241          * Increment device's write pointer in multiples of 8. */
 242         if (rxq->write_actual != (rxq->write & ~0x7)) {
 243                 spin_lock_irqsave(&rxq->lock, flags);
 244                 rxq->need_update = 1;
 245                 spin_unlock_irqrestore(&rxq->lock, flags);
 246                 iwl_rx_queue_update_write_ptr(trans, rxq);
 247         }
 248 }
 249
 250 /*
 251  * iwl_rx_allocate - allocate a page for each used RBD
 252  *
 253  * A used RBD is an Rx buffer that has been given to the stack. To use it again
 254  * a page must be allocated and the RBD must point to the page. This function
 255  * doesn't change the HW pointer but handles the list of pages that is used by
 256  * iwl_rx_queue_restock. The latter function will update the HW to use the newly
 257  * allocated buffers.
 258  */
 259 static void iwl_rx_allocate(struct iwl_trans *trans, gfp_t priority)
 260 {
 261         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 262         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 263         struct list_head *element;
 264         struct iwl_rx_mem_buffer *rxb;
 265         struct page *page;
 266         unsigned long flags;
 267         gfp_t gfp_mask = priority;
 268
 269         while (1) {
 270                 spin_lock_irqsave(&rxq->lock, flags);
 271                 if (list_empty(&rxq->rx_used)) {
 272                         spin_unlock_irqrestore(&rxq->lock, flags);
 273                         return;
 274                 }
 275                 spin_unlock_irqrestore(&rxq->lock, flags);
 276
 277                 if (rxq->free_count > RX_LOW_WATERMARK)
 278                         gfp_mask |= __GFP_NOWARN;
 279
 280                 if (trans_pcie->rx_page_order > 0)
 281                         gfp_mask |= __GFP_COMP;
 282
 283                 /* Alloc a new receive buffer */
 284                 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
 285                 if (!page) {
 286                         if (net_ratelimit())
 287                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 288                                            "order: %d\n",
 289                                            trans_pcie->rx_page_order);
 290
 291                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 292                             net_ratelimit())
 293                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 294                                          "Only %u free buffers remaining.\n",
 295                                          priority == GFP_ATOMIC ?
 296                                          "GFP_ATOMIC" : "GFP_KERNEL",
 297                                          rxq->free_count);
 298                         /* We don't reschedule replenish work here -- we will
 299                          * call the restock method and if it still needs
 300                          * more buffers it will schedule replenish */
 301                         return;
 302                 }
 303
 304                 spin_lock_irqsave(&rxq->lock, flags);
 305
 306                 if (list_empty(&rxq->rx_used)) {
 307                         spin_unlock_irqrestore(&rxq->lock, flags);
 308                         __free_pages(page, trans_pcie->rx_page_order);
 309                         return;
 310                 }
 311                 element = rxq->rx_used.next;
 312                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 313                 list_del(element);
 314
 315                 spin_unlock_irqrestore(&rxq->lock, flags);
 316
 317                 BUG_ON(rxb->page);
 318                 rxb->page = page;
 319                 /* Get physical address of the RB */
 320                 rxb->page_dma =
 321                         dma_map_page(trans->dev, page, 0,
 322                                      PAGE_SIZE << trans_pcie->rx_page_order,
 323                                      DMA_FROM_DEVICE);
 324                 /* dma address must be no more than 36 bits */
 325                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 326                 /* and also 256 byte aligned! */
 327                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 328
 329                 spin_lock_irqsave(&rxq->lock, flags);
 330
 331                 list_add_tail(&rxb->list, &rxq->rx_free);
 332                 rxq->free_count++;
 333
 334                 spin_unlock_irqrestore(&rxq->lock, flags);
 335         }
 336 }
 337
 338 /*
 339  * iwl_rx_replenish - Move all used buffers from rx_used to rx_free
 340  *
 341  * When moving to rx_free an page is allocated for the slot.
 342  *
 343  * Also restock the Rx queue via iwl_rx_queue_restock.
 344  * This is called as a scheduled work item (except for during initialization)
 345  */
 346 void iwl_rx_replenish(struct iwl_trans *trans)
 347 {
 348         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 349         unsigned long flags;
 350
 351         iwl_rx_allocate(trans, GFP_KERNEL);
 352
 353         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 354         iwl_rx_queue_restock(trans);
 355         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 356 }
 357
 358 static void iwl_rx_replenish_now(struct iwl_trans *trans)
 359 {
 360         iwl_rx_allocate(trans, GFP_ATOMIC);
 361
 362         iwl_rx_queue_restock(trans);
 363 }
 364
 365 void iwl_bg_rx_replenish(struct work_struct *data)
 366 {
 367         struct iwl_trans_pcie *trans_pcie =
 368             container_of(data, struct iwl_trans_pcie, rx_replenish);
 369
 370         iwl_rx_replenish(trans_pcie->trans);
 371 }
 372
 373 static void iwl_rx_handle_rxbuf(struct iwl_trans *trans,
 374                                 struct iwl_rx_mem_buffer *rxb)
 375 {
 376         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 377         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 378         struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
 379         unsigned long flags;
 380         bool page_stolen = false;
 381         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
 382         u32 offset = 0;
 383
 384         if (WARN_ON(!rxb))
 385                 return;
 386
 387         dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
 388
 389         while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
 390                 struct iwl_rx_packet *pkt;
 391                 struct iwl_device_cmd *cmd;
 392                 u16 sequence;
 393                 bool reclaim;
 394                 int index, cmd_index, err, len;
 395                 struct iwl_rx_cmd_buffer rxcb = {
 396                         ._offset = offset,
 397                         ._page = rxb->page,
 398                         ._page_stolen = false,
 399                         .truesize = max_len,
 400                 };
 401
 402                 pkt = rxb_addr(&rxcb);
 403
 404                 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID))
 405                         break;
 406
 407                 IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n",
 408                         rxcb._offset,
 409                         trans_pcie_get_cmd_string(trans_pcie, pkt->hdr.cmd),
 410                         pkt->hdr.cmd);
 411
 412                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 413                 len += sizeof(u32); /* account for status word */
 414                 trace_iwlwifi_dev_rx(trans->dev, pkt, len);
 415
 416                 /* Reclaim a command buffer only if this packet is a response
 417                  *   to a (driver-originated) command.
 418                  * If the packet (e.g. Rx frame) originated from uCode,
 419                  *   there is no command buffer to reclaim.
 420                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 421                  *   but apparently a few don't get set; catch them here. */
 422                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
 423                 if (reclaim) {
 424                         int i;
 425
 426                         for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
 427                                 if (trans_pcie->no_reclaim_cmds[i] ==
 428                                                         pkt->hdr.cmd) {
 429                                         reclaim = false;
 430                                         break;
 431                                 }
 432                         }
 433                 }
 434
 435                 sequence = le16_to_cpu(pkt->hdr.sequence);
 436                 index = SEQ_TO_INDEX(sequence);
 437                 cmd_index = get_cmd_index(&txq->q, index);
 438
 439                 if (reclaim) {
 440                         struct iwl_pcie_tx_queue_entry *ent;
 441                         ent = &txq->entries[cmd_index];
 442                         cmd = ent->copy_cmd;
 443                         WARN_ON_ONCE(!cmd && ent->meta.flags & CMD_WANT_HCMD);
 444                 } else {
 445                         cmd = NULL;
 446                 }
 447
 448                 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
 449
 450                 if (reclaim) {
 451                         /* The original command isn't needed any more */
 452                         kfree(txq->entries[cmd_index].copy_cmd);
 453                         txq->entries[cmd_index].copy_cmd = NULL;
 454                 }
 455
 456                 /*
 457                  * After here, we should always check rxcb._page_stolen,
 458                  * if it is true then one of the handlers took the page.
 459                  */
 460
 461                 if (reclaim) {
 462                         /* Invoke any callbacks, transfer the buffer to caller,
 463                          * and fire off the (possibly) blocking
 464                          * iwl_trans_send_cmd()
 465                          * as we reclaim the driver command queue */
 466                         if (!rxcb._page_stolen)
 467                                 iwl_tx_cmd_complete(trans, &rxcb, err);
 468                         else
 469                                 IWL_WARN(trans, "Claim null rxb?\n");
 470                 }
 471
 472                 page_stolen |= rxcb._page_stolen;
 473                 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
 474         }
 475
 476         /* page was stolen from us -- free our reference */
 477         if (page_stolen) {
 478                 __free_pages(rxb->page, trans_pcie->rx_page_order);
 479                 rxb->page = NULL;
 480         }
 481
 482         /* Reuse the page if possible. For notification packets and
 483          * SKBs that fail to Rx correctly, add them back into the
 484          * rx_free list for reuse later. */
 485         spin_lock_irqsave(&rxq->lock, flags);
 486         if (rxb->page != NULL) {
 487                 rxb->page_dma =
 488                         dma_map_page(trans->dev, rxb->page, 0,
 489                                      PAGE_SIZE << trans_pcie->rx_page_order,
 490                                      DMA_FROM_DEVICE);
 491                 list_add_tail(&rxb->list, &rxq->rx_free);
 492                 rxq->free_count++;
 493         } else
 494                 list_add_tail(&rxb->list, &rxq->rx_used);
 495         spin_unlock_irqrestore(&rxq->lock, flags);
 496 }
 497
 498 /**
 499  * iwl_rx_handle - Main entry function for receiving responses from uCode
 500  *
 501  * Uses the priv->rx_handlers callback function array to invoke
 502  * the appropriate handlers, including command responses,
 503  * frame-received notifications, and other notifications.
 504  */
 505 static void iwl_rx_handle(struct iwl_trans *trans)
 506 {
 507         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 508         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 509         u32 r, i;
 510         u8 fill_rx = 0;
 511         u32 count = 8;
 512         int total_empty;
 513
 514         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 515          * buffer that the driver may process (last buffer filled by ucode). */
 516         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 517         i = rxq->read;
 518
 519         /* Rx interrupt, but nothing sent from uCode */
 520         if (i == r)
 521                 IWL_DEBUG_RX(trans, "HW = SW = %d\n", r);
 522
 523         /* calculate total frames need to be restock after handling RX */
 524         total_empty = r - rxq->write_actual;
 525         if (total_empty < 0)
 526                 total_empty += RX_QUEUE_SIZE;
 527
 528         if (total_empty > (RX_QUEUE_SIZE / 2))
 529                 fill_rx = 1;
 530
 531         while (i != r) {
 532                 struct iwl_rx_mem_buffer *rxb;
 533
 534                 rxb = rxq->queue[i];
 535                 rxq->queue[i] = NULL;
 536
 537                 IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n",
 538                              r, i, rxb);
 539                 iwl_rx_handle_rxbuf(trans, rxb);
 540
 541                 i = (i + 1) & RX_QUEUE_MASK;
 542                 /* If there are a lot of unused frames,
 543                  * restock the Rx queue so ucode wont assert. */
 544                 if (fill_rx) {
 545                         count++;
 546                         if (count >= 8) {
 547                                 rxq->read = i;
 548                                 iwl_rx_replenish_now(trans);
 549                                 count = 0;
 550                         }
 551                 }
 552         }
 553
 554         /* Backtrack one entry */
 555         rxq->read = i;
 556         if (fill_rx)
 557                 iwl_rx_replenish_now(trans);
 558         else
 559                 iwl_rx_queue_restock(trans);
 560 }
 561
 562 /**
 563  * iwl_irq_handle_error - called for HW or SW error interrupt from card
 564  */
 565 static void iwl_irq_handle_error(struct iwl_trans *trans)
 566 {
 567         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 568         if (trans->cfg->internal_wimax_coex &&
 569             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
 570                              APMS_CLK_VAL_MRB_FUNC_MODE) ||
 571              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
 572                             APMG_PS_CTRL_VAL_RESET_REQ))) {
 573                 struct iwl_trans_pcie *trans_pcie =
 574                         IWL_TRANS_GET_PCIE_TRANS(trans);
 575
 576                 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 577                 iwl_op_mode_wimax_active(trans->op_mode);
 578                 wake_up(&trans->wait_command_queue);
 579                 return;
 580         }
 581
 582         iwl_dump_csr(trans);
 583         iwl_dump_fh(trans, NULL, false);
 584
 585         iwl_op_mode_nic_error(trans->op_mode);
 586 }
 587
 588 /* tasklet for iwlagn interrupt */
 589 void iwl_irq_tasklet(struct iwl_trans *trans)
 590 {
 591         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 592         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 593         u32 inta = 0;
 594         u32 handled = 0;
 595         unsigned long flags;
 596         u32 i;
 597 #ifdef CONFIG_IWLWIFI_DEBUG
 598         u32 inta_mask;
 599 #endif
 600
 601         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 602
 603         /* Ack/clear/reset pending uCode interrupts.
 604          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 605          */
 606         /* There is a hardware bug in the interrupt mask function that some
 607          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 608          * they are disabled in the CSR_INT_MASK register. Furthermore the
 609          * ICT interrupt handling mechanism has another bug that might cause
 610          * these unmasked interrupts fail to be detected. We workaround the
 611          * hardware bugs here by ACKing all the possible interrupts so that
 612          * interrupt coalescing can still be achieved.
 613          */
 614         iwl_write32(trans, CSR_INT,
 615                     trans_pcie->inta | ~trans_pcie->inta_mask);
 616
 617         inta = trans_pcie->inta;
 618
 619 #ifdef CONFIG_IWLWIFI_DEBUG
 620         if (iwl_have_debug_level(IWL_DL_ISR)) {
 621                 /* just for debug */
 622                 inta_mask = iwl_read32(trans, CSR_INT_MASK);
 623                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
 624                               inta, inta_mask);
 625         }
 626 #endif
 627
 628         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 629         trans_pcie->inta = 0;
 630
 631         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 632
 633         /* Now service all interrupt bits discovered above. */
 634         if (inta & CSR_INT_BIT_HW_ERR) {
 635                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 636
 637                 /* Tell the device to stop sending interrupts */
 638                 iwl_disable_interrupts(trans);
 639
 640                 isr_stats->hw++;
 641                 iwl_irq_handle_error(trans);
 642
 643                 handled |= CSR_INT_BIT_HW_ERR;
 644
 645                 return;
 646         }
 647
 648 #ifdef CONFIG_IWLWIFI_DEBUG
 649         if (iwl_have_debug_level(IWL_DL_ISR)) {
 650                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 651                 if (inta & CSR_INT_BIT_SCD) {
 652                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
 653                                       "the frame/frames.\n");
 654                         isr_stats->sch++;
 655                 }
 656
 657                 /* Alive notification via Rx interrupt will do the real work */
 658                 if (inta & CSR_INT_BIT_ALIVE) {
 659                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
 660                         isr_stats->alive++;
 661                 }
 662         }
 663 #endif
 664         /* Safely ignore these bits for debug checks below */
 665         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 666
 667         /* HW RF KILL switch toggled */
 668         if (inta & CSR_INT_BIT_RF_KILL) {
 669                 bool hw_rfkill;
 670
 671                 hw_rfkill = iwl_is_rfkill_set(trans);
 672                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
 673                          hw_rfkill ? "disable radio" : "enable radio");
 674
 675                 isr_stats->rfkill++;
 676
 677                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 678
 679                 handled |= CSR_INT_BIT_RF_KILL;
 680         }
 681
 682         /* Chip got too hot and stopped itself */
 683         if (inta & CSR_INT_BIT_CT_KILL) {
 684                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
 685                 isr_stats->ctkill++;
 686                 handled |= CSR_INT_BIT_CT_KILL;
 687         }
 688
 689         /* Error detected by uCode */
 690         if (inta & CSR_INT_BIT_SW_ERR) {
 691                 IWL_ERR(trans, "Microcode SW error detected. "
 692                         " Restarting 0x%X.\n", inta);
 693                 isr_stats->sw++;
 694                 iwl_irq_handle_error(trans);
 695                 handled |= CSR_INT_BIT_SW_ERR;
 696         }
 697
 698         /* uCode wakes up after power-down sleep */
 699         if (inta & CSR_INT_BIT_WAKEUP) {
 700                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
 701                 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
 702                 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++)
 703                         iwl_txq_update_write_ptr(trans,
 704                                                  &trans_pcie->txq[i]);
 705
 706                 isr_stats->wakeup++;
 707
 708                 handled |= CSR_INT_BIT_WAKEUP;
 709         }
 710
 711         /* All uCode command responses, including Tx command responses,
 712          * Rx "responses" (frame-received notification), and other
 713          * notifications from uCode come through here*/
 714         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
 715                     CSR_INT_BIT_RX_PERIODIC)) {
 716                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
 717                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
 718                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
 719                         iwl_write32(trans, CSR_FH_INT_STATUS,
 720                                         CSR_FH_INT_RX_MASK);
 721                 }
 722                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
 723                         handled |= CSR_INT_BIT_RX_PERIODIC;
 724                         iwl_write32(trans,
 725                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
 726                 }
 727                 /* Sending RX interrupt require many steps to be done in the
 728                  * the device:
 729                  * 1- write interrupt to current index in ICT table.
 730                  * 2- dma RX frame.
 731                  * 3- update RX shared data to indicate last write index.
 732                  * 4- send interrupt.
 733                  * This could lead to RX race, driver could receive RX interrupt
 734                  * but the shared data changes does not reflect this;
 735                  * periodic interrupt will detect any dangling Rx activity.
 736                  */
 737
 738                 /* Disable periodic interrupt; we use it as just a one-shot. */
 739                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
 740                             CSR_INT_PERIODIC_DIS);
 741
 742                 iwl_rx_handle(trans);
 743
 744                 /*
 745                  * Enable periodic interrupt in 8 msec only if we received
 746                  * real RX interrupt (instead of just periodic int), to catch
 747                  * any dangling Rx interrupt.  If it was just the periodic
 748                  * interrupt, there was no dangling Rx activity, and no need
 749                  * to extend the periodic interrupt; one-shot is enough.
 750                  */
 751                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
 752                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
 753                                    CSR_INT_PERIODIC_ENA);
 754
 755                 isr_stats->rx++;
 756         }
 757
 758         /* This "Tx" DMA channel is used only for loading uCode */
 759         if (inta & CSR_INT_BIT_FH_TX) {
 760                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
 761                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
 762                 isr_stats->tx++;
 763                 handled |= CSR_INT_BIT_FH_TX;
 764                 /* Wake up uCode load routine, now that load is complete */
 765                 trans_pcie->ucode_write_complete = true;
 766                 wake_up(&trans_pcie->ucode_write_waitq);
 767         }
 768
 769         if (inta & ~handled) {
 770                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
 771                 isr_stats->unhandled++;
 772         }
 773
 774         if (inta & ~(trans_pcie->inta_mask)) {
 775                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
 776                          inta & ~trans_pcie->inta_mask);
 777         }
 778
 779         /* Re-enable all interrupts */
 780         /* only Re-enable if disabled by irq */
 781         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status))
 782                 iwl_enable_interrupts(trans);
 783         /* Re-enable RF_KILL if it occurred */
 784         else if (handled & CSR_INT_BIT_RF_KILL)
 785                 iwl_enable_rfkill_int(trans);
 786 }
 787
 788 /******************************************************************************
 789  *
 790  * ICT functions
 791  *
 792  ******************************************************************************/
 793
 794 /* a device (PCI-E) page is 4096 bytes long */
 795 #define ICT_SHIFT       12
 796 #define ICT_SIZE        (1 << ICT_SHIFT)
 797 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
 798
 799 /* Free dram table */
 800 void iwl_free_isr_ict(struct iwl_trans *trans)
 801 {
 802         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 803
 804         if (trans_pcie->ict_tbl) {
 805                 dma_free_coherent(trans->dev, ICT_SIZE,
 806                                   trans_pcie->ict_tbl,
 807                                   trans_pcie->ict_tbl_dma);
 808                 trans_pcie->ict_tbl = NULL;
 809                 trans_pcie->ict_tbl_dma = 0;
 810         }
 811 }
 812
 813
 814 /*
 815  * allocate dram shared table, it is an aligned memory
 816  * block of ICT_SIZE.
 817  * also reset all data related to ICT table interrupt.
 818  */
 819 int iwl_alloc_isr_ict(struct iwl_trans *trans)
 820 {
 821         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 822
 823         trans_pcie->ict_tbl =
 824                 dma_alloc_coherent(trans->dev, ICT_SIZE,
 825                                    &trans_pcie->ict_tbl_dma,
 826                                    GFP_KERNEL);
 827         if (!trans_pcie->ict_tbl)
 828                 return -ENOMEM;
 829
 830         /* just an API sanity check ... it is guaranteed to be aligned */
 831         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
 832                 iwl_free_isr_ict(trans);
 833                 return -EINVAL;
 834         }
 835
 836         IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
 837                       (unsigned long long)trans_pcie->ict_tbl_dma);
 838
 839         IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
 840
 841         /* reset table and index to all 0 */
 842         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
 843         trans_pcie->ict_index = 0;
 844
 845         /* add periodic RX interrupt */
 846         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
 847         return 0;
 848 }
 849
 850 /* Device is going up inform it about using ICT interrupt table,
 851  * also we need to tell the driver to start using ICT interrupt.
 852  */
 853 void iwl_reset_ict(struct iwl_trans *trans)
 854 {
 855         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 856         u32 val;
 857         unsigned long flags;
 858
 859         if (!trans_pcie->ict_tbl)
 860                 return;
 861
 862         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 863         iwl_disable_interrupts(trans);
 864
 865         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
 866
 867         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
 868
 869         val |= CSR_DRAM_INT_TBL_ENABLE;
 870         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
 871
 872         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
 873
 874         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
 875         trans_pcie->use_ict = true;
 876         trans_pcie->ict_index = 0;
 877         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
 878         iwl_enable_interrupts(trans);
 879         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 880 }
 881
 882 /* Device is going down disable ict interrupt usage */
 883 void iwl_disable_ict(struct iwl_trans *trans)
 884 {
 885         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 886         unsigned long flags;
 887
 888         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 889         trans_pcie->use_ict = false;
 890         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 891 }
 892
 893 /* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
 894 static irqreturn_t iwl_isr(int irq, void *data)
 895 {
 896         struct iwl_trans *trans = data;
 897         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 898         u32 inta, inta_mask;
 899 #ifdef CONFIG_IWLWIFI_DEBUG
 900         u32 inta_fh;
 901 #endif
 902
 903         lockdep_assert_held(&trans_pcie->irq_lock);
 904
 905         trace_iwlwifi_dev_irq(trans->dev);
 906
 907         /* Disable (but don't clear!) interrupts here to avoid
 908          *    back-to-back ISRs and sporadic interrupts from our NIC.
 909          * If we have something to service, the tasklet will re-enable ints.
 910          * If we *don't* have something, we'll re-enable before leaving here. */
 911         inta_mask = iwl_read32(trans, CSR_INT_MASK);  /* just for debug */
 912         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
 913
 914         /* Discover which interrupts are active/pending */
 915         inta = iwl_read32(trans, CSR_INT);
 916
 917         /* Ignore interrupt if there's nothing in NIC to service.
 918          * This may be due to IRQ shared with another device,
 919          * or due to sporadic interrupts thrown from our NIC. */
 920         if (!inta) {
 921                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
 922                 goto none;
 923         }
 924
 925         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
 926                 /* Hardware disappeared. It might have already raised
 927                  * an interrupt */
 928                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
 929                 return IRQ_HANDLED;
 930         }
 931
 932 #ifdef CONFIG_IWLWIFI_DEBUG
 933         if (iwl_have_debug_level(IWL_DL_ISR)) {
 934                 inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS);
 935                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
 936                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
 937         }
 938 #endif
 939
 940         trans_pcie->inta |= inta;
 941         /* iwl_irq_tasklet() will service interrupts and re-enable them */
 942         if (likely(inta))
 943                 tasklet_schedule(&trans_pcie->irq_tasklet);
 944         else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
 945                  !trans_pcie->inta)
 946                 iwl_enable_interrupts(trans);
 947
 948 none:
 949         /* re-enable interrupts here since we don't have anything to service. */
 950         /* only Re-enable if disabled by irq  and no schedules tasklet. */
 951         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
 952             !trans_pcie->inta)
 953                 iwl_enable_interrupts(trans);
 954
 955         return IRQ_NONE;
 956 }
 957
 958 /* interrupt handler using ict table, with this interrupt driver will
 959  * stop using INTA register to get device's interrupt, reading this register
 960  * is expensive, device will write interrupts in ICT dram table, increment
 961  * index then will fire interrupt to driver, driver will OR all ICT table
 962  * entries from current index up to table entry with 0 value. the result is
 963  * the interrupt we need to service, driver will set the entries back to 0 and
 964  * set index.
 965  */
 966 irqreturn_t iwl_isr_ict(int irq, void *data)
 967 {
 968         struct iwl_trans *trans = data;
 969         struct iwl_trans_pcie *trans_pcie;
 970         u32 inta, inta_mask;
 971         u32 val = 0;
 972         u32 read;
 973         unsigned long flags;
 974
 975         if (!trans)
 976                 return IRQ_NONE;
 977
 978         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 979
 980         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 981
 982         /* dram interrupt table not set yet,
 983          * use legacy interrupt.
 984          */
 985         if (unlikely(!trans_pcie->use_ict)) {
 986                 irqreturn_t ret = iwl_isr(irq, data);
 987                 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 988                 return ret;
 989         }
 990
 991         trace_iwlwifi_dev_irq(trans->dev);
 992
 993
 994         /* Disable (but don't clear!) interrupts here to avoid
 995          * back-to-back ISRs and sporadic interrupts from our NIC.
 996          * If we have something to service, the tasklet will re-enable ints.
 997          * If we *don't* have something, we'll re-enable before leaving here.
 998          */
 999         inta_mask = iwl_read32(trans, CSR_INT_MASK);  /* just for debug */
1000         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1001
1002
1003         /* Ignore interrupt if there's nothing in NIC to service.
1004          * This may be due to IRQ shared with another device,
1005          * or due to sporadic interrupts thrown from our NIC. */
1006         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1007         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1008         if (!read) {
1009                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1010                 goto none;
1011         }
1012
1013         /*
1014          * Collect all entries up to the first 0, starting from ict_index;
1015          * note we already read at ict_index.
1016          */
1017         do {
1018                 val |= read;
1019                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1020                                 trans_pcie->ict_index, read);
1021                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1022                 trans_pcie->ict_index =
1023                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1024
1025                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1026                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1027                                            read);
1028         } while (read);
1029
1030         /* We should not get this value, just ignore it. */
1031         if (val == 0xffffffff)
1032                 val = 0;
1033
1034         /*
1035          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1036          * (bit 15 before shifting it to 31) to clear when using interrupt
1037          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1038          * so we use them to decide on the real state of the Rx bit.
1039          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1040          */
1041         if (val & 0xC0000)
1042                 val |= 0x8000;
1043
1044         inta = (0xff & val) | ((0xff00 & val) << 16);
1045         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1046                       inta, inta_mask, val);
1047
1048         inta &= trans_pcie->inta_mask;
1049         trans_pcie->inta |= inta;
1050
1051         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1052         if (likely(inta))
1053                 tasklet_schedule(&trans_pcie->irq_tasklet);
1054         else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1055                  !trans_pcie->inta) {
1056                 /* Allow interrupt if was disabled by this handler and
1057                  * no tasklet was schedules, We should not enable interrupt,
1058                  * tasklet will enable it.
1059                  */
1060                 iwl_enable_interrupts(trans);
1061         }
1062
1063         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1064         return IRQ_HANDLED;
1065
1066  none:
1067         /* re-enable interrupts here since we don't have anything to service.
1068          * only Re-enable if disabled by irq.
1069          */
1070         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1071             !trans_pcie->inta)
1072                 iwl_enable_interrupts(trans);
1073
1074         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1075         return IRQ_NONE;
1076 }