drivers/net/wireless/iwlwifi/pcie/rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 #include "iwl-prph.h"
  34 #include "iwl-io.h"
  35 #include "internal.h"
  36 #include "iwl-op-mode.h"
  37
  38 #ifdef CONFIG_IWLWIFI_IDI
  39 #include "iwl-amfh.h"
  40 #endif
  41
  42 /******************************************************************************
  43  *
  44  * RX path functions
  45  *
  46  ******************************************************************************/
  47
  48 /*
  49  * Rx theory of operation
  50  *
  51  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  52  * each of which point to Receive Buffers to be filled by the NIC.  These get
  53  * used not only for Rx frames, but for any command response or notification
  54  * from the NIC.  The driver and NIC manage the Rx buffers by means
  55  * of indexes into the circular buffer.
  56  *
  57  * Rx Queue Indexes
  58  * The host/firmware share two index registers for managing the Rx buffers.
  59  *
  60  * The READ index maps to the first position that the firmware may be writing
  61  * to -- the driver can read up to (but not including) this position and get
  62  * good data.
  63  * The READ index is managed by the firmware once the card is enabled.
  64  *
  65  * The WRITE index maps to the last position the driver has read from -- the
  66  * position preceding WRITE is the last slot the firmware can place a packet.
  67  *
  68  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  69  * WRITE = READ.
  70  *
  71  * During initialization, the host sets up the READ queue position to the first
  72  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  73  *
  74  * When the firmware places a packet in a buffer, it will advance the READ index
  75  * and fire the RX interrupt.  The driver can then query the READ index and
  76  * process as many packets as possible, moving the WRITE index forward as it
  77  * resets the Rx queue buffers with new memory.
  78  *
  79  * The management in the driver is as follows:
  80  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  81  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  82  *   to replenish the iwl->rxq->rx_free.
  83  * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  84  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  85  *   'processed' and 'read' driver indexes as well)
  86  * + A received packet is processed and handed to the kernel network stack,
  87  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  88  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  89  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  90  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
  91  *   were enough free buffers and RX_STALLED is set it is cleared.
  92  *
  93  *
  94  * Driver sequence:
  95  *
  96  * iwl_rx_queue_alloc()   Allocates rx_free
  97  * iwl_rx_replenish()     Replenishes rx_free list from rx_used, and calls
  98  *                            iwl_rx_queue_restock
  99  * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
 100  *                            queue, updates firmware pointers, and updates
 101  *                            the WRITE index.  If insufficient rx_free buffers
 102  *                            are available, schedules iwl_rx_replenish
 103  *
 104  * -- enable interrupts --
 105  * ISR - iwl_rx()         Detach iwl_rx_mem_buffers from pool up to the
 106  *                            READ INDEX, detaching the SKB from the pool.
 107  *                            Moves the packet buffer from queue to rx_used.
 108  *                            Calls iwl_rx_queue_restock to refill any empty
 109  *                            slots.
 110  * ...
 111  *
 112  */
 113
 114 /**
 115  * iwl_rx_queue_space - Return number of free slots available in queue.
 116  */
 117 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
 118 {
 119         int s = q->read - q->write;
 120         if (s <= 0)
 121                 s += RX_QUEUE_SIZE;
 122         /* keep some buffer to not confuse full and empty queue */
 123         s -= 2;
 124         if (s < 0)
 125                 s = 0;
 126         return s;
 127 }
 128
 129 /**
 130  * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
 131  */
 132 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
 133                                    struct iwl_rx_queue *q)
 134 {
 135         unsigned long flags;
 136         u32 reg;
 137
 138         spin_lock_irqsave(&q->lock, flags);
 139
 140         if (q->need_update == 0)
 141                 goto exit_unlock;
 142
 143         if (trans->cfg->base_params->shadow_reg_enable) {
 144                 /* shadow register enabled */
 145                 /* Device expects a multiple of 8 */
 146                 q->write_actual = (q->write & ~0x7);
 147                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
 148         } else {
 149                 struct iwl_trans_pcie *trans_pcie =
 150                         IWL_TRANS_GET_PCIE_TRANS(trans);
 151
 152                 /* If power-saving is in use, make sure device is awake */
 153                 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
 154                         reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 155
 156                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 157                                 IWL_DEBUG_INFO(trans,
 158                                         "Rx queue requesting wakeup,"
 159                                         " GP1 = 0x%x\n", reg);
 160                                 iwl_set_bit(trans, CSR_GP_CNTRL,
 161                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 162                                 goto exit_unlock;
 163                         }
 164
 165                         q->write_actual = (q->write & ~0x7);
 166                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 167                                         q->write_actual);
 168
 169                 /* Else device is assumed to be awake */
 170                 } else {
 171                         /* Device expects a multiple of 8 */
 172                         q->write_actual = (q->write & ~0x7);
 173                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 174                                 q->write_actual);
 175                 }
 176         }
 177         q->need_update = 0;
 178
 179  exit_unlock:
 180         spin_unlock_irqrestore(&q->lock, flags);
 181 }
 182
 183 /**
 184  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 185  */
 186 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 187 {
 188         return cpu_to_le32((u32)(dma_addr >> 8));
 189 }
 190
 191 /**
 192  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 193  *
 194  * If there are slots in the RX queue that need to be restocked,
 195  * and we have free pre-allocated buffers, fill the ranks as much
 196  * as we can, pulling from rx_free.
 197  *
 198  * This moves the 'write' index forward to catch up with 'processed', and
 199  * also updates the memory address in the firmware to reference the new
 200  * target buffer.
 201  */
 202 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
 203 {
 204         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 205         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 206         struct list_head *element;
 207         struct iwl_rx_mem_buffer *rxb;
 208         unsigned long flags;
 209
 210         spin_lock_irqsave(&rxq->lock, flags);
 211         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 212                 /* The overwritten rxb must be a used one */
 213                 rxb = rxq->queue[rxq->write];
 214                 BUG_ON(rxb && rxb->page);
 215
 216                 /* Get next free Rx buffer, remove from free list */
 217                 element = rxq->rx_free.next;
 218                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 219                 list_del(element);
 220
 221                 /* Point to Rx buffer via next RBD in circular buffer */
 222                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
 223                 rxq->queue[rxq->write] = rxb;
 224                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 225                 rxq->free_count--;
 226         }
 227         spin_unlock_irqrestore(&rxq->lock, flags);
 228         /* If the pre-allocated buffer pool is dropping low, schedule to
 229          * refill it */
 230         if (rxq->free_count <= RX_LOW_WATERMARK)
 231                 schedule_work(&trans_pcie->rx_replenish);
 232
 233
 234         /* If we've added more space for the firmware to place data, tell it.
 235          * Increment device's write pointer in multiples of 8. */
 236         if (rxq->write_actual != (rxq->write & ~0x7)) {
 237                 spin_lock_irqsave(&rxq->lock, flags);
 238                 rxq->need_update = 1;
 239                 spin_unlock_irqrestore(&rxq->lock, flags);
 240                 iwl_rx_queue_update_write_ptr(trans, rxq);
 241         }
 242 }
 243
 244 /**
 245  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 246  *
 247  * When moving to rx_free an SKB is allocated for the slot.
 248  *
 249  * Also restock the Rx queue via iwl_rx_queue_restock.
 250  * This is called as a scheduled work item (except for during initialization)
 251  */
 252 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
 253 {
 254         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 255         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 256         struct list_head *element;
 257         struct iwl_rx_mem_buffer *rxb;
 258         struct page *page;
 259         unsigned long flags;
 260         gfp_t gfp_mask = priority;
 261
 262         while (1) {
 263                 spin_lock_irqsave(&rxq->lock, flags);
 264                 if (list_empty(&rxq->rx_used)) {
 265                         spin_unlock_irqrestore(&rxq->lock, flags);
 266                         return;
 267                 }
 268                 spin_unlock_irqrestore(&rxq->lock, flags);
 269
 270                 if (rxq->free_count > RX_LOW_WATERMARK)
 271                         gfp_mask |= __GFP_NOWARN;
 272
 273                 if (trans_pcie->rx_page_order > 0)
 274                         gfp_mask |= __GFP_COMP;
 275
 276                 /* Alloc a new receive buffer */
 277                 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
 278                 if (!page) {
 279                         if (net_ratelimit())
 280                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 281                                            "order: %d\n",
 282                                            trans_pcie->rx_page_order);
 283
 284                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 285                             net_ratelimit())
 286                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 287                                          "Only %u free buffers remaining.\n",
 288                                          priority == GFP_ATOMIC ?
 289                                          "GFP_ATOMIC" : "GFP_KERNEL",
 290                                          rxq->free_count);
 291                         /* We don't reschedule replenish work here -- we will
 292                          * call the restock method and if it still needs
 293                          * more buffers it will schedule replenish */
 294                         return;
 295                 }
 296
 297                 spin_lock_irqsave(&rxq->lock, flags);
 298
 299                 if (list_empty(&rxq->rx_used)) {
 300                         spin_unlock_irqrestore(&rxq->lock, flags);
 301                         __free_pages(page, trans_pcie->rx_page_order);
 302                         return;
 303                 }
 304                 element = rxq->rx_used.next;
 305                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 306                 list_del(element);
 307
 308                 spin_unlock_irqrestore(&rxq->lock, flags);
 309
 310                 BUG_ON(rxb->page);
 311                 rxb->page = page;
 312                 /* Get physical address of the RB */
 313                 rxb->page_dma =
 314                         dma_map_page(trans->dev, page, 0,
 315                                      PAGE_SIZE << trans_pcie->rx_page_order,
 316                                      DMA_FROM_DEVICE);
 317                 /* dma address must be no more than 36 bits */
 318                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 319                 /* and also 256 byte aligned! */
 320                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 321
 322                 spin_lock_irqsave(&rxq->lock, flags);
 323
 324                 list_add_tail(&rxb->list, &rxq->rx_free);
 325                 rxq->free_count++;
 326
 327                 spin_unlock_irqrestore(&rxq->lock, flags);
 328         }
 329 }
 330
 331 void iwlagn_rx_replenish(struct iwl_trans *trans)
 332 {
 333         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 334         unsigned long flags;
 335
 336         iwlagn_rx_allocate(trans, GFP_KERNEL);
 337
 338         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 339         iwlagn_rx_queue_restock(trans);
 340         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 341 }
 342
 343 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
 344 {
 345         iwlagn_rx_allocate(trans, GFP_ATOMIC);
 346
 347         iwlagn_rx_queue_restock(trans);
 348 }
 349
 350 void iwl_bg_rx_replenish(struct work_struct *data)
 351 {
 352         struct iwl_trans_pcie *trans_pcie =
 353             container_of(data, struct iwl_trans_pcie, rx_replenish);
 354
 355         iwlagn_rx_replenish(trans_pcie->trans);
 356 }
 357
 358 static void iwl_rx_handle_rxbuf(struct iwl_trans *trans,
 359                                 struct iwl_rx_mem_buffer *rxb)
 360 {
 361         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 362         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 363         struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
 364         unsigned long flags;
 365         bool page_stolen = false;
 366         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
 367         u32 offset = 0;
 368
 369         if (WARN_ON(!rxb))
 370                 return;
 371
 372         dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
 373
 374         while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
 375                 struct iwl_rx_packet *pkt;
 376                 struct iwl_device_cmd *cmd;
 377                 u16 sequence;
 378                 bool reclaim;
 379                 int index, cmd_index, err, len;
 380                 struct iwl_rx_cmd_buffer rxcb = {
 381                         ._offset = offset,
 382                         ._page = rxb->page,
 383                         ._page_stolen = false,
 384                         .truesize = max_len,
 385                 };
 386
 387                 pkt = rxb_addr(&rxcb);
 388
 389                 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID))
 390                         break;
 391
 392                 IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n",
 393                         rxcb._offset,
 394                         trans_pcie_get_cmd_string(trans_pcie, pkt->hdr.cmd),
 395                         pkt->hdr.cmd);
 396
 397                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 398                 len += sizeof(u32); /* account for status word */
 399                 trace_iwlwifi_dev_rx(trans->dev, pkt, len);
 400
 401                 /* Reclaim a command buffer only if this packet is a response
 402                  *   to a (driver-originated) command.
 403                  * If the packet (e.g. Rx frame) originated from uCode,
 404                  *   there is no command buffer to reclaim.
 405                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 406                  *   but apparently a few don't get set; catch them here. */
 407                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
 408                 if (reclaim) {
 409                         int i;
 410
 411                         for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
 412                                 if (trans_pcie->no_reclaim_cmds[i] ==
 413                                                         pkt->hdr.cmd) {
 414                                         reclaim = false;
 415                                         break;
 416                                 }
 417                         }
 418                 }
 419
 420                 sequence = le16_to_cpu(pkt->hdr.sequence);
 421                 index = SEQ_TO_INDEX(sequence);
 422                 cmd_index = get_cmd_index(&txq->q, index);
 423
 424                 if (reclaim) {
 425                         struct iwl_pcie_tx_queue_entry *ent;
 426                         ent = &txq->entries[cmd_index];
 427                         cmd = ent->copy_cmd;
 428                         WARN_ON_ONCE(!cmd && ent->meta.flags & CMD_WANT_HCMD);
 429                 } else {
 430                         cmd = NULL;
 431                 }
 432
 433                 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
 434
 435                 if (reclaim) {
 436                         /* The original command isn't needed any more */
 437                         kfree(txq->entries[cmd_index].copy_cmd);
 438                         txq->entries[cmd_index].copy_cmd = NULL;
 439                 }
 440
 441                 /*
 442                  * After here, we should always check rxcb._page_stolen,
 443                  * if it is true then one of the handlers took the page.
 444                  */
 445
 446                 if (reclaim) {
 447                         /* Invoke any callbacks, transfer the buffer to caller,
 448                          * and fire off the (possibly) blocking
 449                          * iwl_trans_send_cmd()
 450                          * as we reclaim the driver command queue */
 451                         if (!rxcb._page_stolen)
 452                                 iwl_tx_cmd_complete(trans, &rxcb, err);
 453                         else
 454                                 IWL_WARN(trans, "Claim null rxb?\n");
 455                 }
 456
 457                 page_stolen |= rxcb._page_stolen;
 458                 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
 459         }
 460
 461         /* page was stolen from us -- free our reference */
 462         if (page_stolen) {
 463                 __free_pages(rxb->page, trans_pcie->rx_page_order);
 464                 rxb->page = NULL;
 465         }
 466
 467         /* Reuse the page if possible. For notification packets and
 468          * SKBs that fail to Rx correctly, add them back into the
 469          * rx_free list for reuse later. */
 470         spin_lock_irqsave(&rxq->lock, flags);
 471         if (rxb->page != NULL) {
 472                 rxb->page_dma =
 473                         dma_map_page(trans->dev, rxb->page, 0,
 474                                      PAGE_SIZE << trans_pcie->rx_page_order,
 475                                      DMA_FROM_DEVICE);
 476                 list_add_tail(&rxb->list, &rxq->rx_free);
 477                 rxq->free_count++;
 478         } else
 479                 list_add_tail(&rxb->list, &rxq->rx_used);
 480         spin_unlock_irqrestore(&rxq->lock, flags);
 481 }
 482
 483 /**
 484  * iwl_rx_handle - Main entry function for receiving responses from uCode
 485  *
 486  * Uses the priv->rx_handlers callback function array to invoke
 487  * the appropriate handlers, including command responses,
 488  * frame-received notifications, and other notifications.
 489  */
 490 static void iwl_rx_handle(struct iwl_trans *trans)
 491 {
 492         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 493         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 494         u32 r, i;
 495         u8 fill_rx = 0;
 496         u32 count = 8;
 497         int total_empty;
 498
 499         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 500          * buffer that the driver may process (last buffer filled by ucode). */
 501         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 502         i = rxq->read;
 503
 504         /* Rx interrupt, but nothing sent from uCode */
 505         if (i == r)
 506                 IWL_DEBUG_RX(trans, "HW = SW = %d\n", r);
 507
 508         /* calculate total frames need to be restock after handling RX */
 509         total_empty = r - rxq->write_actual;
 510         if (total_empty < 0)
 511                 total_empty += RX_QUEUE_SIZE;
 512
 513         if (total_empty > (RX_QUEUE_SIZE / 2))
 514                 fill_rx = 1;
 515
 516         while (i != r) {
 517                 struct iwl_rx_mem_buffer *rxb;
 518
 519                 rxb = rxq->queue[i];
 520                 rxq->queue[i] = NULL;
 521
 522                 IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n",
 523                              r, i, rxb);
 524                 iwl_rx_handle_rxbuf(trans, rxb);
 525
 526                 i = (i + 1) & RX_QUEUE_MASK;
 527                 /* If there are a lot of unused frames,
 528                  * restock the Rx queue so ucode wont assert. */
 529                 if (fill_rx) {
 530                         count++;
 531                         if (count >= 8) {
 532                                 rxq->read = i;
 533                                 iwlagn_rx_replenish_now(trans);
 534                                 count = 0;
 535                         }
 536                 }
 537         }
 538
 539         /* Backtrack one entry */
 540         rxq->read = i;
 541         if (fill_rx)
 542                 iwlagn_rx_replenish_now(trans);
 543         else
 544                 iwlagn_rx_queue_restock(trans);
 545 }
 546
 547 /**
 548  * iwl_irq_handle_error - called for HW or SW error interrupt from card
 549  */
 550 static void iwl_irq_handle_error(struct iwl_trans *trans)
 551 {
 552         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 553         if (trans->cfg->internal_wimax_coex &&
 554             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
 555                              APMS_CLK_VAL_MRB_FUNC_MODE) ||
 556              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
 557                             APMG_PS_CTRL_VAL_RESET_REQ))) {
 558                 struct iwl_trans_pcie *trans_pcie =
 559                         IWL_TRANS_GET_PCIE_TRANS(trans);
 560
 561                 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 562                 iwl_op_mode_wimax_active(trans->op_mode);
 563                 wake_up(&trans->wait_command_queue);
 564                 return;
 565         }
 566
 567         iwl_dump_csr(trans);
 568         iwl_dump_fh(trans, NULL);
 569
 570         iwl_op_mode_nic_error(trans->op_mode);
 571 }
 572
 573 /* tasklet for iwlagn interrupt */
 574 void iwl_irq_tasklet(struct iwl_trans *trans)
 575 {
 576         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 577         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 578         u32 inta = 0;
 579         u32 handled = 0;
 580         unsigned long flags;
 581         u32 i;
 582 #ifdef CONFIG_IWLWIFI_DEBUG
 583         u32 inta_mask;
 584 #endif
 585
 586         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 587
 588         /* Ack/clear/reset pending uCode interrupts.
 589          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 590          */
 591         /* There is a hardware bug in the interrupt mask function that some
 592          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 593          * they are disabled in the CSR_INT_MASK register. Furthermore the
 594          * ICT interrupt handling mechanism has another bug that might cause
 595          * these unmasked interrupts fail to be detected. We workaround the
 596          * hardware bugs here by ACKing all the possible interrupts so that
 597          * interrupt coalescing can still be achieved.
 598          */
 599         iwl_write32(trans, CSR_INT,
 600                     trans_pcie->inta | ~trans_pcie->inta_mask);
 601
 602         inta = trans_pcie->inta;
 603
 604 #ifdef CONFIG_IWLWIFI_DEBUG
 605         if (iwl_have_debug_level(IWL_DL_ISR)) {
 606                 /* just for debug */
 607                 inta_mask = iwl_read32(trans, CSR_INT_MASK);
 608                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
 609                               inta, inta_mask);
 610         }
 611 #endif
 612
 613         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 614         trans_pcie->inta = 0;
 615
 616         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 617
 618         /* Now service all interrupt bits discovered above. */
 619         if (inta & CSR_INT_BIT_HW_ERR) {
 620                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 621
 622                 /* Tell the device to stop sending interrupts */
 623                 iwl_disable_interrupts(trans);
 624
 625                 isr_stats->hw++;
 626                 iwl_irq_handle_error(trans);
 627
 628                 handled |= CSR_INT_BIT_HW_ERR;
 629
 630                 return;
 631         }
 632
 633 #ifdef CONFIG_IWLWIFI_DEBUG
 634         if (iwl_have_debug_level(IWL_DL_ISR)) {
 635                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 636                 if (inta & CSR_INT_BIT_SCD) {
 637                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
 638                                       "the frame/frames.\n");
 639                         isr_stats->sch++;
 640                 }
 641
 642                 /* Alive notification via Rx interrupt will do the real work */
 643                 if (inta & CSR_INT_BIT_ALIVE) {
 644                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
 645                         isr_stats->alive++;
 646                 }
 647         }
 648 #endif
 649         /* Safely ignore these bits for debug checks below */
 650         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 651
 652         /* HW RF KILL switch toggled */
 653         if (inta & CSR_INT_BIT_RF_KILL) {
 654                 bool hw_rfkill;
 655
 656                 hw_rfkill = iwl_is_rfkill_set(trans);
 657                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
 658                          hw_rfkill ? "disable radio" : "enable radio");
 659
 660                 isr_stats->rfkill++;
 661
 662                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 663
 664                 handled |= CSR_INT_BIT_RF_KILL;
 665         }
 666
 667         /* Chip got too hot and stopped itself */
 668         if (inta & CSR_INT_BIT_CT_KILL) {
 669                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
 670                 isr_stats->ctkill++;
 671                 handled |= CSR_INT_BIT_CT_KILL;
 672         }
 673
 674         /* Error detected by uCode */
 675         if (inta & CSR_INT_BIT_SW_ERR) {
 676                 IWL_ERR(trans, "Microcode SW error detected. "
 677                         " Restarting 0x%X.\n", inta);
 678                 isr_stats->sw++;
 679                 iwl_irq_handle_error(trans);
 680                 handled |= CSR_INT_BIT_SW_ERR;
 681         }
 682
 683         /* uCode wakes up after power-down sleep */
 684         if (inta & CSR_INT_BIT_WAKEUP) {
 685                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
 686                 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
 687                 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++)
 688                         iwl_txq_update_write_ptr(trans,
 689                                                  &trans_pcie->txq[i]);
 690
 691                 isr_stats->wakeup++;
 692
 693                 handled |= CSR_INT_BIT_WAKEUP;
 694         }
 695
 696         /* All uCode command responses, including Tx command responses,
 697          * Rx "responses" (frame-received notification), and other
 698          * notifications from uCode come through here*/
 699         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
 700                     CSR_INT_BIT_RX_PERIODIC)) {
 701                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
 702                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
 703                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
 704                         iwl_write32(trans, CSR_FH_INT_STATUS,
 705                                         CSR_FH_INT_RX_MASK);
 706                 }
 707                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
 708                         handled |= CSR_INT_BIT_RX_PERIODIC;
 709                         iwl_write32(trans,
 710                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
 711                 }
 712                 /* Sending RX interrupt require many steps to be done in the
 713                  * the device:
 714                  * 1- write interrupt to current index in ICT table.
 715                  * 2- dma RX frame.
 716                  * 3- update RX shared data to indicate last write index.
 717                  * 4- send interrupt.
 718                  * This could lead to RX race, driver could receive RX interrupt
 719                  * but the shared data changes does not reflect this;
 720                  * periodic interrupt will detect any dangling Rx activity.
 721                  */
 722
 723                 /* Disable periodic interrupt; we use it as just a one-shot. */
 724                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
 725                             CSR_INT_PERIODIC_DIS);
 726 #ifdef CONFIG_IWLWIFI_IDI
 727                 iwl_amfh_rx_handler();
 728 #else
 729                 iwl_rx_handle(trans);
 730 #endif
 731                 /*
 732                  * Enable periodic interrupt in 8 msec only if we received
 733                  * real RX interrupt (instead of just periodic int), to catch
 734                  * any dangling Rx interrupt.  If it was just the periodic
 735                  * interrupt, there was no dangling Rx activity, and no need
 736                  * to extend the periodic interrupt; one-shot is enough.
 737                  */
 738                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
 739                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
 740                                    CSR_INT_PERIODIC_ENA);
 741
 742                 isr_stats->rx++;
 743         }
 744
 745         /* This "Tx" DMA channel is used only for loading uCode */
 746         if (inta & CSR_INT_BIT_FH_TX) {
 747                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
 748                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
 749                 isr_stats->tx++;
 750                 handled |= CSR_INT_BIT_FH_TX;
 751                 /* Wake up uCode load routine, now that load is complete */
 752                 trans_pcie->ucode_write_complete = true;
 753                 wake_up(&trans_pcie->ucode_write_waitq);
 754         }
 755
 756         if (inta & ~handled) {
 757                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
 758                 isr_stats->unhandled++;
 759         }
 760
 761         if (inta & ~(trans_pcie->inta_mask)) {
 762                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
 763                          inta & ~trans_pcie->inta_mask);
 764         }
 765
 766         /* Re-enable all interrupts */
 767         /* only Re-enable if disabled by irq */
 768         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status))
 769                 iwl_enable_interrupts(trans);
 770         /* Re-enable RF_KILL if it occurred */
 771         else if (handled & CSR_INT_BIT_RF_KILL)
 772                 iwl_enable_rfkill_int(trans);
 773 }
 774
 775 /******************************************************************************
 776  *
 777  * ICT functions
 778  *
 779  ******************************************************************************/
 780
 781 /* a device (PCI-E) page is 4096 bytes long */
 782 #define ICT_SHIFT       12
 783 #define ICT_SIZE        (1 << ICT_SHIFT)
 784 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
 785
 786 /* Free dram table */
 787 void iwl_free_isr_ict(struct iwl_trans *trans)
 788 {
 789         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 790
 791         if (trans_pcie->ict_tbl) {
 792                 dma_free_coherent(trans->dev, ICT_SIZE,
 793                                   trans_pcie->ict_tbl,
 794                                   trans_pcie->ict_tbl_dma);
 795                 trans_pcie->ict_tbl = NULL;
 796                 trans_pcie->ict_tbl_dma = 0;
 797         }
 798 }
 799
 800
 801 /*
 802  * allocate dram shared table, it is an aligned memory
 803  * block of ICT_SIZE.
 804  * also reset all data related to ICT table interrupt.
 805  */
 806 int iwl_alloc_isr_ict(struct iwl_trans *trans)
 807 {
 808         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 809
 810         trans_pcie->ict_tbl =
 811                 dma_alloc_coherent(trans->dev, ICT_SIZE,
 812                                    &trans_pcie->ict_tbl_dma,
 813                                    GFP_KERNEL);
 814         if (!trans_pcie->ict_tbl)
 815                 return -ENOMEM;
 816
 817         /* just an API sanity check ... it is guaranteed to be aligned */
 818         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
 819                 iwl_free_isr_ict(trans);
 820                 return -EINVAL;
 821         }
 822
 823         IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
 824                       (unsigned long long)trans_pcie->ict_tbl_dma);
 825
 826         IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
 827
 828         /* reset table and index to all 0 */
 829         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
 830         trans_pcie->ict_index = 0;
 831
 832         /* add periodic RX interrupt */
 833         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
 834         return 0;
 835 }
 836
 837 /* Device is going up inform it about using ICT interrupt table,
 838  * also we need to tell the driver to start using ICT interrupt.
 839  */
 840 void iwl_reset_ict(struct iwl_trans *trans)
 841 {
 842         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 843         u32 val;
 844         unsigned long flags;
 845
 846         if (!trans_pcie->ict_tbl)
 847                 return;
 848
 849         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 850         iwl_disable_interrupts(trans);
 851
 852         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
 853
 854         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
 855
 856         val |= CSR_DRAM_INT_TBL_ENABLE;
 857         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
 858
 859         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
 860
 861         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
 862         trans_pcie->use_ict = true;
 863         trans_pcie->ict_index = 0;
 864         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
 865         iwl_enable_interrupts(trans);
 866         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 867 }
 868
 869 /* Device is going down disable ict interrupt usage */
 870 void iwl_disable_ict(struct iwl_trans *trans)
 871 {
 872         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 873         unsigned long flags;
 874
 875         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 876         trans_pcie->use_ict = false;
 877         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 878 }
 879
 880 /* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
 881 static irqreturn_t iwl_isr(int irq, void *data)
 882 {
 883         struct iwl_trans *trans = data;
 884         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 885         u32 inta, inta_mask;
 886 #ifdef CONFIG_IWLWIFI_DEBUG
 887         u32 inta_fh;
 888 #endif
 889
 890         lockdep_assert_held(&trans_pcie->irq_lock);
 891
 892         trace_iwlwifi_dev_irq(trans->dev);
 893
 894         /* Disable (but don't clear!) interrupts here to avoid
 895          *    back-to-back ISRs and sporadic interrupts from our NIC.
 896          * If we have something to service, the tasklet will re-enable ints.
 897          * If we *don't* have something, we'll re-enable before leaving here. */
 898         inta_mask = iwl_read32(trans, CSR_INT_MASK);  /* just for debug */
 899         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
 900
 901         /* Discover which interrupts are active/pending */
 902         inta = iwl_read32(trans, CSR_INT);
 903
 904         /* Ignore interrupt if there's nothing in NIC to service.
 905          * This may be due to IRQ shared with another device,
 906          * or due to sporadic interrupts thrown from our NIC. */
 907         if (!inta) {
 908                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
 909                 goto none;
 910         }
 911
 912         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
 913                 /* Hardware disappeared. It might have already raised
 914                  * an interrupt */
 915                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
 916                 return IRQ_HANDLED;
 917         }
 918
 919 #ifdef CONFIG_IWLWIFI_DEBUG
 920         if (iwl_have_debug_level(IWL_DL_ISR)) {
 921                 inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS);
 922                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
 923                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
 924         }
 925 #endif
 926
 927         trans_pcie->inta |= inta;
 928         /* iwl_irq_tasklet() will service interrupts and re-enable them */
 929         if (likely(inta))
 930                 tasklet_schedule(&trans_pcie->irq_tasklet);
 931         else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
 932                  !trans_pcie->inta)
 933                 iwl_enable_interrupts(trans);
 934
 935 none:
 936         /* re-enable interrupts here since we don't have anything to service. */
 937         /* only Re-enable if disabled by irq  and no schedules tasklet. */
 938         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
 939             !trans_pcie->inta)
 940                 iwl_enable_interrupts(trans);
 941
 942         return IRQ_NONE;
 943 }
 944
 945 /* interrupt handler using ict table, with this interrupt driver will
 946  * stop using INTA register to get device's interrupt, reading this register
 947  * is expensive, device will write interrupts in ICT dram table, increment
 948  * index then will fire interrupt to driver, driver will OR all ICT table
 949  * entries from current index up to table entry with 0 value. the result is
 950  * the interrupt we need to service, driver will set the entries back to 0 and
 951  * set index.
 952  */
 953 irqreturn_t iwl_isr_ict(int irq, void *data)
 954 {
 955         struct iwl_trans *trans = data;
 956         struct iwl_trans_pcie *trans_pcie;
 957         u32 inta, inta_mask;
 958         u32 val = 0;
 959         u32 read;
 960         unsigned long flags;
 961
 962         if (!trans)
 963                 return IRQ_NONE;
 964
 965         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 966
 967         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 968
 969         /* dram interrupt table not set yet,
 970          * use legacy interrupt.
 971          */
 972         if (unlikely(!trans_pcie->use_ict)) {
 973                 irqreturn_t ret = iwl_isr(irq, data);
 974                 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 975                 return ret;
 976         }
 977
 978         trace_iwlwifi_dev_irq(trans->dev);
 979
 980
 981         /* Disable (but don't clear!) interrupts here to avoid
 982          * back-to-back ISRs and sporadic interrupts from our NIC.
 983          * If we have something to service, the tasklet will re-enable ints.
 984          * If we *don't* have something, we'll re-enable before leaving here.
 985          */
 986         inta_mask = iwl_read32(trans, CSR_INT_MASK);  /* just for debug */
 987         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
 988
 989
 990         /* Ignore interrupt if there's nothing in NIC to service.
 991          * This may be due to IRQ shared with another device,
 992          * or due to sporadic interrupts thrown from our NIC. */
 993         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
 994         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
 995         if (!read) {
 996                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
 997                 goto none;
 998         }
 999
1000         /*
1001          * Collect all entries up to the first 0, starting from ict_index;
1002          * note we already read at ict_index.
1003          */
1004         do {
1005                 val |= read;
1006                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1007                                 trans_pcie->ict_index, read);
1008                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1009                 trans_pcie->ict_index =
1010                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1011
1012                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1013                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1014                                            read);
1015         } while (read);
1016
1017         /* We should not get this value, just ignore it. */
1018         if (val == 0xffffffff)
1019                 val = 0;
1020
1021         /*
1022          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1023          * (bit 15 before shifting it to 31) to clear when using interrupt
1024          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1025          * so we use them to decide on the real state of the Rx bit.
1026          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1027          */
1028         if (val & 0xC0000)
1029                 val |= 0x8000;
1030
1031         inta = (0xff & val) | ((0xff00 & val) << 16);
1032         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1033                       inta, inta_mask, val);
1034
1035         inta &= trans_pcie->inta_mask;
1036         trans_pcie->inta |= inta;
1037
1038         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1039         if (likely(inta))
1040                 tasklet_schedule(&trans_pcie->irq_tasklet);
1041         else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1042                  !trans_pcie->inta) {
1043                 /* Allow interrupt if was disabled by this handler and
1044                  * no tasklet was schedules, We should not enable interrupt,
1045                  * tasklet will enable it.
1046                  */
1047                 iwl_enable_interrupts(trans);
1048         }
1049
1050         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1051         return IRQ_HANDLED;
1052
1053  none:
1054         /* re-enable interrupts here since we don't have anything to service.
1055          * only Re-enable if disabled by irq.
1056          */
1057         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1058             !trans_pcie->inta)
1059                 iwl_enable_interrupts(trans);
1060
1061         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1062         return IRQ_NONE;
1063 }