drivers/net/wireless/iwlwifi/pcie/rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 #include "iwl-prph.h"
  34 #include "iwl-io.h"
  35 #include "internal.h"
  36 #include "iwl-op-mode.h"
  37
  38 /******************************************************************************
  39  *
  40  * RX path functions
  41  *
  42  ******************************************************************************/
  43
  44 /*
  45  * Rx theory of operation
  46  *
  47  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  48  * each of which point to Receive Buffers to be filled by the NIC.  These get
  49  * used not only for Rx frames, but for any command response or notification
  50  * from the NIC.  The driver and NIC manage the Rx buffers by means
  51  * of indexes into the circular buffer.
  52  *
  53  * Rx Queue Indexes
  54  * The host/firmware share two index registers for managing the Rx buffers.
  55  *
  56  * The READ index maps to the first position that the firmware may be writing
  57  * to -- the driver can read up to (but not including) this position and get
  58  * good data.
  59  * The READ index is managed by the firmware once the card is enabled.
  60  *
  61  * The WRITE index maps to the last position the driver has read from -- the
  62  * position preceding WRITE is the last slot the firmware can place a packet.
  63  *
  64  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  65  * WRITE = READ.
  66  *
  67  * During initialization, the host sets up the READ queue position to the first
  68  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  69  *
  70  * When the firmware places a packet in a buffer, it will advance the READ index
  71  * and fire the RX interrupt.  The driver can then query the READ index and
  72  * process as many packets as possible, moving the WRITE index forward as it
  73  * resets the Rx queue buffers with new memory.
  74  *
  75  * The management in the driver is as follows:
  76  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  77  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  78  *   to replenish the iwl->rxq->rx_free.
  79  * + In iwl_pcie_rx_replenish (scheduled) if 'processed' != 'read' then the
  80  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  81  *   'processed' and 'read' driver indexes as well)
  82  * + A received packet is processed and handed to the kernel network stack,
  83  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  84  * + The Host/Firmware iwl->rxq is replenished at irq thread time from the
  85  *   rx_free list. If there are no allocated buffers in iwl->rxq->rx_free,
  86  *   the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
  87  *   If there were enough free buffers and RX_STALLED is set it is cleared.
  88  *
  89  *
  90  * Driver sequence:
  91  *
  92  * iwl_rxq_alloc()            Allocates rx_free
  93  * iwl_pcie_rx_replenish()    Replenishes rx_free list from rx_used, and calls
  94  *                            iwl_pcie_rxq_restock
  95  * iwl_pcie_rxq_restock()     Moves available buffers from rx_free into Rx
  96  *                            queue, updates firmware pointers, and updates
  97  *                            the WRITE index.  If insufficient rx_free buffers
  98  *                            are available, schedules iwl_pcie_rx_replenish
  99  *
 100  * -- enable interrupts --
 101  * ISR - iwl_rx()             Detach iwl_rx_mem_buffers from pool up to the
 102  *                            READ INDEX, detaching the SKB from the pool.
 103  *                            Moves the packet buffer from queue to rx_used.
 104  *                            Calls iwl_pcie_rxq_restock to refill any empty
 105  *                            slots.
 106  * ...
 107  *
 108  */
 109
 110 /*
 111  * iwl_rxq_space - Return number of free slots available in queue.
 112  */
 113 static int iwl_rxq_space(const struct iwl_rxq *rxq)
 114 {
 115         /* Make sure RX_QUEUE_SIZE is a power of 2 */
 116         BUILD_BUG_ON(RX_QUEUE_SIZE & (RX_QUEUE_SIZE - 1));
 117
 118         /*
 119          * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
 120          * between empty and completely full queues.
 121          * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
 122          * defined for negative dividends.
 123          */
 124         return (rxq->read - rxq->write - 1) & (RX_QUEUE_SIZE - 1);
 125 }
 126
 127 /*
 128  * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 129  */
 130 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 131 {
 132         return cpu_to_le32((u32)(dma_addr >> 8));
 133 }
 134
 135 /*
 136  * iwl_pcie_rx_stop - stops the Rx DMA
 137  */
 138 int iwl_pcie_rx_stop(struct iwl_trans *trans)
 139 {
 140         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 141         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 142                                    FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 143 }
 144
 145 /*
 146  * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
 147  */
 148 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
 149                                     struct iwl_rxq *rxq)
 150 {
 151         unsigned long flags;
 152         u32 reg;
 153
 154         spin_lock_irqsave(&rxq->lock, flags);
 155
 156         if (rxq->need_update == 0)
 157                 goto exit_unlock;
 158
 159         if (trans->cfg->base_params->shadow_reg_enable) {
 160                 /* shadow register enabled */
 161                 /* Device expects a multiple of 8 */
 162                 rxq->write_actual = (rxq->write & ~0x7);
 163                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
 164         } else {
 165                 struct iwl_trans_pcie *trans_pcie =
 166                         IWL_TRANS_GET_PCIE_TRANS(trans);
 167
 168                 /* If power-saving is in use, make sure device is awake */
 169                 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
 170                         reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 171
 172                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 173                                 IWL_DEBUG_INFO(trans,
 174                                         "Rx queue requesting wakeup,"
 175                                         " GP1 = 0x%x\n", reg);
 176                                 iwl_set_bit(trans, CSR_GP_CNTRL,
 177                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 178                                 goto exit_unlock;
 179                         }
 180
 181                         rxq->write_actual = (rxq->write & ~0x7);
 182                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 183                                            rxq->write_actual);
 184
 185                 /* Else device is assumed to be awake */
 186                 } else {
 187                         /* Device expects a multiple of 8 */
 188                         rxq->write_actual = (rxq->write & ~0x7);
 189                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 190                                            rxq->write_actual);
 191                 }
 192         }
 193         rxq->need_update = 0;
 194
 195  exit_unlock:
 196         spin_unlock_irqrestore(&rxq->lock, flags);
 197 }
 198
 199 /*
 200  * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
 201  *
 202  * If there are slots in the RX queue that need to be restocked,
 203  * and we have free pre-allocated buffers, fill the ranks as much
 204  * as we can, pulling from rx_free.
 205  *
 206  * This moves the 'write' index forward to catch up with 'processed', and
 207  * also updates the memory address in the firmware to reference the new
 208  * target buffer.
 209  */
 210 static void iwl_pcie_rxq_restock(struct iwl_trans *trans)
 211 {
 212         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 213         struct iwl_rxq *rxq = &trans_pcie->rxq;
 214         struct iwl_rx_mem_buffer *rxb;
 215         unsigned long flags;
 216
 217         /*
 218          * If the device isn't enabled - not need to try to add buffers...
 219          * This can happen when we stop the device and still have an interrupt
 220          * pending. We stop the APM before we sync the interrupts because we
 221          * have to (see comment there). On the other hand, since the APM is
 222          * stopped, we cannot access the HW (in particular not prph).
 223          * So don't try to restock if the APM has been already stopped.
 224          */
 225         if (!test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status))
 226                 return;
 227
 228         spin_lock_irqsave(&rxq->lock, flags);
 229         while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
 230                 /* The overwritten rxb must be a used one */
 231                 rxb = rxq->queue[rxq->write];
 232                 BUG_ON(rxb && rxb->page);
 233
 234                 /* Get next free Rx buffer, remove from free list */
 235                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 236                                        list);
 237                 list_del(&rxb->list);
 238
 239                 /* Point to Rx buffer via next RBD in circular buffer */
 240                 rxq->bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
 241                 rxq->queue[rxq->write] = rxb;
 242                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 243                 rxq->free_count--;
 244         }
 245         spin_unlock_irqrestore(&rxq->lock, flags);
 246         /* If the pre-allocated buffer pool is dropping low, schedule to
 247          * refill it */
 248         if (rxq->free_count <= RX_LOW_WATERMARK)
 249                 schedule_work(&trans_pcie->rx_replenish);
 250
 251         /* If we've added more space for the firmware to place data, tell it.
 252          * Increment device's write pointer in multiples of 8. */
 253         if (rxq->write_actual != (rxq->write & ~0x7)) {
 254                 spin_lock_irqsave(&rxq->lock, flags);
 255                 rxq->need_update = 1;
 256                 spin_unlock_irqrestore(&rxq->lock, flags);
 257                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 258         }
 259 }
 260
 261 /*
 262  * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
 263  *
 264  * A used RBD is an Rx buffer that has been given to the stack. To use it again
 265  * a page must be allocated and the RBD must point to the page. This function
 266  * doesn't change the HW pointer but handles the list of pages that is used by
 267  * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
 268  * allocated buffers.
 269  */
 270 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority)
 271 {
 272         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 273         struct iwl_rxq *rxq = &trans_pcie->rxq;
 274         struct iwl_rx_mem_buffer *rxb;
 275         struct page *page;
 276         unsigned long flags;
 277         gfp_t gfp_mask = priority;
 278
 279         while (1) {
 280                 spin_lock_irqsave(&rxq->lock, flags);
 281                 if (list_empty(&rxq->rx_used)) {
 282                         spin_unlock_irqrestore(&rxq->lock, flags);
 283                         return;
 284                 }
 285                 spin_unlock_irqrestore(&rxq->lock, flags);
 286
 287                 if (rxq->free_count > RX_LOW_WATERMARK)
 288                         gfp_mask |= __GFP_NOWARN;
 289
 290                 if (trans_pcie->rx_page_order > 0)
 291                         gfp_mask |= __GFP_COMP;
 292
 293                 /* Alloc a new receive buffer */
 294                 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
 295                 if (!page) {
 296                         if (net_ratelimit())
 297                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 298                                            "order: %d\n",
 299                                            trans_pcie->rx_page_order);
 300
 301                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 302                             net_ratelimit())
 303                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 304                                          "Only %u free buffers remaining.\n",
 305                                          priority == GFP_ATOMIC ?
 306                                          "GFP_ATOMIC" : "GFP_KERNEL",
 307                                          rxq->free_count);
 308                         /* We don't reschedule replenish work here -- we will
 309                          * call the restock method and if it still needs
 310                          * more buffers it will schedule replenish */
 311                         return;
 312                 }
 313
 314                 spin_lock_irqsave(&rxq->lock, flags);
 315
 316                 if (list_empty(&rxq->rx_used)) {
 317                         spin_unlock_irqrestore(&rxq->lock, flags);
 318                         __free_pages(page, trans_pcie->rx_page_order);
 319                         return;
 320                 }
 321                 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
 322                                        list);
 323                 list_del(&rxb->list);
 324                 spin_unlock_irqrestore(&rxq->lock, flags);
 325
 326                 BUG_ON(rxb->page);
 327                 rxb->page = page;
 328                 /* Get physical address of the RB */
 329                 rxb->page_dma =
 330                         dma_map_page(trans->dev, page, 0,
 331                                      PAGE_SIZE << trans_pcie->rx_page_order,
 332                                      DMA_FROM_DEVICE);
 333                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 334                         rxb->page = NULL;
 335                         spin_lock_irqsave(&rxq->lock, flags);
 336                         list_add(&rxb->list, &rxq->rx_used);
 337                         spin_unlock_irqrestore(&rxq->lock, flags);
 338                         __free_pages(page, trans_pcie->rx_page_order);
 339                         return;
 340                 }
 341                 /* dma address must be no more than 36 bits */
 342                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 343                 /* and also 256 byte aligned! */
 344                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 345
 346                 spin_lock_irqsave(&rxq->lock, flags);
 347
 348                 list_add_tail(&rxb->list, &rxq->rx_free);
 349                 rxq->free_count++;
 350
 351                 spin_unlock_irqrestore(&rxq->lock, flags);
 352         }
 353 }
 354
 355 static void iwl_pcie_rxq_free_rbs(struct iwl_trans *trans)
 356 {
 357         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 358         struct iwl_rxq *rxq = &trans_pcie->rxq;
 359         int i;
 360
 361         lockdep_assert_held(&rxq->lock);
 362
 363         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 364                 if (!rxq->pool[i].page)
 365                         continue;
 366                 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 367                                PAGE_SIZE << trans_pcie->rx_page_order,
 368                                DMA_FROM_DEVICE);
 369                 __free_pages(rxq->pool[i].page, trans_pcie->rx_page_order);
 370                 rxq->pool[i].page = NULL;
 371         }
 372 }
 373
 374 /*
 375  * iwl_pcie_rx_replenish - Move all used buffers from rx_used to rx_free
 376  *
 377  * When moving to rx_free an page is allocated for the slot.
 378  *
 379  * Also restock the Rx queue via iwl_pcie_rxq_restock.
 380  * This is called as a scheduled work item (except for during initialization)
 381  */
 382 static void iwl_pcie_rx_replenish(struct iwl_trans *trans)
 383 {
 384         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 385         unsigned long flags;
 386
 387         iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL);
 388
 389         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 390         iwl_pcie_rxq_restock(trans);
 391         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 392 }
 393
 394 static void iwl_pcie_rx_replenish_now(struct iwl_trans *trans)
 395 {
 396         iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC);
 397
 398         iwl_pcie_rxq_restock(trans);
 399 }
 400
 401 static void iwl_pcie_rx_replenish_work(struct work_struct *data)
 402 {
 403         struct iwl_trans_pcie *trans_pcie =
 404             container_of(data, struct iwl_trans_pcie, rx_replenish);
 405
 406         iwl_pcie_rx_replenish(trans_pcie->trans);
 407 }
 408
 409 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
 410 {
 411         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 412         struct iwl_rxq *rxq = &trans_pcie->rxq;
 413         struct device *dev = trans->dev;
 414
 415         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
 416
 417         spin_lock_init(&rxq->lock);
 418
 419         if (WARN_ON(rxq->bd || rxq->rb_stts))
 420                 return -EINVAL;
 421
 422         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
 423         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 424                                       &rxq->bd_dma, GFP_KERNEL);
 425         if (!rxq->bd)
 426                 goto err_bd;
 427
 428         /*Allocate the driver's pointer to receive buffer status */
 429         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 430                                            &rxq->rb_stts_dma, GFP_KERNEL);
 431         if (!rxq->rb_stts)
 432                 goto err_rb_stts;
 433
 434         return 0;
 435
 436 err_rb_stts:
 437         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 438                           rxq->bd, rxq->bd_dma);
 439         rxq->bd_dma = 0;
 440         rxq->bd = NULL;
 441 err_bd:
 442         return -ENOMEM;
 443 }
 444
 445 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
 446 {
 447         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 448         u32 rb_size;
 449         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 450
 451         if (trans_pcie->rx_buf_size_8k)
 452                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 453         else
 454                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 455
 456         /* Stop Rx DMA */
 457         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 458         /* reset and flush pointers */
 459         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
 460         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
 461         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
 462
 463         /* Reset driver's Rx queue write index */
 464         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 465
 466         /* Tell device where to find RBD circular buffer in DRAM */
 467         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 468                            (u32)(rxq->bd_dma >> 8));
 469
 470         /* Tell device where in DRAM to update its Rx status */
 471         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 472                            rxq->rb_stts_dma >> 4);
 473
 474         /* Enable Rx DMA
 475          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 476          *      the credit mechanism in 5000 HW RX FIFO
 477          * Direct rx interrupts to hosts
 478          * Rx buffer size 4 or 8k
 479          * RB timeout 0x10
 480          * 256 RBDs
 481          */
 482         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 483                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 484                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 485                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 486                            rb_size|
 487                            (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 488                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 489
 490         /* Set interrupt coalescing timer to default (2048 usecs) */
 491         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 492 }
 493
 494 static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
 495 {
 496         int i;
 497
 498         lockdep_assert_held(&rxq->lock);
 499
 500         INIT_LIST_HEAD(&rxq->rx_free);
 501         INIT_LIST_HEAD(&rxq->rx_used);
 502         rxq->free_count = 0;
 503
 504         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
 505                 list_add(&rxq->pool[i].list, &rxq->rx_used);
 506 }
 507
 508 int iwl_pcie_rx_init(struct iwl_trans *trans)
 509 {
 510         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 511         struct iwl_rxq *rxq = &trans_pcie->rxq;
 512         int i, err;
 513         unsigned long flags;
 514
 515         if (!rxq->bd) {
 516                 err = iwl_pcie_rx_alloc(trans);
 517                 if (err)
 518                         return err;
 519         }
 520
 521         spin_lock_irqsave(&rxq->lock, flags);
 522
 523         INIT_WORK(&trans_pcie->rx_replenish, iwl_pcie_rx_replenish_work);
 524
 525         /* free all first - we might be reconfigured for a different size */
 526         iwl_pcie_rxq_free_rbs(trans);
 527         iwl_pcie_rx_init_rxb_lists(rxq);
 528
 529         for (i = 0; i < RX_QUEUE_SIZE; i++)
 530                 rxq->queue[i] = NULL;
 531
 532         /* Set us so that we have processed and used all buffers, but have
 533          * not restocked the Rx queue with fresh buffers */
 534         rxq->read = rxq->write = 0;
 535         rxq->write_actual = 0;
 536         memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
 537         spin_unlock_irqrestore(&rxq->lock, flags);
 538
 539         iwl_pcie_rx_replenish(trans);
 540
 541         iwl_pcie_rx_hw_init(trans, rxq);
 542
 543         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 544         rxq->need_update = 1;
 545         iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 546         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 547
 548         return 0;
 549 }
 550
 551 void iwl_pcie_rx_free(struct iwl_trans *trans)
 552 {
 553         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 554         struct iwl_rxq *rxq = &trans_pcie->rxq;
 555         unsigned long flags;
 556
 557         /*if rxq->bd is NULL, it means that nothing has been allocated,
 558          * exit now */
 559         if (!rxq->bd) {
 560                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 561                 return;
 562         }
 563
 564         cancel_work_sync(&trans_pcie->rx_replenish);
 565
 566         spin_lock_irqsave(&rxq->lock, flags);
 567         iwl_pcie_rxq_free_rbs(trans);
 568         spin_unlock_irqrestore(&rxq->lock, flags);
 569
 570         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 571                           rxq->bd, rxq->bd_dma);
 572         rxq->bd_dma = 0;
 573         rxq->bd = NULL;
 574
 575         if (rxq->rb_stts)
 576                 dma_free_coherent(trans->dev,
 577                                   sizeof(struct iwl_rb_status),
 578                                   rxq->rb_stts, rxq->rb_stts_dma);
 579         else
 580                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 581         rxq->rb_stts_dma = 0;
 582         rxq->rb_stts = NULL;
 583 }
 584
 585 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
 586                                 struct iwl_rx_mem_buffer *rxb)
 587 {
 588         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 589         struct iwl_rxq *rxq = &trans_pcie->rxq;
 590         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
 591         unsigned long flags;
 592         bool page_stolen = false;
 593         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
 594         u32 offset = 0;
 595
 596         if (WARN_ON(!rxb))
 597                 return;
 598
 599         dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
 600
 601         while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
 602                 struct iwl_rx_packet *pkt;
 603                 struct iwl_device_cmd *cmd;
 604                 u16 sequence;
 605                 bool reclaim;
 606                 int index, cmd_index, err, len;
 607                 struct iwl_rx_cmd_buffer rxcb = {
 608                         ._offset = offset,
 609                         ._rx_page_order = trans_pcie->rx_page_order,
 610                         ._page = rxb->page,
 611                         ._page_stolen = false,
 612                         .truesize = max_len,
 613                 };
 614
 615                 pkt = rxb_addr(&rxcb);
 616
 617                 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID))
 618                         break;
 619
 620                 IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n",
 621                         rxcb._offset, get_cmd_string(trans_pcie, pkt->hdr.cmd),
 622                         pkt->hdr.cmd);
 623
 624                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 625                 len += sizeof(u32); /* account for status word */
 626                 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
 627                 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
 628
 629                 /* Reclaim a command buffer only if this packet is a response
 630                  *   to a (driver-originated) command.
 631                  * If the packet (e.g. Rx frame) originated from uCode,
 632                  *   there is no command buffer to reclaim.
 633                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 634                  *   but apparently a few don't get set; catch them here. */
 635                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
 636                 if (reclaim) {
 637                         int i;
 638
 639                         for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
 640                                 if (trans_pcie->no_reclaim_cmds[i] ==
 641                                                         pkt->hdr.cmd) {
 642                                         reclaim = false;
 643                                         break;
 644                                 }
 645                         }
 646                 }
 647
 648                 sequence = le16_to_cpu(pkt->hdr.sequence);
 649                 index = SEQ_TO_INDEX(sequence);
 650                 cmd_index = get_cmd_index(&txq->q, index);
 651
 652                 if (reclaim)
 653                         cmd = txq->entries[cmd_index].cmd;
 654                 else
 655                         cmd = NULL;
 656
 657                 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
 658
 659                 if (reclaim) {
 660                         kfree(txq->entries[cmd_index].free_buf);
 661                         txq->entries[cmd_index].free_buf = NULL;
 662                 }
 663
 664                 /*
 665                  * After here, we should always check rxcb._page_stolen,
 666                  * if it is true then one of the handlers took the page.
 667                  */
 668
 669                 if (reclaim) {
 670                         /* Invoke any callbacks, transfer the buffer to caller,
 671                          * and fire off the (possibly) blocking
 672                          * iwl_trans_send_cmd()
 673                          * as we reclaim the driver command queue */
 674                         if (!rxcb._page_stolen)
 675                                 iwl_pcie_hcmd_complete(trans, &rxcb, err);
 676                         else
 677                                 IWL_WARN(trans, "Claim null rxb?\n");
 678                 }
 679
 680                 page_stolen |= rxcb._page_stolen;
 681                 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
 682         }
 683
 684         /* page was stolen from us -- free our reference */
 685         if (page_stolen) {
 686                 __free_pages(rxb->page, trans_pcie->rx_page_order);
 687                 rxb->page = NULL;
 688         }
 689
 690         /* Reuse the page if possible. For notification packets and
 691          * SKBs that fail to Rx correctly, add them back into the
 692          * rx_free list for reuse later. */
 693         spin_lock_irqsave(&rxq->lock, flags);
 694         if (rxb->page != NULL) {
 695                 rxb->page_dma =
 696                         dma_map_page(trans->dev, rxb->page, 0,
 697                                      PAGE_SIZE << trans_pcie->rx_page_order,
 698                                      DMA_FROM_DEVICE);
 699                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 700                         /*
 701                          * free the page(s) as well to not break
 702                          * the invariant that the items on the used
 703                          * list have no page(s)
 704                          */
 705                         __free_pages(rxb->page, trans_pcie->rx_page_order);
 706                         rxb->page = NULL;
 707                         list_add_tail(&rxb->list, &rxq->rx_used);
 708                 } else {
 709                         list_add_tail(&rxb->list, &rxq->rx_free);
 710                         rxq->free_count++;
 711                 }
 712         } else
 713                 list_add_tail(&rxb->list, &rxq->rx_used);
 714         spin_unlock_irqrestore(&rxq->lock, flags);
 715 }
 716
 717 /*
 718  * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
 719  */
 720 static void iwl_pcie_rx_handle(struct iwl_trans *trans)
 721 {
 722         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 723         struct iwl_rxq *rxq = &trans_pcie->rxq;
 724         u32 r, i;
 725         u8 fill_rx = 0;
 726         u32 count = 8;
 727         int total_empty;
 728
 729         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 730          * buffer that the driver may process (last buffer filled by ucode). */
 731         r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
 732         i = rxq->read;
 733
 734         /* Rx interrupt, but nothing sent from uCode */
 735         if (i == r)
 736                 IWL_DEBUG_RX(trans, "HW = SW = %d\n", r);
 737
 738         /* calculate total frames need to be restock after handling RX */
 739         total_empty = r - rxq->write_actual;
 740         if (total_empty < 0)
 741                 total_empty += RX_QUEUE_SIZE;
 742
 743         if (total_empty > (RX_QUEUE_SIZE / 2))
 744                 fill_rx = 1;
 745
 746         while (i != r) {
 747                 struct iwl_rx_mem_buffer *rxb;
 748
 749                 rxb = rxq->queue[i];
 750                 rxq->queue[i] = NULL;
 751
 752                 IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n",
 753                              r, i, rxb);
 754                 iwl_pcie_rx_handle_rb(trans, rxb);
 755
 756                 i = (i + 1) & RX_QUEUE_MASK;
 757                 /* If there are a lot of unused frames,
 758                  * restock the Rx queue so ucode wont assert. */
 759                 if (fill_rx) {
 760                         count++;
 761                         if (count >= 8) {
 762                                 rxq->read = i;
 763                                 iwl_pcie_rx_replenish_now(trans);
 764                                 count = 0;
 765                         }
 766                 }
 767         }
 768
 769         /* Backtrack one entry */
 770         rxq->read = i;
 771         if (fill_rx)
 772                 iwl_pcie_rx_replenish_now(trans);
 773         else
 774                 iwl_pcie_rxq_restock(trans);
 775 }
 776
 777 /*
 778  * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
 779  */
 780 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
 781 {
 782         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 783
 784         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 785         if (trans->cfg->internal_wimax_coex &&
 786             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
 787                              APMS_CLK_VAL_MRB_FUNC_MODE) ||
 788              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
 789                             APMG_PS_CTRL_VAL_RESET_REQ))) {
 790                 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 791                 iwl_op_mode_wimax_active(trans->op_mode);
 792                 wake_up(&trans_pcie->wait_command_queue);
 793                 return;
 794         }
 795
 796         iwl_pcie_dump_csr(trans);
 797         iwl_dump_fh(trans, NULL);
 798
 799         set_bit(STATUS_FW_ERROR, &trans_pcie->status);
 800         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 801         wake_up(&trans_pcie->wait_command_queue);
 802
 803         local_bh_disable();
 804         iwl_op_mode_nic_error(trans->op_mode);
 805         local_bh_enable();
 806 }
 807
 808 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
 809 {
 810         struct iwl_trans *trans = dev_id;
 811         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 812         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 813         u32 inta = 0;
 814         u32 handled = 0;
 815         unsigned long flags;
 816         u32 i;
 817
 818         lock_map_acquire(&trans->sync_cmd_lockdep_map);
 819
 820         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 821
 822         /* Ack/clear/reset pending uCode interrupts.
 823          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 824          */
 825         /* There is a hardware bug in the interrupt mask function that some
 826          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 827          * they are disabled in the CSR_INT_MASK register. Furthermore the
 828          * ICT interrupt handling mechanism has another bug that might cause
 829          * these unmasked interrupts fail to be detected. We workaround the
 830          * hardware bugs here by ACKing all the possible interrupts so that
 831          * interrupt coalescing can still be achieved.
 832          */
 833         iwl_write32(trans, CSR_INT,
 834                     trans_pcie->inta | ~trans_pcie->inta_mask);
 835
 836         inta = trans_pcie->inta;
 837
 838         if (iwl_have_debug_level(IWL_DL_ISR))
 839                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
 840                               inta, iwl_read32(trans, CSR_INT_MASK));
 841
 842         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 843         trans_pcie->inta = 0;
 844
 845         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 846
 847         /* Now service all interrupt bits discovered above. */
 848         if (inta & CSR_INT_BIT_HW_ERR) {
 849                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 850
 851                 /* Tell the device to stop sending interrupts */
 852                 iwl_disable_interrupts(trans);
 853
 854                 isr_stats->hw++;
 855                 iwl_pcie_irq_handle_error(trans);
 856
 857                 handled |= CSR_INT_BIT_HW_ERR;
 858
 859                 goto out;
 860         }
 861
 862         if (iwl_have_debug_level(IWL_DL_ISR)) {
 863                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 864                 if (inta & CSR_INT_BIT_SCD) {
 865                         IWL_DEBUG_ISR(trans,
 866                                       "Scheduler finished to transmit the frame/frames.\n");
 867                         isr_stats->sch++;
 868                 }
 869
 870                 /* Alive notification via Rx interrupt will do the real work */
 871                 if (inta & CSR_INT_BIT_ALIVE) {
 872                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
 873                         isr_stats->alive++;
 874                 }
 875         }
 876
 877         /* Safely ignore these bits for debug checks below */
 878         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 879
 880         /* HW RF KILL switch toggled */
 881         if (inta & CSR_INT_BIT_RF_KILL) {
 882                 bool hw_rfkill;
 883
 884                 hw_rfkill = iwl_is_rfkill_set(trans);
 885                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
 886                          hw_rfkill ? "disable radio" : "enable radio");
 887
 888                 isr_stats->rfkill++;
 889
 890                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 891                 if (hw_rfkill) {
 892                         set_bit(STATUS_RFKILL, &trans_pcie->status);
 893                         if (test_and_clear_bit(STATUS_HCMD_ACTIVE,
 894                                                &trans_pcie->status))
 895                                 IWL_DEBUG_RF_KILL(trans,
 896                                                   "Rfkill while SYNC HCMD in flight\n");
 897                         wake_up(&trans_pcie->wait_command_queue);
 898                 } else {
 899                         clear_bit(STATUS_RFKILL, &trans_pcie->status);
 900                 }
 901
 902                 handled |= CSR_INT_BIT_RF_KILL;
 903         }
 904
 905         /* Chip got too hot and stopped itself */
 906         if (inta & CSR_INT_BIT_CT_KILL) {
 907                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
 908                 isr_stats->ctkill++;
 909                 handled |= CSR_INT_BIT_CT_KILL;
 910         }
 911
 912         /* Error detected by uCode */
 913         if (inta & CSR_INT_BIT_SW_ERR) {
 914                 IWL_ERR(trans, "Microcode SW error detected. "
 915                         " Restarting 0x%X.\n", inta);
 916                 isr_stats->sw++;
 917                 iwl_pcie_irq_handle_error(trans);
 918                 handled |= CSR_INT_BIT_SW_ERR;
 919         }
 920
 921         /* uCode wakes up after power-down sleep */
 922         if (inta & CSR_INT_BIT_WAKEUP) {
 923                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
 924                 iwl_pcie_rxq_inc_wr_ptr(trans, &trans_pcie->rxq);
 925                 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++)
 926                         iwl_pcie_txq_inc_wr_ptr(trans, &trans_pcie->txq[i]);
 927
 928                 isr_stats->wakeup++;
 929
 930                 handled |= CSR_INT_BIT_WAKEUP;
 931         }
 932
 933         /* All uCode command responses, including Tx command responses,
 934          * Rx "responses" (frame-received notification), and other
 935          * notifications from uCode come through here*/
 936         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
 937                     CSR_INT_BIT_RX_PERIODIC)) {
 938                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
 939                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
 940                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
 941                         iwl_write32(trans, CSR_FH_INT_STATUS,
 942                                         CSR_FH_INT_RX_MASK);
 943                 }
 944                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
 945                         handled |= CSR_INT_BIT_RX_PERIODIC;
 946                         iwl_write32(trans,
 947                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
 948                 }
 949                 /* Sending RX interrupt require many steps to be done in the
 950                  * the device:
 951                  * 1- write interrupt to current index in ICT table.
 952                  * 2- dma RX frame.
 953                  * 3- update RX shared data to indicate last write index.
 954                  * 4- send interrupt.
 955                  * This could lead to RX race, driver could receive RX interrupt
 956                  * but the shared data changes does not reflect this;
 957                  * periodic interrupt will detect any dangling Rx activity.
 958                  */
 959
 960                 /* Disable periodic interrupt; we use it as just a one-shot. */
 961                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
 962                             CSR_INT_PERIODIC_DIS);
 963
 964                 iwl_pcie_rx_handle(trans);
 965
 966                 /*
 967                  * Enable periodic interrupt in 8 msec only if we received
 968                  * real RX interrupt (instead of just periodic int), to catch
 969                  * any dangling Rx interrupt.  If it was just the periodic
 970                  * interrupt, there was no dangling Rx activity, and no need
 971                  * to extend the periodic interrupt; one-shot is enough.
 972                  */
 973                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
 974                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
 975                                    CSR_INT_PERIODIC_ENA);
 976
 977                 isr_stats->rx++;
 978         }
 979
 980         /* This "Tx" DMA channel is used only for loading uCode */
 981         if (inta & CSR_INT_BIT_FH_TX) {
 982                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
 983                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
 984                 isr_stats->tx++;
 985                 handled |= CSR_INT_BIT_FH_TX;
 986                 /* Wake up uCode load routine, now that load is complete */
 987                 trans_pcie->ucode_write_complete = true;
 988                 wake_up(&trans_pcie->ucode_write_waitq);
 989         }
 990
 991         if (inta & ~handled) {
 992                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
 993                 isr_stats->unhandled++;
 994         }
 995
 996         if (inta & ~(trans_pcie->inta_mask)) {
 997                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
 998                          inta & ~trans_pcie->inta_mask);
 999         }
1000
1001         /* Re-enable all interrupts */
1002         /* only Re-enable if disabled by irq */
1003         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status))
1004                 iwl_enable_interrupts(trans);
1005         /* Re-enable RF_KILL if it occurred */
1006         else if (handled & CSR_INT_BIT_RF_KILL)
1007                 iwl_enable_rfkill_int(trans);
1008
1009 out:
1010         lock_map_release(&trans->sync_cmd_lockdep_map);
1011         return IRQ_HANDLED;
1012 }
1013
1014 /******************************************************************************
1015  *
1016  * ICT functions
1017  *
1018  ******************************************************************************/
1019
1020 /* a device (PCI-E) page is 4096 bytes long */
1021 #define ICT_SHIFT       12
1022 #define ICT_SIZE        (1 << ICT_SHIFT)
1023 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
1024
1025 /* Free dram table */
1026 void iwl_pcie_free_ict(struct iwl_trans *trans)
1027 {
1028         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1029
1030         if (trans_pcie->ict_tbl) {
1031                 dma_free_coherent(trans->dev, ICT_SIZE,
1032                                   trans_pcie->ict_tbl,
1033                                   trans_pcie->ict_tbl_dma);
1034                 trans_pcie->ict_tbl = NULL;
1035                 trans_pcie->ict_tbl_dma = 0;
1036         }
1037 }
1038
1039 /*
1040  * allocate dram shared table, it is an aligned memory
1041  * block of ICT_SIZE.
1042  * also reset all data related to ICT table interrupt.
1043  */
1044 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
1045 {
1046         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1047
1048         trans_pcie->ict_tbl =
1049                 dma_alloc_coherent(trans->dev, ICT_SIZE,
1050                                    &trans_pcie->ict_tbl_dma,
1051                                    GFP_KERNEL);
1052         if (!trans_pcie->ict_tbl)
1053                 return -ENOMEM;
1054
1055         /* just an API sanity check ... it is guaranteed to be aligned */
1056         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1057                 iwl_pcie_free_ict(trans);
1058                 return -EINVAL;
1059         }
1060
1061         IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
1062                       (unsigned long long)trans_pcie->ict_tbl_dma);
1063
1064         IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
1065
1066         /* reset table and index to all 0 */
1067         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1068         trans_pcie->ict_index = 0;
1069
1070         /* add periodic RX interrupt */
1071         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1072         return 0;
1073 }
1074
1075 /* Device is going up inform it about using ICT interrupt table,
1076  * also we need to tell the driver to start using ICT interrupt.
1077  */
1078 void iwl_pcie_reset_ict(struct iwl_trans *trans)
1079 {
1080         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1081         u32 val;
1082         unsigned long flags;
1083
1084         if (!trans_pcie->ict_tbl)
1085                 return;
1086
1087         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1088         iwl_disable_interrupts(trans);
1089
1090         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1091
1092         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1093
1094         val |= CSR_DRAM_INT_TBL_ENABLE;
1095         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1096
1097         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1098
1099         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1100         trans_pcie->use_ict = true;
1101         trans_pcie->ict_index = 0;
1102         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1103         iwl_enable_interrupts(trans);
1104         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1105 }
1106
1107 /* Device is going down disable ict interrupt usage */
1108 void iwl_pcie_disable_ict(struct iwl_trans *trans)
1109 {
1110         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1111         unsigned long flags;
1112
1113         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1114         trans_pcie->use_ict = false;
1115         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1116 }
1117
1118 /* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
1119 static irqreturn_t iwl_pcie_isr(int irq, void *data)
1120 {
1121         struct iwl_trans *trans = data;
1122         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1123         u32 inta, inta_mask;
1124         irqreturn_t ret = IRQ_NONE;
1125
1126         lockdep_assert_held(&trans_pcie->irq_lock);
1127
1128         trace_iwlwifi_dev_irq(trans->dev);
1129
1130         /* Disable (but don't clear!) interrupts here to avoid
1131          *    back-to-back ISRs and sporadic interrupts from our NIC.
1132          * If we have something to service, the irq thread will re-enable ints.
1133          * If we *don't* have something, we'll re-enable before leaving here. */
1134         inta_mask = iwl_read32(trans, CSR_INT_MASK);
1135         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1136
1137         /* Discover which interrupts are active/pending */
1138         inta = iwl_read32(trans, CSR_INT);
1139
1140         if (inta & (~inta_mask)) {
1141                 IWL_DEBUG_ISR(trans,
1142                               "We got a masked interrupt (0x%08x)...Ack and ignore\n",
1143                               inta & (~inta_mask));
1144                 iwl_write32(trans, CSR_INT, inta & (~inta_mask));
1145                 inta &= inta_mask;
1146         }
1147
1148         /* Ignore interrupt if there's nothing in NIC to service.
1149          * This may be due to IRQ shared with another device,
1150          * or due to sporadic interrupts thrown from our NIC. */
1151         if (!inta) {
1152                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1153                 goto none;
1154         }
1155
1156         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1157                 /* Hardware disappeared. It might have already raised
1158                  * an interrupt */
1159                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1160                 return IRQ_HANDLED;
1161         }
1162
1163         if (iwl_have_debug_level(IWL_DL_ISR))
1164                 IWL_DEBUG_ISR(trans,
1165                               "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1166                               inta, inta_mask,
1167                               iwl_read32(trans, CSR_FH_INT_STATUS));
1168
1169         trans_pcie->inta |= inta;
1170         /* the thread will service interrupts and re-enable them */
1171         if (likely(inta))
1172                 return IRQ_WAKE_THREAD;
1173
1174         ret = IRQ_HANDLED;
1175
1176 none:
1177         /* re-enable interrupts here since we don't have anything to service. */
1178         /* only Re-enable if disabled by irq  and no schedules tasklet. */
1179         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1180             !trans_pcie->inta)
1181                 iwl_enable_interrupts(trans);
1182
1183         return ret;
1184 }
1185
1186 /* interrupt handler using ict table, with this interrupt driver will
1187  * stop using INTA register to get device's interrupt, reading this register
1188  * is expensive, device will write interrupts in ICT dram table, increment
1189  * index then will fire interrupt to driver, driver will OR all ICT table
1190  * entries from current index up to table entry with 0 value. the result is
1191  * the interrupt we need to service, driver will set the entries back to 0 and
1192  * set index.
1193  */
1194 irqreturn_t iwl_pcie_isr_ict(int irq, void *data)
1195 {
1196         struct iwl_trans *trans = data;
1197         struct iwl_trans_pcie *trans_pcie;
1198         u32 inta;
1199         u32 val = 0;
1200         u32 read;
1201         unsigned long flags;
1202         irqreturn_t ret = IRQ_NONE;
1203
1204         if (!trans)
1205                 return IRQ_NONE;
1206
1207         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1208
1209         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1210
1211         /* dram interrupt table not set yet,
1212          * use legacy interrupt.
1213          */
1214         if (unlikely(!trans_pcie->use_ict)) {
1215                 ret = iwl_pcie_isr(irq, data);
1216                 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1217                 return ret;
1218         }
1219
1220         trace_iwlwifi_dev_irq(trans->dev);
1221
1222         /* Disable (but don't clear!) interrupts here to avoid
1223          * back-to-back ISRs and sporadic interrupts from our NIC.
1224          * If we have something to service, the tasklet will re-enable ints.
1225          * If we *don't* have something, we'll re-enable before leaving here.
1226          */
1227         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1228
1229         /* Ignore interrupt if there's nothing in NIC to service.
1230          * This may be due to IRQ shared with another device,
1231          * or due to sporadic interrupts thrown from our NIC. */
1232         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1233         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1234         if (!read) {
1235                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1236                 goto none;
1237         }
1238
1239         /*
1240          * Collect all entries up to the first 0, starting from ict_index;
1241          * note we already read at ict_index.
1242          */
1243         do {
1244                 val |= read;
1245                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1246                                 trans_pcie->ict_index, read);
1247                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1248                 trans_pcie->ict_index =
1249                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1250
1251                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1252                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1253                                            read);
1254         } while (read);
1255
1256         /* We should not get this value, just ignore it. */
1257         if (val == 0xffffffff)
1258                 val = 0;
1259
1260         /*
1261          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1262          * (bit 15 before shifting it to 31) to clear when using interrupt
1263          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1264          * so we use them to decide on the real state of the Rx bit.
1265          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1266          */
1267         if (val & 0xC0000)
1268                 val |= 0x8000;
1269
1270         inta = (0xff & val) | ((0xff00 & val) << 16);
1271         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled(sw) 0x%08x ict 0x%08x\n",
1272                       inta, trans_pcie->inta_mask, val);
1273         if (iwl_have_debug_level(IWL_DL_ISR))
1274                 IWL_DEBUG_ISR(trans, "enabled(hw) 0x%08x\n",
1275                               iwl_read32(trans, CSR_INT_MASK));
1276
1277         inta &= trans_pcie->inta_mask;
1278         trans_pcie->inta |= inta;
1279
1280         /* iwl_pcie_tasklet() will service interrupts and re-enable them */
1281         if (likely(inta)) {
1282                 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1283                 return IRQ_WAKE_THREAD;
1284         }
1285
1286         ret = IRQ_HANDLED;
1287
1288  none:
1289         /* re-enable interrupts here since we don't have anything to service.
1290          * only Re-enable if disabled by irq.
1291          */
1292         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1293             !trans_pcie->inta)
1294                 iwl_enable_interrupts(trans);
1295
1296         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1297         return ret;
1298 }