drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 #include "iwl-prph.h"
  34 #include "iwl-io.h"
  35 #include "iwl-trans-pcie-int.h"
  36 #include "iwl-op-mode.h"
  37
  38 #ifdef CONFIG_IWLWIFI_IDI
  39 #include "iwl-amfh.h"
  40 #endif
  41
  42 /******************************************************************************
  43  *
  44  * RX path functions
  45  *
  46  ******************************************************************************/
  47
  48 /*
  49  * Rx theory of operation
  50  *
  51  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  52  * each of which point to Receive Buffers to be filled by the NIC.  These get
  53  * used not only for Rx frames, but for any command response or notification
  54  * from the NIC.  The driver and NIC manage the Rx buffers by means
  55  * of indexes into the circular buffer.
  56  *
  57  * Rx Queue Indexes
  58  * The host/firmware share two index registers for managing the Rx buffers.
  59  *
  60  * The READ index maps to the first position that the firmware may be writing
  61  * to -- the driver can read up to (but not including) this position and get
  62  * good data.
  63  * The READ index is managed by the firmware once the card is enabled.
  64  *
  65  * The WRITE index maps to the last position the driver has read from -- the
  66  * position preceding WRITE is the last slot the firmware can place a packet.
  67  *
  68  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  69  * WRITE = READ.
  70  *
  71  * During initialization, the host sets up the READ queue position to the first
  72  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  73  *
  74  * When the firmware places a packet in a buffer, it will advance the READ index
  75  * and fire the RX interrupt.  The driver can then query the READ index and
  76  * process as many packets as possible, moving the WRITE index forward as it
  77  * resets the Rx queue buffers with new memory.
  78  *
  79  * The management in the driver is as follows:
  80  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  81  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  82  *   to replenish the iwl->rxq->rx_free.
  83  * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  84  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  85  *   'processed' and 'read' driver indexes as well)
  86  * + A received packet is processed and handed to the kernel network stack,
  87  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  88  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  89  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  90  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
  91  *   were enough free buffers and RX_STALLED is set it is cleared.
  92  *
  93  *
  94  * Driver sequence:
  95  *
  96  * iwl_rx_queue_alloc()   Allocates rx_free
  97  * iwl_rx_replenish()     Replenishes rx_free list from rx_used, and calls
  98  *                            iwl_rx_queue_restock
  99  * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
 100  *                            queue, updates firmware pointers, and updates
 101  *                            the WRITE index.  If insufficient rx_free buffers
 102  *                            are available, schedules iwl_rx_replenish
 103  *
 104  * -- enable interrupts --
 105  * ISR - iwl_rx()         Detach iwl_rx_mem_buffers from pool up to the
 106  *                            READ INDEX, detaching the SKB from the pool.
 107  *                            Moves the packet buffer from queue to rx_used.
 108  *                            Calls iwl_rx_queue_restock to refill any empty
 109  *                            slots.
 110  * ...
 111  *
 112  */
 113
 114 /**
 115  * iwl_rx_queue_space - Return number of free slots available in queue.
 116  */
 117 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
 118 {
 119         int s = q->read - q->write;
 120         if (s <= 0)
 121                 s += RX_QUEUE_SIZE;
 122         /* keep some buffer to not confuse full and empty queue */
 123         s -= 2;
 124         if (s < 0)
 125                 s = 0;
 126         return s;
 127 }
 128
 129 /**
 130  * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
 131  */
 132 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
 133                         struct iwl_rx_queue *q)
 134 {
 135         unsigned long flags;
 136         u32 reg;
 137
 138         spin_lock_irqsave(&q->lock, flags);
 139
 140         if (q->need_update == 0)
 141                 goto exit_unlock;
 142
 143         if (cfg(trans)->base_params->shadow_reg_enable) {
 144                 /* shadow register enabled */
 145                 /* Device expects a multiple of 8 */
 146                 q->write_actual = (q->write & ~0x7);
 147                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
 148         } else {
 149                 /* If power-saving is in use, make sure device is awake */
 150                 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
 151                         reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 152
 153                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 154                                 IWL_DEBUG_INFO(trans,
 155                                         "Rx queue requesting wakeup,"
 156                                         " GP1 = 0x%x\n", reg);
 157                                 iwl_set_bit(trans, CSR_GP_CNTRL,
 158                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 159                                 goto exit_unlock;
 160                         }
 161
 162                         q->write_actual = (q->write & ~0x7);
 163                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 164                                         q->write_actual);
 165
 166                 /* Else device is assumed to be awake */
 167                 } else {
 168                         /* Device expects a multiple of 8 */
 169                         q->write_actual = (q->write & ~0x7);
 170                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 171                                 q->write_actual);
 172                 }
 173         }
 174         q->need_update = 0;
 175
 176  exit_unlock:
 177         spin_unlock_irqrestore(&q->lock, flags);
 178 }
 179
 180 /**
 181  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 182  */
 183 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 184 {
 185         return cpu_to_le32((u32)(dma_addr >> 8));
 186 }
 187
 188 /**
 189  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 190  *
 191  * If there are slots in the RX queue that need to be restocked,
 192  * and we have free pre-allocated buffers, fill the ranks as much
 193  * as we can, pulling from rx_free.
 194  *
 195  * This moves the 'write' index forward to catch up with 'processed', and
 196  * also updates the memory address in the firmware to reference the new
 197  * target buffer.
 198  */
 199 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
 200 {
 201         struct iwl_trans_pcie *trans_pcie =
 202                 IWL_TRANS_GET_PCIE_TRANS(trans);
 203
 204         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 205         struct list_head *element;
 206         struct iwl_rx_mem_buffer *rxb;
 207         unsigned long flags;
 208
 209         spin_lock_irqsave(&rxq->lock, flags);
 210         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 211                 /* The overwritten rxb must be a used one */
 212                 rxb = rxq->queue[rxq->write];
 213                 BUG_ON(rxb && rxb->page);
 214
 215                 /* Get next free Rx buffer, remove from free list */
 216                 element = rxq->rx_free.next;
 217                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 218                 list_del(element);
 219
 220                 /* Point to Rx buffer via next RBD in circular buffer */
 221                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
 222                 rxq->queue[rxq->write] = rxb;
 223                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 224                 rxq->free_count--;
 225         }
 226         spin_unlock_irqrestore(&rxq->lock, flags);
 227         /* If the pre-allocated buffer pool is dropping low, schedule to
 228          * refill it */
 229         if (rxq->free_count <= RX_LOW_WATERMARK)
 230                 schedule_work(&trans_pcie->rx_replenish);
 231
 232
 233         /* If we've added more space for the firmware to place data, tell it.
 234          * Increment device's write pointer in multiples of 8. */
 235         if (rxq->write_actual != (rxq->write & ~0x7)) {
 236                 spin_lock_irqsave(&rxq->lock, flags);
 237                 rxq->need_update = 1;
 238                 spin_unlock_irqrestore(&rxq->lock, flags);
 239                 iwl_rx_queue_update_write_ptr(trans, rxq);
 240         }
 241 }
 242
 243 /**
 244  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 245  *
 246  * When moving to rx_free an SKB is allocated for the slot.
 247  *
 248  * Also restock the Rx queue via iwl_rx_queue_restock.
 249  * This is called as a scheduled work item (except for during initialization)
 250  */
 251 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
 252 {
 253         struct iwl_trans_pcie *trans_pcie =
 254                 IWL_TRANS_GET_PCIE_TRANS(trans);
 255
 256         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 257         struct list_head *element;
 258         struct iwl_rx_mem_buffer *rxb;
 259         struct page *page;
 260         unsigned long flags;
 261         gfp_t gfp_mask = priority;
 262
 263         while (1) {
 264                 spin_lock_irqsave(&rxq->lock, flags);
 265                 if (list_empty(&rxq->rx_used)) {
 266                         spin_unlock_irqrestore(&rxq->lock, flags);
 267                         return;
 268                 }
 269                 spin_unlock_irqrestore(&rxq->lock, flags);
 270
 271                 if (rxq->free_count > RX_LOW_WATERMARK)
 272                         gfp_mask |= __GFP_NOWARN;
 273
 274                 if (hw_params(trans).rx_page_order > 0)
 275                         gfp_mask |= __GFP_COMP;
 276
 277                 /* Alloc a new receive buffer */
 278                 page = alloc_pages(gfp_mask,
 279                                   hw_params(trans).rx_page_order);
 280                 if (!page) {
 281                         if (net_ratelimit())
 282                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 283                                            "order: %d\n",
 284                                            hw_params(trans).rx_page_order);
 285
 286                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 287                             net_ratelimit())
 288                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 289                                          "Only %u free buffers remaining.\n",
 290                                          priority == GFP_ATOMIC ?
 291                                          "GFP_ATOMIC" : "GFP_KERNEL",
 292                                          rxq->free_count);
 293                         /* We don't reschedule replenish work here -- we will
 294                          * call the restock method and if it still needs
 295                          * more buffers it will schedule replenish */
 296                         return;
 297                 }
 298
 299                 spin_lock_irqsave(&rxq->lock, flags);
 300
 301                 if (list_empty(&rxq->rx_used)) {
 302                         spin_unlock_irqrestore(&rxq->lock, flags);
 303                         __free_pages(page, hw_params(trans).rx_page_order);
 304                         return;
 305                 }
 306                 element = rxq->rx_used.next;
 307                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 308                 list_del(element);
 309
 310                 spin_unlock_irqrestore(&rxq->lock, flags);
 311
 312                 BUG_ON(rxb->page);
 313                 rxb->page = page;
 314                 /* Get physical address of the RB */
 315                 rxb->page_dma = dma_map_page(trans->dev, page, 0,
 316                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 317                                 DMA_FROM_DEVICE);
 318                 /* dma address must be no more than 36 bits */
 319                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 320                 /* and also 256 byte aligned! */
 321                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 322
 323                 spin_lock_irqsave(&rxq->lock, flags);
 324
 325                 list_add_tail(&rxb->list, &rxq->rx_free);
 326                 rxq->free_count++;
 327
 328                 spin_unlock_irqrestore(&rxq->lock, flags);
 329         }
 330 }
 331
 332 void iwlagn_rx_replenish(struct iwl_trans *trans)
 333 {
 334         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 335         unsigned long flags;
 336
 337         iwlagn_rx_allocate(trans, GFP_KERNEL);
 338
 339         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 340         iwlagn_rx_queue_restock(trans);
 341         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 342 }
 343
 344 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
 345 {
 346         iwlagn_rx_allocate(trans, GFP_ATOMIC);
 347
 348         iwlagn_rx_queue_restock(trans);
 349 }
 350
 351 void iwl_bg_rx_replenish(struct work_struct *data)
 352 {
 353         struct iwl_trans_pcie *trans_pcie =
 354             container_of(data, struct iwl_trans_pcie, rx_replenish);
 355
 356         iwlagn_rx_replenish(trans_pcie->trans);
 357 }
 358
 359 static void iwl_rx_handle_rxbuf(struct iwl_trans *trans,
 360                                 struct iwl_rx_mem_buffer *rxb)
 361 {
 362         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 363         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 364         struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
 365         struct iwl_device_cmd *cmd;
 366         unsigned long flags;
 367         int len, err;
 368         u16 sequence;
 369         struct iwl_rx_cmd_buffer rxcb;
 370         struct iwl_rx_packet *pkt;
 371         bool reclaim;
 372         int index, cmd_index;
 373
 374         if (WARN_ON(!rxb))
 375                 return;
 376
 377         dma_unmap_page(trans->dev, rxb->page_dma,
 378                        PAGE_SIZE << hw_params(trans).rx_page_order,
 379                        DMA_FROM_DEVICE);
 380
 381         rxcb._page = rxb->page;
 382         pkt = rxb_addr(&rxcb);
 383
 384         IWL_DEBUG_RX(trans, "%s, 0x%02x\n",
 385                      get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 386
 387
 388         len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 389         len += sizeof(u32); /* account for status word */
 390         trace_iwlwifi_dev_rx(trans->dev, pkt, len);
 391
 392         /* Reclaim a command buffer only if this packet is a response
 393          *   to a (driver-originated) command.
 394          * If the packet (e.g. Rx frame) originated from uCode,
 395          *   there is no command buffer to reclaim.
 396          * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 397          *   but apparently a few don't get set; catch them here. */
 398         reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 399                   (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 400                   (pkt->hdr.cmd != REPLY_RX) &&
 401                   (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 402                   (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 403                   (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 404                   (pkt->hdr.cmd != REPLY_TX);
 405
 406         sequence = le16_to_cpu(pkt->hdr.sequence);
 407         index = SEQ_TO_INDEX(sequence);
 408         cmd_index = get_cmd_index(&txq->q, index);
 409
 410         if (reclaim)
 411                 cmd = txq->cmd[cmd_index];
 412         else
 413                 cmd = NULL;
 414
 415         /* warn if this is cmd response / notification and the uCode
 416          * didn't set the SEQ_RX_FRAME for a frame that is
 417          * uCode-originated
 418          * If you saw this code after the second half of 2012, then
 419          * please remove it
 420          */
 421         WARN(pkt->hdr.cmd != REPLY_TX && reclaim == false &&
 422              (!(pkt->hdr.sequence & SEQ_RX_FRAME)),
 423              "reclaim is false, SEQ_RX_FRAME unset: %s\n",
 424              get_cmd_string(pkt->hdr.cmd));
 425
 426         err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
 427
 428         /*
 429          * XXX: After here, we should always check rxcb._page
 430          * against NULL before touching it or its virtual
 431          * memory (pkt). Because some rx_handler might have
 432          * already taken or freed the pages.
 433          */
 434
 435         if (reclaim) {
 436                 /* Invoke any callbacks, transfer the buffer to caller,
 437                  * and fire off the (possibly) blocking
 438                  * iwl_trans_send_cmd()
 439                  * as we reclaim the driver command queue */
 440                 if (rxcb._page)
 441                         iwl_tx_cmd_complete(trans, &rxcb, err);
 442                 else
 443                         IWL_WARN(trans, "Claim null rxb?\n");
 444         }
 445
 446         /* page was stolen from us */
 447         if (rxcb._page == NULL)
 448                 rxb->page = NULL;
 449
 450         /* Reuse the page if possible. For notification packets and
 451          * SKBs that fail to Rx correctly, add them back into the
 452          * rx_free list for reuse later. */
 453         spin_lock_irqsave(&rxq->lock, flags);
 454         if (rxb->page != NULL) {
 455                 rxb->page_dma =
 456                         dma_map_page(trans->dev, rxb->page, 0,
 457                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 458                                 DMA_FROM_DEVICE);
 459                 list_add_tail(&rxb->list, &rxq->rx_free);
 460                 rxq->free_count++;
 461         } else
 462                 list_add_tail(&rxb->list, &rxq->rx_used);
 463         spin_unlock_irqrestore(&rxq->lock, flags);
 464 }
 465
 466 /**
 467  * iwl_rx_handle - Main entry function for receiving responses from uCode
 468  *
 469  * Uses the priv->rx_handlers callback function array to invoke
 470  * the appropriate handlers, including command responses,
 471  * frame-received notifications, and other notifications.
 472  */
 473 static void iwl_rx_handle(struct iwl_trans *trans)
 474 {
 475         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 476         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 477         u32 r, i;
 478         u8 fill_rx = 0;
 479         u32 count = 8;
 480         int total_empty;
 481
 482         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 483          * buffer that the driver may process (last buffer filled by ucode). */
 484         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 485         i = rxq->read;
 486
 487         /* Rx interrupt, but nothing sent from uCode */
 488         if (i == r)
 489                 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
 490
 491         /* calculate total frames need to be restock after handling RX */
 492         total_empty = r - rxq->write_actual;
 493         if (total_empty < 0)
 494                 total_empty += RX_QUEUE_SIZE;
 495
 496         if (total_empty > (RX_QUEUE_SIZE / 2))
 497                 fill_rx = 1;
 498
 499         while (i != r) {
 500                 struct iwl_rx_mem_buffer *rxb;
 501
 502                 rxb = rxq->queue[i];
 503                 rxq->queue[i] = NULL;
 504
 505                 IWL_DEBUG_RX(trans, "rxbuf: r = %d, i = %d (%p)\n", rxb);
 506
 507                 iwl_rx_handle_rxbuf(trans, rxb);
 508
 509                 i = (i + 1) & RX_QUEUE_MASK;
 510                 /* If there are a lot of unused frames,
 511                  * restock the Rx queue so ucode wont assert. */
 512                 if (fill_rx) {
 513                         count++;
 514                         if (count >= 8) {
 515                                 rxq->read = i;
 516                                 iwlagn_rx_replenish_now(trans);
 517                                 count = 0;
 518                         }
 519                 }
 520         }
 521
 522         /* Backtrack one entry */
 523         rxq->read = i;
 524         if (fill_rx)
 525                 iwlagn_rx_replenish_now(trans);
 526         else
 527                 iwlagn_rx_queue_restock(trans);
 528 }
 529
 530 static const char * const desc_lookup_text[] = {
 531         "OK",
 532         "FAIL",
 533         "BAD_PARAM",
 534         "BAD_CHECKSUM",
 535         "NMI_INTERRUPT_WDG",
 536         "SYSASSERT",
 537         "FATAL_ERROR",
 538         "BAD_COMMAND",
 539         "HW_ERROR_TUNE_LOCK",
 540         "HW_ERROR_TEMPERATURE",
 541         "ILLEGAL_CHAN_FREQ",
 542         "VCC_NOT_STABLE",
 543         "FH_ERROR",
 544         "NMI_INTERRUPT_HOST",
 545         "NMI_INTERRUPT_ACTION_PT",
 546         "NMI_INTERRUPT_UNKNOWN",
 547         "UCODE_VERSION_MISMATCH",
 548         "HW_ERROR_ABS_LOCK",
 549         "HW_ERROR_CAL_LOCK_FAIL",
 550         "NMI_INTERRUPT_INST_ACTION_PT",
 551         "NMI_INTERRUPT_DATA_ACTION_PT",
 552         "NMI_TRM_HW_ER",
 553         "NMI_INTERRUPT_TRM",
 554         "NMI_INTERRUPT_BREAK_POINT",
 555         "DEBUG_0",
 556         "DEBUG_1",
 557         "DEBUG_2",
 558         "DEBUG_3",
 559 };
 560
 561 static struct { char *name; u8 num; } advanced_lookup[] = {
 562         { "NMI_INTERRUPT_WDG", 0x34 },
 563         { "SYSASSERT", 0x35 },
 564         { "UCODE_VERSION_MISMATCH", 0x37 },
 565         { "BAD_COMMAND", 0x38 },
 566         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
 567         { "FATAL_ERROR", 0x3D },
 568         { "NMI_TRM_HW_ERR", 0x46 },
 569         { "NMI_INTERRUPT_TRM", 0x4C },
 570         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
 571         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
 572         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
 573         { "NMI_INTERRUPT_HOST", 0x66 },
 574         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
 575         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
 576         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
 577         { "ADVANCED_SYSASSERT", 0 },
 578 };
 579
 580 static const char *desc_lookup(u32 num)
 581 {
 582         int i;
 583         int max = ARRAY_SIZE(desc_lookup_text);
 584
 585         if (num < max)
 586                 return desc_lookup_text[num];
 587
 588         max = ARRAY_SIZE(advanced_lookup) - 1;
 589         for (i = 0; i < max; i++) {
 590                 if (advanced_lookup[i].num == num)
 591                         break;
 592         }
 593         return advanced_lookup[i].name;
 594 }
 595
 596 #define ERROR_START_OFFSET  (1 * sizeof(u32))
 597 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
 598
 599 static void iwl_dump_nic_error_log(struct iwl_trans *trans)
 600 {
 601         u32 base;
 602         struct iwl_error_event_table table;
 603         struct iwl_trans_pcie *trans_pcie =
 604                 IWL_TRANS_GET_PCIE_TRANS(trans);
 605
 606         base = trans->shrd->device_pointers.error_event_table;
 607         if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
 608                 if (!base)
 609                         base = trans->shrd->fw->init_errlog_ptr;
 610         } else {
 611                 if (!base)
 612                         base = trans->shrd->fw->inst_errlog_ptr;
 613         }
 614
 615         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 616                 IWL_ERR(trans,
 617                         "Not valid error log pointer 0x%08X for %s uCode\n",
 618                         base,
 619                         (trans->shrd->ucode_type == IWL_UCODE_INIT)
 620                                         ? "Init" : "RT");
 621                 return;
 622         }
 623
 624         iwl_read_targ_mem_words(trans, base, &table, sizeof(table));
 625
 626         if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
 627                 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
 628                 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
 629                         trans->shrd->status, table.valid);
 630         }
 631
 632         trans_pcie->isr_stats.err_code = table.error_id;
 633
 634         trace_iwlwifi_dev_ucode_error(trans->dev, table.error_id, table.tsf_low,
 635                                       table.data1, table.data2, table.line,
 636                                       table.blink1, table.blink2, table.ilink1,
 637                                       table.ilink2, table.bcon_time, table.gp1,
 638                                       table.gp2, table.gp3, table.ucode_ver,
 639                                       table.hw_ver, table.brd_ver);
 640         IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id,
 641                 desc_lookup(table.error_id));
 642         IWL_ERR(trans, "0x%08X | uPc\n", table.pc);
 643         IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1);
 644         IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2);
 645         IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1);
 646         IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2);
 647         IWL_ERR(trans, "0x%08X | data1\n", table.data1);
 648         IWL_ERR(trans, "0x%08X | data2\n", table.data2);
 649         IWL_ERR(trans, "0x%08X | line\n", table.line);
 650         IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time);
 651         IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low);
 652         IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi);
 653         IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1);
 654         IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2);
 655         IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3);
 656         IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver);
 657         IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver);
 658         IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver);
 659         IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd);
 660
 661         IWL_ERR(trans, "0x%08X | isr0\n", table.isr0);
 662         IWL_ERR(trans, "0x%08X | isr1\n", table.isr1);
 663         IWL_ERR(trans, "0x%08X | isr2\n", table.isr2);
 664         IWL_ERR(trans, "0x%08X | isr3\n", table.isr3);
 665         IWL_ERR(trans, "0x%08X | isr4\n", table.isr4);
 666         IWL_ERR(trans, "0x%08X | isr_pref\n", table.isr_pref);
 667         IWL_ERR(trans, "0x%08X | wait_event\n", table.wait_event);
 668         IWL_ERR(trans, "0x%08X | l2p_control\n", table.l2p_control);
 669         IWL_ERR(trans, "0x%08X | l2p_duration\n", table.l2p_duration);
 670         IWL_ERR(trans, "0x%08X | l2p_mhvalid\n", table.l2p_mhvalid);
 671         IWL_ERR(trans, "0x%08X | l2p_addr_match\n", table.l2p_addr_match);
 672         IWL_ERR(trans, "0x%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel);
 673         IWL_ERR(trans, "0x%08X | timestamp\n", table.u_timestamp);
 674         IWL_ERR(trans, "0x%08X | flow_handler\n", table.flow_handler);
 675 }
 676
 677 /**
 678  * iwl_irq_handle_error - called for HW or SW error interrupt from card
 679  */
 680 static void iwl_irq_handle_error(struct iwl_trans *trans)
 681 {
 682         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 683         if (cfg(trans)->internal_wimax_coex &&
 684             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
 685                         APMS_CLK_VAL_MRB_FUNC_MODE) ||
 686              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
 687                         APMG_PS_CTRL_VAL_RESET_REQ))) {
 688                 /*
 689                  * Keep the restart process from trying to send host
 690                  * commands by clearing the ready bit.
 691                  */
 692                 clear_bit(STATUS_READY, &trans->shrd->status);
 693                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
 694                 wake_up(&trans->shrd->wait_command_queue);
 695                 IWL_ERR(trans, "RF is used by WiMAX\n");
 696                 return;
 697         }
 698
 699         IWL_ERR(trans, "Loaded firmware version: %s\n",
 700                 trans->shrd->fw->fw_version);
 701
 702         iwl_dump_nic_error_log(trans);
 703         iwl_dump_csr(trans);
 704         iwl_dump_fh(trans, NULL, false);
 705         iwl_dump_nic_event_log(trans, false, NULL, false);
 706
 707         iwl_op_mode_nic_error(trans->op_mode);
 708 }
 709
 710 #define EVENT_START_OFFSET  (4 * sizeof(u32))
 711
 712 /**
 713  * iwl_print_event_log - Dump error event log to syslog
 714  *
 715  */
 716 static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
 717                                u32 num_events, u32 mode,
 718                                int pos, char **buf, size_t bufsz)
 719 {
 720         u32 i;
 721         u32 base;       /* SRAM byte address of event log header */
 722         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
 723         u32 ptr;        /* SRAM byte address of log data */
 724         u32 ev, time, data; /* event log data */
 725         unsigned long reg_flags;
 726
 727         if (num_events == 0)
 728                 return pos;
 729
 730         base = trans->shrd->device_pointers.log_event_table;
 731         if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
 732                 if (!base)
 733                         base = trans->shrd->fw->init_evtlog_ptr;
 734         } else {
 735                 if (!base)
 736                         base = trans->shrd->fw->inst_evtlog_ptr;
 737         }
 738
 739         if (mode == 0)
 740                 event_size = 2 * sizeof(u32);
 741         else
 742                 event_size = 3 * sizeof(u32);
 743
 744         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
 745
 746         /* Make sure device is powered up for SRAM reads */
 747         spin_lock_irqsave(&trans->reg_lock, reg_flags);
 748         if (unlikely(!iwl_grab_nic_access(trans)))
 749                 goto out_unlock;
 750
 751         /* Set starting address; reads will auto-increment */
 752         iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr);
 753
 754         /* "time" is actually "data" for mode 0 (no timestamp).
 755         * place event id # at far right for easier visual parsing. */
 756         for (i = 0; i < num_events; i++) {
 757                 ev = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
 758                 time = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
 759                 if (mode == 0) {
 760                         /* data, ev */
 761                         if (bufsz) {
 762                                 pos += scnprintf(*buf + pos, bufsz - pos,
 763                                                 "EVT_LOG:0x%08x:%04u\n",
 764                                                 time, ev);
 765                         } else {
 766                                 trace_iwlwifi_dev_ucode_event(trans->dev, 0,
 767                                         time, ev);
 768                                 IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n",
 769                                         time, ev);
 770                         }
 771                 } else {
 772                         data = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
 773                         if (bufsz) {
 774                                 pos += scnprintf(*buf + pos, bufsz - pos,
 775                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
 776                                                  time, data, ev);
 777                         } else {
 778                                 IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n",
 779                                         time, data, ev);
 780                                 trace_iwlwifi_dev_ucode_event(trans->dev, time,
 781                                         data, ev);
 782                         }
 783                 }
 784         }
 785
 786         /* Allow device to power down */
 787         iwl_release_nic_access(trans);
 788 out_unlock:
 789         spin_unlock_irqrestore(&trans->reg_lock, reg_flags);
 790         return pos;
 791 }
 792
 793 /**
 794  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
 795  */
 796 static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity,
 797                                     u32 num_wraps, u32 next_entry,
 798                                     u32 size, u32 mode,
 799                                     int pos, char **buf, size_t bufsz)
 800 {
 801         /*
 802          * display the newest DEFAULT_LOG_ENTRIES entries
 803          * i.e the entries just before the next ont that uCode would fill.
 804          */
 805         if (num_wraps) {
 806                 if (next_entry < size) {
 807                         pos = iwl_print_event_log(trans,
 808                                                 capacity - (size - next_entry),
 809                                                 size - next_entry, mode,
 810                                                 pos, buf, bufsz);
 811                         pos = iwl_print_event_log(trans, 0,
 812                                                   next_entry, mode,
 813                                                   pos, buf, bufsz);
 814                 } else
 815                         pos = iwl_print_event_log(trans, next_entry - size,
 816                                                   size, mode, pos, buf, bufsz);
 817         } else {
 818                 if (next_entry < size) {
 819                         pos = iwl_print_event_log(trans, 0, next_entry,
 820                                                   mode, pos, buf, bufsz);
 821                 } else {
 822                         pos = iwl_print_event_log(trans, next_entry - size,
 823                                                   size, mode, pos, buf, bufsz);
 824                 }
 825         }
 826         return pos;
 827 }
 828
 829 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
 830
 831 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
 832                             char **buf, bool display)
 833 {
 834         u32 base;       /* SRAM byte address of event log header */
 835         u32 capacity;   /* event log capacity in # entries */
 836         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 837         u32 num_wraps;  /* # times uCode wrapped to top of log */
 838         u32 next_entry; /* index of next entry to be written by uCode */
 839         u32 size;       /* # entries that we'll print */
 840         u32 logsize;
 841         int pos = 0;
 842         size_t bufsz = 0;
 843
 844         base = trans->shrd->device_pointers.log_event_table;
 845         if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
 846                 logsize = trans->shrd->fw->init_evtlog_size;
 847                 if (!base)
 848                         base = trans->shrd->fw->init_evtlog_ptr;
 849         } else {
 850                 logsize = trans->shrd->fw->inst_evtlog_size;
 851                 if (!base)
 852                         base = trans->shrd->fw->inst_evtlog_ptr;
 853         }
 854
 855         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 856                 IWL_ERR(trans,
 857                         "Invalid event log pointer 0x%08X for %s uCode\n",
 858                         base,
 859                         (trans->shrd->ucode_type == IWL_UCODE_INIT)
 860                                         ? "Init" : "RT");
 861                 return -EINVAL;
 862         }
 863
 864         /* event log header */
 865         capacity = iwl_read_targ_mem(trans, base);
 866         mode = iwl_read_targ_mem(trans, base + (1 * sizeof(u32)));
 867         num_wraps = iwl_read_targ_mem(trans, base + (2 * sizeof(u32)));
 868         next_entry = iwl_read_targ_mem(trans, base + (3 * sizeof(u32)));
 869
 870         if (capacity > logsize) {
 871                 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
 872                         "entries\n", capacity, logsize);
 873                 capacity = logsize;
 874         }
 875
 876         if (next_entry > logsize) {
 877                 IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n",
 878                         next_entry, logsize);
 879                 next_entry = logsize;
 880         }
 881
 882         size = num_wraps ? capacity : next_entry;
 883
 884         /* bail out if nothing in log */
 885         if (size == 0) {
 886                 IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n");
 887                 return pos;
 888         }
 889
 890 #ifdef CONFIG_IWLWIFI_DEBUG
 891         if (!(iwl_have_debug_level(IWL_DL_FW_ERRORS)) && !full_log)
 892                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 893                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 894 #else
 895         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 896                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 897 #endif
 898         IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n",
 899                 size);
 900
 901 #ifdef CONFIG_IWLWIFI_DEBUG
 902         if (display) {
 903                 if (full_log)
 904                         bufsz = capacity * 48;
 905                 else
 906                         bufsz = size * 48;
 907                 *buf = kmalloc(bufsz, GFP_KERNEL);
 908                 if (!*buf)
 909                         return -ENOMEM;
 910         }
 911         if (iwl_have_debug_level(IWL_DL_FW_ERRORS) || full_log) {
 912                 /*
 913                  * if uCode has wrapped back to top of log,
 914                  * start at the oldest entry,
 915                  * i.e the next one that uCode would fill.
 916                  */
 917                 if (num_wraps)
 918                         pos = iwl_print_event_log(trans, next_entry,
 919                                                 capacity - next_entry, mode,
 920                                                 pos, buf, bufsz);
 921                 /* (then/else) start at top of log */
 922                 pos = iwl_print_event_log(trans, 0,
 923                                           next_entry, mode, pos, buf, bufsz);
 924         } else
 925                 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 926                                                 next_entry, size, mode,
 927                                                 pos, buf, bufsz);
 928 #else
 929         pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 930                                         next_entry, size, mode,
 931                                         pos, buf, bufsz);
 932 #endif
 933         return pos;
 934 }
 935
 936 /* tasklet for iwlagn interrupt */
 937 void iwl_irq_tasklet(struct iwl_trans *trans)
 938 {
 939         u32 inta = 0;
 940         u32 handled = 0;
 941         unsigned long flags;
 942         u32 i;
 943 #ifdef CONFIG_IWLWIFI_DEBUG
 944         u32 inta_mask;
 945 #endif
 946
 947         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 948         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 949
 950
 951         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 952
 953         /* Ack/clear/reset pending uCode interrupts.
 954          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 955          */
 956         /* There is a hardware bug in the interrupt mask function that some
 957          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 958          * they are disabled in the CSR_INT_MASK register. Furthermore the
 959          * ICT interrupt handling mechanism has another bug that might cause
 960          * these unmasked interrupts fail to be detected. We workaround the
 961          * hardware bugs here by ACKing all the possible interrupts so that
 962          * interrupt coalescing can still be achieved.
 963          */
 964         iwl_write32(trans, CSR_INT,
 965                 trans_pcie->inta | ~trans_pcie->inta_mask);
 966
 967         inta = trans_pcie->inta;
 968
 969 #ifdef CONFIG_IWLWIFI_DEBUG
 970         if (iwl_have_debug_level(IWL_DL_ISR)) {
 971                 /* just for debug */
 972                 inta_mask = iwl_read32(trans, CSR_INT_MASK);
 973                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
 974                                 inta, inta_mask);
 975         }
 976 #endif
 977
 978         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 979         trans_pcie->inta = 0;
 980
 981         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 982
 983         /* Now service all interrupt bits discovered above. */
 984         if (inta & CSR_INT_BIT_HW_ERR) {
 985                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 986
 987                 /* Tell the device to stop sending interrupts */
 988                 iwl_disable_interrupts(trans);
 989
 990                 isr_stats->hw++;
 991                 iwl_irq_handle_error(trans);
 992
 993                 handled |= CSR_INT_BIT_HW_ERR;
 994
 995                 return;
 996         }
 997
 998 #ifdef CONFIG_IWLWIFI_DEBUG
 999         if (iwl_have_debug_level(IWL_DL_ISR)) {
1000                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1001                 if (inta & CSR_INT_BIT_SCD) {
1002                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
1003                                       "the frame/frames.\n");
1004                         isr_stats->sch++;
1005                 }
1006
1007                 /* Alive notification via Rx interrupt will do the real work */
1008                 if (inta & CSR_INT_BIT_ALIVE) {
1009                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1010                         isr_stats->alive++;
1011                 }
1012         }
1013 #endif
1014         /* Safely ignore these bits for debug checks below */
1015         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1016
1017         /* HW RF KILL switch toggled */
1018         if (inta & CSR_INT_BIT_RF_KILL) {
1019                 bool hw_rfkill;
1020
1021                 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1022                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1023                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1024                                 hw_rfkill ? "disable radio" : "enable radio");
1025
1026                 isr_stats->rfkill++;
1027
1028                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1029
1030                 handled |= CSR_INT_BIT_RF_KILL;
1031         }
1032
1033         /* Chip got too hot and stopped itself */
1034         if (inta & CSR_INT_BIT_CT_KILL) {
1035                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1036                 isr_stats->ctkill++;
1037                 handled |= CSR_INT_BIT_CT_KILL;
1038         }
1039
1040         /* Error detected by uCode */
1041         if (inta & CSR_INT_BIT_SW_ERR) {
1042                 IWL_ERR(trans, "Microcode SW error detected. "
1043                         " Restarting 0x%X.\n", inta);
1044                 isr_stats->sw++;
1045                 iwl_irq_handle_error(trans);
1046                 handled |= CSR_INT_BIT_SW_ERR;
1047         }
1048
1049         /* uCode wakes up after power-down sleep */
1050         if (inta & CSR_INT_BIT_WAKEUP) {
1051                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1052                 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
1053                 for (i = 0; i < hw_params(trans).max_txq_num; i++)
1054                         iwl_txq_update_write_ptr(trans,
1055                                                  &trans_pcie->txq[i]);
1056
1057                 isr_stats->wakeup++;
1058
1059                 handled |= CSR_INT_BIT_WAKEUP;
1060         }
1061
1062         /* All uCode command responses, including Tx command responses,
1063          * Rx "responses" (frame-received notification), and other
1064          * notifications from uCode come through here*/
1065         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1066                         CSR_INT_BIT_RX_PERIODIC)) {
1067                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1068                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1069                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1070                         iwl_write32(trans, CSR_FH_INT_STATUS,
1071                                         CSR_FH_INT_RX_MASK);
1072                 }
1073                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1074                         handled |= CSR_INT_BIT_RX_PERIODIC;
1075                         iwl_write32(trans,
1076                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1077                 }
1078                 /* Sending RX interrupt require many steps to be done in the
1079                  * the device:
1080                  * 1- write interrupt to current index in ICT table.
1081                  * 2- dma RX frame.
1082                  * 3- update RX shared data to indicate last write index.
1083                  * 4- send interrupt.
1084                  * This could lead to RX race, driver could receive RX interrupt
1085                  * but the shared data changes does not reflect this;
1086                  * periodic interrupt will detect any dangling Rx activity.
1087                  */
1088
1089                 /* Disable periodic interrupt; we use it as just a one-shot. */
1090                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1091                             CSR_INT_PERIODIC_DIS);
1092 #ifdef CONFIG_IWLWIFI_IDI
1093                 iwl_amfh_rx_handler();
1094 #else
1095                 iwl_rx_handle(trans);
1096 #endif
1097                 /*
1098                  * Enable periodic interrupt in 8 msec only if we received
1099                  * real RX interrupt (instead of just periodic int), to catch
1100                  * any dangling Rx interrupt.  If it was just the periodic
1101                  * interrupt, there was no dangling Rx activity, and no need
1102                  * to extend the periodic interrupt; one-shot is enough.
1103                  */
1104                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1105                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
1106                                     CSR_INT_PERIODIC_ENA);
1107
1108                 isr_stats->rx++;
1109         }
1110
1111         /* This "Tx" DMA channel is used only for loading uCode */
1112         if (inta & CSR_INT_BIT_FH_TX) {
1113                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1114                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1115                 isr_stats->tx++;
1116                 handled |= CSR_INT_BIT_FH_TX;
1117                 /* Wake up uCode load routine, now that load is complete */
1118                 trans_pcie->ucode_write_complete = true;
1119                 wake_up(&trans_pcie->ucode_write_waitq);
1120         }
1121
1122         if (inta & ~handled) {
1123                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1124                 isr_stats->unhandled++;
1125         }
1126
1127         if (inta & ~(trans_pcie->inta_mask)) {
1128                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1129                          inta & ~trans_pcie->inta_mask);
1130         }
1131
1132         /* Re-enable all interrupts */
1133         /* only Re-enable if disabled by irq */
1134         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status))
1135                 iwl_enable_interrupts(trans);
1136         /* Re-enable RF_KILL if it occurred */
1137         else if (handled & CSR_INT_BIT_RF_KILL) {
1138                 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
1139                 iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
1140         }
1141 }
1142
1143 /******************************************************************************
1144  *
1145  * ICT functions
1146  *
1147  ******************************************************************************/
1148
1149 /* a device (PCI-E) page is 4096 bytes long */
1150 #define ICT_SHIFT       12
1151 #define ICT_SIZE        (1 << ICT_SHIFT)
1152 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
1153
1154 /* Free dram table */
1155 void iwl_free_isr_ict(struct iwl_trans *trans)
1156 {
1157         struct iwl_trans_pcie *trans_pcie =
1158                 IWL_TRANS_GET_PCIE_TRANS(trans);
1159
1160         if (trans_pcie->ict_tbl) {
1161                 dma_free_coherent(trans->dev, ICT_SIZE,
1162                                   trans_pcie->ict_tbl,
1163                                   trans_pcie->ict_tbl_dma);
1164                 trans_pcie->ict_tbl = NULL;
1165                 trans_pcie->ict_tbl_dma = 0;
1166         }
1167 }
1168
1169
1170 /*
1171  * allocate dram shared table, it is an aligned memory
1172  * block of ICT_SIZE.
1173  * also reset all data related to ICT table interrupt.
1174  */
1175 int iwl_alloc_isr_ict(struct iwl_trans *trans)
1176 {
1177         struct iwl_trans_pcie *trans_pcie =
1178                 IWL_TRANS_GET_PCIE_TRANS(trans);
1179
1180         trans_pcie->ict_tbl =
1181                 dma_alloc_coherent(trans->dev, ICT_SIZE,
1182                                    &trans_pcie->ict_tbl_dma,
1183                                    GFP_KERNEL);
1184         if (!trans_pcie->ict_tbl)
1185                 return -ENOMEM;
1186
1187         /* just an API sanity check ... it is guaranteed to be aligned */
1188         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1189                 iwl_free_isr_ict(trans);
1190                 return -EINVAL;
1191         }
1192
1193         IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
1194                       (unsigned long long)trans_pcie->ict_tbl_dma);
1195
1196         IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
1197
1198         /* reset table and index to all 0 */
1199         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1200         trans_pcie->ict_index = 0;
1201
1202         /* add periodic RX interrupt */
1203         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1204         return 0;
1205 }
1206
1207 /* Device is going up inform it about using ICT interrupt table,
1208  * also we need to tell the driver to start using ICT interrupt.
1209  */
1210 void iwl_reset_ict(struct iwl_trans *trans)
1211 {
1212         u32 val;
1213         unsigned long flags;
1214         struct iwl_trans_pcie *trans_pcie =
1215                 IWL_TRANS_GET_PCIE_TRANS(trans);
1216
1217         if (!trans_pcie->ict_tbl)
1218                 return;
1219
1220         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1221         iwl_disable_interrupts(trans);
1222
1223         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1224
1225         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1226
1227         val |= CSR_DRAM_INT_TBL_ENABLE;
1228         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1229
1230         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1231
1232         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1233         trans_pcie->use_ict = true;
1234         trans_pcie->ict_index = 0;
1235         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1236         iwl_enable_interrupts(trans);
1237         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1238 }
1239
1240 /* Device is going down disable ict interrupt usage */
1241 void iwl_disable_ict(struct iwl_trans *trans)
1242 {
1243         struct iwl_trans_pcie *trans_pcie =
1244                 IWL_TRANS_GET_PCIE_TRANS(trans);
1245
1246         unsigned long flags;
1247
1248         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1249         trans_pcie->use_ict = false;
1250         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1251 }
1252
1253 static irqreturn_t iwl_isr(int irq, void *data)
1254 {
1255         struct iwl_trans *trans = data;
1256         struct iwl_trans_pcie *trans_pcie;
1257         u32 inta, inta_mask;
1258         unsigned long flags;
1259 #ifdef CONFIG_IWLWIFI_DEBUG
1260         u32 inta_fh;
1261 #endif
1262         if (!trans)
1263                 return IRQ_NONE;
1264
1265         trace_iwlwifi_dev_irq(trans->dev);
1266
1267         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1268
1269         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1270
1271         /* Disable (but don't clear!) interrupts here to avoid
1272          *    back-to-back ISRs and sporadic interrupts from our NIC.
1273          * If we have something to service, the tasklet will re-enable ints.
1274          * If we *don't* have something, we'll re-enable before leaving here. */
1275         inta_mask = iwl_read32(trans, CSR_INT_MASK);  /* just for debug */
1276         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1277
1278         /* Discover which interrupts are active/pending */
1279         inta = iwl_read32(trans, CSR_INT);
1280
1281         /* Ignore interrupt if there's nothing in NIC to service.
1282          * This may be due to IRQ shared with another device,
1283          * or due to sporadic interrupts thrown from our NIC. */
1284         if (!inta) {
1285                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1286                 goto none;
1287         }
1288
1289         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1290                 /* Hardware disappeared. It might have already raised
1291                  * an interrupt */
1292                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1293                 goto unplugged;
1294         }
1295
1296 #ifdef CONFIG_IWLWIFI_DEBUG
1297         if (iwl_have_debug_level(IWL_DL_ISR)) {
1298                 inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS);
1299                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1300                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
1301         }
1302 #endif
1303
1304         trans_pcie->inta |= inta;
1305         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1306         if (likely(inta))
1307                 tasklet_schedule(&trans_pcie->irq_tasklet);
1308         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1309                         !trans_pcie->inta)
1310                 iwl_enable_interrupts(trans);
1311
1312  unplugged:
1313         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1314         return IRQ_HANDLED;
1315
1316  none:
1317         /* re-enable interrupts here since we don't have anything to service. */
1318         /* only Re-enable if disabled by irq  and no schedules tasklet. */
1319         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1320                 !trans_pcie->inta)
1321                 iwl_enable_interrupts(trans);
1322
1323         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1324         return IRQ_NONE;
1325 }
1326
1327 /* interrupt handler using ict table, with this interrupt driver will
1328  * stop using INTA register to get device's interrupt, reading this register
1329  * is expensive, device will write interrupts in ICT dram table, increment
1330  * index then will fire interrupt to driver, driver will OR all ICT table
1331  * entries from current index up to table entry with 0 value. the result is
1332  * the interrupt we need to service, driver will set the entries back to 0 and
1333  * set index.
1334  */
1335 irqreturn_t iwl_isr_ict(int irq, void *data)
1336 {
1337         struct iwl_trans *trans = data;
1338         struct iwl_trans_pcie *trans_pcie;
1339         u32 inta, inta_mask;
1340         u32 val = 0;
1341         u32 read;
1342         unsigned long flags;
1343
1344         if (!trans)
1345                 return IRQ_NONE;
1346
1347         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1348
1349         /* dram interrupt table not set yet,
1350          * use legacy interrupt.
1351          */
1352         if (!trans_pcie->use_ict)
1353                 return iwl_isr(irq, data);
1354
1355         trace_iwlwifi_dev_irq(trans->dev);
1356
1357         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1358
1359         /* Disable (but don't clear!) interrupts here to avoid
1360          * back-to-back ISRs and sporadic interrupts from our NIC.
1361          * If we have something to service, the tasklet will re-enable ints.
1362          * If we *don't* have something, we'll re-enable before leaving here.
1363          */
1364         inta_mask = iwl_read32(trans, CSR_INT_MASK);  /* just for debug */
1365         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1366
1367
1368         /* Ignore interrupt if there's nothing in NIC to service.
1369          * This may be due to IRQ shared with another device,
1370          * or due to sporadic interrupts thrown from our NIC. */
1371         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1372         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1373         if (!read) {
1374                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1375                 goto none;
1376         }
1377
1378         /*
1379          * Collect all entries up to the first 0, starting from ict_index;
1380          * note we already read at ict_index.
1381          */
1382         do {
1383                 val |= read;
1384                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1385                                 trans_pcie->ict_index, read);
1386                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1387                 trans_pcie->ict_index =
1388                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1389
1390                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1391                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1392                                            read);
1393         } while (read);
1394
1395         /* We should not get this value, just ignore it. */
1396         if (val == 0xffffffff)
1397                 val = 0;
1398
1399         /*
1400          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1401          * (bit 15 before shifting it to 31) to clear when using interrupt
1402          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1403          * so we use them to decide on the real state of the Rx bit.
1404          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1405          */
1406         if (val & 0xC0000)
1407                 val |= 0x8000;
1408
1409         inta = (0xff & val) | ((0xff00 & val) << 16);
1410         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1411                         inta, inta_mask, val);
1412
1413         inta &= trans_pcie->inta_mask;
1414         trans_pcie->inta |= inta;
1415
1416         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1417         if (likely(inta))
1418                 tasklet_schedule(&trans_pcie->irq_tasklet);
1419         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1420                  !trans_pcie->inta) {
1421                 /* Allow interrupt if was disabled by this handler and
1422                  * no tasklet was schedules, We should not enable interrupt,
1423                  * tasklet will enable it.
1424                  */
1425                 iwl_enable_interrupts(trans);
1426         }
1427
1428         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1429         return IRQ_HANDLED;
1430
1431  none:
1432         /* re-enable interrupts here since we don't have anything to service.
1433          * only Re-enable if disabled by irq.
1434          */
1435         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1436             !trans_pcie->inta)
1437                 iwl_enable_interrupts(trans);
1438
1439         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1440         return IRQ_NONE;
1441 }