1 /******************************************************************************
3 * Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
35 #include <net/mac80211.h>
37 #include "iwl-eeprom.h"
41 #include "iwl-commands.h"
42 #include "iwl-debug.h"
43 #include "iwl-power.h"
46 * Setting power level allows the card to go to sleep when not busy.
48 * We calculate a sleep command based on the required latency, which
49 * we get from mac80211. In order to handle thermal throttling, we can
50 * also use pre-defined power levels.
54 * For now, keep using power level 1 instead of automatically
57 bool no_sleep_autoadjust = true;
58 module_param(no_sleep_autoadjust, bool, S_IRUGO);
59 MODULE_PARM_DESC(no_sleep_autoadjust,
60 "don't automatically adjust sleep level "
61 "according to maximum network latency");
64 * This defines the old power levels. They are still used by default
65 * (level 1) and for thermal throttle (levels 3 through 5)
68 struct iwl_power_vec_entry {
69 struct iwl_powertable_cmd cmd;
70 u8 no_dtim; /* number of skip dtim */
73 #define IWL_DTIM_RANGE_0_MAX 2
74 #define IWL_DTIM_RANGE_1_MAX 10
76 #define NOSLP cpu_to_le16(0), 0, 0
77 #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
78 #define TU_TO_USEC 1024
79 #define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
80 #define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
85 /* default power management (not Tx power) table values */
86 /* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */
88 static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
89 {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0},
90 {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
91 {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
92 {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
93 {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
97 /* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
99 static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
100 {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
101 {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
102 {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
103 {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
104 {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2}
107 /* for DTIM period > IWL_DTIM_RANGE_1_MAX */
109 static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
110 {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
111 {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
112 {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
113 {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
114 {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
117 static void iwl_static_sleep_cmd(struct iwl_priv *priv,
118 struct iwl_powertable_cmd *cmd,
119 enum iwl_power_level lvl, int period)
121 const struct iwl_power_vec_entry *table;
122 int max_sleep[IWL_POWER_VEC_SIZE] = { 0 };
128 if (period <= IWL_DTIM_RANGE_1_MAX)
130 if (period <= IWL_DTIM_RANGE_0_MAX)
133 BUG_ON(lvl < 0 || lvl >= IWL_POWER_NUM);
135 *cmd = table[lvl].cmd;
140 for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
144 skip = table[lvl].no_dtim;
145 for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
146 max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]);
147 max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1;
150 slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
151 /* figure out the listen interval based on dtim period and skip */
152 if (slp_itrvl == 0xFF)
153 cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
154 cpu_to_le32(period * (skip + 1));
156 slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
157 if (slp_itrvl > period)
158 cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
159 cpu_to_le32((slp_itrvl / period) * period);
162 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
164 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
166 if (priv->cfg->base_params->shadow_reg_enable)
167 cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
169 cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
171 if (priv->cfg->bt_params &&
172 priv->cfg->bt_params->advanced_bt_coexist) {
173 if (!priv->cfg->bt_params->bt_sco_disable)
174 cmd->flags |= IWL_POWER_BT_SCO_ENA;
176 cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
180 slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
181 if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL)
182 cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
183 cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL);
185 /* enforce max sleep interval */
186 for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) {
187 if (le32_to_cpu(cmd->sleep_interval[i]) >
188 (max_sleep[i] * period))
189 cmd->sleep_interval[i] =
190 cpu_to_le32(max_sleep[i] * period);
191 if (i != (IWL_POWER_VEC_SIZE - 1)) {
192 if (le32_to_cpu(cmd->sleep_interval[i]) >
193 le32_to_cpu(cmd->sleep_interval[i+1]))
194 cmd->sleep_interval[i] =
195 cmd->sleep_interval[i+1];
199 if (priv->power_data.pci_pm)
200 cmd->flags |= IWL_POWER_PCI_PM_MSK;
202 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
204 IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n",
206 IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1);
209 static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
210 struct iwl_powertable_cmd *cmd)
212 memset(cmd, 0, sizeof(*cmd));
214 if (priv->power_data.pci_pm)
215 cmd->flags |= IWL_POWER_PCI_PM_MSK;
217 IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
220 static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv,
221 struct iwl_powertable_cmd *cmd,
222 int dynps_ms, int wakeup_period)
225 * These are the original power level 3 sleep successions. The
226 * device may behave better with such succession and was also
227 * only tested with that. Just like the original sleep commands,
228 * also adjust the succession here to the wakeup_period below.
229 * The ranges are the same as for the sleep commands, 0-2, 3-9
230 * and >10, which is selected based on the DTIM interval for
231 * the sleep index but here we use the wakeup period since that
232 * is what we need to do for the latency requirements.
234 static const u8 slp_succ_r0[IWL_POWER_VEC_SIZE] = { 2, 2, 2, 2, 2 };
235 static const u8 slp_succ_r1[IWL_POWER_VEC_SIZE] = { 2, 4, 6, 7, 9 };
236 static const u8 slp_succ_r2[IWL_POWER_VEC_SIZE] = { 2, 7, 9, 9, 0xFF };
237 const u8 *slp_succ = slp_succ_r0;
240 if (wakeup_period > IWL_DTIM_RANGE_0_MAX)
241 slp_succ = slp_succ_r1;
242 if (wakeup_period > IWL_DTIM_RANGE_1_MAX)
243 slp_succ = slp_succ_r2;
245 memset(cmd, 0, sizeof(*cmd));
247 cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK |
248 IWL_POWER_FAST_PD; /* no use seeing frames for others */
250 if (priv->power_data.pci_pm)
251 cmd->flags |= IWL_POWER_PCI_PM_MSK;
253 if (priv->cfg->base_params->shadow_reg_enable)
254 cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
256 cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
258 if (priv->cfg->bt_params &&
259 priv->cfg->bt_params->advanced_bt_coexist) {
260 if (!priv->cfg->bt_params->bt_sco_disable)
261 cmd->flags |= IWL_POWER_BT_SCO_ENA;
263 cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
266 cmd->rx_data_timeout = cpu_to_le32(1000 * dynps_ms);
267 cmd->tx_data_timeout = cpu_to_le32(1000 * dynps_ms);
269 for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
270 cmd->sleep_interval[i] =
271 cpu_to_le32(min_t(int, slp_succ[i], wakeup_period));
273 IWL_DEBUG_POWER(priv, "Automatic sleep command\n");
276 static int iwl_set_power(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd)
278 IWL_DEBUG_POWER(priv, "Sending power/sleep command\n");
279 IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
280 IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
281 IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
282 IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
283 le32_to_cpu(cmd->sleep_interval[0]),
284 le32_to_cpu(cmd->sleep_interval[1]),
285 le32_to_cpu(cmd->sleep_interval[2]),
286 le32_to_cpu(cmd->sleep_interval[3]),
287 le32_to_cpu(cmd->sleep_interval[4]));
289 return iwl_send_cmd_pdu(priv, POWER_TABLE_CMD,
290 sizeof(struct iwl_powertable_cmd), cmd);
293 static void iwl_power_build_cmd(struct iwl_priv *priv,
294 struct iwl_powertable_cmd *cmd)
296 bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS;
299 dtimper = priv->hw->conf.ps_dtim_period ?: 1;
301 if (priv->cfg->base_params->broken_powersave)
302 iwl_power_sleep_cam_cmd(priv, cmd);
303 else if (priv->cfg->base_params->supports_idle &&
304 priv->hw->conf.flags & IEEE80211_CONF_IDLE)
305 iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20);
306 else if (priv->cfg->ops->lib->tt_ops.lower_power_detection &&
307 priv->cfg->ops->lib->tt_ops.tt_power_mode &&
308 priv->cfg->ops->lib->tt_ops.lower_power_detection(priv)) {
309 /* in thermal throttling low power state */
310 iwl_static_sleep_cmd(priv, cmd,
311 priv->cfg->ops->lib->tt_ops.tt_power_mode(priv), dtimper);
313 iwl_power_sleep_cam_cmd(priv, cmd);
314 else if (priv->power_data.debug_sleep_level_override >= 0)
315 iwl_static_sleep_cmd(priv, cmd,
316 priv->power_data.debug_sleep_level_override,
318 else if (no_sleep_autoadjust)
319 iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_1, dtimper);
321 iwl_power_fill_sleep_cmd(priv, cmd,
322 priv->hw->conf.dynamic_ps_timeout,
323 priv->hw->conf.max_sleep_period);
326 int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd,
332 lockdep_assert_held(&priv->mutex);
334 /* Don't update the RX chain when chain noise calibration is running */
335 update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE ||
336 priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;
338 if (!memcmp(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
341 if (!iwl_is_ready_rf(priv))
344 /* scan complete use sleep_power_next, need to be updated */
345 memcpy(&priv->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
346 if (test_bit(STATUS_SCANNING, &priv->status) && !force) {
347 IWL_DEBUG_INFO(priv, "Defer power set mode while scanning\n");
351 if (cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
352 set_bit(STATUS_POWER_PMI, &priv->status);
354 ret = iwl_set_power(priv, cmd);
356 if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
357 clear_bit(STATUS_POWER_PMI, &priv->status);
359 if (priv->cfg->ops->lib->update_chain_flags && update_chains)
360 priv->cfg->ops->lib->update_chain_flags(priv);
361 else if (priv->cfg->ops->lib->update_chain_flags)
362 IWL_DEBUG_POWER(priv,
363 "Cannot update the power, chain noise "
364 "calibration running: %d\n",
365 priv->chain_noise_data.state);
367 memcpy(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd));
369 IWL_ERR(priv, "set power fail, ret = %d", ret);
373 EXPORT_SYMBOL(iwl_power_set_mode);
375 int iwl_power_update_mode(struct iwl_priv *priv, bool force)
377 struct iwl_powertable_cmd cmd;
379 iwl_power_build_cmd(priv, &cmd);
380 return iwl_power_set_mode(priv, &cmd, force);
382 EXPORT_SYMBOL(iwl_power_update_mode);
384 /* initialize to default */
385 void iwl_power_initialize(struct iwl_priv *priv)
387 u16 lctl = iwl_pcie_link_ctl(priv);
389 priv->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
391 priv->power_data.debug_sleep_level_override = -1;
393 memset(&priv->power_data.sleep_cmd, 0,
394 sizeof(priv->power_data.sleep_cmd));
396 EXPORT_SYMBOL(iwl_power_initialize);