drivers/net/wireless/iwlwifi/iwl-agn-lib.c

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/etherdevice.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/init.h>
  33 #include <linux/sched.h>
  34
  35 #include "iwl-dev.h"
  36 #include "iwl-core.h"
  37 #include "iwl-io.h"
  38 #include "iwl-helpers.h"
  39 #include "iwl-agn-hw.h"
  40 #include "iwl-agn.h"
  41 #include "iwl-sta.h"
  42
  43 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
  44 {
  45         return le32_to_cpup((__le32 *)&tx_resp->status +
  46                             tx_resp->frame_count) & MAX_SN;
  47 }
  48
  49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
  50 {
  51         status &= TX_STATUS_MSK;
  52
  53         switch (status) {
  54         case TX_STATUS_POSTPONE_DELAY:
  55                 priv->_agn.reply_tx_stats.pp_delay++;
  56                 break;
  57         case TX_STATUS_POSTPONE_FEW_BYTES:
  58                 priv->_agn.reply_tx_stats.pp_few_bytes++;
  59                 break;
  60         case TX_STATUS_POSTPONE_BT_PRIO:
  61                 priv->_agn.reply_tx_stats.pp_bt_prio++;
  62                 break;
  63         case TX_STATUS_POSTPONE_QUIET_PERIOD:
  64                 priv->_agn.reply_tx_stats.pp_quiet_period++;
  65                 break;
  66         case TX_STATUS_POSTPONE_CALC_TTAK:
  67                 priv->_agn.reply_tx_stats.pp_calc_ttak++;
  68                 break;
  69         case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
  70                 priv->_agn.reply_tx_stats.int_crossed_retry++;
  71                 break;
  72         case TX_STATUS_FAIL_SHORT_LIMIT:
  73                 priv->_agn.reply_tx_stats.short_limit++;
  74                 break;
  75         case TX_STATUS_FAIL_LONG_LIMIT:
  76                 priv->_agn.reply_tx_stats.long_limit++;
  77                 break;
  78         case TX_STATUS_FAIL_FIFO_UNDERRUN:
  79                 priv->_agn.reply_tx_stats.fifo_underrun++;
  80                 break;
  81         case TX_STATUS_FAIL_DRAIN_FLOW:
  82                 priv->_agn.reply_tx_stats.drain_flow++;
  83                 break;
  84         case TX_STATUS_FAIL_RFKILL_FLUSH:
  85                 priv->_agn.reply_tx_stats.rfkill_flush++;
  86                 break;
  87         case TX_STATUS_FAIL_LIFE_EXPIRE:
  88                 priv->_agn.reply_tx_stats.life_expire++;
  89                 break;
  90         case TX_STATUS_FAIL_DEST_PS:
  91                 priv->_agn.reply_tx_stats.dest_ps++;
  92                 break;
  93         case TX_STATUS_FAIL_HOST_ABORTED:
  94                 priv->_agn.reply_tx_stats.host_abort++;
  95                 break;
  96         case TX_STATUS_FAIL_BT_RETRY:
  97                 priv->_agn.reply_tx_stats.bt_retry++;
  98                 break;
  99         case TX_STATUS_FAIL_STA_INVALID:
 100                 priv->_agn.reply_tx_stats.sta_invalid++;
 101                 break;
 102         case TX_STATUS_FAIL_FRAG_DROPPED:
 103                 priv->_agn.reply_tx_stats.frag_drop++;
 104                 break;
 105         case TX_STATUS_FAIL_TID_DISABLE:
 106                 priv->_agn.reply_tx_stats.tid_disable++;
 107                 break;
 108         case TX_STATUS_FAIL_FIFO_FLUSHED:
 109                 priv->_agn.reply_tx_stats.fifo_flush++;
 110                 break;
 111         case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
 112                 priv->_agn.reply_tx_stats.insuff_cf_poll++;
 113                 break;
 114         case TX_STATUS_FAIL_PASSIVE_NO_RX:
 115                 priv->_agn.reply_tx_stats.fail_hw_drop++;
 116                 break;
 117         case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
 118                 priv->_agn.reply_tx_stats.sta_color_mismatch++;
 119                 break;
 120         default:
 121                 priv->_agn.reply_tx_stats.unknown++;
 122                 break;
 123         }
 124 }
 125
 126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
 127 {
 128         status &= AGG_TX_STATUS_MSK;
 129
 130         switch (status) {
 131         case AGG_TX_STATE_UNDERRUN_MSK:
 132                 priv->_agn.reply_agg_tx_stats.underrun++;
 133                 break;
 134         case AGG_TX_STATE_BT_PRIO_MSK:
 135                 priv->_agn.reply_agg_tx_stats.bt_prio++;
 136                 break;
 137         case AGG_TX_STATE_FEW_BYTES_MSK:
 138                 priv->_agn.reply_agg_tx_stats.few_bytes++;
 139                 break;
 140         case AGG_TX_STATE_ABORT_MSK:
 141                 priv->_agn.reply_agg_tx_stats.abort++;
 142                 break;
 143         case AGG_TX_STATE_LAST_SENT_TTL_MSK:
 144                 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
 145                 break;
 146         case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
 147                 priv->_agn.reply_agg_tx_stats.last_sent_try++;
 148                 break;
 149         case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
 150                 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
 151                 break;
 152         case AGG_TX_STATE_SCD_QUERY_MSK:
 153                 priv->_agn.reply_agg_tx_stats.scd_query++;
 154                 break;
 155         case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
 156                 priv->_agn.reply_agg_tx_stats.bad_crc32++;
 157                 break;
 158         case AGG_TX_STATE_RESPONSE_MSK:
 159                 priv->_agn.reply_agg_tx_stats.response++;
 160                 break;
 161         case AGG_TX_STATE_DUMP_TX_MSK:
 162                 priv->_agn.reply_agg_tx_stats.dump_tx++;
 163                 break;
 164         case AGG_TX_STATE_DELAY_TX_MSK:
 165                 priv->_agn.reply_agg_tx_stats.delay_tx++;
 166                 break;
 167         default:
 168                 priv->_agn.reply_agg_tx_stats.unknown++;
 169                 break;
 170         }
 171 }
 172
 173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
 174                                  struct ieee80211_tx_info *info,
 175                                  struct iwlagn_tx_resp *tx_resp,
 176                                  int txq_id, bool is_agg)
 177 {
 178         u16  status = le16_to_cpu(tx_resp->status.status);
 179
 180         info->status.rates[0].count = tx_resp->failure_frame + 1;
 181         if (is_agg)
 182                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
 183         info->flags |= iwl_tx_status_to_mac80211(status);
 184         iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
 185                                     info);
 186         if (!iwl_is_tx_success(status))
 187                 iwlagn_count_tx_err_status(priv, status);
 188
 189         IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
 190                            "0x%x retries %d\n",
 191                            txq_id,
 192                            iwl_get_tx_fail_reason(status), status,
 193                            le32_to_cpu(tx_resp->rate_n_flags),
 194                            tx_resp->failure_frame);
 195 }
 196
 197 #ifdef CONFIG_IWLWIFI_DEBUG
 198 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
 199
 200 const char *iwl_get_agg_tx_fail_reason(u16 status)
 201 {
 202         status &= AGG_TX_STATUS_MSK;
 203         switch (status) {
 204         case AGG_TX_STATE_TRANSMITTED:
 205                 return "SUCCESS";
 206                 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
 207                 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
 208                 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
 209                 AGG_TX_STATE_FAIL(ABORT_MSK);
 210                 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
 211                 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
 212                 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
 213                 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
 214                 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
 215                 AGG_TX_STATE_FAIL(RESPONSE_MSK);
 216                 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
 217                 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
 218         }
 219
 220         return "UNKNOWN";
 221 }
 222 #endif /* CONFIG_IWLWIFI_DEBUG */
 223
 224 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
 225                                       struct iwl_ht_agg *agg,
 226                                       struct iwlagn_tx_resp *tx_resp,
 227                                       int txq_id, u16 start_idx)
 228 {
 229         u16 status;
 230         struct agg_tx_status *frame_status = &tx_resp->status;
 231         struct ieee80211_hdr *hdr = NULL;
 232         int i, sh, idx;
 233         u16 seq;
 234
 235         if (agg->wait_for_ba)
 236                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
 237
 238         agg->frame_count = tx_resp->frame_count;
 239         agg->start_idx = start_idx;
 240         agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
 241         agg->bitmap = 0;
 242
 243         /* # frames attempted by Tx command */
 244         if (agg->frame_count == 1) {
 245                 /* Only one frame was attempted; no block-ack will arrive */
 246                 idx = start_idx;
 247
 248                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
 249                                    agg->frame_count, agg->start_idx, idx);
 250                 iwlagn_set_tx_status(priv,
 251                                      IEEE80211_SKB_CB(
 252                                         priv->txq[txq_id].txb[idx].skb),
 253                                      tx_resp, txq_id, true);
 254                 agg->wait_for_ba = 0;
 255         } else {
 256                 /* Two or more frames were attempted; expect block-ack */
 257                 u64 bitmap = 0;
 258
 259                 /*
 260                  * Start is the lowest frame sent. It may not be the first
 261                  * frame in the batch; we figure this out dynamically during
 262                  * the following loop.
 263                  */
 264                 int start = agg->start_idx;
 265
 266                 /* Construct bit-map of pending frames within Tx window */
 267                 for (i = 0; i < agg->frame_count; i++) {
 268                         u16 sc;
 269                         status = le16_to_cpu(frame_status[i].status);
 270                         seq  = le16_to_cpu(frame_status[i].sequence);
 271                         idx = SEQ_TO_INDEX(seq);
 272                         txq_id = SEQ_TO_QUEUE(seq);
 273
 274                         if (status & AGG_TX_STATUS_MSK)
 275                                 iwlagn_count_agg_tx_err_status(priv, status);
 276
 277                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
 278                                       AGG_TX_STATE_ABORT_MSK))
 279                                 continue;
 280
 281                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
 282                                            agg->frame_count, txq_id, idx);
 283                         IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
 284                                            "try-count (0x%08x)\n",
 285                                            iwl_get_agg_tx_fail_reason(status),
 286                                            status & AGG_TX_STATUS_MSK,
 287                                            status & AGG_TX_TRY_MSK);
 288
 289                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
 290                         if (!hdr) {
 291                                 IWL_ERR(priv,
 292                                         "BUG_ON idx doesn't point to valid skb"
 293                                         " idx=%d, txq_id=%d\n", idx, txq_id);
 294                                 return -1;
 295                         }
 296
 297                         sc = le16_to_cpu(hdr->seq_ctrl);
 298                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
 299                                 IWL_ERR(priv,
 300                                         "BUG_ON idx doesn't match seq control"
 301                                         " idx=%d, seq_idx=%d, seq=%d\n",
 302                                           idx, SEQ_TO_SN(sc),
 303                                           hdr->seq_ctrl);
 304                                 return -1;
 305                         }
 306
 307                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
 308                                            i, idx, SEQ_TO_SN(sc));
 309
 310                         /*
 311                          * sh -> how many frames ahead of the starting frame is
 312                          * the current one?
 313                          *
 314                          * Note that all frames sent in the batch must be in a
 315                          * 64-frame window, so this number should be in [0,63].
 316                          * If outside of this window, then we've found a new
 317                          * "first" frame in the batch and need to change start.
 318                          */
 319                         sh = idx - start;
 320
 321                         /*
 322                          * If >= 64, out of window. start must be at the front
 323                          * of the circular buffer, idx must be near the end of
 324                          * the buffer, and idx is the new "first" frame. Shift
 325                          * the indices around.
 326                          */
 327                         if (sh >= 64) {
 328                                 /* Shift bitmap by start - idx, wrapped */
 329                                 sh = 0x100 - idx + start;
 330                                 bitmap = bitmap << sh;
 331                                 /* Now idx is the new start so sh = 0 */
 332                                 sh = 0;
 333                                 start = idx;
 334                         /*
 335                          * If <= -64 then wraps the 256-pkt circular buffer
 336                          * (e.g., start = 255 and idx = 0, sh should be 1)
 337                          */
 338                         } else if (sh <= -64) {
 339                                 sh  = 0x100 - start + idx;
 340                         /*
 341                          * If < 0 but > -64, out of window. idx is before start
 342                          * but not wrapped. Shift the indices around.
 343                          */
 344                         } else if (sh < 0) {
 345                                 /* Shift by how far start is ahead of idx */
 346                                 sh = start - idx;
 347                                 bitmap = bitmap << sh;
 348                                 /* Now idx is the new start so sh = 0 */
 349                                 start = idx;
 350                                 sh = 0;
 351                         }
 352                         /* Sequence number start + sh was sent in this batch */
 353                         bitmap |= 1ULL << sh;
 354                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
 355                                            start, (unsigned long long)bitmap);
 356                 }
 357
 358                 /*
 359                  * Store the bitmap and possibly the new start, if we wrapped
 360                  * the buffer above
 361                  */
 362                 agg->bitmap = bitmap;
 363                 agg->start_idx = start;
 364                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
 365                                    agg->frame_count, agg->start_idx,
 366                                    (unsigned long long)agg->bitmap);
 367
 368                 if (bitmap)
 369                         agg->wait_for_ba = 1;
 370         }
 371         return 0;
 372 }
 373
 374 void iwl_check_abort_status(struct iwl_priv *priv,
 375                             u8 frame_count, u32 status)
 376 {
 377         if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
 378                 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
 379                 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 380                         queue_work(priv->workqueue, &priv->tx_flush);
 381         }
 382 }
 383
 384 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
 385                                 struct iwl_rx_mem_buffer *rxb)
 386 {
 387         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 388         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 389         int txq_id = SEQ_TO_QUEUE(sequence);
 390         int index = SEQ_TO_INDEX(sequence);
 391         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 392         struct ieee80211_tx_info *info;
 393         struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 394         u32  status = le16_to_cpu(tx_resp->status.status);
 395         int tid;
 396         int sta_id;
 397         int freed;
 398         unsigned long flags;
 399
 400         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 401                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 402                           "is out of range [0-%d] %d %d\n", txq_id,
 403                           index, txq->q.n_bd, txq->q.write_ptr,
 404                           txq->q.read_ptr);
 405                 return;
 406         }
 407
 408         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
 409         memset(&info->status, 0, sizeof(info->status));
 410
 411         tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
 412                 IWLAGN_TX_RES_TID_POS;
 413         sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
 414                 IWLAGN_TX_RES_RA_POS;
 415
 416         spin_lock_irqsave(&priv->sta_lock, flags);
 417         if (txq->sched_retry) {
 418                 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
 419                 struct iwl_ht_agg *agg;
 420
 421                 agg = &priv->stations[sta_id].tid[tid].agg;
 422                 /*
 423                  * If the BT kill count is non-zero, we'll get this
 424                  * notification again.
 425                  */
 426                 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
 427                     priv->cfg->bt_params &&
 428                     priv->cfg->bt_params->advanced_bt_coexist) {
 429                         IWL_WARN(priv, "receive reply tx with bt_kill\n");
 430                 }
 431                 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
 432
 433                 /* check if BAR is needed */
 434                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
 435                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
 436
 437                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
 438                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
 439                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
 440                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
 441                                         scd_ssn , index, txq_id, txq->swq_id);
 442
 443                         freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
 444                         iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
 445
 446                         if (priv->mac80211_registered &&
 447                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
 448                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
 449                                 if (agg->state == IWL_AGG_OFF)
 450                                         iwl_wake_queue(priv, txq_id);
 451                                 else
 452                                         iwl_wake_queue(priv, txq->swq_id);
 453                         }
 454                 }
 455         } else {
 456                 BUG_ON(txq_id != txq->swq_id);
 457                 iwlagn_set_tx_status(priv, info, tx_resp, txq_id, false);
 458                 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
 459                 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
 460
 461                 if (priv->mac80211_registered &&
 462                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
 463                         iwl_wake_queue(priv, txq_id);
 464         }
 465
 466         iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
 467
 468         iwl_check_abort_status(priv, tx_resp->frame_count, status);
 469         spin_unlock_irqrestore(&priv->sta_lock, flags);
 470 }
 471
 472 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
 473 {
 474         /* init calibration handlers */
 475         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
 476                                         iwlagn_rx_calib_result;
 477         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
 478                                         iwlagn_rx_calib_complete;
 479         priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
 480 }
 481
 482 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
 483 {
 484         /* in agn, the tx power calibration is done in uCode */
 485         priv->disable_tx_power_cal = 1;
 486 }
 487
 488 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
 489 {
 490         return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
 491                 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
 492 }
 493
 494 int iwlagn_send_tx_power(struct iwl_priv *priv)
 495 {
 496         struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
 497         u8 tx_ant_cfg_cmd;
 498
 499         /* half dBm need to multiply */
 500         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
 501
 502         if (priv->tx_power_lmt_in_half_dbm &&
 503             priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
 504                 /*
 505                  * For the newer devices which using enhanced/extend tx power
 506                  * table in EEPROM, the format is in half dBm. driver need to
 507                  * convert to dBm format before report to mac80211.
 508                  * By doing so, there is a possibility of 1/2 dBm resolution
 509                  * lost. driver will perform "round-up" operation before
 510                  * reporting, but it will cause 1/2 dBm tx power over the
 511                  * regulatory limit. Perform the checking here, if the
 512                  * "tx_power_user_lmt" is higher than EEPROM value (in
 513                  * half-dBm format), lower the tx power based on EEPROM
 514                  */
 515                 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
 516         }
 517         tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
 518         tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
 519
 520         if (IWL_UCODE_API(priv->ucode_ver) == 1)
 521                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
 522         else
 523                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
 524
 525         return  iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
 526                                        sizeof(tx_power_cmd), &tx_power_cmd,
 527                                        NULL);
 528 }
 529
 530 void iwlagn_temperature(struct iwl_priv *priv)
 531 {
 532         /* store temperature from statistics (in Celsius) */
 533         priv->temperature =
 534                 le32_to_cpu(priv->_agn.statistics.general.common.temperature);
 535         iwl_tt_handler(priv);
 536 }
 537
 538 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
 539 {
 540         struct iwl_eeprom_calib_hdr {
 541                 u8 version;
 542                 u8 pa_type;
 543                 u16 voltage;
 544         } *hdr;
 545
 546         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 547                                                         EEPROM_CALIB_ALL);
 548         return hdr->version;
 549
 550 }
 551
 552 /*
 553  * EEPROM
 554  */
 555 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 556 {
 557         u16 offset = 0;
 558
 559         if ((address & INDIRECT_ADDRESS) == 0)
 560                 return address;
 561
 562         switch (address & INDIRECT_TYPE_MSK) {
 563         case INDIRECT_HOST:
 564                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
 565                 break;
 566         case INDIRECT_GENERAL:
 567                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
 568                 break;
 569         case INDIRECT_REGULATORY:
 570                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
 571                 break;
 572         case INDIRECT_CALIBRATION:
 573                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
 574                 break;
 575         case INDIRECT_PROCESS_ADJST:
 576                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
 577                 break;
 578         case INDIRECT_OTHERS:
 579                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
 580                 break;
 581         default:
 582                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
 583                 address & INDIRECT_TYPE_MSK);
 584                 break;
 585         }
 586
 587         /* translate the offset from words to byte */
 588         return (address & ADDRESS_MSK) + (offset << 1);
 589 }
 590
 591 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
 592                                            size_t offset)
 593 {
 594         u32 address = eeprom_indirect_address(priv, offset);
 595         BUG_ON(address >= priv->cfg->base_params->eeprom_size);
 596         return &priv->eeprom[address];
 597 }
 598
 599 struct iwl_mod_params iwlagn_mod_params = {
 600         .amsdu_size_8K = 1,
 601         .restart_fw = 1,
 602         /* the rest are 0 by default */
 603 };
 604
 605 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 606 {
 607         unsigned long flags;
 608         int i;
 609         spin_lock_irqsave(&rxq->lock, flags);
 610         INIT_LIST_HEAD(&rxq->rx_free);
 611         INIT_LIST_HEAD(&rxq->rx_used);
 612         /* Fill the rx_used queue with _all_ of the Rx buffers */
 613         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 614                 /* In the reset function, these buffers may have been allocated
 615                  * to an SKB, so we need to unmap and free potential storage */
 616                 if (rxq->pool[i].page != NULL) {
 617                         pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
 618                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 619                                 PCI_DMA_FROMDEVICE);
 620                         __iwl_free_pages(priv, rxq->pool[i].page);
 621                         rxq->pool[i].page = NULL;
 622                 }
 623                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 624         }
 625
 626         for (i = 0; i < RX_QUEUE_SIZE; i++)
 627                 rxq->queue[i] = NULL;
 628
 629         /* Set us so that we have processed and used all buffers, but have
 630          * not restocked the Rx queue with fresh buffers */
 631         rxq->read = rxq->write = 0;
 632         rxq->write_actual = 0;
 633         rxq->free_count = 0;
 634         spin_unlock_irqrestore(&rxq->lock, flags);
 635 }
 636
 637 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 638 {
 639         u32 rb_size;
 640         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 641         u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
 642
 643         if (!priv->cfg->base_params->use_isr_legacy)
 644                 rb_timeout = RX_RB_TIMEOUT;
 645
 646         if (priv->cfg->mod_params->amsdu_size_8K)
 647                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 648         else
 649                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 650
 651         /* Stop Rx DMA */
 652         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 653
 654         /* Reset driver's Rx queue write index */
 655         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 656
 657         /* Tell device where to find RBD circular buffer in DRAM */
 658         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 659                            (u32)(rxq->bd_dma >> 8));
 660
 661         /* Tell device where in DRAM to update its Rx status */
 662         iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 663                            rxq->rb_stts_dma >> 4);
 664
 665         /* Enable Rx DMA
 666          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 667          *      the credit mechanism in 5000 HW RX FIFO
 668          * Direct rx interrupts to hosts
 669          * Rx buffer size 4 or 8k
 670          * RB timeout 0x10
 671          * 256 RBDs
 672          */
 673         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 674                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 675                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 676                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 677                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 678                            rb_size|
 679                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 680                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 681
 682         /* Set interrupt coalescing timer to default (2048 usecs) */
 683         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 684
 685         return 0;
 686 }
 687
 688 int iwlagn_hw_nic_init(struct iwl_priv *priv)
 689 {
 690         unsigned long flags;
 691         struct iwl_rx_queue *rxq = &priv->rxq;
 692         int ret;
 693
 694         /* nic_init */
 695         spin_lock_irqsave(&priv->lock, flags);
 696         priv->cfg->ops->lib->apm_ops.init(priv);
 697
 698         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 699         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 700
 701         spin_unlock_irqrestore(&priv->lock, flags);
 702
 703         ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
 704
 705         priv->cfg->ops->lib->apm_ops.config(priv);
 706
 707         /* Allocate the RX queue, or reset if it is already allocated */
 708         if (!rxq->bd) {
 709                 ret = iwl_rx_queue_alloc(priv);
 710                 if (ret) {
 711                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
 712                         return -ENOMEM;
 713                 }
 714         } else
 715                 iwlagn_rx_queue_reset(priv, rxq);
 716
 717         iwlagn_rx_replenish(priv);
 718
 719         iwlagn_rx_init(priv, rxq);
 720
 721         spin_lock_irqsave(&priv->lock, flags);
 722
 723         rxq->need_update = 1;
 724         iwl_rx_queue_update_write_ptr(priv, rxq);
 725
 726         spin_unlock_irqrestore(&priv->lock, flags);
 727
 728         /* Allocate or reset and init all Tx and Command queues */
 729         if (!priv->txq) {
 730                 ret = iwlagn_txq_ctx_alloc(priv);
 731                 if (ret)
 732                         return ret;
 733         } else
 734                 iwlagn_txq_ctx_reset(priv);
 735
 736         set_bit(STATUS_INIT, &priv->status);
 737
 738         return 0;
 739 }
 740
 741 /**
 742  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 743  */
 744 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
 745                                           dma_addr_t dma_addr)
 746 {
 747         return cpu_to_le32((u32)(dma_addr >> 8));
 748 }
 749
 750 /**
 751  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 752  *
 753  * If there are slots in the RX queue that need to be restocked,
 754  * and we have free pre-allocated buffers, fill the ranks as much
 755  * as we can, pulling from rx_free.
 756  *
 757  * This moves the 'write' index forward to catch up with 'processed', and
 758  * also updates the memory address in the firmware to reference the new
 759  * target buffer.
 760  */
 761 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
 762 {
 763         struct iwl_rx_queue *rxq = &priv->rxq;
 764         struct list_head *element;
 765         struct iwl_rx_mem_buffer *rxb;
 766         unsigned long flags;
 767
 768         spin_lock_irqsave(&rxq->lock, flags);
 769         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 770                 /* The overwritten rxb must be a used one */
 771                 rxb = rxq->queue[rxq->write];
 772                 BUG_ON(rxb && rxb->page);
 773
 774                 /* Get next free Rx buffer, remove from free list */
 775                 element = rxq->rx_free.next;
 776                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 777                 list_del(element);
 778
 779                 /* Point to Rx buffer via next RBD in circular buffer */
 780                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
 781                                                               rxb->page_dma);
 782                 rxq->queue[rxq->write] = rxb;
 783                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 784                 rxq->free_count--;
 785         }
 786         spin_unlock_irqrestore(&rxq->lock, flags);
 787         /* If the pre-allocated buffer pool is dropping low, schedule to
 788          * refill it */
 789         if (rxq->free_count <= RX_LOW_WATERMARK)
 790                 queue_work(priv->workqueue, &priv->rx_replenish);
 791
 792
 793         /* If we've added more space for the firmware to place data, tell it.
 794          * Increment device's write pointer in multiples of 8. */
 795         if (rxq->write_actual != (rxq->write & ~0x7)) {
 796                 spin_lock_irqsave(&rxq->lock, flags);
 797                 rxq->need_update = 1;
 798                 spin_unlock_irqrestore(&rxq->lock, flags);
 799                 iwl_rx_queue_update_write_ptr(priv, rxq);
 800         }
 801 }
 802
 803 /**
 804  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 805  *
 806  * When moving to rx_free an SKB is allocated for the slot.
 807  *
 808  * Also restock the Rx queue via iwl_rx_queue_restock.
 809  * This is called as a scheduled work item (except for during initialization)
 810  */
 811 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
 812 {
 813         struct iwl_rx_queue *rxq = &priv->rxq;
 814         struct list_head *element;
 815         struct iwl_rx_mem_buffer *rxb;
 816         struct page *page;
 817         unsigned long flags;
 818         gfp_t gfp_mask = priority;
 819
 820         while (1) {
 821                 spin_lock_irqsave(&rxq->lock, flags);
 822                 if (list_empty(&rxq->rx_used)) {
 823                         spin_unlock_irqrestore(&rxq->lock, flags);
 824                         return;
 825                 }
 826                 spin_unlock_irqrestore(&rxq->lock, flags);
 827
 828                 if (rxq->free_count > RX_LOW_WATERMARK)
 829                         gfp_mask |= __GFP_NOWARN;
 830
 831                 if (priv->hw_params.rx_page_order > 0)
 832                         gfp_mask |= __GFP_COMP;
 833
 834                 /* Alloc a new receive buffer */
 835                 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
 836                 if (!page) {
 837                         if (net_ratelimit())
 838                                 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
 839                                                "order: %d\n",
 840                                                priv->hw_params.rx_page_order);
 841
 842                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 843                             net_ratelimit())
 844                                 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
 845                                          priority == GFP_ATOMIC ?  "GFP_ATOMIC" : "GFP_KERNEL",
 846                                          rxq->free_count);
 847                         /* We don't reschedule replenish work here -- we will
 848                          * call the restock method and if it still needs
 849                          * more buffers it will schedule replenish */
 850                         return;
 851                 }
 852
 853                 spin_lock_irqsave(&rxq->lock, flags);
 854
 855                 if (list_empty(&rxq->rx_used)) {
 856                         spin_unlock_irqrestore(&rxq->lock, flags);
 857                         __free_pages(page, priv->hw_params.rx_page_order);
 858                         return;
 859                 }
 860                 element = rxq->rx_used.next;
 861                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 862                 list_del(element);
 863
 864                 spin_unlock_irqrestore(&rxq->lock, flags);
 865
 866                 BUG_ON(rxb->page);
 867                 rxb->page = page;
 868                 /* Get physical address of the RB */
 869                 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
 870                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 871                                 PCI_DMA_FROMDEVICE);
 872                 /* dma address must be no more than 36 bits */
 873                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 874                 /* and also 256 byte aligned! */
 875                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 876
 877                 spin_lock_irqsave(&rxq->lock, flags);
 878
 879                 list_add_tail(&rxb->list, &rxq->rx_free);
 880                 rxq->free_count++;
 881                 priv->alloc_rxb_page++;
 882
 883                 spin_unlock_irqrestore(&rxq->lock, flags);
 884         }
 885 }
 886
 887 void iwlagn_rx_replenish(struct iwl_priv *priv)
 888 {
 889         unsigned long flags;
 890
 891         iwlagn_rx_allocate(priv, GFP_KERNEL);
 892
 893         spin_lock_irqsave(&priv->lock, flags);
 894         iwlagn_rx_queue_restock(priv);
 895         spin_unlock_irqrestore(&priv->lock, flags);
 896 }
 897
 898 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
 899 {
 900         iwlagn_rx_allocate(priv, GFP_ATOMIC);
 901
 902         iwlagn_rx_queue_restock(priv);
 903 }
 904
 905 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
 906  * If an SKB has been detached, the POOL needs to have its SKB set to NULL
 907  * This free routine walks the list of POOL entries and if SKB is set to
 908  * non NULL it is unmapped and freed
 909  */
 910 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 911 {
 912         int i;
 913         for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
 914                 if (rxq->pool[i].page != NULL) {
 915                         pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
 916                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 917                                 PCI_DMA_FROMDEVICE);
 918                         __iwl_free_pages(priv, rxq->pool[i].page);
 919                         rxq->pool[i].page = NULL;
 920                 }
 921         }
 922
 923         dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
 924                           rxq->bd_dma);
 925         dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
 926                           rxq->rb_stts, rxq->rb_stts_dma);
 927         rxq->bd = NULL;
 928         rxq->rb_stts  = NULL;
 929 }
 930
 931 int iwlagn_rxq_stop(struct iwl_priv *priv)
 932 {
 933
 934         /* stop Rx DMA */
 935         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 936         iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
 937                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 938
 939         return 0;
 940 }
 941
 942 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
 943 {
 944         int idx = 0;
 945         int band_offset = 0;
 946
 947         /* HT rate format: mac80211 wants an MCS number, which is just LSB */
 948         if (rate_n_flags & RATE_MCS_HT_MSK) {
 949                 idx = (rate_n_flags & 0xff);
 950                 return idx;
 951         /* Legacy rate format, search for match in table */
 952         } else {
 953                 if (band == IEEE80211_BAND_5GHZ)
 954                         band_offset = IWL_FIRST_OFDM_RATE;
 955                 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
 956                         if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
 957                                 return idx - band_offset;
 958         }
 959
 960         return -1;
 961 }
 962
 963 /* Calc max signal level (dBm) among 3 possible receivers */
 964 static inline int iwlagn_calc_rssi(struct iwl_priv *priv,
 965                                 struct iwl_rx_phy_res *rx_resp)
 966 {
 967         return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
 968 }
 969
 970 static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
 971 {
 972         u32 decrypt_out = 0;
 973
 974         if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
 975                                         RX_RES_STATUS_STATION_FOUND)
 976                 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
 977                                 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
 978
 979         decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
 980
 981         /* packet was not encrypted */
 982         if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
 983                                         RX_RES_STATUS_SEC_TYPE_NONE)
 984                 return decrypt_out;
 985
 986         /* packet was encrypted with unknown alg */
 987         if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
 988                                         RX_RES_STATUS_SEC_TYPE_ERR)
 989                 return decrypt_out;
 990
 991         /* decryption was not done in HW */
 992         if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
 993                                         RX_MPDU_RES_STATUS_DEC_DONE_MSK)
 994                 return decrypt_out;
 995
 996         switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
 997
 998         case RX_RES_STATUS_SEC_TYPE_CCMP:
 999                 /* alg is CCM: check MIC only */
1000                 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
1001                         /* Bad MIC */
1002                         decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1003                 else
1004                         decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1005
1006                 break;
1007
1008         case RX_RES_STATUS_SEC_TYPE_TKIP:
1009                 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
1010                         /* Bad TTAK */
1011                         decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
1012                         break;
1013                 }
1014                 /* fall through if TTAK OK */
1015         default:
1016                 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
1017                         decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1018                 else
1019                         decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1020                 break;
1021         }
1022
1023         IWL_DEBUG_RX(priv, "decrypt_in:0x%x  decrypt_out = 0x%x\n",
1024                                         decrypt_in, decrypt_out);
1025
1026         return decrypt_out;
1027 }
1028
1029 static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv,
1030                                         struct ieee80211_hdr *hdr,
1031                                         u16 len,
1032                                         u32 ampdu_status,
1033                                         struct iwl_rx_mem_buffer *rxb,
1034                                         struct ieee80211_rx_status *stats)
1035 {
1036         struct sk_buff *skb;
1037         __le16 fc = hdr->frame_control;
1038
1039         /* We only process data packets if the interface is open */
1040         if (unlikely(!priv->is_open)) {
1041                 IWL_DEBUG_DROP_LIMIT(priv,
1042                     "Dropping packet while interface is not open.\n");
1043                 return;
1044         }
1045
1046         /* In case of HW accelerated crypto and bad decryption, drop */
1047         if (!priv->cfg->mod_params->sw_crypto &&
1048             iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
1049                 return;
1050
1051         skb = dev_alloc_skb(128);
1052         if (!skb) {
1053                 IWL_ERR(priv, "dev_alloc_skb failed\n");
1054                 return;
1055         }
1056
1057         skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
1058
1059         iwl_update_stats(priv, false, fc, len);
1060         memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
1061
1062         ieee80211_rx(priv->hw, skb);
1063         priv->alloc_rxb_page--;
1064         rxb->page = NULL;
1065 }
1066
1067 /* Called for REPLY_RX (legacy ABG frames), or
1068  * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
1069 void iwlagn_rx_reply_rx(struct iwl_priv *priv,
1070                                 struct iwl_rx_mem_buffer *rxb)
1071 {
1072         struct ieee80211_hdr *header;
1073         struct ieee80211_rx_status rx_status;
1074         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1075         struct iwl_rx_phy_res *phy_res;
1076         __le32 rx_pkt_status;
1077         struct iwl_rx_mpdu_res_start *amsdu;
1078         u32 len;
1079         u32 ampdu_status;
1080         u32 rate_n_flags;
1081
1082         /**
1083          * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
1084          *      REPLY_RX: physical layer info is in this buffer
1085          *      REPLY_RX_MPDU_CMD: physical layer info was sent in separate
1086          *              command and cached in priv->last_phy_res
1087          *
1088          * Here we set up local variables depending on which command is
1089          * received.
1090          */
1091         if (pkt->hdr.cmd == REPLY_RX) {
1092                 phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
1093                 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
1094                                 + phy_res->cfg_phy_cnt);
1095
1096                 len = le16_to_cpu(phy_res->byte_count);
1097                 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
1098                                 phy_res->cfg_phy_cnt + len);
1099                 ampdu_status = le32_to_cpu(rx_pkt_status);
1100         } else {
1101                 if (!priv->_agn.last_phy_res_valid) {
1102                         IWL_ERR(priv, "MPDU frame without cached PHY data\n");
1103                         return;
1104                 }
1105                 phy_res = &priv->_agn.last_phy_res;
1106                 amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw;
1107                 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
1108                 len = le16_to_cpu(amsdu->byte_count);
1109                 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
1110                 ampdu_status = iwlagn_translate_rx_status(priv,
1111                                 le32_to_cpu(rx_pkt_status));
1112         }
1113
1114         if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
1115                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
1116                                 phy_res->cfg_phy_cnt);
1117                 return;
1118         }
1119
1120         if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
1121             !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
1122                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
1123                                 le32_to_cpu(rx_pkt_status));
1124                 return;
1125         }
1126
1127         /* This will be used in several places later */
1128         rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
1129
1130         /* rx_status carries information about the packet to mac80211 */
1131         rx_status.mactime = le64_to_cpu(phy_res->timestamp);
1132         rx_status.freq =
1133                 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
1134         rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
1135                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1136         rx_status.rate_idx =
1137                 iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
1138         rx_status.flag = 0;
1139
1140         /* TSF isn't reliable. In order to allow smooth user experience,
1141          * this W/A doesn't propagate it to the mac80211 */
1142         /*rx_status.flag |= RX_FLAG_TSFT;*/
1143
1144         priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
1145
1146         /* Find max signal strength (dBm) among 3 antenna/receiver chains */
1147         rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
1148
1149         iwl_dbg_log_rx_data_frame(priv, len, header);
1150         IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
1151                 rx_status.signal, (unsigned long long)rx_status.mactime);
1152
1153         /*
1154          * "antenna number"
1155          *
1156          * It seems that the antenna field in the phy flags value
1157          * is actually a bit field. This is undefined by radiotap,
1158          * it wants an actual antenna number but I always get "7"
1159          * for most legacy frames I receive indicating that the
1160          * same frame was received on all three RX chains.
1161          *
1162          * I think this field should be removed in favor of a
1163          * new 802.11n radiotap field "RX chains" that is defined
1164          * as a bitmask.
1165          */
1166         rx_status.antenna =
1167                 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
1168                 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
1169
1170         /* set the preamble flag if appropriate */
1171         if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
1172                 rx_status.flag |= RX_FLAG_SHORTPRE;
1173
1174         /* Set up the HT phy flags */
1175         if (rate_n_flags & RATE_MCS_HT_MSK)
1176                 rx_status.flag |= RX_FLAG_HT;
1177         if (rate_n_flags & RATE_MCS_HT40_MSK)
1178                 rx_status.flag |= RX_FLAG_40MHZ;
1179         if (rate_n_flags & RATE_MCS_SGI_MSK)
1180                 rx_status.flag |= RX_FLAG_SHORT_GI;
1181
1182         iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status,
1183                                     rxb, &rx_status);
1184 }
1185
1186 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1187  * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1188 void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv,
1189                             struct iwl_rx_mem_buffer *rxb)
1190 {
1191         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1192         priv->_agn.last_phy_res_valid = true;
1193         memcpy(&priv->_agn.last_phy_res, pkt->u.raw,
1194                sizeof(struct iwl_rx_phy_res));
1195 }
1196
1197 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1198                                            struct ieee80211_vif *vif,
1199                                            enum ieee80211_band band,
1200                                            struct iwl_scan_channel *scan_ch)
1201 {
1202         const struct ieee80211_supported_band *sband;
1203         u16 passive_dwell = 0;
1204         u16 active_dwell = 0;
1205         int added = 0;
1206         u16 channel = 0;
1207
1208         sband = iwl_get_hw_mode(priv, band);
1209         if (!sband) {
1210                 IWL_ERR(priv, "invalid band\n");
1211                 return added;
1212         }
1213
1214         active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1215         passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1216
1217         if (passive_dwell <= active_dwell)
1218                 passive_dwell = active_dwell + 1;
1219
1220         channel = iwl_get_single_channel_number(priv, band);
1221         if (channel) {
1222                 scan_ch->channel = cpu_to_le16(channel);
1223                 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1224                 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1225                 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1226                 /* Set txpower levels to defaults */
1227                 scan_ch->dsp_atten = 110;
1228                 if (band == IEEE80211_BAND_5GHZ)
1229                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1230                 else
1231                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1232                 added++;
1233         } else
1234                 IWL_ERR(priv, "no valid channel found\n");
1235         return added;
1236 }
1237
1238 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1239                                      struct ieee80211_vif *vif,
1240                                      enum ieee80211_band band,
1241                                      u8 is_active, u8 n_probes,
1242                                      struct iwl_scan_channel *scan_ch)
1243 {
1244         struct ieee80211_channel *chan;
1245         const struct ieee80211_supported_band *sband;
1246         const struct iwl_channel_info *ch_info;
1247         u16 passive_dwell = 0;
1248         u16 active_dwell = 0;
1249         int added, i;
1250         u16 channel;
1251
1252         sband = iwl_get_hw_mode(priv, band);
1253         if (!sband)
1254                 return 0;
1255
1256         active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1257         passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1258
1259         if (passive_dwell <= active_dwell)
1260                 passive_dwell = active_dwell + 1;
1261
1262         for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1263                 chan = priv->scan_request->channels[i];
1264
1265                 if (chan->band != band)
1266                         continue;
1267
1268                 channel = chan->hw_value;
1269                 scan_ch->channel = cpu_to_le16(channel);
1270
1271                 ch_info = iwl_get_channel_info(priv, band, channel);
1272                 if (!is_channel_valid(ch_info)) {
1273                         IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1274                                         channel);
1275                         continue;
1276                 }
1277
1278                 if (!is_active || is_channel_passive(ch_info) ||
1279                     (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1280                         scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1281                 else
1282                         scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1283
1284                 if (n_probes)
1285                         scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1286
1287                 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1288                 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1289
1290                 /* Set txpower levels to defaults */
1291                 scan_ch->dsp_atten = 110;
1292
1293                 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1294                  * power level:
1295                  * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1296                  */
1297                 if (band == IEEE80211_BAND_5GHZ)
1298                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1299                 else
1300                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1301
1302                 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1303                                channel, le32_to_cpu(scan_ch->type),
1304                                (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1305                                 "ACTIVE" : "PASSIVE",
1306                                (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1307                                active_dwell : passive_dwell);
1308
1309                 scan_ch++;
1310                 added++;
1311         }
1312
1313         IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1314         return added;
1315 }
1316
1317 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1318 {
1319         struct iwl_host_cmd cmd = {
1320                 .id = REPLY_SCAN_CMD,
1321                 .len = sizeof(struct iwl_scan_cmd),
1322                 .flags = CMD_SIZE_HUGE,
1323         };
1324         struct iwl_scan_cmd *scan;
1325         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1326         u32 rate_flags = 0;
1327         u16 cmd_len;
1328         u16 rx_chain = 0;
1329         enum ieee80211_band band;
1330         u8 n_probes = 0;
1331         u8 rx_ant = priv->hw_params.valid_rx_ant;
1332         u8 rate;
1333         bool is_active = false;
1334         int  chan_mod;
1335         u8 active_chains;
1336         u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1337         int ret;
1338
1339         lockdep_assert_held(&priv->mutex);
1340
1341         if (vif)
1342                 ctx = iwl_rxon_ctx_from_vif(vif);
1343
1344         if (!priv->scan_cmd) {
1345                 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1346                                          IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1347                 if (!priv->scan_cmd) {
1348                         IWL_DEBUG_SCAN(priv,
1349                                        "fail to allocate memory for scan\n");
1350                         return -ENOMEM;
1351                 }
1352         }
1353         scan = priv->scan_cmd;
1354         memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1355
1356         scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1357         scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1358
1359         if (iwl_is_any_associated(priv)) {
1360                 u16 interval = 0;
1361                 u32 extra;
1362                 u32 suspend_time = 100;
1363                 u32 scan_suspend_time = 100;
1364                 unsigned long flags;
1365
1366                 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1367                 spin_lock_irqsave(&priv->lock, flags);
1368                 if (priv->is_internal_short_scan)
1369                         interval = 0;
1370                 else
1371                         interval = vif->bss_conf.beacon_int;
1372                 spin_unlock_irqrestore(&priv->lock, flags);
1373
1374                 scan->suspend_time = 0;
1375                 scan->max_out_time = cpu_to_le32(200 * 1024);
1376                 if (!interval)
1377                         interval = suspend_time;
1378
1379                 extra = (suspend_time / interval) << 22;
1380                 scan_suspend_time = (extra |
1381                     ((suspend_time % interval) * 1024));
1382                 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1383                 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1384                                scan_suspend_time, interval);
1385         }
1386
1387         if (priv->is_internal_short_scan) {
1388                 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1389         } else if (priv->scan_request->n_ssids) {
1390                 int i, p = 0;
1391                 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1392                 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1393                         /* always does wildcard anyway */
1394                         if (!priv->scan_request->ssids[i].ssid_len)
1395                                 continue;
1396                         scan->direct_scan[p].id = WLAN_EID_SSID;
1397                         scan->direct_scan[p].len =
1398                                 priv->scan_request->ssids[i].ssid_len;
1399                         memcpy(scan->direct_scan[p].ssid,
1400                                priv->scan_request->ssids[i].ssid,
1401                                priv->scan_request->ssids[i].ssid_len);
1402                         n_probes++;
1403                         p++;
1404                 }
1405                 is_active = true;
1406         } else
1407                 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1408
1409         scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1410         scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1411         scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1412
1413         switch (priv->scan_band) {
1414         case IEEE80211_BAND_2GHZ:
1415                 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1416                 chan_mod = le32_to_cpu(
1417                         priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1418                                                 RXON_FLG_CHANNEL_MODE_MSK)
1419                                        >> RXON_FLG_CHANNEL_MODE_POS;
1420                 if (chan_mod == CHANNEL_MODE_PURE_40) {
1421                         rate = IWL_RATE_6M_PLCP;
1422                 } else {
1423                         rate = IWL_RATE_1M_PLCP;
1424                         rate_flags = RATE_MCS_CCK_MSK;
1425                 }
1426                 /*
1427                  * Internal scans are passive, so we can indiscriminately set
1428                  * the BT ignore flag on 2.4 GHz since it applies to TX only.
1429                  */
1430                 if (priv->cfg->bt_params &&
1431                     priv->cfg->bt_params->advanced_bt_coexist)
1432                         scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1433                 scan->good_CRC_th = IWL_GOOD_CRC_TH_DISABLED;
1434                 break;
1435         case IEEE80211_BAND_5GHZ:
1436                 rate = IWL_RATE_6M_PLCP;
1437                 /*
1438                  * If active scanning is requested but a certain channel is
1439                  * marked passive, we can do active scanning if we detect
1440                  * transmissions.
1441                  *
1442                  * There is an issue with some firmware versions that triggers
1443                  * a sysassert on a "good CRC threshold" of zero (== disabled),
1444                  * on a radar channel even though this means that we should NOT
1445                  * send probes.
1446                  *
1447                  * The "good CRC threshold" is the number of frames that we
1448                  * need to receive during our dwell time on a channel before
1449                  * sending out probes -- setting this to a huge value will
1450                  * mean we never reach it, but at the same time work around
1451                  * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1452                  * here instead of IWL_GOOD_CRC_TH_DISABLED.
1453                  */
1454                 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1455                                                 IWL_GOOD_CRC_TH_NEVER;
1456                 break;
1457         default:
1458                 IWL_WARN(priv, "Invalid scan band\n");
1459                 return -EIO;
1460         }
1461
1462         band = priv->scan_band;
1463
1464         if (priv->cfg->scan_rx_antennas[band])
1465                 rx_ant = priv->cfg->scan_rx_antennas[band];
1466
1467         if (priv->cfg->scan_tx_antennas[band])
1468                 scan_tx_antennas = priv->cfg->scan_tx_antennas[band];
1469
1470         if (priv->cfg->bt_params &&
1471             priv->cfg->bt_params->advanced_bt_coexist &&
1472             priv->bt_full_concurrent) {
1473                 /* operated as 1x1 in full concurrency mode */
1474                 scan_tx_antennas = first_antenna(
1475                         priv->cfg->scan_tx_antennas[band]);
1476         }
1477
1478         priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1479                                                     scan_tx_antennas);
1480         rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1481         scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1482
1483         /* In power save mode use one chain, otherwise use all chains */
1484         if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1485                 /* rx_ant has been set to all valid chains previously */
1486                 active_chains = rx_ant &
1487                                 ((u8)(priv->chain_noise_data.active_chains));
1488                 if (!active_chains)
1489                         active_chains = rx_ant;
1490
1491                 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1492                                 priv->chain_noise_data.active_chains);
1493
1494                 rx_ant = first_antenna(active_chains);
1495         }
1496         if (priv->cfg->bt_params &&
1497             priv->cfg->bt_params->advanced_bt_coexist &&
1498             priv->bt_full_concurrent) {
1499                 /* operated as 1x1 in full concurrency mode */
1500                 rx_ant = first_antenna(rx_ant);
1501         }
1502
1503         /* MIMO is not used here, but value is required */
1504         rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1505         rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1506         rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1507         rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1508         scan->rx_chain = cpu_to_le16(rx_chain);
1509         if (!priv->is_internal_short_scan) {
1510                 cmd_len = iwl_fill_probe_req(priv,
1511                                         (struct ieee80211_mgmt *)scan->data,
1512                                         vif->addr,
1513                                         priv->scan_request->ie,
1514                                         priv->scan_request->ie_len,
1515                                         IWL_MAX_SCAN_SIZE - sizeof(*scan));
1516         } else {
1517                 /* use bcast addr, will not be transmitted but must be valid */
1518                 cmd_len = iwl_fill_probe_req(priv,
1519                                         (struct ieee80211_mgmt *)scan->data,
1520                                         iwl_bcast_addr, NULL, 0,
1521                                         IWL_MAX_SCAN_SIZE - sizeof(*scan));
1522
1523         }
1524         scan->tx_cmd.len = cpu_to_le16(cmd_len);
1525
1526         scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1527                                RXON_FILTER_BCON_AWARE_MSK);
1528
1529         if (priv->is_internal_short_scan) {
1530                 scan->channel_count =
1531                         iwl_get_single_channel_for_scan(priv, vif, band,
1532                                 (void *)&scan->data[le16_to_cpu(
1533                                 scan->tx_cmd.len)]);
1534         } else {
1535                 scan->channel_count =
1536                         iwl_get_channels_for_scan(priv, vif, band,
1537                                 is_active, n_probes,
1538                                 (void *)&scan->data[le16_to_cpu(
1539                                 scan->tx_cmd.len)]);
1540         }
1541         if (scan->channel_count == 0) {
1542                 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1543                 return -EIO;
1544         }
1545
1546         cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1547             scan->channel_count * sizeof(struct iwl_scan_channel);
1548         cmd.data = scan;
1549         scan->len = cpu_to_le16(cmd.len);
1550
1551         if (priv->cfg->ops->hcmd->set_pan_params) {
1552                 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1553                 if (ret)
1554                         return ret;
1555         }
1556
1557         set_bit(STATUS_SCAN_HW, &priv->status);
1558         ret = iwl_send_cmd_sync(priv, &cmd);
1559         if (ret) {
1560                 clear_bit(STATUS_SCAN_HW, &priv->status);
1561                 if (priv->cfg->ops->hcmd->set_pan_params)
1562                         priv->cfg->ops->hcmd->set_pan_params(priv);
1563         }
1564
1565         return ret;
1566 }
1567
1568 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1569                                struct ieee80211_vif *vif, bool add)
1570 {
1571         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1572
1573         if (add)
1574                 return iwl_add_bssid_station(priv, vif_priv->ctx,
1575                                              vif->bss_conf.bssid, true,
1576                                              &vif_priv->ibss_bssid_sta_id);
1577         return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1578                                   vif->bss_conf.bssid);
1579 }
1580
1581 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1582                             int sta_id, int tid, int freed)
1583 {
1584         lockdep_assert_held(&priv->sta_lock);
1585
1586         if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1587                 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1588         else {
1589                 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1590                         priv->stations[sta_id].tid[tid].tfds_in_queue,
1591                         freed);
1592                 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1593         }
1594 }
1595
1596 #define IWL_FLUSH_WAIT_MS       2000
1597
1598 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1599 {
1600         struct iwl_tx_queue *txq;
1601         struct iwl_queue *q;
1602         int cnt;
1603         unsigned long now = jiffies;
1604         int ret = 0;
1605
1606         /* waiting for all the tx frames complete might take a while */
1607         for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1608                 if (cnt == priv->cmd_queue)
1609                         continue;
1610                 txq = &priv->txq[cnt];
1611                 q = &txq->q;
1612                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1613                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1614                                 msleep(1);
1615
1616                 if (q->read_ptr != q->write_ptr) {
1617                         IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1618                         ret = -ETIMEDOUT;
1619                         break;
1620                 }
1621         }
1622         return ret;
1623 }
1624
1625 #define IWL_TX_QUEUE_MSK        0xfffff
1626
1627 /**
1628  * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1629  *
1630  * pre-requirements:
1631  *  1. acquire mutex before calling
1632  *  2. make sure rf is on and not in exit state
1633  */
1634 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1635 {
1636         struct iwl_txfifo_flush_cmd flush_cmd;
1637         struct iwl_host_cmd cmd = {
1638                 .id = REPLY_TXFIFO_FLUSH,
1639                 .len = sizeof(struct iwl_txfifo_flush_cmd),
1640                 .flags = CMD_SYNC,
1641                 .data = &flush_cmd,
1642         };
1643
1644         might_sleep();
1645
1646         memset(&flush_cmd, 0, sizeof(flush_cmd));
1647         flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1648                                  IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1649         if (priv->cfg->sku & IWL_SKU_N)
1650                 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1651
1652         IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1653                        flush_cmd.fifo_control);
1654         flush_cmd.flush_control = cpu_to_le16(flush_control);
1655
1656         return iwl_send_cmd(priv, &cmd);
1657 }
1658
1659 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1660 {
1661         mutex_lock(&priv->mutex);
1662         ieee80211_stop_queues(priv->hw);
1663         if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1664                 IWL_ERR(priv, "flush request fail\n");
1665                 goto done;
1666         }
1667         IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1668         iwlagn_wait_tx_queue_empty(priv);
1669 done:
1670         ieee80211_wake_queues(priv->hw);
1671         mutex_unlock(&priv->mutex);
1672 }
1673
1674 /*
1675  * BT coex
1676  */
1677 /*
1678  * Macros to access the lookup table.
1679  *
1680  * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1681 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1682  *
1683  * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1684  *
1685  * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1686  * one after another in 32-bit registers, and "registers" 0 through 7 contain
1687  * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1688  *
1689  * These macros encode that format.
1690  */
1691 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1692                   wifi_txrx, wifi_sh_ant_req) \
1693         (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1694         (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1695
1696 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1697         lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1698 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1699                                  wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1700         (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1701                                    bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1702                                    wifi_sh_ant_req))))
1703 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1704                                 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1705         LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1706                                bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1707                                wifi_sh_ant_req))
1708 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1709                                   wifi_req, wifi_prio, wifi_txrx, \
1710                                   wifi_sh_ant_req) \
1711         LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1712                                bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1713                                wifi_sh_ant_req))
1714
1715 #define LUT_WLAN_KILL_OP(lut, op, val) \
1716         lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1717 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1718                            wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1719         (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1720                              wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1721 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1722                           wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1723         LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1724                          wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1725 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1726                             wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1727         LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1728                          wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1729
1730 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1731         lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1732 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1733                             wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1734         (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1735                               wifi_req, wifi_prio, wifi_txrx, \
1736                               wifi_sh_ant_req))))
1737 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1738                            wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1739         LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1740                           wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1741 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1742                              wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1743         LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1744                           wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1745
1746 static const __le32 iwlagn_def_3w_lookup[12] = {
1747         cpu_to_le32(0xaaaaaaaa),
1748         cpu_to_le32(0xaaaaaaaa),
1749         cpu_to_le32(0xaeaaaaaa),
1750         cpu_to_le32(0xaaaaaaaa),
1751         cpu_to_le32(0xcc00ff28),
1752         cpu_to_le32(0x0000aaaa),
1753         cpu_to_le32(0xcc00aaaa),
1754         cpu_to_le32(0x0000aaaa),
1755         cpu_to_le32(0xc0004000),
1756         cpu_to_le32(0x00004000),
1757         cpu_to_le32(0xf0005000),
1758         cpu_to_le32(0xf0004000),
1759 };
1760
1761 static const __le32 iwlagn_concurrent_lookup[12] = {
1762         cpu_to_le32(0xaaaaaaaa),
1763         cpu_to_le32(0xaaaaaaaa),
1764         cpu_to_le32(0xaaaaaaaa),
1765         cpu_to_le32(0xaaaaaaaa),
1766         cpu_to_le32(0xaaaaaaaa),
1767         cpu_to_le32(0xaaaaaaaa),
1768         cpu_to_le32(0xaaaaaaaa),
1769         cpu_to_le32(0xaaaaaaaa),
1770         cpu_to_le32(0x00000000),
1771         cpu_to_le32(0x00000000),
1772         cpu_to_le32(0x00000000),
1773         cpu_to_le32(0x00000000),
1774 };
1775
1776 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1777 {
1778         struct iwlagn_bt_cmd bt_cmd = {
1779                 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1780                 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1781                 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1782                 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1783         };
1784
1785         BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1786                         sizeof(bt_cmd.bt3_lookup_table));
1787
1788         if (priv->cfg->bt_params)
1789                 bt_cmd.prio_boost = priv->cfg->bt_params->bt_prio_boost;
1790         else
1791                 bt_cmd.prio_boost = 0;
1792         bt_cmd.kill_ack_mask = priv->kill_ack_mask;
1793         bt_cmd.kill_cts_mask = priv->kill_cts_mask;
1794         bt_cmd.valid = priv->bt_valid;
1795         bt_cmd.tx_prio_boost = 0;
1796         bt_cmd.rx_prio_boost = 0;
1797
1798         /*
1799          * Configure BT coex mode to "no coexistence" when the
1800          * user disabled BT coexistence, we have no interface
1801          * (might be in monitor mode), or the interface is in
1802          * IBSS mode (no proper uCode support for coex then).
1803          */
1804         if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1805                 bt_cmd.flags = 0;
1806         } else {
1807                 bt_cmd.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1808                                         IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1809                 if (priv->bt_ch_announce)
1810                         bt_cmd.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1811                 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", bt_cmd.flags);
1812         }
1813         if (priv->bt_full_concurrent)
1814                 memcpy(bt_cmd.bt3_lookup_table, iwlagn_concurrent_lookup,
1815                         sizeof(iwlagn_concurrent_lookup));
1816         else
1817                 memcpy(bt_cmd.bt3_lookup_table, iwlagn_def_3w_lookup,
1818                         sizeof(iwlagn_def_3w_lookup));
1819
1820         IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1821                        bt_cmd.flags ? "active" : "disabled",
1822                        priv->bt_full_concurrent ?
1823                        "full concurrency" : "3-wire");
1824
1825         if (iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, sizeof(bt_cmd), &bt_cmd))
1826                 IWL_ERR(priv, "failed to send BT Coex Config\n");
1827
1828         /*
1829          * When we are doing a restart, need to also reconfigure BT
1830          * SCO to the device. If not doing a restart, bt_sco_active
1831          * will always be false, so there's no need to have an extra
1832          * variable to check for it.
1833          */
1834         if (priv->bt_sco_active) {
1835                 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
1836
1837                 if (priv->bt_sco_active)
1838                         sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
1839                 if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_SCO,
1840                                      sizeof(sco_cmd), &sco_cmd))
1841                         IWL_ERR(priv, "failed to send BT SCO command\n");
1842         }
1843 }
1844
1845 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1846 {
1847         struct iwl_priv *priv =
1848                 container_of(work, struct iwl_priv, bt_traffic_change_work);
1849         struct iwl_rxon_context *ctx;
1850         int smps_request = -1;
1851
1852         IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1853                        priv->bt_traffic_load);
1854
1855         switch (priv->bt_traffic_load) {
1856         case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1857                 smps_request = IEEE80211_SMPS_AUTOMATIC;
1858                 break;
1859         case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1860                 smps_request = IEEE80211_SMPS_DYNAMIC;
1861                 break;
1862         case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1863         case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1864                 smps_request = IEEE80211_SMPS_STATIC;
1865                 break;
1866         default:
1867                 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1868                         priv->bt_traffic_load);
1869                 break;
1870         }
1871
1872         mutex_lock(&priv->mutex);
1873
1874         if (priv->cfg->ops->lib->update_chain_flags)
1875                 priv->cfg->ops->lib->update_chain_flags(priv);
1876
1877         if (smps_request != -1) {
1878                 for_each_context(priv, ctx) {
1879                         if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1880                                 ieee80211_request_smps(ctx->vif, smps_request);
1881                 }
1882         }
1883
1884         mutex_unlock(&priv->mutex);
1885 }
1886
1887 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1888                                 struct iwl_bt_uart_msg *uart_msg)
1889 {
1890         IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1891                         "Update Req = 0x%X",
1892                 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1893                         BT_UART_MSG_FRAME1MSGTYPE_POS,
1894                 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1895                         BT_UART_MSG_FRAME1SSN_POS,
1896                 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1897                         BT_UART_MSG_FRAME1UPDATEREQ_POS);
1898
1899         IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1900                         "Chl_SeqN = 0x%X, In band = 0x%X",
1901                 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1902                         BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1903                 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1904                         BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1905                 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1906                         BT_UART_MSG_FRAME2CHLSEQN_POS,
1907                 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1908                         BT_UART_MSG_FRAME2INBAND_POS);
1909
1910         IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1911                         "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1912                 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1913                         BT_UART_MSG_FRAME3SCOESCO_POS,
1914                 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1915                         BT_UART_MSG_FRAME3SNIFF_POS,
1916                 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1917                         BT_UART_MSG_FRAME3A2DP_POS,
1918                 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1919                         BT_UART_MSG_FRAME3ACL_POS,
1920                 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1921                         BT_UART_MSG_FRAME3MASTER_POS,
1922                 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1923                         BT_UART_MSG_FRAME3OBEX_POS);
1924
1925         IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1926                 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1927                         BT_UART_MSG_FRAME4IDLEDURATION_POS);
1928
1929         IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1930                         "eSCO Retransmissions = 0x%X",
1931                 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1932                         BT_UART_MSG_FRAME5TXACTIVITY_POS,
1933                 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1934                         BT_UART_MSG_FRAME5RXACTIVITY_POS,
1935                 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1936                         BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1937
1938         IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1939                 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1940                         BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1941                 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1942                         BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1943
1944         IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Inquiry/Page SR Mode = "
1945                         "0x%X, Connectable = 0x%X",
1946                 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1947                         BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1948                 (BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_MSK & uart_msg->frame7) >>
1949                         BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_POS,
1950                 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1951                         BT_UART_MSG_FRAME7CONNECTABLE_POS);
1952 }
1953
1954 static void iwlagn_set_kill_ack_msk(struct iwl_priv *priv,
1955                                      struct iwl_bt_uart_msg *uart_msg)
1956 {
1957         u8 kill_ack_msk;
1958         __le32 bt_kill_ack_msg[2] = {
1959                         cpu_to_le32(0xFFFFFFF), cpu_to_le32(0xFFFFFC00) };
1960
1961         kill_ack_msk = (((BT_UART_MSG_FRAME3A2DP_MSK |
1962                         BT_UART_MSG_FRAME3SNIFF_MSK |
1963                         BT_UART_MSG_FRAME3SCOESCO_MSK) &
1964                         uart_msg->frame3) == 0) ? 1 : 0;
1965         if (priv->kill_ack_mask != bt_kill_ack_msg[kill_ack_msk]) {
1966                 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
1967                 priv->kill_ack_mask = bt_kill_ack_msg[kill_ack_msk];
1968                 /* schedule to send runtime bt_config */
1969                 queue_work(priv->workqueue, &priv->bt_runtime_config);
1970         }
1971
1972 }
1973
1974 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
1975                                              struct iwl_rx_mem_buffer *rxb)
1976 {
1977         unsigned long flags;
1978         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1979         struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
1980         struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
1981         struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
1982         u8 last_traffic_load;
1983
1984         IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
1985         IWL_DEBUG_NOTIF(priv, "    status: %d\n", coex->bt_status);
1986         IWL_DEBUG_NOTIF(priv, "    traffic load: %d\n", coex->bt_traffic_load);
1987         IWL_DEBUG_NOTIF(priv, "    CI compliance: %d\n",
1988                         coex->bt_ci_compliance);
1989         iwlagn_print_uartmsg(priv, uart_msg);
1990
1991         last_traffic_load = priv->notif_bt_traffic_load;
1992         priv->notif_bt_traffic_load = coex->bt_traffic_load;
1993         if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
1994                 if (priv->bt_status != coex->bt_status ||
1995                     last_traffic_load != coex->bt_traffic_load) {
1996                         if (coex->bt_status) {
1997                                 /* BT on */
1998                                 if (!priv->bt_ch_announce)
1999                                         priv->bt_traffic_load =
2000                                                 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
2001                                 else
2002                                         priv->bt_traffic_load =
2003                                                 coex->bt_traffic_load;
2004                         } else {
2005                                 /* BT off */
2006                                 priv->bt_traffic_load =
2007                                         IWL_BT_COEX_TRAFFIC_LOAD_NONE;
2008                         }
2009                         priv->bt_status = coex->bt_status;
2010                         queue_work(priv->workqueue,
2011                                    &priv->bt_traffic_change_work);
2012                 }
2013                 if (priv->bt_sco_active !=
2014                     (uart_msg->frame3 & BT_UART_MSG_FRAME3SCOESCO_MSK)) {
2015                         priv->bt_sco_active = uart_msg->frame3 &
2016                                 BT_UART_MSG_FRAME3SCOESCO_MSK;
2017                         if (priv->bt_sco_active)
2018                                 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
2019                         iwl_send_cmd_pdu_async(priv, REPLY_BT_COEX_SCO,
2020                                        sizeof(sco_cmd), &sco_cmd, NULL);
2021                 }
2022         }
2023
2024         iwlagn_set_kill_ack_msk(priv, uart_msg);
2025
2026         /* FIXME: based on notification, adjust the prio_boost */
2027
2028         spin_lock_irqsave(&priv->lock, flags);
2029         priv->bt_ci_compliance = coex->bt_ci_compliance;
2030         spin_unlock_irqrestore(&priv->lock, flags);
2031 }
2032
2033 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
2034 {
2035         iwlagn_rx_handler_setup(priv);
2036         priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
2037                 iwlagn_bt_coex_profile_notif;
2038 }
2039
2040 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
2041 {
2042         iwlagn_setup_deferred_work(priv);
2043
2044         INIT_WORK(&priv->bt_traffic_change_work,
2045                   iwlagn_bt_traffic_change_work);
2046 }
2047
2048 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
2049 {
2050         cancel_work_sync(&priv->bt_traffic_change_work);
2051 }