drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/sched.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <net/mac80211.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39
  40 #include "iwl-eeprom.h"
  41 #include "iwl-dev.h"
  42 #include "iwl-core.h"
  43 #include "iwl-io.h"
  44 #include "iwl-sta.h"
  45 #include "iwl-helpers.h"
  46 #include "iwl-agn-led.h"
  47 #include "iwl-5000-hw.h"
  48 #include "iwl-6000-hw.h"
  49
  50 /* Highest firmware API version supported */
  51 #define IWL5000_UCODE_API_MAX 2
  52 #define IWL5150_UCODE_API_MAX 2
  53
  54 /* Lowest firmware API version supported */
  55 #define IWL5000_UCODE_API_MIN 1
  56 #define IWL5150_UCODE_API_MIN 1
  57
  58 #define IWL5000_FW_PRE "iwlwifi-5000-"
  59 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
  60 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
  61
  62 #define IWL5150_FW_PRE "iwlwifi-5150-"
  63 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
  64 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
  65
  66 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  67         IWL_TX_FIFO_AC3,
  68         IWL_TX_FIFO_AC2,
  69         IWL_TX_FIFO_AC1,
  70         IWL_TX_FIFO_AC0,
  71         IWL50_CMD_FIFO_NUM,
  72         IWL_TX_FIFO_HCCA_1,
  73         IWL_TX_FIFO_HCCA_2
  74 };
  75
  76 /* NIC configuration for 5000 series */
  77 void iwl5000_nic_config(struct iwl_priv *priv)
  78 {
  79         unsigned long flags;
  80         u16 radio_cfg;
  81
  82         spin_lock_irqsave(&priv->lock, flags);
  83
  84         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
  85
  86         /* write radio config values to register */
  87         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
  88                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  89                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
  90                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
  91                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
  92
  93         /* set CSR_HW_CONFIG_REG for uCode use */
  94         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  95                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  96                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
  97
  98         /* W/A : NIC is stuck in a reset state after Early PCIe power off
  99          * (PCIe power is lost before PERST# is asserted),
 100          * causing ME FW to lose ownership and not being able to obtain it back.
 101          */
 102         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 103                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
 104                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 105
 106
 107         spin_unlock_irqrestore(&priv->lock, flags);
 108 }
 109
 110
 111 /*
 112  * EEPROM
 113  */
 114 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 115 {
 116         u16 offset = 0;
 117
 118         if ((address & INDIRECT_ADDRESS) == 0)
 119                 return address;
 120
 121         switch (address & INDIRECT_TYPE_MSK) {
 122         case INDIRECT_HOST:
 123                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 124                 break;
 125         case INDIRECT_GENERAL:
 126                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 127                 break;
 128         case INDIRECT_REGULATORY:
 129                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 130                 break;
 131         case INDIRECT_CALIBRATION:
 132                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 133                 break;
 134         case INDIRECT_PROCESS_ADJST:
 135                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 136                 break;
 137         case INDIRECT_OTHERS:
 138                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 139                 break;
 140         default:
 141                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
 142                 address & INDIRECT_TYPE_MSK);
 143                 break;
 144         }
 145
 146         /* translate the offset from words to byte */
 147         return (address & ADDRESS_MSK) + (offset << 1);
 148 }
 149
 150 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
 151 {
 152         struct iwl_eeprom_calib_hdr {
 153                 u8 version;
 154                 u8 pa_type;
 155                 u16 voltage;
 156         } *hdr;
 157
 158         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 159                                                         EEPROM_5000_CALIB_ALL);
 160         return hdr->version;
 161
 162 }
 163
 164 static void iwl5000_gain_computation(struct iwl_priv *priv,
 165                 u32 average_noise[NUM_RX_CHAINS],
 166                 u16 min_average_noise_antenna_i,
 167                 u32 min_average_noise,
 168                 u8 default_chain)
 169 {
 170         int i;
 171         s32 delta_g;
 172         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 173
 174         /*
 175          * Find Gain Code for the chains based on "default chain"
 176          */
 177         for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
 178                 if ((data->disconn_array[i])) {
 179                         data->delta_gain_code[i] = 0;
 180                         continue;
 181                 }
 182                 delta_g = (1000 * ((s32)average_noise[default_chain] -
 183                         (s32)average_noise[i])) / 1500;
 184                 /* bound gain by 2 bits value max, 3rd bit is sign */
 185                 data->delta_gain_code[i] =
 186                         min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 187
 188                 if (delta_g < 0)
 189                         /* set negative sign */
 190                         data->delta_gain_code[i] |= (1 << 2);
 191         }
 192
 193         IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d  ANT_C = %d\n",
 194                         data->delta_gain_code[1], data->delta_gain_code[2]);
 195
 196         if (!data->radio_write) {
 197                 struct iwl_calib_chain_noise_gain_cmd cmd;
 198
 199                 memset(&cmd, 0, sizeof(cmd));
 200
 201                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 202                 cmd.hdr.first_group = 0;
 203                 cmd.hdr.groups_num = 1;
 204                 cmd.hdr.data_valid = 1;
 205                 cmd.delta_gain_1 = data->delta_gain_code[1];
 206                 cmd.delta_gain_2 = data->delta_gain_code[2];
 207                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 208                         sizeof(cmd), &cmd, NULL);
 209
 210                 data->radio_write = 1;
 211                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 212         }
 213
 214         data->chain_noise_a = 0;
 215         data->chain_noise_b = 0;
 216         data->chain_noise_c = 0;
 217         data->chain_signal_a = 0;
 218         data->chain_signal_b = 0;
 219         data->chain_signal_c = 0;
 220         data->beacon_count = 0;
 221 }
 222
 223 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 224 {
 225         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 226         int ret;
 227
 228         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 229                 struct iwl_calib_chain_noise_reset_cmd cmd;
 230                 memset(&cmd, 0, sizeof(cmd));
 231
 232                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 233                 cmd.hdr.first_group = 0;
 234                 cmd.hdr.groups_num = 1;
 235                 cmd.hdr.data_valid = 1;
 236                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 237                                         sizeof(cmd), &cmd);
 238                 if (ret)
 239                         IWL_ERR(priv,
 240                                 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
 241                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 242                 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
 243         }
 244 }
 245
 246 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
 247                         __le32 *tx_flags)
 248 {
 249         if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
 250             (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
 251                 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
 252         else
 253                 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
 254 }
 255
 256 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 257         .min_nrg_cck = 95,
 258         .max_nrg_cck = 0, /* not used, set to 0 */
 259         .auto_corr_min_ofdm = 90,
 260         .auto_corr_min_ofdm_mrc = 170,
 261         .auto_corr_min_ofdm_x1 = 120,
 262         .auto_corr_min_ofdm_mrc_x1 = 240,
 263
 264         .auto_corr_max_ofdm = 120,
 265         .auto_corr_max_ofdm_mrc = 210,
 266         .auto_corr_max_ofdm_x1 = 155,
 267         .auto_corr_max_ofdm_mrc_x1 = 290,
 268
 269         .auto_corr_min_cck = 125,
 270         .auto_corr_max_cck = 200,
 271         .auto_corr_min_cck_mrc = 170,
 272         .auto_corr_max_cck_mrc = 400,
 273         .nrg_th_cck = 95,
 274         .nrg_th_ofdm = 95,
 275
 276         .barker_corr_th_min = 190,
 277         .barker_corr_th_min_mrc = 390,
 278         .nrg_th_cca = 62,
 279 };
 280
 281 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
 282         .min_nrg_cck = 95,
 283         .max_nrg_cck = 0, /* not used, set to 0 */
 284         .auto_corr_min_ofdm = 90,
 285         .auto_corr_min_ofdm_mrc = 170,
 286         .auto_corr_min_ofdm_x1 = 105,
 287         .auto_corr_min_ofdm_mrc_x1 = 220,
 288
 289         .auto_corr_max_ofdm = 120,
 290         .auto_corr_max_ofdm_mrc = 210,
 291         /* max = min for performance bug in 5150 DSP */
 292         .auto_corr_max_ofdm_x1 = 105,
 293         .auto_corr_max_ofdm_mrc_x1 = 220,
 294
 295         .auto_corr_min_cck = 125,
 296         .auto_corr_max_cck = 200,
 297         .auto_corr_min_cck_mrc = 170,
 298         .auto_corr_max_cck_mrc = 400,
 299         .nrg_th_cck = 95,
 300         .nrg_th_ofdm = 95,
 301
 302         .barker_corr_th_min = 190,
 303         .barker_corr_th_min_mrc = 390,
 304         .nrg_th_cca = 62,
 305 };
 306
 307 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 308                                            size_t offset)
 309 {
 310         u32 address = eeprom_indirect_address(priv, offset);
 311         BUG_ON(address >= priv->cfg->eeprom_size);
 312         return &priv->eeprom[address];
 313 }
 314
 315 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
 316 {
 317         const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
 318         s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
 319                         iwl_temp_calib_to_offset(priv);
 320
 321         priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
 322 }
 323
 324 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
 325 {
 326         /* want Celsius */
 327         priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
 328 }
 329
 330 /*
 331  *  Calibration
 332  */
 333 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
 334 {
 335         struct iwl_calib_xtal_freq_cmd cmd;
 336         u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
 337
 338         cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
 339         cmd.hdr.first_group = 0;
 340         cmd.hdr.groups_num = 1;
 341         cmd.hdr.data_valid = 1;
 342         cmd.cap_pin1 = (u8)xtal_calib[0];
 343         cmd.cap_pin2 = (u8)xtal_calib[1];
 344         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
 345                              (u8 *)&cmd, sizeof(cmd));
 346 }
 347
 348 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
 349 {
 350         struct iwl_calib_cfg_cmd calib_cfg_cmd;
 351         struct iwl_host_cmd cmd = {
 352                 .id = CALIBRATION_CFG_CMD,
 353                 .len = sizeof(struct iwl_calib_cfg_cmd),
 354                 .data = &calib_cfg_cmd,
 355         };
 356
 357         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 358         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 359         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 360         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 361         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 362
 363         return iwl_send_cmd(priv, &cmd);
 364 }
 365
 366 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
 367                              struct iwl_rx_mem_buffer *rxb)
 368 {
 369         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 370         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
 371         int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 372         int index;
 373
 374         /* reduce the size of the length field itself */
 375         len -= 4;
 376
 377         /* Define the order in which the results will be sent to the runtime
 378          * uCode. iwl_send_calib_results sends them in a row according to their
 379          * index. We sort them here */
 380         switch (hdr->op_code) {
 381         case IWL_PHY_CALIBRATE_DC_CMD:
 382                 index = IWL_CALIB_DC;
 383                 break;
 384         case IWL_PHY_CALIBRATE_LO_CMD:
 385                 index = IWL_CALIB_LO;
 386                 break;
 387         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
 388                 index = IWL_CALIB_TX_IQ;
 389                 break;
 390         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 391                 index = IWL_CALIB_TX_IQ_PERD;
 392                 break;
 393         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
 394                 index = IWL_CALIB_BASE_BAND;
 395                 break;
 396         default:
 397                 IWL_ERR(priv, "Unknown calibration notification %d\n",
 398                           hdr->op_code);
 399                 return;
 400         }
 401         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
 402 }
 403
 404 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
 405                                struct iwl_rx_mem_buffer *rxb)
 406 {
 407         IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
 408         queue_work(priv->workqueue, &priv->restart);
 409 }
 410
 411 /*
 412  * ucode
 413  */
 414 static int iwl5000_load_section(struct iwl_priv *priv,
 415                                 struct fw_desc *image,
 416                                 u32 dst_addr)
 417 {
 418         dma_addr_t phy_addr = image->p_addr;
 419         u32 byte_cnt = image->len;
 420
 421         iwl_write_direct32(priv,
 422                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 423                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 424
 425         iwl_write_direct32(priv,
 426                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 427
 428         iwl_write_direct32(priv,
 429                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 430                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 431
 432         iwl_write_direct32(priv,
 433                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 434                 (iwl_get_dma_hi_addr(phy_addr)
 435                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 436
 437         iwl_write_direct32(priv,
 438                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 439                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 440                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 441                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 442
 443         iwl_write_direct32(priv,
 444                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 445                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 446                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 447                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 448
 449         return 0;
 450 }
 451
 452 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 453                 struct fw_desc *inst_image,
 454                 struct fw_desc *data_image)
 455 {
 456         int ret = 0;
 457
 458         ret = iwl5000_load_section(priv, inst_image,
 459                                    IWL50_RTC_INST_LOWER_BOUND);
 460         if (ret)
 461                 return ret;
 462
 463         IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
 464         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 465                                         priv->ucode_write_complete, 5 * HZ);
 466         if (ret == -ERESTARTSYS) {
 467                 IWL_ERR(priv, "Could not load the INST uCode section due "
 468                         "to interrupt\n");
 469                 return ret;
 470         }
 471         if (!ret) {
 472                 IWL_ERR(priv, "Could not load the INST uCode section\n");
 473                 return -ETIMEDOUT;
 474         }
 475
 476         priv->ucode_write_complete = 0;
 477
 478         ret = iwl5000_load_section(
 479                 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
 480         if (ret)
 481                 return ret;
 482
 483         IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
 484
 485         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 486                                 priv->ucode_write_complete, 5 * HZ);
 487         if (ret == -ERESTARTSYS) {
 488                 IWL_ERR(priv, "Could not load the INST uCode section due "
 489                         "to interrupt\n");
 490                 return ret;
 491         } else if (!ret) {
 492                 IWL_ERR(priv, "Could not load the DATA uCode section\n");
 493                 return -ETIMEDOUT;
 494         } else
 495                 ret = 0;
 496
 497         priv->ucode_write_complete = 0;
 498
 499         return ret;
 500 }
 501
 502 int iwl5000_load_ucode(struct iwl_priv *priv)
 503 {
 504         int ret = 0;
 505
 506         /* check whether init ucode should be loaded, or rather runtime ucode */
 507         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 508                 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
 509                 ret = iwl5000_load_given_ucode(priv,
 510                         &priv->ucode_init, &priv->ucode_init_data);
 511                 if (!ret) {
 512                         IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
 513                         priv->ucode_type = UCODE_INIT;
 514                 }
 515         } else {
 516                 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
 517                         "Loading runtime ucode...\n");
 518                 ret = iwl5000_load_given_ucode(priv,
 519                         &priv->ucode_code, &priv->ucode_data);
 520                 if (!ret) {
 521                         IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
 522                         priv->ucode_type = UCODE_RT;
 523                 }
 524         }
 525
 526         return ret;
 527 }
 528
 529 void iwl5000_init_alive_start(struct iwl_priv *priv)
 530 {
 531         int ret = 0;
 532
 533         /* Check alive response for "valid" sign from uCode */
 534         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 535                 /* We had an error bringing up the hardware, so take it
 536                  * all the way back down so we can try again */
 537                 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
 538                 goto restart;
 539         }
 540
 541         /* initialize uCode was loaded... verify inst image.
 542          * This is a paranoid check, because we would not have gotten the
 543          * "initialize" alive if code weren't properly loaded.  */
 544         if (iwl_verify_ucode(priv)) {
 545                 /* Runtime instruction load was bad;
 546                  * take it all the way back down so we can try again */
 547                 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
 548                 goto restart;
 549         }
 550
 551         iwl_clear_stations_table(priv);
 552         ret = priv->cfg->ops->lib->alive_notify(priv);
 553         if (ret) {
 554                 IWL_WARN(priv,
 555                         "Could not complete ALIVE transition: %d\n", ret);
 556                 goto restart;
 557         }
 558
 559         iwl5000_send_calib_cfg(priv);
 560         return;
 561
 562 restart:
 563         /* real restart (first load init_ucode) */
 564         queue_work(priv->workqueue, &priv->restart);
 565 }
 566
 567 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 568                                 int txq_id, u32 index)
 569 {
 570         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 571                         (index & 0xff) | (txq_id << 8));
 572         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 573 }
 574
 575 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 576                                         struct iwl_tx_queue *txq,
 577                                         int tx_fifo_id, int scd_retry)
 578 {
 579         int txq_id = txq->q.id;
 580         int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
 581
 582         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 583                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 584                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 585                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 586                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 587
 588         txq->sched_retry = scd_retry;
 589
 590         IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
 591                        active ? "Activate" : "Deactivate",
 592                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 593 }
 594
 595 int iwl5000_alive_notify(struct iwl_priv *priv)
 596 {
 597         u32 a;
 598         unsigned long flags;
 599         int i, chan;
 600         u32 reg_val;
 601
 602         spin_lock_irqsave(&priv->lock, flags);
 603
 604         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 605         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 606         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 607                 a += 4)
 608                 iwl_write_targ_mem(priv, a, 0);
 609         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 610                 a += 4)
 611                 iwl_write_targ_mem(priv, a, 0);
 612         for (; a < priv->scd_base_addr +
 613                IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
 614                 iwl_write_targ_mem(priv, a, 0);
 615
 616         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 617                        priv->scd_bc_tbls.dma >> 10);
 618
 619         /* Enable DMA channel */
 620         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
 621                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 622                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 623                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 624
 625         /* Update FH chicken bits */
 626         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 627         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 628                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 629
 630         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 631                 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
 632         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 633
 634         /* initiate the queues */
 635         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 636                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 637                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 638                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 639                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 640                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 641                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 642                                 sizeof(u32),
 643                                 ((SCD_WIN_SIZE <<
 644                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 645                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 646                                 ((SCD_FRAME_LIMIT <<
 647                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 648                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 649         }
 650
 651         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 652                         IWL_MASK(0, priv->hw_params.max_txq_num));
 653
 654         /* Activate all Tx DMA/FIFO channels */
 655         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
 656
 657         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 658
 659         /* map qos queues to fifos one-to-one */
 660         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 661                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 662                 iwl_txq_ctx_activate(priv, i);
 663                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 664         }
 665
 666         /*
 667          * TODO - need to initialize these queues and map them to FIFOs
 668          * in the loop above, not only mark them as active. We do this
 669          * because we want the first aggregation queue to be queue #10,
 670          * but do not use 8 or 9 otherwise yet.
 671          */
 672         iwl_txq_ctx_activate(priv, 7);
 673         iwl_txq_ctx_activate(priv, 8);
 674         iwl_txq_ctx_activate(priv, 9);
 675
 676         spin_unlock_irqrestore(&priv->lock, flags);
 677
 678
 679         iwl_send_wimax_coex(priv);
 680
 681         iwl5000_set_Xtal_calib(priv);
 682         iwl_send_calib_results(priv);
 683
 684         return 0;
 685 }
 686
 687 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 688 {
 689         if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
 690             priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES)
 691                 priv->cfg->num_of_queues =
 692                         priv->cfg->mod_params->num_of_queues;
 693
 694         priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
 695         priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
 696         priv->hw_params.scd_bc_tbls_size =
 697                         priv->cfg->num_of_queues *
 698                         sizeof(struct iwl5000_scd_bc_tbl);
 699         priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
 700         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 701         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 702
 703         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 704         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 705
 706         priv->hw_params.max_bsm_size = 0;
 707         priv->hw_params.ht40_channel =  BIT(IEEE80211_BAND_2GHZ) |
 708                                         BIT(IEEE80211_BAND_5GHZ);
 709         priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
 710
 711         priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
 712         priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
 713         priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
 714         priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
 715
 716         if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
 717                 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
 718
 719         /* Set initial sensitivity parameters */
 720         /* Set initial calibration set */
 721         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 722         case CSR_HW_REV_TYPE_5150:
 723                 priv->hw_params.sens = &iwl5150_sensitivity;
 724                 priv->hw_params.calib_init_cfg =
 725                         BIT(IWL_CALIB_DC)               |
 726                         BIT(IWL_CALIB_LO)               |
 727                         BIT(IWL_CALIB_TX_IQ)            |
 728                         BIT(IWL_CALIB_BASE_BAND);
 729
 730                 break;
 731         default:
 732                 priv->hw_params.sens = &iwl5000_sensitivity;
 733                 priv->hw_params.calib_init_cfg =
 734                         BIT(IWL_CALIB_XTAL)             |
 735                         BIT(IWL_CALIB_LO)               |
 736                         BIT(IWL_CALIB_TX_IQ)            |
 737                         BIT(IWL_CALIB_TX_IQ_PERD)       |
 738                         BIT(IWL_CALIB_BASE_BAND);
 739                 break;
 740         }
 741
 742         return 0;
 743 }
 744
 745 /**
 746  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 747  */
 748 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 749                                             struct iwl_tx_queue *txq,
 750                                             u16 byte_cnt)
 751 {
 752         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 753         int write_ptr = txq->q.write_ptr;
 754         int txq_id = txq->q.id;
 755         u8 sec_ctl = 0;
 756         u8 sta_id = 0;
 757         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 758         __le16 bc_ent;
 759
 760         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
 761
 762         if (txq_id != IWL_CMD_QUEUE_NUM) {
 763                 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
 764                 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
 765
 766                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 767                 case TX_CMD_SEC_CCM:
 768                         len += CCMP_MIC_LEN;
 769                         break;
 770                 case TX_CMD_SEC_TKIP:
 771                         len += TKIP_ICV_LEN;
 772                         break;
 773                 case TX_CMD_SEC_WEP:
 774                         len += WEP_IV_LEN + WEP_ICV_LEN;
 775                         break;
 776                 }
 777         }
 778
 779         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
 780
 781         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 782
 783         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 784                 scd_bc_tbl[txq_id].
 785                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 786 }
 787
 788 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
 789                                            struct iwl_tx_queue *txq)
 790 {
 791         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 792         int txq_id = txq->q.id;
 793         int read_ptr = txq->q.read_ptr;
 794         u8 sta_id = 0;
 795         __le16 bc_ent;
 796
 797         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 798
 799         if (txq_id != IWL_CMD_QUEUE_NUM)
 800                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
 801
 802         bc_ent =  cpu_to_le16(1 | (sta_id << 12));
 803         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 804
 805         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 806                 scd_bc_tbl[txq_id].
 807                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] =  bc_ent;
 808 }
 809
 810 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
 811                                         u16 txq_id)
 812 {
 813         u32 tbl_dw_addr;
 814         u32 tbl_dw;
 815         u16 scd_q2ratid;
 816
 817         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 818
 819         tbl_dw_addr = priv->scd_base_addr +
 820                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
 821
 822         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
 823
 824         if (txq_id & 0x1)
 825                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 826         else
 827                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 828
 829         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
 830
 831         return 0;
 832 }
 833 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
 834 {
 835         /* Simply stop the queue, but don't change any configuration;
 836          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
 837         iwl_write_prph(priv,
 838                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 839                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
 840                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
 841 }
 842
 843 int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
 844                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
 845 {
 846         unsigned long flags;
 847         u16 ra_tid;
 848
 849         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
 850             (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
 851              <= txq_id)) {
 852                 IWL_WARN(priv,
 853                         "queue number out of range: %d, must be %d to %d\n",
 854                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
 855                         IWL50_FIRST_AMPDU_QUEUE +
 856                         priv->cfg->num_of_ampdu_queues - 1);
 857                 return -EINVAL;
 858         }
 859
 860         ra_tid = BUILD_RAxTID(sta_id, tid);
 861
 862         /* Modify device's station table to Tx this TID */
 863         iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
 864
 865         spin_lock_irqsave(&priv->lock, flags);
 866
 867         /* Stop this Tx queue before configuring it */
 868         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
 869
 870         /* Map receiver-address / traffic-ID to this queue */
 871         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
 872
 873         /* Set this queue as a chain-building queue */
 874         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
 875
 876         /* enable aggregations for the queue */
 877         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
 878
 879         /* Place first TFD at index corresponding to start sequence number.
 880          * Assumes that ssn_idx is valid (!= 0xFFF) */
 881         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
 882         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
 883         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
 884
 885         /* Set up Tx window size and frame limit for this queue */
 886         iwl_write_targ_mem(priv, priv->scd_base_addr +
 887                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
 888                         sizeof(u32),
 889                         ((SCD_WIN_SIZE <<
 890                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 891                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 892                         ((SCD_FRAME_LIMIT <<
 893                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 894                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 895
 896         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
 897
 898         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
 899         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
 900
 901         spin_unlock_irqrestore(&priv->lock, flags);
 902
 903         return 0;
 904 }
 905
 906 int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
 907                                    u16 ssn_idx, u8 tx_fifo)
 908 {
 909         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
 910             (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
 911              <= txq_id)) {
 912                 IWL_ERR(priv,
 913                         "queue number out of range: %d, must be %d to %d\n",
 914                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
 915                         IWL50_FIRST_AMPDU_QUEUE +
 916                         priv->cfg->num_of_ampdu_queues - 1);
 917                 return -EINVAL;
 918         }
 919
 920         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
 921
 922         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
 923
 924         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
 925         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
 926         /* supposes that ssn_idx is valid (!= 0xFFF) */
 927         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
 928
 929         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
 930         iwl_txq_ctx_deactivate(priv, txq_id);
 931         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
 932
 933         return 0;
 934 }
 935
 936 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
 937 {
 938         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
 939         struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
 940         memcpy(addsta, cmd, size);
 941         /* resrved in 5000 */
 942         addsta->rate_n_flags = cpu_to_le16(0);
 943         return size;
 944 }
 945
 946
 947 /*
 948  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
 949  * must be called under priv->lock and mac access
 950  */
 951 void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
 952 {
 953         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
 954 }
 955
 956
 957 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
 958 {
 959         return le32_to_cpup((__le32 *)&tx_resp->status +
 960                             tx_resp->frame_count) & MAX_SN;
 961 }
 962
 963 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
 964                                       struct iwl_ht_agg *agg,
 965                                       struct iwl5000_tx_resp *tx_resp,
 966                                       int txq_id, u16 start_idx)
 967 {
 968         u16 status;
 969         struct agg_tx_status *frame_status = &tx_resp->status;
 970         struct ieee80211_tx_info *info = NULL;
 971         struct ieee80211_hdr *hdr = NULL;
 972         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
 973         int i, sh, idx;
 974         u16 seq;
 975
 976         if (agg->wait_for_ba)
 977                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
 978
 979         agg->frame_count = tx_resp->frame_count;
 980         agg->start_idx = start_idx;
 981         agg->rate_n_flags = rate_n_flags;
 982         agg->bitmap = 0;
 983
 984         /* # frames attempted by Tx command */
 985         if (agg->frame_count == 1) {
 986                 /* Only one frame was attempted; no block-ack will arrive */
 987                 status = le16_to_cpu(frame_status[0].status);
 988                 idx = start_idx;
 989
 990                 /* FIXME: code repetition */
 991                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
 992                                    agg->frame_count, agg->start_idx, idx);
 993
 994                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
 995                 info->status.rates[0].count = tx_resp->failure_frame + 1;
 996                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
 997                 info->flags |= iwl_is_tx_success(status) ?
 998                                         IEEE80211_TX_STAT_ACK : 0;
 999                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1000
1001                 /* FIXME: code repetition end */
1002
1003                 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1004                                     status & 0xff, tx_resp->failure_frame);
1005                 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1006
1007                 agg->wait_for_ba = 0;
1008         } else {
1009                 /* Two or more frames were attempted; expect block-ack */
1010                 u64 bitmap = 0;
1011                 int start = agg->start_idx;
1012
1013                 /* Construct bit-map of pending frames within Tx window */
1014                 for (i = 0; i < agg->frame_count; i++) {
1015                         u16 sc;
1016                         status = le16_to_cpu(frame_status[i].status);
1017                         seq  = le16_to_cpu(frame_status[i].sequence);
1018                         idx = SEQ_TO_INDEX(seq);
1019                         txq_id = SEQ_TO_QUEUE(seq);
1020
1021                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1022                                       AGG_TX_STATE_ABORT_MSK))
1023                                 continue;
1024
1025                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1026                                            agg->frame_count, txq_id, idx);
1027
1028                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1029                         if (!hdr) {
1030                                 IWL_ERR(priv,
1031                                         "BUG_ON idx doesn't point to valid skb"
1032                                         " idx=%d, txq_id=%d\n", idx, txq_id);
1033                                 return -1;
1034                         }
1035
1036                         sc = le16_to_cpu(hdr->seq_ctrl);
1037                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1038                                 IWL_ERR(priv,
1039                                         "BUG_ON idx doesn't match seq control"
1040                                         " idx=%d, seq_idx=%d, seq=%d\n",
1041                                           idx, SEQ_TO_SN(sc),
1042                                           hdr->seq_ctrl);
1043                                 return -1;
1044                         }
1045
1046                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1047                                            i, idx, SEQ_TO_SN(sc));
1048
1049                         sh = idx - start;
1050                         if (sh > 64) {
1051                                 sh = (start - idx) + 0xff;
1052                                 bitmap = bitmap << sh;
1053                                 sh = 0;
1054                                 start = idx;
1055                         } else if (sh < -64)
1056                                 sh  = 0xff - (start - idx);
1057                         else if (sh < 0) {
1058                                 sh = start - idx;
1059                                 start = idx;
1060                                 bitmap = bitmap << sh;
1061                                 sh = 0;
1062                         }
1063                         bitmap |= 1ULL << sh;
1064                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1065                                            start, (unsigned long long)bitmap);
1066                 }
1067
1068                 agg->bitmap = bitmap;
1069                 agg->start_idx = start;
1070                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1071                                    agg->frame_count, agg->start_idx,
1072                                    (unsigned long long)agg->bitmap);
1073
1074                 if (bitmap)
1075                         agg->wait_for_ba = 1;
1076         }
1077         return 0;
1078 }
1079
1080 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1081                                 struct iwl_rx_mem_buffer *rxb)
1082 {
1083         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1084         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1085         int txq_id = SEQ_TO_QUEUE(sequence);
1086         int index = SEQ_TO_INDEX(sequence);
1087         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1088         struct ieee80211_tx_info *info;
1089         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1090         u32  status = le16_to_cpu(tx_resp->status.status);
1091         int tid;
1092         int sta_id;
1093         int freed;
1094
1095         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1096                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1097                           "is out of range [0-%d] %d %d\n", txq_id,
1098                           index, txq->q.n_bd, txq->q.write_ptr,
1099                           txq->q.read_ptr);
1100                 return;
1101         }
1102
1103         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1104         memset(&info->status, 0, sizeof(info->status));
1105
1106         tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1107         sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1108
1109         if (txq->sched_retry) {
1110                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1111                 struct iwl_ht_agg *agg = NULL;
1112
1113                 agg = &priv->stations[sta_id].tid[tid].agg;
1114
1115                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1116
1117                 /* check if BAR is needed */
1118                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1119                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1120
1121                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1122                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1123                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1124                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1125                                         scd_ssn , index, txq_id, txq->swq_id);
1126
1127                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1128                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1129
1130                         if (priv->mac80211_registered &&
1131                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1132                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1133                                 if (agg->state == IWL_AGG_OFF)
1134                                         iwl_wake_queue(priv, txq_id);
1135                                 else
1136                                         iwl_wake_queue(priv, txq->swq_id);
1137                         }
1138                 }
1139         } else {
1140                 BUG_ON(txq_id != txq->swq_id);
1141
1142                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1143                 info->flags |= iwl_is_tx_success(status) ?
1144                                         IEEE80211_TX_STAT_ACK : 0;
1145                 iwl_hwrate_to_tx_control(priv,
1146                                         le32_to_cpu(tx_resp->rate_n_flags),
1147                                         info);
1148
1149                 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1150                                    "0x%x retries %d\n",
1151                                    txq_id,
1152                                    iwl_get_tx_fail_reason(status), status,
1153                                    le32_to_cpu(tx_resp->rate_n_flags),
1154                                    tx_resp->failure_frame);
1155
1156                 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1157                 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1158                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1159
1160                 if (priv->mac80211_registered &&
1161                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
1162                         iwl_wake_queue(priv, txq_id);
1163         }
1164
1165         if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1166                 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1167
1168         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1169                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
1170 }
1171
1172 /* Currently 5000 is the superset of everything */
1173 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1174 {
1175         return len;
1176 }
1177
1178 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1179 {
1180         /* in 5000 the tx power calibration is done in uCode */
1181         priv->disable_tx_power_cal = 1;
1182 }
1183
1184 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1185 {
1186         /* init calibration handlers */
1187         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1188                                         iwl5000_rx_calib_result;
1189         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1190                                         iwl5000_rx_calib_complete;
1191         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1192 }
1193
1194
1195 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1196 {
1197         return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1198                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1199 }
1200
1201 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1202 {
1203         int ret = 0;
1204         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1205         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1206         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1207
1208         if ((rxon1->flags == rxon2->flags) &&
1209             (rxon1->filter_flags == rxon2->filter_flags) &&
1210             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1211             (rxon1->ofdm_ht_single_stream_basic_rates ==
1212              rxon2->ofdm_ht_single_stream_basic_rates) &&
1213             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1214              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1215             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1216              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1217             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1218             (rxon1->rx_chain == rxon2->rx_chain) &&
1219             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1220                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1221                 return 0;
1222         }
1223
1224         rxon_assoc.flags = priv->staging_rxon.flags;
1225         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1226         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1227         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1228         rxon_assoc.reserved1 = 0;
1229         rxon_assoc.reserved2 = 0;
1230         rxon_assoc.reserved3 = 0;
1231         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1232             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1233         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1234             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1235         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1236         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1237                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1238         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1239
1240         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1241                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1242         if (ret)
1243                 return ret;
1244
1245         return ret;
1246 }
1247 int  iwl5000_send_tx_power(struct iwl_priv *priv)
1248 {
1249         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1250         u8 tx_ant_cfg_cmd;
1251
1252         /* half dBm need to multiply */
1253         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1254         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1255         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1256
1257         if (IWL_UCODE_API(priv->ucode_ver) == 1)
1258                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1259         else
1260                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1261
1262         return  iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1263                                        sizeof(tx_power_cmd), &tx_power_cmd,
1264                                        NULL);
1265 }
1266
1267 void iwl5000_temperature(struct iwl_priv *priv)
1268 {
1269         /* store temperature from statistics (in Celsius) */
1270         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1271         iwl_tt_handler(priv);
1272 }
1273
1274 static void iwl5150_temperature(struct iwl_priv *priv)
1275 {
1276         u32 vt = 0;
1277         s32 offset =  iwl_temp_calib_to_offset(priv);
1278
1279         vt = le32_to_cpu(priv->statistics.general.temperature);
1280         vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1281         /* now vt hold the temperature in Kelvin */
1282         priv->temperature = KELVIN_TO_CELSIUS(vt);
1283         iwl_tt_handler(priv);
1284 }
1285
1286 /* Calc max signal level (dBm) among 3 possible receivers */
1287 int iwl5000_calc_rssi(struct iwl_priv *priv,
1288                              struct iwl_rx_phy_res *rx_resp)
1289 {
1290         /* data from PHY/DSP regarding signal strength, etc.,
1291          *   contents are always there, not configurable by host
1292          */
1293         struct iwl5000_non_cfg_phy *ncphy =
1294                 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1295         u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1296         u8 agc;
1297
1298         val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1299         agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1300
1301         /* Find max rssi among 3 possible receivers.
1302          * These values are measured by the digital signal processor (DSP).
1303          * They should stay fairly constant even as the signal strength varies,
1304          *   if the radio's automatic gain control (AGC) is working right.
1305          * AGC value (see below) will provide the "interesting" info.
1306          */
1307         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1308         rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1309         rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1310         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1311         rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1312
1313         max_rssi = max_t(u32, rssi_a, rssi_b);
1314         max_rssi = max_t(u32, max_rssi, rssi_c);
1315
1316         IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1317                 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1318
1319         /* dBm = max_rssi dB - agc dB - constant.
1320          * Higher AGC (higher radio gain) means lower signal. */
1321         return max_rssi - agc - IWL49_RSSI_OFFSET;
1322 }
1323
1324 static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1325 {
1326         struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1327           .valid = cpu_to_le32(valid_tx_ant),
1328         };
1329
1330         if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1331                 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1332                 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1333                                         sizeof(struct iwl_tx_ant_config_cmd),
1334                                         &tx_ant_cmd);
1335         } else {
1336                 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1337                 return -EOPNOTSUPP;
1338         }
1339 }
1340
1341
1342 #define IWL5000_UCODE_GET(item)                                         \
1343 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1344                                     u32 api_ver)                        \
1345 {                                                                       \
1346         if (api_ver <= 2)                                               \
1347                 return le32_to_cpu(ucode->u.v1.item);                   \
1348         return le32_to_cpu(ucode->u.v2.item);                           \
1349 }
1350
1351 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1352 {
1353         if (api_ver <= 2)
1354                 return UCODE_HEADER_SIZE(1);
1355         return UCODE_HEADER_SIZE(2);
1356 }
1357
1358 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1359                                    u32 api_ver)
1360 {
1361         if (api_ver <= 2)
1362                 return 0;
1363         return le32_to_cpu(ucode->u.v2.build);
1364 }
1365
1366 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1367                                   u32 api_ver)
1368 {
1369         if (api_ver <= 2)
1370                 return (u8 *) ucode->u.v1.data;
1371         return (u8 *) ucode->u.v2.data;
1372 }
1373
1374 IWL5000_UCODE_GET(inst_size);
1375 IWL5000_UCODE_GET(data_size);
1376 IWL5000_UCODE_GET(init_size);
1377 IWL5000_UCODE_GET(init_data_size);
1378 IWL5000_UCODE_GET(boot_size);
1379
1380 static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1381 {
1382         struct iwl5000_channel_switch_cmd cmd;
1383         const struct iwl_channel_info *ch_info;
1384         struct iwl_host_cmd hcmd = {
1385                 .id = REPLY_CHANNEL_SWITCH,
1386                 .len = sizeof(cmd),
1387                 .flags = CMD_SIZE_HUGE,
1388                 .data = &cmd,
1389         };
1390
1391         IWL_DEBUG_11H(priv, "channel switch from %d to %d\n",
1392                 priv->active_rxon.channel, channel);
1393         cmd.band = priv->band == IEEE80211_BAND_2GHZ;
1394         cmd.channel = cpu_to_le16(channel);
1395         cmd.rxon_flags = priv->staging_rxon.flags;
1396         cmd.rxon_filter_flags = priv->staging_rxon.filter_flags;
1397         cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1398         ch_info = iwl_get_channel_info(priv, priv->band, channel);
1399         if (ch_info)
1400                 cmd.expect_beacon = is_channel_radar(ch_info);
1401         else {
1402                 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
1403                         priv->active_rxon.channel, channel);
1404                 return -EFAULT;
1405         }
1406         priv->switch_rxon.channel = cpu_to_le16(channel);
1407         priv->switch_rxon.switch_in_progress = true;
1408
1409         return iwl_send_cmd_sync(priv, &hcmd);
1410 }
1411
1412 struct iwl_hcmd_ops iwl5000_hcmd = {
1413         .rxon_assoc = iwl5000_send_rxon_assoc,
1414         .commit_rxon = iwl_commit_rxon,
1415         .set_rxon_chain = iwl_set_rxon_chain,
1416         .set_tx_ant = iwl5000_send_tx_ant_config,
1417 };
1418
1419 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1420         .get_hcmd_size = iwl5000_get_hcmd_size,
1421         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1422         .gain_computation = iwl5000_gain_computation,
1423         .chain_noise_reset = iwl5000_chain_noise_reset,
1424         .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1425         .calc_rssi = iwl5000_calc_rssi,
1426 };
1427
1428 struct iwl_ucode_ops iwl5000_ucode = {
1429         .get_header_size = iwl5000_ucode_get_header_size,
1430         .get_build = iwl5000_ucode_get_build,
1431         .get_inst_size = iwl5000_ucode_get_inst_size,
1432         .get_data_size = iwl5000_ucode_get_data_size,
1433         .get_init_size = iwl5000_ucode_get_init_size,
1434         .get_init_data_size = iwl5000_ucode_get_init_data_size,
1435         .get_boot_size = iwl5000_ucode_get_boot_size,
1436         .get_data = iwl5000_ucode_get_data,
1437 };
1438
1439 struct iwl_lib_ops iwl5000_lib = {
1440         .set_hw_params = iwl5000_hw_set_hw_params,
1441         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1442         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1443         .txq_set_sched = iwl5000_txq_set_sched,
1444         .txq_agg_enable = iwl5000_txq_agg_enable,
1445         .txq_agg_disable = iwl5000_txq_agg_disable,
1446         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1447         .txq_free_tfd = iwl_hw_txq_free_tfd,
1448         .txq_init = iwl_hw_tx_queue_init,
1449         .rx_handler_setup = iwl5000_rx_handler_setup,
1450         .setup_deferred_work = iwl5000_setup_deferred_work,
1451         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1452         .dump_nic_event_log = iwl_dump_nic_event_log,
1453         .dump_nic_error_log = iwl_dump_nic_error_log,
1454         .load_ucode = iwl5000_load_ucode,
1455         .init_alive_start = iwl5000_init_alive_start,
1456         .alive_notify = iwl5000_alive_notify,
1457         .send_tx_power = iwl5000_send_tx_power,
1458         .update_chain_flags = iwl_update_chain_flags,
1459         .set_channel_switch = iwl5000_hw_channel_switch,
1460         .apm_ops = {
1461                 .init = iwl_apm_init,
1462                 .stop = iwl_apm_stop,
1463                 .config = iwl5000_nic_config,
1464                 .set_pwr_src = iwl_set_pwr_src,
1465         },
1466         .eeprom_ops = {
1467                 .regulatory_bands = {
1468                         EEPROM_5000_REG_BAND_1_CHANNELS,
1469                         EEPROM_5000_REG_BAND_2_CHANNELS,
1470                         EEPROM_5000_REG_BAND_3_CHANNELS,
1471                         EEPROM_5000_REG_BAND_4_CHANNELS,
1472                         EEPROM_5000_REG_BAND_5_CHANNELS,
1473                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1474                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1475                 },
1476                 .verify_signature  = iwlcore_eeprom_verify_signature,
1477                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1478                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1479                 .calib_version  = iwl5000_eeprom_calib_version,
1480                 .query_addr = iwl5000_eeprom_query_addr,
1481         },
1482         .post_associate = iwl_post_associate,
1483         .isr = iwl_isr_ict,
1484         .config_ap = iwl_config_ap,
1485         .temp_ops = {
1486                 .temperature = iwl5000_temperature,
1487                 .set_ct_kill = iwl5000_set_ct_threshold,
1488          },
1489 };
1490
1491 static struct iwl_lib_ops iwl5150_lib = {
1492         .set_hw_params = iwl5000_hw_set_hw_params,
1493         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1494         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1495         .txq_set_sched = iwl5000_txq_set_sched,
1496         .txq_agg_enable = iwl5000_txq_agg_enable,
1497         .txq_agg_disable = iwl5000_txq_agg_disable,
1498         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1499         .txq_free_tfd = iwl_hw_txq_free_tfd,
1500         .txq_init = iwl_hw_tx_queue_init,
1501         .rx_handler_setup = iwl5000_rx_handler_setup,
1502         .setup_deferred_work = iwl5000_setup_deferred_work,
1503         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1504         .dump_nic_event_log = iwl_dump_nic_event_log,
1505         .dump_nic_error_log = iwl_dump_nic_error_log,
1506         .load_ucode = iwl5000_load_ucode,
1507         .init_alive_start = iwl5000_init_alive_start,
1508         .alive_notify = iwl5000_alive_notify,
1509         .send_tx_power = iwl5000_send_tx_power,
1510         .update_chain_flags = iwl_update_chain_flags,
1511         .set_channel_switch = iwl5000_hw_channel_switch,
1512         .apm_ops = {
1513                 .init = iwl_apm_init,
1514                 .stop = iwl_apm_stop,
1515                 .config = iwl5000_nic_config,
1516                 .set_pwr_src = iwl_set_pwr_src,
1517         },
1518         .eeprom_ops = {
1519                 .regulatory_bands = {
1520                         EEPROM_5000_REG_BAND_1_CHANNELS,
1521                         EEPROM_5000_REG_BAND_2_CHANNELS,
1522                         EEPROM_5000_REG_BAND_3_CHANNELS,
1523                         EEPROM_5000_REG_BAND_4_CHANNELS,
1524                         EEPROM_5000_REG_BAND_5_CHANNELS,
1525                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1526                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1527                 },
1528                 .verify_signature  = iwlcore_eeprom_verify_signature,
1529                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1530                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1531                 .calib_version  = iwl5000_eeprom_calib_version,
1532                 .query_addr = iwl5000_eeprom_query_addr,
1533         },
1534         .post_associate = iwl_post_associate,
1535         .isr = iwl_isr_ict,
1536         .config_ap = iwl_config_ap,
1537         .temp_ops = {
1538                 .temperature = iwl5150_temperature,
1539                 .set_ct_kill = iwl5150_set_ct_threshold,
1540          },
1541 };
1542
1543 static struct iwl_ops iwl5000_ops = {
1544         .ucode = &iwl5000_ucode,
1545         .lib = &iwl5000_lib,
1546         .hcmd = &iwl5000_hcmd,
1547         .utils = &iwl5000_hcmd_utils,
1548         .led = &iwlagn_led_ops,
1549 };
1550
1551 static struct iwl_ops iwl5150_ops = {
1552         .ucode = &iwl5000_ucode,
1553         .lib = &iwl5150_lib,
1554         .hcmd = &iwl5000_hcmd,
1555         .utils = &iwl5000_hcmd_utils,
1556         .led = &iwlagn_led_ops,
1557 };
1558
1559 struct iwl_mod_params iwl50_mod_params = {
1560         .amsdu_size_8K = 1,
1561         .restart_fw = 1,
1562         /* the rest are 0 by default */
1563 };
1564
1565
1566 struct iwl_cfg iwl5300_agn_cfg = {
1567         .name = "5300AGN",
1568         .fw_name_pre = IWL5000_FW_PRE,
1569         .ucode_api_max = IWL5000_UCODE_API_MAX,
1570         .ucode_api_min = IWL5000_UCODE_API_MIN,
1571         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1572         .ops = &iwl5000_ops,
1573         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1574         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1575         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1576         .num_of_queues = IWL50_NUM_QUEUES,
1577         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1578         .mod_params = &iwl50_mod_params,
1579         .valid_tx_ant = ANT_ABC,
1580         .valid_rx_ant = ANT_ABC,
1581         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1582         .set_l0s = true,
1583         .use_bsm = false,
1584         .ht_greenfield_support = true,
1585         .led_compensation = 51,
1586         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1587 };
1588
1589 struct iwl_cfg iwl5100_bg_cfg = {
1590         .name = "5100BG",
1591         .fw_name_pre = IWL5000_FW_PRE,
1592         .ucode_api_max = IWL5000_UCODE_API_MAX,
1593         .ucode_api_min = IWL5000_UCODE_API_MIN,
1594         .sku = IWL_SKU_G,
1595         .ops = &iwl5000_ops,
1596         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1597         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1598         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1599         .num_of_queues = IWL50_NUM_QUEUES,
1600         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1601         .mod_params = &iwl50_mod_params,
1602         .valid_tx_ant = ANT_B,
1603         .valid_rx_ant = ANT_AB,
1604         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1605         .set_l0s = true,
1606         .use_bsm = false,
1607         .ht_greenfield_support = true,
1608         .led_compensation = 51,
1609         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1610 };
1611
1612 struct iwl_cfg iwl5100_abg_cfg = {
1613         .name = "5100ABG",
1614         .fw_name_pre = IWL5000_FW_PRE,
1615         .ucode_api_max = IWL5000_UCODE_API_MAX,
1616         .ucode_api_min = IWL5000_UCODE_API_MIN,
1617         .sku = IWL_SKU_A|IWL_SKU_G,
1618         .ops = &iwl5000_ops,
1619         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1620         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1621         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1622         .num_of_queues = IWL50_NUM_QUEUES,
1623         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1624         .mod_params = &iwl50_mod_params,
1625         .valid_tx_ant = ANT_B,
1626         .valid_rx_ant = ANT_AB,
1627         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1628         .set_l0s = true,
1629         .use_bsm = false,
1630         .ht_greenfield_support = true,
1631         .led_compensation = 51,
1632         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1633 };
1634
1635 struct iwl_cfg iwl5100_agn_cfg = {
1636         .name = "5100AGN",
1637         .fw_name_pre = IWL5000_FW_PRE,
1638         .ucode_api_max = IWL5000_UCODE_API_MAX,
1639         .ucode_api_min = IWL5000_UCODE_API_MIN,
1640         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1641         .ops = &iwl5000_ops,
1642         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1643         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1644         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1645         .num_of_queues = IWL50_NUM_QUEUES,
1646         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1647         .mod_params = &iwl50_mod_params,
1648         .valid_tx_ant = ANT_B,
1649         .valid_rx_ant = ANT_AB,
1650         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1651         .set_l0s = true,
1652         .use_bsm = false,
1653         .ht_greenfield_support = true,
1654         .led_compensation = 51,
1655         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1656 };
1657
1658 struct iwl_cfg iwl5350_agn_cfg = {
1659         .name = "5350AGN",
1660         .fw_name_pre = IWL5000_FW_PRE,
1661         .ucode_api_max = IWL5000_UCODE_API_MAX,
1662         .ucode_api_min = IWL5000_UCODE_API_MIN,
1663         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1664         .ops = &iwl5000_ops,
1665         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1666         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1667         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1668         .num_of_queues = IWL50_NUM_QUEUES,
1669         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1670         .mod_params = &iwl50_mod_params,
1671         .valid_tx_ant = ANT_ABC,
1672         .valid_rx_ant = ANT_ABC,
1673         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1674         .set_l0s = true,
1675         .use_bsm = false,
1676         .ht_greenfield_support = true,
1677         .led_compensation = 51,
1678         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1679 };
1680
1681 struct iwl_cfg iwl5150_agn_cfg = {
1682         .name = "5150AGN",
1683         .fw_name_pre = IWL5150_FW_PRE,
1684         .ucode_api_max = IWL5150_UCODE_API_MAX,
1685         .ucode_api_min = IWL5150_UCODE_API_MIN,
1686         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1687         .ops = &iwl5150_ops,
1688         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1689         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1690         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1691         .num_of_queues = IWL50_NUM_QUEUES,
1692         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1693         .mod_params = &iwl50_mod_params,
1694         .valid_tx_ant = ANT_A,
1695         .valid_rx_ant = ANT_AB,
1696         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1697         .set_l0s = true,
1698         .use_bsm = false,
1699         .ht_greenfield_support = true,
1700         .led_compensation = 51,
1701         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1702 };
1703
1704 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1705 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1706
1707 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
1708 MODULE_PARM_DESC(swcrypto50,
1709                   "using software crypto engine (default 0 [hardware])\n");
1710 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
1711 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1712 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
1713 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1714 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1715                    int, S_IRUGO);
1716 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1717 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
1718 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");