drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/delay.h>
  34 #include <linux/sched.h>
  35 #include <linux/skbuff.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/wireless.h>
  38 #include <linux/firmware.h>
  39 #include <linux/etherdevice.h>
  40 #include <asm/unaligned.h>
  41 #include <net/mac80211.h>
  42
  43 #include "iwl-fh.h"
  44 #include "iwl-3945-fh.h"
  45 #include "iwl-commands.h"
  46 #include "iwl-sta.h"
  47 #include "iwl-3945.h"
  48 #include "iwl-eeprom.h"
  49 #include "iwl-core.h"
  50 #include "iwl-helpers.h"
  51 #include "iwl-led.h"
  52 #include "iwl-3945-led.h"
  53 #include "iwl-3945-debugfs.h"
  54
  55 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  56         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  57                                     IWL_RATE_##r##M_IEEE,   \
  58                                     IWL_RATE_##ip##M_INDEX, \
  59                                     IWL_RATE_##in##M_INDEX, \
  60                                     IWL_RATE_##rp##M_INDEX, \
  61                                     IWL_RATE_##rn##M_INDEX, \
  62                                     IWL_RATE_##pp##M_INDEX, \
  63                                     IWL_RATE_##np##M_INDEX, \
  64                                     IWL_RATE_##r##M_INDEX_TABLE, \
  65                                     IWL_RATE_##ip##M_INDEX_TABLE }
  66
  67 /*
  68  * Parameter order:
  69  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  70  *
  71  * If there isn't a valid next or previous rate then INV is used which
  72  * maps to IWL_RATE_INVALID
  73  *
  74  */
  75 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
  76         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  77         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  78         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  79         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  80         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  81         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  82         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  83         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  84         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  85         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  86         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  87         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  88 };
  89
  90 /* 1 = enable the iwl3945_disable_events() function */
  91 #define IWL_EVT_DISABLE (0)
  92 #define IWL_EVT_DISABLE_SIZE (1532/32)
  93
  94 /**
  95  * iwl3945_disable_events - Disable selected events in uCode event log
  96  *
  97  * Disable an event by writing "1"s into "disable"
  98  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
  99  *   Default values of 0 enable uCode events to be logged.
 100  * Use for only special debugging.  This function is just a placeholder as-is,
 101  *   you'll need to provide the special bits! ...
 102  *   ... and set IWL_EVT_DISABLE to 1. */
 103 void iwl3945_disable_events(struct iwl_priv *priv)
 104 {
 105         int i;
 106         u32 base;               /* SRAM address of event log header */
 107         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 108         u32 array_size;         /* # of u32 entries in array */
 109         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 110                 0x00000000,     /*   31 -    0  Event id numbers */
 111                 0x00000000,     /*   63 -   32 */
 112                 0x00000000,     /*   95 -   64 */
 113                 0x00000000,     /*  127 -   96 */
 114                 0x00000000,     /*  159 -  128 */
 115                 0x00000000,     /*  191 -  160 */
 116                 0x00000000,     /*  223 -  192 */
 117                 0x00000000,     /*  255 -  224 */
 118                 0x00000000,     /*  287 -  256 */
 119                 0x00000000,     /*  319 -  288 */
 120                 0x00000000,     /*  351 -  320 */
 121                 0x00000000,     /*  383 -  352 */
 122                 0x00000000,     /*  415 -  384 */
 123                 0x00000000,     /*  447 -  416 */
 124                 0x00000000,     /*  479 -  448 */
 125                 0x00000000,     /*  511 -  480 */
 126                 0x00000000,     /*  543 -  512 */
 127                 0x00000000,     /*  575 -  544 */
 128                 0x00000000,     /*  607 -  576 */
 129                 0x00000000,     /*  639 -  608 */
 130                 0x00000000,     /*  671 -  640 */
 131                 0x00000000,     /*  703 -  672 */
 132                 0x00000000,     /*  735 -  704 */
 133                 0x00000000,     /*  767 -  736 */
 134                 0x00000000,     /*  799 -  768 */
 135                 0x00000000,     /*  831 -  800 */
 136                 0x00000000,     /*  863 -  832 */
 137                 0x00000000,     /*  895 -  864 */
 138                 0x00000000,     /*  927 -  896 */
 139                 0x00000000,     /*  959 -  928 */
 140                 0x00000000,     /*  991 -  960 */
 141                 0x00000000,     /* 1023 -  992 */
 142                 0x00000000,     /* 1055 - 1024 */
 143                 0x00000000,     /* 1087 - 1056 */
 144                 0x00000000,     /* 1119 - 1088 */
 145                 0x00000000,     /* 1151 - 1120 */
 146                 0x00000000,     /* 1183 - 1152 */
 147                 0x00000000,     /* 1215 - 1184 */
 148                 0x00000000,     /* 1247 - 1216 */
 149                 0x00000000,     /* 1279 - 1248 */
 150                 0x00000000,     /* 1311 - 1280 */
 151                 0x00000000,     /* 1343 - 1312 */
 152                 0x00000000,     /* 1375 - 1344 */
 153                 0x00000000,     /* 1407 - 1376 */
 154                 0x00000000,     /* 1439 - 1408 */
 155                 0x00000000,     /* 1471 - 1440 */
 156                 0x00000000,     /* 1503 - 1472 */
 157         };
 158
 159         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 160         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 161                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
 162                 return;
 163         }
 164
 165         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
 166         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
 167
 168         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 169                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
 170                                disable_ptr);
 171                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 172                         iwl_write_targ_mem(priv,
 173                                            disable_ptr + (i * sizeof(u32)),
 174                                            evt_disable[i]);
 175
 176         } else {
 177                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
 178                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
 179                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
 180                                disable_ptr, array_size);
 181         }
 182
 183 }
 184
 185 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 186 {
 187         int idx;
 188
 189         for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
 190                 if (iwl3945_rates[idx].plcp == plcp)
 191                         return idx;
 192         return -1;
 193 }
 194
 195 #ifdef CONFIG_IWLWIFI_DEBUG
 196 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
 197
 198 static const char *iwl3945_get_tx_fail_reason(u32 status)
 199 {
 200         switch (status & TX_STATUS_MSK) {
 201         case TX_3945_STATUS_SUCCESS:
 202                 return "SUCCESS";
 203                 TX_STATUS_ENTRY(SHORT_LIMIT);
 204                 TX_STATUS_ENTRY(LONG_LIMIT);
 205                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 206                 TX_STATUS_ENTRY(MGMNT_ABORT);
 207                 TX_STATUS_ENTRY(NEXT_FRAG);
 208                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 209                 TX_STATUS_ENTRY(DEST_PS);
 210                 TX_STATUS_ENTRY(ABORTED);
 211                 TX_STATUS_ENTRY(BT_RETRY);
 212                 TX_STATUS_ENTRY(STA_INVALID);
 213                 TX_STATUS_ENTRY(FRAG_DROPPED);
 214                 TX_STATUS_ENTRY(TID_DISABLE);
 215                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 216                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 217                 TX_STATUS_ENTRY(TX_LOCKED);
 218                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 219         }
 220
 221         return "UNKNOWN";
 222 }
 223 #else
 224 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 225 {
 226         return "";
 227 }
 228 #endif
 229
 230 /*
 231  * get ieee prev rate from rate scale table.
 232  * for A and B mode we need to overright prev
 233  * value
 234  */
 235 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
 236 {
 237         int next_rate = iwl3945_get_prev_ieee_rate(rate);
 238
 239         switch (priv->band) {
 240         case IEEE80211_BAND_5GHZ:
 241                 if (rate == IWL_RATE_12M_INDEX)
 242                         next_rate = IWL_RATE_9M_INDEX;
 243                 else if (rate == IWL_RATE_6M_INDEX)
 244                         next_rate = IWL_RATE_6M_INDEX;
 245                 break;
 246         case IEEE80211_BAND_2GHZ:
 247                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
 248                     iwl_is_associated(priv)) {
 249                         if (rate == IWL_RATE_11M_INDEX)
 250                                 next_rate = IWL_RATE_5M_INDEX;
 251                 }
 252                 break;
 253
 254         default:
 255                 break;
 256         }
 257
 258         return next_rate;
 259 }
 260
 261
 262 /**
 263  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 264  *
 265  * When FW advances 'R' index, all entries between old and new 'R' index
 266  * need to be reclaimed. As result, some free space forms. If there is
 267  * enough free space (> low mark), wake the stack that feeds us.
 268  */
 269 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
 270                                      int txq_id, int index)
 271 {
 272         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 273         struct iwl_queue *q = &txq->q;
 274         struct iwl_tx_info *tx_info;
 275
 276         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
 277
 278         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 279                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 280
 281                 tx_info = &txq->txb[txq->q.read_ptr];
 282                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
 283                 tx_info->skb = NULL;
 284                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
 285         }
 286
 287         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 288                         (txq_id != IWL_CMD_QUEUE_NUM) &&
 289                         priv->mac80211_registered)
 290                 iwl_wake_queue(priv, txq_id);
 291 }
 292
 293 /**
 294  * iwl3945_rx_reply_tx - Handle Tx response
 295  */
 296 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
 297                                 struct iwl_rx_mem_buffer *rxb)
 298 {
 299         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 300         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 301         int txq_id = SEQ_TO_QUEUE(sequence);
 302         int index = SEQ_TO_INDEX(sequence);
 303         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 304         struct ieee80211_tx_info *info;
 305         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 306         u32  status = le32_to_cpu(tx_resp->status);
 307         int rate_idx;
 308         int fail;
 309
 310         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 311                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 312                           "is out of range [0-%d] %d %d\n", txq_id,
 313                           index, txq->q.n_bd, txq->q.write_ptr,
 314                           txq->q.read_ptr);
 315                 return;
 316         }
 317
 318         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
 319         ieee80211_tx_info_clear_status(info);
 320
 321         /* Fill the MRR chain with some info about on-chip retransmissions */
 322         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 323         if (info->band == IEEE80211_BAND_5GHZ)
 324                 rate_idx -= IWL_FIRST_OFDM_RATE;
 325
 326         fail = tx_resp->failure_frame;
 327
 328         info->status.rates[0].idx = rate_idx;
 329         info->status.rates[0].count = fail + 1; /* add final attempt */
 330
 331         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 332         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 333                                 IEEE80211_TX_STAT_ACK : 0;
 334
 335         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 336                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 337                         tx_resp->rate, tx_resp->failure_frame);
 338
 339         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
 340         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 341
 342         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 343                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 344 }
 345
 346
 347
 348 /*****************************************************************************
 349  *
 350  * Intel PRO/Wireless 3945ABG/BG Network Connection
 351  *
 352  *  RX handler implementations
 353  *
 354  *****************************************************************************/
 355 #ifdef CONFIG_IWLWIFI_DEBUGFS
 356 /*
 357  *  based on the assumption of all statistics counter are in DWORD
 358  *  FIXME: This function is for debugging, do not deal with
 359  *  the case of counters roll-over.
 360  */
 361 static void iwl3945_accumulative_statistics(struct iwl_priv *priv,
 362                                             __le32 *stats)
 363 {
 364         int i;
 365         __le32 *prev_stats;
 366         u32 *accum_stats;
 367         u32 *delta, *max_delta;
 368
 369         prev_stats = (__le32 *)&priv->_3945.statistics;
 370         accum_stats = (u32 *)&priv->_3945.accum_statistics;
 371         delta = (u32 *)&priv->_3945.delta_statistics;
 372         max_delta = (u32 *)&priv->_3945.max_delta;
 373
 374         for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics);
 375              i += sizeof(__le32), stats++, prev_stats++, delta++,
 376              max_delta++, accum_stats++) {
 377                 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
 378                         *delta = (le32_to_cpu(*stats) -
 379                                 le32_to_cpu(*prev_stats));
 380                         *accum_stats += *delta;
 381                         if (*delta > *max_delta)
 382                                 *max_delta = *delta;
 383                 }
 384         }
 385
 386         /* reset accumulative statistics for "no-counter" type statistics */
 387         priv->_3945.accum_statistics.general.temperature =
 388                 priv->_3945.statistics.general.temperature;
 389         priv->_3945.accum_statistics.general.ttl_timestamp =
 390                 priv->_3945.statistics.general.ttl_timestamp;
 391 }
 392 #endif
 393
 394 /**
 395  * iwl3945_good_plcp_health - checks for plcp error.
 396  *
 397  * When the plcp error is exceeding the thresholds, reset the radio
 398  * to improve the throughput.
 399  */
 400 static bool iwl3945_good_plcp_health(struct iwl_priv *priv,
 401                                 struct iwl_rx_packet *pkt)
 402 {
 403         bool rc = true;
 404         struct iwl3945_notif_statistics current_stat;
 405         int combined_plcp_delta;
 406         unsigned int plcp_msec;
 407         unsigned long plcp_received_jiffies;
 408
 409         if (priv->cfg->plcp_delta_threshold ==
 410             IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE) {
 411                 IWL_DEBUG_RADIO(priv, "plcp_err check disabled\n");
 412                 return rc;
 413         }
 414         memcpy(&current_stat, pkt->u.raw, sizeof(struct
 415                         iwl3945_notif_statistics));
 416         /*
 417          * check for plcp_err and trigger radio reset if it exceeds
 418          * the plcp error threshold plcp_delta.
 419          */
 420         plcp_received_jiffies = jiffies;
 421         plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies -
 422                                         (long) priv->plcp_jiffies);
 423         priv->plcp_jiffies = plcp_received_jiffies;
 424         /*
 425          * check to make sure plcp_msec is not 0 to prevent division
 426          * by zero.
 427          */
 428         if (plcp_msec) {
 429                 combined_plcp_delta =
 430                         (le32_to_cpu(current_stat.rx.ofdm.plcp_err) -
 431                         le32_to_cpu(priv->_3945.statistics.rx.ofdm.plcp_err));
 432
 433                 if ((combined_plcp_delta > 0) &&
 434                         ((combined_plcp_delta * 100) / plcp_msec) >
 435                         priv->cfg->plcp_delta_threshold) {
 436                         /*
 437                          * if plcp_err exceed the threshold, the following
 438                          * data is printed in csv format:
 439                          *    Text: plcp_err exceeded %d,
 440                          *    Received ofdm.plcp_err,
 441                          *    Current ofdm.plcp_err,
 442                          *    combined_plcp_delta,
 443                          *    plcp_msec
 444                          */
 445                         IWL_DEBUG_RADIO(priv, "plcp_err exceeded %u, "
 446                                 "%u, %d, %u mSecs\n",
 447                                 priv->cfg->plcp_delta_threshold,
 448                                 le32_to_cpu(current_stat.rx.ofdm.plcp_err),
 449                                 combined_plcp_delta, plcp_msec);
 450                         /*
 451                          * Reset the RF radio due to the high plcp
 452                          * error rate
 453                          */
 454                         rc = false;
 455                 }
 456         }
 457         return rc;
 458 }
 459
 460 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
 461                 struct iwl_rx_mem_buffer *rxb)
 462 {
 463         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 464
 465         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
 466                      (int)sizeof(struct iwl3945_notif_statistics),
 467                      le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
 468 #ifdef CONFIG_IWLWIFI_DEBUGFS
 469         iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
 470 #endif
 471         iwl_recover_from_statistics(priv, pkt);
 472
 473         memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
 474 }
 475
 476 void iwl3945_reply_statistics(struct iwl_priv *priv,
 477                               struct iwl_rx_mem_buffer *rxb)
 478 {
 479         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 480         __le32 *flag = (__le32 *)&pkt->u.raw;
 481
 482         if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
 483 #ifdef CONFIG_IWLWIFI_DEBUGFS
 484                 memset(&priv->_3945.accum_statistics, 0,
 485                         sizeof(struct iwl3945_notif_statistics));
 486                 memset(&priv->_3945.delta_statistics, 0,
 487                         sizeof(struct iwl3945_notif_statistics));
 488                 memset(&priv->_3945.max_delta, 0,
 489                         sizeof(struct iwl3945_notif_statistics));
 490 #endif
 491                 IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
 492         }
 493         iwl3945_hw_rx_statistics(priv, rxb);
 494 }
 495
 496
 497 /******************************************************************************
 498  *
 499  * Misc. internal state and helper functions
 500  *
 501  ******************************************************************************/
 502
 503 /* This is necessary only for a number of statistics, see the caller. */
 504 static int iwl3945_is_network_packet(struct iwl_priv *priv,
 505                 struct ieee80211_hdr *header)
 506 {
 507         /* Filter incoming packets to determine if they are targeted toward
 508          * this network, discarding packets coming from ourselves */
 509         switch (priv->iw_mode) {
 510         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 511                 /* packets to our IBSS update information */
 512                 return !compare_ether_addr(header->addr3, priv->bssid);
 513         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 514                 /* packets to our IBSS update information */
 515                 return !compare_ether_addr(header->addr2, priv->bssid);
 516         default:
 517                 return 1;
 518         }
 519 }
 520
 521 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
 522                                    struct iwl_rx_mem_buffer *rxb,
 523                                    struct ieee80211_rx_status *stats)
 524 {
 525         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 526         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 527         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 528         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 529         u16 len = le16_to_cpu(rx_hdr->len);
 530         struct sk_buff *skb;
 531         __le16 fc = hdr->frame_control;
 532
 533         /* We received data from the HW, so stop the watchdog */
 534         if (unlikely(len + IWL39_RX_FRAME_SIZE >
 535                      PAGE_SIZE << priv->hw_params.rx_page_order)) {
 536                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
 537                 return;
 538         }
 539
 540         /* We only process data packets if the interface is open */
 541         if (unlikely(!priv->is_open)) {
 542                 IWL_DEBUG_DROP_LIMIT(priv,
 543                         "Dropping packet while interface is not open.\n");
 544                 return;
 545         }
 546
 547         skb = dev_alloc_skb(128);
 548         if (!skb) {
 549                 IWL_ERR(priv, "dev_alloc_skb failed\n");
 550                 return;
 551         }
 552
 553         if (!iwl3945_mod_params.sw_crypto)
 554                 iwl_set_decrypted_flag(priv,
 555                                        (struct ieee80211_hdr *)rxb_addr(rxb),
 556                                        le32_to_cpu(rx_end->status), stats);
 557
 558         skb_add_rx_frag(skb, 0, rxb->page,
 559                         (void *)rx_hdr->payload - (void *)pkt, len);
 560
 561         iwl_update_stats(priv, false, fc, len);
 562         memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
 563
 564         ieee80211_rx(priv->hw, skb);
 565         priv->alloc_rxb_page--;
 566         rxb->page = NULL;
 567 }
 568
 569 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 570
 571 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
 572                                 struct iwl_rx_mem_buffer *rxb)
 573 {
 574         struct ieee80211_hdr *header;
 575         struct ieee80211_rx_status rx_status;
 576         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 577         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 578         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 579         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 580         u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
 581         u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
 582         u8 network_packet;
 583
 584         rx_status.flag = 0;
 585         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 586         rx_status.freq =
 587                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 588         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 589                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 590
 591         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 592         if (rx_status.band == IEEE80211_BAND_5GHZ)
 593                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 594
 595         rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
 596                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 597
 598         /* set the preamble flag if appropriate */
 599         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 600                 rx_status.flag |= RX_FLAG_SHORTPRE;
 601
 602         if ((unlikely(rx_stats->phy_count > 20))) {
 603                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
 604                                 rx_stats->phy_count);
 605                 return;
 606         }
 607
 608         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 609             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 610                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 611                 return;
 612         }
 613
 614
 615
 616         /* Convert 3945's rssi indicator to dBm */
 617         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
 618
 619         IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
 620                         rx_status.signal, rx_stats_sig_avg,
 621                         rx_stats_noise_diff);
 622
 623         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 624
 625         network_packet = iwl3945_is_network_packet(priv, header);
 626
 627         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
 628                               network_packet ? '*' : ' ',
 629                               le16_to_cpu(rx_hdr->channel),
 630                               rx_status.signal, rx_status.signal,
 631                               rx_status.rate_idx);
 632
 633         iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
 634
 635         if (network_packet) {
 636                 priv->_3945.last_beacon_time =
 637                         le32_to_cpu(rx_end->beacon_timestamp);
 638                 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
 639                 priv->_3945.last_rx_rssi = rx_status.signal;
 640         }
 641
 642         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 643 }
 644
 645 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 646                                      struct iwl_tx_queue *txq,
 647                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
 648 {
 649         int count;
 650         struct iwl_queue *q;
 651         struct iwl3945_tfd *tfd, *tfd_tmp;
 652
 653         q = &txq->q;
 654         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 655         tfd = &tfd_tmp[q->write_ptr];
 656
 657         if (reset)
 658                 memset(tfd, 0, sizeof(*tfd));
 659
 660         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 661
 662         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 663                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 664                           NUM_TFD_CHUNKS);
 665                 return -EINVAL;
 666         }
 667
 668         tfd->tbs[count].addr = cpu_to_le32(addr);
 669         tfd->tbs[count].len = cpu_to_le32(len);
 670
 671         count++;
 672
 673         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 674                                          TFD_CTL_PAD_SET(pad));
 675
 676         return 0;
 677 }
 678
 679 /**
 680  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 681  *
 682  * Does NOT advance any indexes
 683  */
 684 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 685 {
 686         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 687         int index = txq->q.read_ptr;
 688         struct iwl3945_tfd *tfd = &tfd_tmp[index];
 689         struct pci_dev *dev = priv->pci_dev;
 690         int i;
 691         int counter;
 692
 693         /* sanity check */
 694         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 695         if (counter > NUM_TFD_CHUNKS) {
 696                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
 697                 /* @todo issue fatal error, it is quite serious situation */
 698                 return;
 699         }
 700
 701         /* Unmap tx_cmd */
 702         if (counter)
 703                 pci_unmap_single(dev,
 704                                 dma_unmap_addr(&txq->meta[index], mapping),
 705                                 dma_unmap_len(&txq->meta[index], len),
 706                                 PCI_DMA_TODEVICE);
 707
 708         /* unmap chunks if any */
 709
 710         for (i = 1; i < counter; i++)
 711                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
 712                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
 713
 714         /* free SKB */
 715         if (txq->txb) {
 716                 struct sk_buff *skb;
 717
 718                 skb = txq->txb[txq->q.read_ptr].skb;
 719
 720                 /* can be called from irqs-disabled context */
 721                 if (skb) {
 722                         dev_kfree_skb_any(skb);
 723                         txq->txb[txq->q.read_ptr].skb = NULL;
 724                 }
 725         }
 726 }
 727
 728 /**
 729  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 730  *
 731 */
 732 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
 733                                   struct iwl_device_cmd *cmd,
 734                                   struct ieee80211_tx_info *info,
 735                                   struct ieee80211_hdr *hdr,
 736                                   int sta_id, int tx_id)
 737 {
 738         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 739         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
 740         u16 rate_mask;
 741         int rate;
 742         u8 rts_retry_limit;
 743         u8 data_retry_limit;
 744         __le32 tx_flags;
 745         __le16 fc = hdr->frame_control;
 746         struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
 747
 748         rate = iwl3945_rates[rate_index].plcp;
 749         tx_flags = tx_cmd->tx_flags;
 750
 751         /* We need to figure out how to get the sta->supp_rates while
 752          * in this running context */
 753         rate_mask = IWL_RATES_MASK;
 754
 755
 756         /* Set retry limit on DATA packets and Probe Responses*/
 757         if (ieee80211_is_probe_resp(fc))
 758                 data_retry_limit = 3;
 759         else
 760                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 761         tx_cmd->data_retry_limit = data_retry_limit;
 762
 763         if (tx_id >= IWL_CMD_QUEUE_NUM)
 764                 rts_retry_limit = 3;
 765         else
 766                 rts_retry_limit = 7;
 767
 768         if (data_retry_limit < rts_retry_limit)
 769                 rts_retry_limit = data_retry_limit;
 770         tx_cmd->rts_retry_limit = rts_retry_limit;
 771
 772         if (ieee80211_is_mgmt(fc)) {
 773                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 774                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
 775                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 776                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 777                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 778                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
 779                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 780                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
 781                         }
 782                         break;
 783                 default:
 784                         break;
 785                 }
 786         }
 787
 788         tx_cmd->rate = rate;
 789         tx_cmd->tx_flags = tx_flags;
 790
 791         /* OFDM */
 792         tx_cmd->supp_rates[0] =
 793            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 794
 795         /* CCK */
 796         tx_cmd->supp_rates[1] = (rate_mask & 0xF);
 797
 798         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 799                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 800                        tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
 801                        tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
 802 }
 803
 804 static u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate)
 805 {
 806         unsigned long flags_spin;
 807         struct iwl_station_entry *station;
 808
 809         if (sta_id == IWL_INVALID_STATION)
 810                 return IWL_INVALID_STATION;
 811
 812         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 813         station = &priv->stations[sta_id];
 814
 815         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 816         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 817         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 818         iwl_send_add_sta(priv, &station->sta, CMD_ASYNC);
 819         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 820
 821         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
 822                         sta_id, tx_rate);
 823         return sta_id;
 824 }
 825
 826 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 827 {
 828         if (src == IWL_PWR_SRC_VAUX) {
 829                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
 830                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 831                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 832                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 833
 834                         iwl_poll_bit(priv, CSR_GPIO_IN,
 835                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 836                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 837                 }
 838         } else {
 839                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 840                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 841                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 842
 843                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 844                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 845         }
 846
 847         return 0;
 848 }
 849
 850 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 851 {
 852         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
 853         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
 854         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
 855         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
 856                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 857                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 858                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 859                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 860                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 861                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 862                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 863                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 864
 865         /* fake read to flush all prev I/O */
 866         iwl_read_direct32(priv, FH39_RSSR_CTRL);
 867
 868         return 0;
 869 }
 870
 871 static int iwl3945_tx_reset(struct iwl_priv *priv)
 872 {
 873
 874         /* bypass mode */
 875         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
 876
 877         /* RA 0 is active */
 878         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
 879
 880         /* all 6 fifo are active */
 881         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
 882
 883         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
 884         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
 885         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
 886         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
 887
 888         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
 889                              priv->_3945.shared_phys);
 890
 891         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
 892                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
 893                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
 894                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
 895                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
 896                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
 897                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
 898                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
 899
 900
 901         return 0;
 902 }
 903
 904 /**
 905  * iwl3945_txq_ctx_reset - Reset TX queue context
 906  *
 907  * Destroys all DMA structures and initialize them again
 908  */
 909 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
 910 {
 911         int rc;
 912         int txq_id, slots_num;
 913
 914         iwl3945_hw_txq_ctx_free(priv);
 915
 916         /* allocate tx queue structure */
 917         rc = iwl_alloc_txq_mem(priv);
 918         if (rc)
 919                 return rc;
 920
 921         /* Tx CMD queue */
 922         rc = iwl3945_tx_reset(priv);
 923         if (rc)
 924                 goto error;
 925
 926         /* Tx queue(s) */
 927         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
 928                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
 929                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 930                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
 931                                        txq_id);
 932                 if (rc) {
 933                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
 934                         goto error;
 935                 }
 936         }
 937
 938         return rc;
 939
 940  error:
 941         iwl3945_hw_txq_ctx_free(priv);
 942         return rc;
 943 }
 944
 945
 946 /*
 947  * Start up 3945's basic functionality after it has been reset
 948  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 949  * NOTE:  This does not load uCode nor start the embedded processor
 950  */
 951 static int iwl3945_apm_init(struct iwl_priv *priv)
 952 {
 953         int ret = iwl_apm_init(priv);
 954
 955         /* Clear APMG (NIC's internal power management) interrupts */
 956         iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
 957         iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
 958
 959         /* Reset radio chip */
 960         iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
 961         udelay(5);
 962         iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
 963
 964         return ret;
 965 }
 966
 967 static void iwl3945_nic_config(struct iwl_priv *priv)
 968 {
 969         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
 970         unsigned long flags;
 971         u8 rev_id = 0;
 972
 973         spin_lock_irqsave(&priv->lock, flags);
 974
 975         /* Determine HW type */
 976         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
 977
 978         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
 979
 980         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
 981                 IWL_DEBUG_INFO(priv, "RTP type\n");
 982         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
 983                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
 984                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 985                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
 986         } else {
 987                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
 988                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 989                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
 990         }
 991
 992         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
 993                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
 994                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 995                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
 996         } else
 997                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
 998
 999         if ((eeprom->board_revision & 0xF0) == 0xD0) {
1000                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1001                                eeprom->board_revision);
1002                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1003                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1004         } else {
1005                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1006                                eeprom->board_revision);
1007                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1008                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1009         }
1010
1011         if (eeprom->almgor_m_version <= 1) {
1012                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1013                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1014                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1015                                eeprom->almgor_m_version);
1016         } else {
1017                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1018                                eeprom->almgor_m_version);
1019                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1020                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1021         }
1022         spin_unlock_irqrestore(&priv->lock, flags);
1023
1024         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1025                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1026
1027         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1028                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1029 }
1030
1031 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1032 {
1033         int rc;
1034         unsigned long flags;
1035         struct iwl_rx_queue *rxq = &priv->rxq;
1036
1037         spin_lock_irqsave(&priv->lock, flags);
1038         priv->cfg->ops->lib->apm_ops.init(priv);
1039         spin_unlock_irqrestore(&priv->lock, flags);
1040
1041         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1042         if (rc)
1043                 return rc;
1044
1045         priv->cfg->ops->lib->apm_ops.config(priv);
1046
1047         /* Allocate the RX queue, or reset if it is already allocated */
1048         if (!rxq->bd) {
1049                 rc = iwl_rx_queue_alloc(priv);
1050                 if (rc) {
1051                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1052                         return -ENOMEM;
1053                 }
1054         } else
1055                 iwl3945_rx_queue_reset(priv, rxq);
1056
1057         iwl3945_rx_replenish(priv);
1058
1059         iwl3945_rx_init(priv, rxq);
1060
1061
1062         /* Look at using this instead:
1063         rxq->need_update = 1;
1064         iwl_rx_queue_update_write_ptr(priv, rxq);
1065         */
1066
1067         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1068
1069         rc = iwl3945_txq_ctx_reset(priv);
1070         if (rc)
1071                 return rc;
1072
1073         set_bit(STATUS_INIT, &priv->status);
1074
1075         return 0;
1076 }
1077
1078 /**
1079  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1080  *
1081  * Destroy all TX DMA queues and structures
1082  */
1083 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1084 {
1085         int txq_id;
1086
1087         /* Tx queues */
1088         if (priv->txq)
1089                 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1090                      txq_id++)
1091                         if (txq_id == IWL_CMD_QUEUE_NUM)
1092                                 iwl_cmd_queue_free(priv);
1093                         else
1094                                 iwl_tx_queue_free(priv, txq_id);
1095
1096         /* free tx queue structure */
1097         iwl_free_txq_mem(priv);
1098 }
1099
1100 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1101 {
1102         int txq_id;
1103
1104         /* stop SCD */
1105         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1106         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1107
1108         /* reset TFD queues */
1109         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1110                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1111                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1112                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1113                                 1000);
1114         }
1115
1116         iwl3945_hw_txq_ctx_free(priv);
1117 }
1118
1119 /**
1120  * iwl3945_hw_reg_adjust_power_by_temp
1121  * return index delta into power gain settings table
1122 */
1123 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1124 {
1125         return (new_reading - old_reading) * (-11) / 100;
1126 }
1127
1128 /**
1129  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1130  */
1131 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1132 {
1133         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1134 }
1135
1136 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1137 {
1138         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1139 }
1140
1141 /**
1142  * iwl3945_hw_reg_txpower_get_temperature
1143  * get the current temperature by reading from NIC
1144 */
1145 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1146 {
1147         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1148         int temperature;
1149
1150         temperature = iwl3945_hw_get_temperature(priv);
1151
1152         /* driver's okay range is -260 to +25.
1153          *   human readable okay range is 0 to +285 */
1154         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1155
1156         /* handle insane temp reading */
1157         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1158                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1159
1160                 /* if really really hot(?),
1161                  *   substitute the 3rd band/group's temp measured at factory */
1162                 if (priv->last_temperature > 100)
1163                         temperature = eeprom->groups[2].temperature;
1164                 else /* else use most recent "sane" value from driver */
1165                         temperature = priv->last_temperature;
1166         }
1167
1168         return temperature;     /* raw, not "human readable" */
1169 }
1170
1171 /* Adjust Txpower only if temperature variance is greater than threshold.
1172  *
1173  * Both are lower than older versions' 9 degrees */
1174 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1175
1176 /**
1177  * is_temp_calib_needed - determines if new calibration is needed
1178  *
1179  * records new temperature in tx_mgr->temperature.
1180  * replaces tx_mgr->last_temperature *only* if calib needed
1181  *    (assumes caller will actually do the calibration!). */
1182 static int is_temp_calib_needed(struct iwl_priv *priv)
1183 {
1184         int temp_diff;
1185
1186         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1187         temp_diff = priv->temperature - priv->last_temperature;
1188
1189         /* get absolute value */
1190         if (temp_diff < 0) {
1191                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1192                 temp_diff = -temp_diff;
1193         } else if (temp_diff == 0)
1194                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1195         else
1196                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1197
1198         /* if we don't need calibration, *don't* update last_temperature */
1199         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1200                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1201                 return 0;
1202         }
1203
1204         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1205
1206         /* assume that caller will actually do calib ...
1207          *   update the "last temperature" value */
1208         priv->last_temperature = priv->temperature;
1209         return 1;
1210 }
1211
1212 #define IWL_MAX_GAIN_ENTRIES 78
1213 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1214 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1215
1216 /* radio and DSP power table, each step is 1/2 dB.
1217  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1218 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1219         {
1220          {251, 127},            /* 2.4 GHz, highest power */
1221          {251, 127},
1222          {251, 127},
1223          {251, 127},
1224          {251, 125},
1225          {251, 110},
1226          {251, 105},
1227          {251, 98},
1228          {187, 125},
1229          {187, 115},
1230          {187, 108},
1231          {187, 99},
1232          {243, 119},
1233          {243, 111},
1234          {243, 105},
1235          {243, 97},
1236          {243, 92},
1237          {211, 106},
1238          {211, 100},
1239          {179, 120},
1240          {179, 113},
1241          {179, 107},
1242          {147, 125},
1243          {147, 119},
1244          {147, 112},
1245          {147, 106},
1246          {147, 101},
1247          {147, 97},
1248          {147, 91},
1249          {115, 107},
1250          {235, 121},
1251          {235, 115},
1252          {235, 109},
1253          {203, 127},
1254          {203, 121},
1255          {203, 115},
1256          {203, 108},
1257          {203, 102},
1258          {203, 96},
1259          {203, 92},
1260          {171, 110},
1261          {171, 104},
1262          {171, 98},
1263          {139, 116},
1264          {227, 125},
1265          {227, 119},
1266          {227, 113},
1267          {227, 107},
1268          {227, 101},
1269          {227, 96},
1270          {195, 113},
1271          {195, 106},
1272          {195, 102},
1273          {195, 95},
1274          {163, 113},
1275          {163, 106},
1276          {163, 102},
1277          {163, 95},
1278          {131, 113},
1279          {131, 106},
1280          {131, 102},
1281          {131, 95},
1282          {99, 113},
1283          {99, 106},
1284          {99, 102},
1285          {99, 95},
1286          {67, 113},
1287          {67, 106},
1288          {67, 102},
1289          {67, 95},
1290          {35, 113},
1291          {35, 106},
1292          {35, 102},
1293          {35, 95},
1294          {3, 113},
1295          {3, 106},
1296          {3, 102},
1297          {3, 95} },             /* 2.4 GHz, lowest power */
1298         {
1299          {251, 127},            /* 5.x GHz, highest power */
1300          {251, 120},
1301          {251, 114},
1302          {219, 119},
1303          {219, 101},
1304          {187, 113},
1305          {187, 102},
1306          {155, 114},
1307          {155, 103},
1308          {123, 117},
1309          {123, 107},
1310          {123, 99},
1311          {123, 92},
1312          {91, 108},
1313          {59, 125},
1314          {59, 118},
1315          {59, 109},
1316          {59, 102},
1317          {59, 96},
1318          {59, 90},
1319          {27, 104},
1320          {27, 98},
1321          {27, 92},
1322          {115, 118},
1323          {115, 111},
1324          {115, 104},
1325          {83, 126},
1326          {83, 121},
1327          {83, 113},
1328          {83, 105},
1329          {83, 99},
1330          {51, 118},
1331          {51, 111},
1332          {51, 104},
1333          {51, 98},
1334          {19, 116},
1335          {19, 109},
1336          {19, 102},
1337          {19, 98},
1338          {19, 93},
1339          {171, 113},
1340          {171, 107},
1341          {171, 99},
1342          {139, 120},
1343          {139, 113},
1344          {139, 107},
1345          {139, 99},
1346          {107, 120},
1347          {107, 113},
1348          {107, 107},
1349          {107, 99},
1350          {75, 120},
1351          {75, 113},
1352          {75, 107},
1353          {75, 99},
1354          {43, 120},
1355          {43, 113},
1356          {43, 107},
1357          {43, 99},
1358          {11, 120},
1359          {11, 113},
1360          {11, 107},
1361          {11, 99},
1362          {131, 107},
1363          {131, 99},
1364          {99, 120},
1365          {99, 113},
1366          {99, 107},
1367          {99, 99},
1368          {67, 120},
1369          {67, 113},
1370          {67, 107},
1371          {67, 99},
1372          {35, 120},
1373          {35, 113},
1374          {35, 107},
1375          {35, 99},
1376          {3, 120} }             /* 5.x GHz, lowest power */
1377 };
1378
1379 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1380 {
1381         if (index < 0)
1382                 return 0;
1383         if (index >= IWL_MAX_GAIN_ENTRIES)
1384                 return IWL_MAX_GAIN_ENTRIES - 1;
1385         return (u8) index;
1386 }
1387
1388 /* Kick off thermal recalibration check every 60 seconds */
1389 #define REG_RECALIB_PERIOD (60)
1390
1391 /**
1392  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1393  *
1394  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1395  * or 6 Mbit (OFDM) rates.
1396  */
1397 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1398                                s32 rate_index, const s8 *clip_pwrs,
1399                                struct iwl_channel_info *ch_info,
1400                                int band_index)
1401 {
1402         struct iwl3945_scan_power_info *scan_power_info;
1403         s8 power;
1404         u8 power_index;
1405
1406         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1407
1408         /* use this channel group's 6Mbit clipping/saturation pwr,
1409          *   but cap at regulatory scan power restriction (set during init
1410          *   based on eeprom channel data) for this channel.  */
1411         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1412
1413         /* further limit to user's max power preference.
1414          * FIXME:  Other spectrum management power limitations do not
1415          *   seem to apply?? */
1416         power = min(power, priv->tx_power_user_lmt);
1417         scan_power_info->requested_power = power;
1418
1419         /* find difference between new scan *power* and current "normal"
1420          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1421          *   current "normal" temperature-compensated Tx power *index* for
1422          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1423          *   *index*. */
1424         power_index = ch_info->power_info[rate_index].power_table_index
1425             - (power - ch_info->power_info
1426                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1427
1428         /* store reference index that we use when adjusting *all* scan
1429          *   powers.  So we can accommodate user (all channel) or spectrum
1430          *   management (single channel) power changes "between" temperature
1431          *   feedback compensation procedures.
1432          * don't force fit this reference index into gain table; it may be a
1433          *   negative number.  This will help avoid errors when we're at
1434          *   the lower bounds (highest gains, for warmest temperatures)
1435          *   of the table. */
1436
1437         /* don't exceed table bounds for "real" setting */
1438         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1439
1440         scan_power_info->power_table_index = power_index;
1441         scan_power_info->tpc.tx_gain =
1442             power_gain_table[band_index][power_index].tx_gain;
1443         scan_power_info->tpc.dsp_atten =
1444             power_gain_table[band_index][power_index].dsp_atten;
1445 }
1446
1447 /**
1448  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1449  *
1450  * Configures power settings for all rates for the current channel,
1451  * using values from channel info struct, and send to NIC
1452  */
1453 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1454 {
1455         int rate_idx, i;
1456         const struct iwl_channel_info *ch_info = NULL;
1457         struct iwl3945_txpowertable_cmd txpower = {
1458                 .channel = priv->active_rxon.channel,
1459         };
1460
1461         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1462         ch_info = iwl_get_channel_info(priv,
1463                                        priv->band,
1464                                        le16_to_cpu(priv->active_rxon.channel));
1465         if (!ch_info) {
1466                 IWL_ERR(priv,
1467                         "Failed to get channel info for channel %d [%d]\n",
1468                         le16_to_cpu(priv->active_rxon.channel), priv->band);
1469                 return -EINVAL;
1470         }
1471
1472         if (!is_channel_valid(ch_info)) {
1473                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1474                                 "non-Tx channel.\n");
1475                 return 0;
1476         }
1477
1478         /* fill cmd with power settings for all rates for current channel */
1479         /* Fill OFDM rate */
1480         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1481              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1482
1483                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1484                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1485
1486                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1487                                 le16_to_cpu(txpower.channel),
1488                                 txpower.band,
1489                                 txpower.power[i].tpc.tx_gain,
1490                                 txpower.power[i].tpc.dsp_atten,
1491                                 txpower.power[i].rate);
1492         }
1493         /* Fill CCK rates */
1494         for (rate_idx = IWL_FIRST_CCK_RATE;
1495              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1496                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1497                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1498
1499                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1500                                 le16_to_cpu(txpower.channel),
1501                                 txpower.band,
1502                                 txpower.power[i].tpc.tx_gain,
1503                                 txpower.power[i].tpc.dsp_atten,
1504                                 txpower.power[i].rate);
1505         }
1506
1507         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1508                                 sizeof(struct iwl3945_txpowertable_cmd),
1509                                 &txpower);
1510
1511 }
1512
1513 /**
1514  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1515  * @ch_info: Channel to update.  Uses power_info.requested_power.
1516  *
1517  * Replace requested_power and base_power_index ch_info fields for
1518  * one channel.
1519  *
1520  * Called if user or spectrum management changes power preferences.
1521  * Takes into account h/w and modulation limitations (clip power).
1522  *
1523  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1524  *
1525  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1526  *       properly fill out the scan powers, and actual h/w gain settings,
1527  *       and send changes to NIC
1528  */
1529 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1530                              struct iwl_channel_info *ch_info)
1531 {
1532         struct iwl3945_channel_power_info *power_info;
1533         int power_changed = 0;
1534         int i;
1535         const s8 *clip_pwrs;
1536         int power;
1537
1538         /* Get this chnlgrp's rate-to-max/clip-powers table */
1539         clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1540
1541         /* Get this channel's rate-to-current-power settings table */
1542         power_info = ch_info->power_info;
1543
1544         /* update OFDM Txpower settings */
1545         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1546              i++, ++power_info) {
1547                 int delta_idx;
1548
1549                 /* limit new power to be no more than h/w capability */
1550                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1551                 if (power == power_info->requested_power)
1552                         continue;
1553
1554                 /* find difference between old and new requested powers,
1555                  *    update base (non-temp-compensated) power index */
1556                 delta_idx = (power - power_info->requested_power) * 2;
1557                 power_info->base_power_index -= delta_idx;
1558
1559                 /* save new requested power value */
1560                 power_info->requested_power = power;
1561
1562                 power_changed = 1;
1563         }
1564
1565         /* update CCK Txpower settings, based on OFDM 12M setting ...
1566          *    ... all CCK power settings for a given channel are the *same*. */
1567         if (power_changed) {
1568                 power =
1569                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1570                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1571
1572                 /* do all CCK rates' iwl3945_channel_power_info structures */
1573                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1574                         power_info->requested_power = power;
1575                         power_info->base_power_index =
1576                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1577                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1578                         ++power_info;
1579                 }
1580         }
1581
1582         return 0;
1583 }
1584
1585 /**
1586  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1587  *
1588  * NOTE: Returned power limit may be less (but not more) than requested,
1589  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1590  *       (no consideration for h/w clipping limitations).
1591  */
1592 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1593 {
1594         s8 max_power;
1595
1596 #if 0
1597         /* if we're using TGd limits, use lower of TGd or EEPROM */
1598         if (ch_info->tgd_data.max_power != 0)
1599                 max_power = min(ch_info->tgd_data.max_power,
1600                                 ch_info->eeprom.max_power_avg);
1601
1602         /* else just use EEPROM limits */
1603         else
1604 #endif
1605                 max_power = ch_info->eeprom.max_power_avg;
1606
1607         return min(max_power, ch_info->max_power_avg);
1608 }
1609
1610 /**
1611  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1612  *
1613  * Compensate txpower settings of *all* channels for temperature.
1614  * This only accounts for the difference between current temperature
1615  *   and the factory calibration temperatures, and bases the new settings
1616  *   on the channel's base_power_index.
1617  *
1618  * If RxOn is "associated", this sends the new Txpower to NIC!
1619  */
1620 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1621 {
1622         struct iwl_channel_info *ch_info = NULL;
1623         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1624         int delta_index;
1625         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1626         u8 a_band;
1627         u8 rate_index;
1628         u8 scan_tbl_index;
1629         u8 i;
1630         int ref_temp;
1631         int temperature = priv->temperature;
1632
1633         if (priv->disable_tx_power_cal ||
1634             test_bit(STATUS_SCANNING, &priv->status)) {
1635                 /* do not perform tx power calibration */
1636                 return 0;
1637         }
1638         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1639         for (i = 0; i < priv->channel_count; i++) {
1640                 ch_info = &priv->channel_info[i];
1641                 a_band = is_channel_a_band(ch_info);
1642
1643                 /* Get this chnlgrp's factory calibration temperature */
1644                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1645                     temperature;
1646
1647                 /* get power index adjustment based on current and factory
1648                  * temps */
1649                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1650                                                               ref_temp);
1651
1652                 /* set tx power value for all rates, OFDM and CCK */
1653                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1654                      rate_index++) {
1655                         int power_idx =
1656                             ch_info->power_info[rate_index].base_power_index;
1657
1658                         /* temperature compensate */
1659                         power_idx += delta_index;
1660
1661                         /* stay within table range */
1662                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1663                         ch_info->power_info[rate_index].
1664                             power_table_index = (u8) power_idx;
1665                         ch_info->power_info[rate_index].tpc =
1666                             power_gain_table[a_band][power_idx];
1667                 }
1668
1669                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1670                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1671
1672                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1673                 for (scan_tbl_index = 0;
1674                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1675                         s32 actual_index = (scan_tbl_index == 0) ?
1676                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1677                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1678                                            actual_index, clip_pwrs,
1679                                            ch_info, a_band);
1680                 }
1681         }
1682
1683         /* send Txpower command for current channel to ucode */
1684         return priv->cfg->ops->lib->send_tx_power(priv);
1685 }
1686
1687 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1688 {
1689         struct iwl_channel_info *ch_info;
1690         s8 max_power;
1691         u8 a_band;
1692         u8 i;
1693
1694         if (priv->tx_power_user_lmt == power) {
1695                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1696                                 "limit: %ddBm.\n", power);
1697                 return 0;
1698         }
1699
1700         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1701         priv->tx_power_user_lmt = power;
1702
1703         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1704
1705         for (i = 0; i < priv->channel_count; i++) {
1706                 ch_info = &priv->channel_info[i];
1707                 a_band = is_channel_a_band(ch_info);
1708
1709                 /* find minimum power of all user and regulatory constraints
1710                  *    (does not consider h/w clipping limitations) */
1711                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1712                 max_power = min(power, max_power);
1713                 if (max_power != ch_info->curr_txpow) {
1714                         ch_info->curr_txpow = max_power;
1715
1716                         /* this considers the h/w clipping limitations */
1717                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1718                 }
1719         }
1720
1721         /* update txpower settings for all channels,
1722          *   send to NIC if associated. */
1723         is_temp_calib_needed(priv);
1724         iwl3945_hw_reg_comp_txpower_temp(priv);
1725
1726         return 0;
1727 }
1728
1729 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1730 {
1731         int rc = 0;
1732         struct iwl_rx_packet *pkt;
1733         struct iwl3945_rxon_assoc_cmd rxon_assoc;
1734         struct iwl_host_cmd cmd = {
1735                 .id = REPLY_RXON_ASSOC,
1736                 .len = sizeof(rxon_assoc),
1737                 .flags = CMD_WANT_SKB,
1738                 .data = &rxon_assoc,
1739         };
1740         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1741         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1742
1743         if ((rxon1->flags == rxon2->flags) &&
1744             (rxon1->filter_flags == rxon2->filter_flags) &&
1745             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1746             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1747                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1748                 return 0;
1749         }
1750
1751         rxon_assoc.flags = priv->staging_rxon.flags;
1752         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1753         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1754         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1755         rxon_assoc.reserved = 0;
1756
1757         rc = iwl_send_cmd_sync(priv, &cmd);
1758         if (rc)
1759                 return rc;
1760
1761         pkt = (struct iwl_rx_packet *)cmd.reply_page;
1762         if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1763                 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1764                 rc = -EIO;
1765         }
1766
1767         iwl_free_pages(priv, cmd.reply_page);
1768
1769         return rc;
1770 }
1771
1772 /**
1773  * iwl3945_commit_rxon - commit staging_rxon to hardware
1774  *
1775  * The RXON command in staging_rxon is committed to the hardware and
1776  * the active_rxon structure is updated with the new data.  This
1777  * function correctly transitions out of the RXON_ASSOC_MSK state if
1778  * a HW tune is required based on the RXON structure changes.
1779  */
1780 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1781 {
1782         /* cast away the const for active_rxon in this function */
1783         struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1784         struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1785         int rc = 0;
1786         bool new_assoc =
1787                 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1788
1789         if (!iwl_is_alive(priv))
1790                 return -1;
1791
1792         /* always get timestamp with Rx frame */
1793         staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1794
1795         /* select antenna */
1796         staging_rxon->flags &=
1797             ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1798         staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1799
1800         rc = iwl_check_rxon_cmd(priv);
1801         if (rc) {
1802                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
1803                 return -EINVAL;
1804         }
1805
1806         /* If we don't need to send a full RXON, we can use
1807          * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1808          * and other flags for the current radio configuration. */
1809         if (!iwl_full_rxon_required(priv)) {
1810                 rc = iwl_send_rxon_assoc(priv);
1811                 if (rc) {
1812                         IWL_ERR(priv, "Error setting RXON_ASSOC "
1813                                   "configuration (%d).\n", rc);
1814                         return rc;
1815                 }
1816
1817                 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1818
1819                 return 0;
1820         }
1821
1822         /* If we are currently associated and the new config requires
1823          * an RXON_ASSOC and the new config wants the associated mask enabled,
1824          * we must clear the associated from the active configuration
1825          * before we apply the new config */
1826         if (iwl_is_associated(priv) && new_assoc) {
1827                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1828                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1829
1830                 /*
1831                  * reserved4 and 5 could have been filled by the iwlcore code.
1832                  * Let's clear them before pushing to the 3945.
1833                  */
1834                 active_rxon->reserved4 = 0;
1835                 active_rxon->reserved5 = 0;
1836                 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1837                                       sizeof(struct iwl3945_rxon_cmd),
1838                                       &priv->active_rxon);
1839
1840                 /* If the mask clearing failed then we set
1841                  * active_rxon back to what it was previously */
1842                 if (rc) {
1843                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1844                         IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1845                                   "configuration (%d).\n", rc);
1846                         return rc;
1847                 }
1848                 iwl_clear_ucode_stations(priv);
1849                 iwl_restore_stations(priv);
1850         }
1851
1852         IWL_DEBUG_INFO(priv, "Sending RXON\n"
1853                        "* with%s RXON_FILTER_ASSOC_MSK\n"
1854                        "* channel = %d\n"
1855                        "* bssid = %pM\n",
1856                        (new_assoc ? "" : "out"),
1857                        le16_to_cpu(staging_rxon->channel),
1858                        staging_rxon->bssid_addr);
1859
1860         /*
1861          * reserved4 and 5 could have been filled by the iwlcore code.
1862          * Let's clear them before pushing to the 3945.
1863          */
1864         staging_rxon->reserved4 = 0;
1865         staging_rxon->reserved5 = 0;
1866
1867         iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1868
1869         /* Apply the new configuration */
1870         rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1871                               sizeof(struct iwl3945_rxon_cmd),
1872                               staging_rxon);
1873         if (rc) {
1874                 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1875                 return rc;
1876         }
1877
1878         memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1879
1880         if (!new_assoc) {
1881                 iwl_clear_ucode_stations(priv);
1882                 iwl_restore_stations(priv);
1883         }
1884
1885         /* If we issue a new RXON command which required a tune then we must
1886          * send a new TXPOWER command or we won't be able to Tx any frames */
1887         rc = priv->cfg->ops->lib->send_tx_power(priv);
1888         if (rc) {
1889                 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1890                 return rc;
1891         }
1892
1893         /* Init the hardware's rate fallback order based on the band */
1894         rc = iwl3945_init_hw_rate_table(priv);
1895         if (rc) {
1896                 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1897                 return -EIO;
1898         }
1899
1900         return 0;
1901 }
1902
1903 /**
1904  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
1905  *
1906  * -- reset periodic timer
1907  * -- see if temp has changed enough to warrant re-calibration ... if so:
1908  *     -- correct coeffs for temp (can reset temp timer)
1909  *     -- save this temp as "last",
1910  *     -- send new set of gain settings to NIC
1911  * NOTE:  This should continue working, even when we're not associated,
1912  *   so we can keep our internal table of scan powers current. */
1913 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1914 {
1915         /* This will kick in the "brute force"
1916          * iwl3945_hw_reg_comp_txpower_temp() below */
1917         if (!is_temp_calib_needed(priv))
1918                 goto reschedule;
1919
1920         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1921          * This is based *only* on current temperature,
1922          * ignoring any previous power measurements */
1923         iwl3945_hw_reg_comp_txpower_temp(priv);
1924
1925  reschedule:
1926         queue_delayed_work(priv->workqueue,
1927                            &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
1928 }
1929
1930 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1931 {
1932         struct iwl_priv *priv = container_of(work, struct iwl_priv,
1933                                              _3945.thermal_periodic.work);
1934
1935         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1936                 return;
1937
1938         mutex_lock(&priv->mutex);
1939         iwl3945_reg_txpower_periodic(priv);
1940         mutex_unlock(&priv->mutex);
1941 }
1942
1943 /**
1944  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1945  *                                 for the channel.
1946  *
1947  * This function is used when initializing channel-info structs.
1948  *
1949  * NOTE: These channel groups do *NOT* match the bands above!
1950  *       These channel groups are based on factory-tested channels;
1951  *       on A-band, EEPROM's "group frequency" entries represent the top
1952  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
1953  */
1954 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
1955                                        const struct iwl_channel_info *ch_info)
1956 {
1957         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1958         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
1959         u8 group;
1960         u16 group_index = 0;    /* based on factory calib frequencies */
1961         u8 grp_channel;
1962
1963         /* Find the group index for the channel ... don't use index 1(?) */
1964         if (is_channel_a_band(ch_info)) {
1965                 for (group = 1; group < 5; group++) {
1966                         grp_channel = ch_grp[group].group_channel;
1967                         if (ch_info->channel <= grp_channel) {
1968                                 group_index = group;
1969                                 break;
1970                         }
1971                 }
1972                 /* group 4 has a few channels *above* its factory cal freq */
1973                 if (group == 5)
1974                         group_index = 4;
1975         } else
1976                 group_index = 0;        /* 2.4 GHz, group 0 */
1977
1978         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
1979                         group_index);
1980         return group_index;
1981 }
1982
1983 /**
1984  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
1985  *
1986  * Interpolate to get nominal (i.e. at factory calibration temperature) index
1987  *   into radio/DSP gain settings table for requested power.
1988  */
1989 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
1990                                        s8 requested_power,
1991                                        s32 setting_index, s32 *new_index)
1992 {
1993         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
1994         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1995         s32 index0, index1;
1996         s32 power = 2 * requested_power;
1997         s32 i;
1998         const struct iwl3945_eeprom_txpower_sample *samples;
1999         s32 gains0, gains1;
2000         s32 res;
2001         s32 denominator;
2002
2003         chnl_grp = &eeprom->groups[setting_index];
2004         samples = chnl_grp->samples;
2005         for (i = 0; i < 5; i++) {
2006                 if (power == samples[i].power) {
2007                         *new_index = samples[i].gain_index;
2008                         return 0;
2009                 }
2010         }
2011
2012         if (power > samples[1].power) {
2013                 index0 = 0;
2014                 index1 = 1;
2015         } else if (power > samples[2].power) {
2016                 index0 = 1;
2017                 index1 = 2;
2018         } else if (power > samples[3].power) {
2019                 index0 = 2;
2020                 index1 = 3;
2021         } else {
2022                 index0 = 3;
2023                 index1 = 4;
2024         }
2025
2026         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2027         if (denominator == 0)
2028                 return -EINVAL;
2029         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2030         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2031         res = gains0 + (gains1 - gains0) *
2032             ((s32) power - (s32) samples[index0].power) / denominator +
2033             (1 << 18);
2034         *new_index = res >> 19;
2035         return 0;
2036 }
2037
2038 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2039 {
2040         u32 i;
2041         s32 rate_index;
2042         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2043         const struct iwl3945_eeprom_txpower_group *group;
2044
2045         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2046
2047         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2048                 s8 *clip_pwrs;  /* table of power levels for each rate */
2049                 s8 satur_pwr;   /* saturation power for each chnl group */
2050                 group = &eeprom->groups[i];
2051
2052                 /* sanity check on factory saturation power value */
2053                 if (group->saturation_power < 40) {
2054                         IWL_WARN(priv, "Error: saturation power is %d, "
2055                                     "less than minimum expected 40\n",
2056                                     group->saturation_power);
2057                         return;
2058                 }
2059
2060                 /*
2061                  * Derive requested power levels for each rate, based on
2062                  *   hardware capabilities (saturation power for band).
2063                  * Basic value is 3dB down from saturation, with further
2064                  *   power reductions for highest 3 data rates.  These
2065                  *   backoffs provide headroom for high rate modulation
2066                  *   power peaks, without too much distortion (clipping).
2067                  */
2068                 /* we'll fill in this array with h/w max power levels */
2069                 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
2070
2071                 /* divide factory saturation power by 2 to find -3dB level */
2072                 satur_pwr = (s8) (group->saturation_power >> 1);
2073
2074                 /* fill in channel group's nominal powers for each rate */
2075                 for (rate_index = 0;
2076                      rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
2077                         switch (rate_index) {
2078                         case IWL_RATE_36M_INDEX_TABLE:
2079                                 if (i == 0)     /* B/G */
2080                                         *clip_pwrs = satur_pwr;
2081                                 else    /* A */
2082                                         *clip_pwrs = satur_pwr - 5;
2083                                 break;
2084                         case IWL_RATE_48M_INDEX_TABLE:
2085                                 if (i == 0)
2086                                         *clip_pwrs = satur_pwr - 7;
2087                                 else
2088                                         *clip_pwrs = satur_pwr - 10;
2089                                 break;
2090                         case IWL_RATE_54M_INDEX_TABLE:
2091                                 if (i == 0)
2092                                         *clip_pwrs = satur_pwr - 9;
2093                                 else
2094                                         *clip_pwrs = satur_pwr - 12;
2095                                 break;
2096                         default:
2097                                 *clip_pwrs = satur_pwr;
2098                                 break;
2099                         }
2100                 }
2101         }
2102 }
2103
2104 /**
2105  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2106  *
2107  * Second pass (during init) to set up priv->channel_info
2108  *
2109  * Set up Tx-power settings in our channel info database for each VALID
2110  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2111  * and current temperature.
2112  *
2113  * Since this is based on current temperature (at init time), these values may
2114  * not be valid for very long, but it gives us a starting/default point,
2115  * and allows us to active (i.e. using Tx) scan.
2116  *
2117  * This does *not* write values to NIC, just sets up our internal table.
2118  */
2119 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2120 {
2121         struct iwl_channel_info *ch_info = NULL;
2122         struct iwl3945_channel_power_info *pwr_info;
2123         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2124         int delta_index;
2125         u8 rate_index;
2126         u8 scan_tbl_index;
2127         const s8 *clip_pwrs;    /* array of power levels for each rate */
2128         u8 gain, dsp_atten;
2129         s8 power;
2130         u8 pwr_index, base_pwr_index, a_band;
2131         u8 i;
2132         int temperature;
2133
2134         /* save temperature reference,
2135          *   so we can determine next time to calibrate */
2136         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2137         priv->last_temperature = temperature;
2138
2139         iwl3945_hw_reg_init_channel_groups(priv);
2140
2141         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2142         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2143              i++, ch_info++) {
2144                 a_band = is_channel_a_band(ch_info);
2145                 if (!is_channel_valid(ch_info))
2146                         continue;
2147
2148                 /* find this channel's channel group (*not* "band") index */
2149                 ch_info->group_index =
2150                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2151
2152                 /* Get this chnlgrp's rate->max/clip-powers table */
2153                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
2154
2155                 /* calculate power index *adjustment* value according to
2156                  *  diff between current temperature and factory temperature */
2157                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2158                                 eeprom->groups[ch_info->group_index].
2159                                 temperature);
2160
2161                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2162                                 ch_info->channel, delta_index, temperature +
2163                                 IWL_TEMP_CONVERT);
2164
2165                 /* set tx power value for all OFDM rates */
2166                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2167                      rate_index++) {
2168                         s32 uninitialized_var(power_idx);
2169                         int rc;
2170
2171                         /* use channel group's clip-power table,
2172                          *   but don't exceed channel's max power */
2173                         s8 pwr = min(ch_info->max_power_avg,
2174                                      clip_pwrs[rate_index]);
2175
2176                         pwr_info = &ch_info->power_info[rate_index];
2177
2178                         /* get base (i.e. at factory-measured temperature)
2179                          *    power table index for this rate's power */
2180                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2181                                                          ch_info->group_index,
2182                                                          &power_idx);
2183                         if (rc) {
2184                                 IWL_ERR(priv, "Invalid power index\n");
2185                                 return rc;
2186                         }
2187                         pwr_info->base_power_index = (u8) power_idx;
2188
2189                         /* temperature compensate */
2190                         power_idx += delta_index;
2191
2192                         /* stay within range of gain table */
2193                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2194
2195                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2196                         pwr_info->requested_power = pwr;
2197                         pwr_info->power_table_index = (u8) power_idx;
2198                         pwr_info->tpc.tx_gain =
2199                             power_gain_table[a_band][power_idx].tx_gain;
2200                         pwr_info->tpc.dsp_atten =
2201                             power_gain_table[a_band][power_idx].dsp_atten;
2202                 }
2203
2204                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2205                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2206                 power = pwr_info->requested_power +
2207                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2208                 pwr_index = pwr_info->power_table_index +
2209                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2210                 base_pwr_index = pwr_info->base_power_index +
2211                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2212
2213                 /* stay within table range */
2214                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2215                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2216                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2217
2218                 /* fill each CCK rate's iwl3945_channel_power_info structure
2219                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2220                  * NOTE:  CCK rates start at end of OFDM rates! */
2221                 for (rate_index = 0;
2222                      rate_index < IWL_CCK_RATES; rate_index++) {
2223                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2224                         pwr_info->requested_power = power;
2225                         pwr_info->power_table_index = pwr_index;
2226                         pwr_info->base_power_index = base_pwr_index;
2227                         pwr_info->tpc.tx_gain = gain;
2228                         pwr_info->tpc.dsp_atten = dsp_atten;
2229                 }
2230
2231                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2232                 for (scan_tbl_index = 0;
2233                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2234                         s32 actual_index = (scan_tbl_index == 0) ?
2235                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2236                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2237                                 actual_index, clip_pwrs, ch_info, a_band);
2238                 }
2239         }
2240
2241         return 0;
2242 }
2243
2244 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2245 {
2246         int rc;
2247
2248         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2249         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2250                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2251         if (rc < 0)
2252                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2253
2254         return 0;
2255 }
2256
2257 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2258 {
2259         int txq_id = txq->q.id;
2260
2261         struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
2262
2263         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2264
2265         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2266         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2267
2268         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2269                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2270                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2271                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2272                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2273                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2274
2275         /* fake read to flush all prev. writes */
2276         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2277
2278         return 0;
2279 }
2280
2281 /*
2282  * HCMD utils
2283  */
2284 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2285 {
2286         switch (cmd_id) {
2287         case REPLY_RXON:
2288                 return sizeof(struct iwl3945_rxon_cmd);
2289         case POWER_TABLE_CMD:
2290                 return sizeof(struct iwl3945_powertable_cmd);
2291         default:
2292                 return len;
2293         }
2294 }
2295
2296
2297 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2298 {
2299         struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2300         addsta->mode = cmd->mode;
2301         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2302         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2303         addsta->station_flags = cmd->station_flags;
2304         addsta->station_flags_msk = cmd->station_flags_msk;
2305         addsta->tid_disable_tx = cpu_to_le16(0);
2306         addsta->rate_n_flags = cmd->rate_n_flags;
2307         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2308         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2309         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2310
2311         return (u16)sizeof(struct iwl3945_addsta_cmd);
2312 }
2313
2314 static int iwl3945_manage_ibss_station(struct iwl_priv *priv,
2315                                        struct ieee80211_vif *vif, bool add)
2316 {
2317         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2318         int ret;
2319
2320         if (add) {
2321                 ret = iwl_add_bssid_station(priv, vif->bss_conf.bssid, false,
2322                                             &vif_priv->ibss_bssid_sta_id);
2323                 if (ret)
2324                         return ret;
2325
2326                 iwl3945_sync_sta(priv, vif_priv->ibss_bssid_sta_id,
2327                                  (priv->band == IEEE80211_BAND_5GHZ) ?
2328                                  IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP);
2329                 iwl3945_rate_scale_init(priv->hw, vif_priv->ibss_bssid_sta_id);
2330
2331                 return 0;
2332         }
2333
2334         return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
2335                                   vif->bss_conf.bssid);
2336 }
2337
2338 /**
2339  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2340  */
2341 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2342 {
2343         int rc, i, index, prev_index;
2344         struct iwl3945_rate_scaling_cmd rate_cmd = {
2345                 .reserved = {0, 0, 0},
2346         };
2347         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2348
2349         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2350                 index = iwl3945_rates[i].table_rs_index;
2351
2352                 table[index].rate_n_flags =
2353                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2354                 table[index].try_cnt = priv->retry_rate;
2355                 prev_index = iwl3945_get_prev_ieee_rate(i);
2356                 table[index].next_rate_index =
2357                                 iwl3945_rates[prev_index].table_rs_index;
2358         }
2359
2360         switch (priv->band) {
2361         case IEEE80211_BAND_5GHZ:
2362                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2363                 /* If one of the following CCK rates is used,
2364                  * have it fall back to the 6M OFDM rate */
2365                 for (i = IWL_RATE_1M_INDEX_TABLE;
2366                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2367                         table[i].next_rate_index =
2368                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2369
2370                 /* Don't fall back to CCK rates */
2371                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2372                                                 IWL_RATE_9M_INDEX_TABLE;
2373
2374                 /* Don't drop out of OFDM rates */
2375                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2376                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2377                 break;
2378
2379         case IEEE80211_BAND_2GHZ:
2380                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2381                 /* If an OFDM rate is used, have it fall back to the
2382                  * 1M CCK rates */
2383
2384                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2385                     iwl_is_associated(priv)) {
2386
2387                         index = IWL_FIRST_CCK_RATE;
2388                         for (i = IWL_RATE_6M_INDEX_TABLE;
2389                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2390                                 table[i].next_rate_index =
2391                                         iwl3945_rates[index].table_rs_index;
2392
2393                         index = IWL_RATE_11M_INDEX_TABLE;
2394                         /* CCK shouldn't fall back to OFDM... */
2395                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2396                 }
2397                 break;
2398
2399         default:
2400                 WARN_ON(1);
2401                 break;
2402         }
2403
2404         /* Update the rate scaling for control frame Tx */
2405         rate_cmd.table_id = 0;
2406         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2407                               &rate_cmd);
2408         if (rc)
2409                 return rc;
2410
2411         /* Update the rate scaling for data frame Tx */
2412         rate_cmd.table_id = 1;
2413         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2414                                 &rate_cmd);
2415 }
2416
2417 /* Called when initializing driver */
2418 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2419 {
2420         memset((void *)&priv->hw_params, 0,
2421                sizeof(struct iwl_hw_params));
2422
2423         priv->_3945.shared_virt =
2424                 dma_alloc_coherent(&priv->pci_dev->dev,
2425                                    sizeof(struct iwl3945_shared),
2426                                    &priv->_3945.shared_phys, GFP_KERNEL);
2427         if (!priv->_3945.shared_virt) {
2428                 IWL_ERR(priv, "failed to allocate pci memory\n");
2429                 return -ENOMEM;
2430         }
2431
2432         /* Assign number of Usable TX queues */
2433         priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
2434
2435         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2436         priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2437         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2438         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2439         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2440         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2441
2442         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2443         priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2444         priv->hw_params.beacon_time_tsf_bits = IWL3945_EXT_BEACON_TIME_POS;
2445
2446         return 0;
2447 }
2448
2449 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2450                           struct iwl3945_frame *frame, u8 rate)
2451 {
2452         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2453         unsigned int frame_size;
2454
2455         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2456         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2457
2458         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2459         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2460
2461         frame_size = iwl3945_fill_beacon_frame(priv,
2462                                 tx_beacon_cmd->frame,
2463                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2464
2465         BUG_ON(frame_size > MAX_MPDU_SIZE);
2466         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2467
2468         tx_beacon_cmd->tx.rate = rate;
2469         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2470                                       TX_CMD_FLG_TSF_MSK);
2471
2472         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2473         tx_beacon_cmd->tx.supp_rates[0] =
2474                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2475
2476         tx_beacon_cmd->tx.supp_rates[1] =
2477                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2478
2479         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2480 }
2481
2482 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2483 {
2484         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2485         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2486 }
2487
2488 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2489 {
2490         INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
2491                           iwl3945_bg_reg_txpower_periodic);
2492 }
2493
2494 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2495 {
2496         cancel_delayed_work(&priv->_3945.thermal_periodic);
2497 }
2498
2499 /* check contents of special bootstrap uCode SRAM */
2500 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2501  {
2502         __le32 *image = priv->ucode_boot.v_addr;
2503         u32 len = priv->ucode_boot.len;
2504         u32 reg;
2505         u32 val;
2506
2507         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2508
2509         /* verify BSM SRAM contents */
2510         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2511         for (reg = BSM_SRAM_LOWER_BOUND;
2512              reg < BSM_SRAM_LOWER_BOUND + len;
2513              reg += sizeof(u32), image++) {
2514                 val = iwl_read_prph(priv, reg);
2515                 if (val != le32_to_cpu(*image)) {
2516                         IWL_ERR(priv, "BSM uCode verification failed at "
2517                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2518                                   BSM_SRAM_LOWER_BOUND,
2519                                   reg - BSM_SRAM_LOWER_BOUND, len,
2520                                   val, le32_to_cpu(*image));
2521                         return -EIO;
2522                 }
2523         }
2524
2525         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2526
2527         return 0;
2528 }
2529
2530
2531 /******************************************************************************
2532  *
2533  * EEPROM related functions
2534  *
2535  ******************************************************************************/
2536
2537 /*
2538  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2539  * embedded controller) as EEPROM reader; each read is a series of pulses
2540  * to/from the EEPROM chip, not a single event, so even reads could conflict
2541  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2542  * simply claims ownership, which should be safe when this function is called
2543  * (i.e. before loading uCode!).
2544  */
2545 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2546 {
2547         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2548         return 0;
2549 }
2550
2551
2552 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2553 {
2554         return;
2555 }
2556
2557  /**
2558   * iwl3945_load_bsm - Load bootstrap instructions
2559   *
2560   * BSM operation:
2561   *
2562   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2563   * in special SRAM that does not power down during RFKILL.  When powering back
2564   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2565   * the bootstrap program into the on-board processor, and starts it.
2566   *
2567   * The bootstrap program loads (via DMA) instructions and data for a new
2568   * program from host DRAM locations indicated by the host driver in the
2569   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2570   * automatically.
2571   *
2572   * When initializing the NIC, the host driver points the BSM to the
2573   * "initialize" uCode image.  This uCode sets up some internal data, then
2574   * notifies host via "initialize alive" that it is complete.
2575   *
2576   * The host then replaces the BSM_DRAM_* pointer values to point to the
2577   * normal runtime uCode instructions and a backup uCode data cache buffer
2578   * (filled initially with starting data values for the on-board processor),
2579   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2580   * which begins normal operation.
2581   *
2582   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2583   * the backup data cache in DRAM before SRAM is powered down.
2584   *
2585   * When powering back up, the BSM loads the bootstrap program.  This reloads
2586   * the runtime uCode instructions and the backup data cache into SRAM,
2587   * and re-launches the runtime uCode from where it left off.
2588   */
2589 static int iwl3945_load_bsm(struct iwl_priv *priv)
2590 {
2591         __le32 *image = priv->ucode_boot.v_addr;
2592         u32 len = priv->ucode_boot.len;
2593         dma_addr_t pinst;
2594         dma_addr_t pdata;
2595         u32 inst_len;
2596         u32 data_len;
2597         int rc;
2598         int i;
2599         u32 done;
2600         u32 reg_offset;
2601
2602         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2603
2604         /* make sure bootstrap program is no larger than BSM's SRAM size */
2605         if (len > IWL39_MAX_BSM_SIZE)
2606                 return -EINVAL;
2607
2608         /* Tell bootstrap uCode where to find the "Initialize" uCode
2609         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2610         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2611         *        after the "initialize" uCode has run, to point to
2612         *        runtime/protocol instructions and backup data cache. */
2613         pinst = priv->ucode_init.p_addr;
2614         pdata = priv->ucode_init_data.p_addr;
2615         inst_len = priv->ucode_init.len;
2616         data_len = priv->ucode_init_data.len;
2617
2618         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2619         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2620         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2621         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2622
2623         /* Fill BSM memory with bootstrap instructions */
2624         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2625              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2626              reg_offset += sizeof(u32), image++)
2627                 _iwl_write_prph(priv, reg_offset,
2628                                           le32_to_cpu(*image));
2629
2630         rc = iwl3945_verify_bsm(priv);
2631         if (rc)
2632                 return rc;
2633
2634         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2635         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2636         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2637                                  IWL39_RTC_INST_LOWER_BOUND);
2638         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2639
2640         /* Load bootstrap code into instruction SRAM now,
2641          *   to prepare to load "initialize" uCode */
2642         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2643                 BSM_WR_CTRL_REG_BIT_START);
2644
2645         /* Wait for load of bootstrap uCode to finish */
2646         for (i = 0; i < 100; i++) {
2647                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2648                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2649                         break;
2650                 udelay(10);
2651         }
2652         if (i < 100)
2653                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2654         else {
2655                 IWL_ERR(priv, "BSM write did not complete!\n");
2656                 return -EIO;
2657         }
2658
2659         /* Enable future boot loads whenever power management unit triggers it
2660          *   (e.g. when powering back up after power-save shutdown) */
2661         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2662                 BSM_WR_CTRL_REG_BIT_START_EN);
2663
2664         return 0;
2665 }
2666
2667 static struct iwl_hcmd_ops iwl3945_hcmd = {
2668         .rxon_assoc = iwl3945_send_rxon_assoc,
2669         .commit_rxon = iwl3945_commit_rxon,
2670         .send_bt_config = iwl_send_bt_config,
2671 };
2672
2673 static struct iwl_lib_ops iwl3945_lib = {
2674         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2675         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2676         .txq_init = iwl3945_hw_tx_queue_init,
2677         .load_ucode = iwl3945_load_bsm,
2678         .dump_nic_event_log = iwl3945_dump_nic_event_log,
2679         .dump_nic_error_log = iwl3945_dump_nic_error_log,
2680         .apm_ops = {
2681                 .init = iwl3945_apm_init,
2682                 .stop = iwl_apm_stop,
2683                 .config = iwl3945_nic_config,
2684                 .set_pwr_src = iwl3945_set_pwr_src,
2685         },
2686         .eeprom_ops = {
2687                 .regulatory_bands = {
2688                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2689                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2690                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2691                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2692                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2693                         EEPROM_REGULATORY_BAND_NO_HT40,
2694                         EEPROM_REGULATORY_BAND_NO_HT40,
2695                 },
2696                 .verify_signature  = iwlcore_eeprom_verify_signature,
2697                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2698                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2699                 .query_addr = iwlcore_eeprom_query_addr,
2700         },
2701         .send_tx_power  = iwl3945_send_tx_power,
2702         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2703         .post_associate = iwl3945_post_associate,
2704         .isr = iwl_isr_legacy,
2705         .config_ap = iwl3945_config_ap,
2706         .manage_ibss_station = iwl3945_manage_ibss_station,
2707         .recover_from_tx_stall = iwl_bg_monitor_recover,
2708         .check_plcp_health = iwl3945_good_plcp_health,
2709
2710         .debugfs_ops = {
2711                 .rx_stats_read = iwl3945_ucode_rx_stats_read,
2712                 .tx_stats_read = iwl3945_ucode_tx_stats_read,
2713                 .general_stats_read = iwl3945_ucode_general_stats_read,
2714         },
2715 };
2716
2717 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2718         .get_hcmd_size = iwl3945_get_hcmd_size,
2719         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2720         .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2721         .request_scan = iwl3945_request_scan,
2722 };
2723
2724 static const struct iwl_ops iwl3945_ops = {
2725         .lib = &iwl3945_lib,
2726         .hcmd = &iwl3945_hcmd,
2727         .utils = &iwl3945_hcmd_utils,
2728         .led = &iwl3945_led_ops,
2729 };
2730
2731 static struct iwl_cfg iwl3945_bg_cfg = {
2732         .name = "3945BG",
2733         .fw_name_pre = IWL3945_FW_PRE,
2734         .ucode_api_max = IWL3945_UCODE_API_MAX,
2735         .ucode_api_min = IWL3945_UCODE_API_MIN,
2736         .sku = IWL_SKU_G,
2737         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2738         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2739         .ops = &iwl3945_ops,
2740         .num_of_queues = IWL39_NUM_QUEUES,
2741         .mod_params = &iwl3945_mod_params,
2742         .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2743         .set_l0s = false,
2744         .use_bsm = true,
2745         .use_isr_legacy = true,
2746         .ht_greenfield_support = false,
2747         .led_compensation = 64,
2748         .broken_powersave = true,
2749         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
2750         .monitor_recover_period = IWL_MONITORING_PERIOD,
2751         .max_event_log_size = 512,
2752         .tx_power_by_driver = true,
2753 };
2754
2755 static struct iwl_cfg iwl3945_abg_cfg = {
2756         .name = "3945ABG",
2757         .fw_name_pre = IWL3945_FW_PRE,
2758         .ucode_api_max = IWL3945_UCODE_API_MAX,
2759         .ucode_api_min = IWL3945_UCODE_API_MIN,
2760         .sku = IWL_SKU_A|IWL_SKU_G,
2761         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2762         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2763         .ops = &iwl3945_ops,
2764         .num_of_queues = IWL39_NUM_QUEUES,
2765         .mod_params = &iwl3945_mod_params,
2766         .use_isr_legacy = true,
2767         .ht_greenfield_support = false,
2768         .led_compensation = 64,
2769         .broken_powersave = true,
2770         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
2771         .monitor_recover_period = IWL_MONITORING_PERIOD,
2772         .max_event_log_size = 512,
2773         .tx_power_by_driver = true,
2774 };
2775
2776 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
2777         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2778         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2779         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2780         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2781         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2782         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2783         {0}
2784 };
2785
2786 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);