drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/delay.h>
  34 #include <linux/sched.h>
  35 #include <linux/skbuff.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/wireless.h>
  38 #include <linux/firmware.h>
  39 #include <linux/etherdevice.h>
  40 #include <asm/unaligned.h>
  41 #include <net/mac80211.h>
  42
  43 #include "iwl-fh.h"
  44 #include "iwl-3945-fh.h"
  45 #include "iwl-commands.h"
  46 #include "iwl-sta.h"
  47 #include "iwl-3945.h"
  48 #include "iwl-eeprom.h"
  49 #include "iwl-core.h"
  50 #include "iwl-helpers.h"
  51 #include "iwl-led.h"
  52 #include "iwl-3945-led.h"
  53
  54 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  55         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  56                                     IWL_RATE_##r##M_IEEE,   \
  57                                     IWL_RATE_##ip##M_INDEX, \
  58                                     IWL_RATE_##in##M_INDEX, \
  59                                     IWL_RATE_##rp##M_INDEX, \
  60                                     IWL_RATE_##rn##M_INDEX, \
  61                                     IWL_RATE_##pp##M_INDEX, \
  62                                     IWL_RATE_##np##M_INDEX, \
  63                                     IWL_RATE_##r##M_INDEX_TABLE, \
  64                                     IWL_RATE_##ip##M_INDEX_TABLE }
  65
  66 /*
  67  * Parameter order:
  68  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  69  *
  70  * If there isn't a valid next or previous rate then INV is used which
  71  * maps to IWL_RATE_INVALID
  72  *
  73  */
  74 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
  75         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  76         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  77         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  78         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  79         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  80         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  81         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  82         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  83         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  84         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  85         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  86         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  87 };
  88
  89 /* 1 = enable the iwl3945_disable_events() function */
  90 #define IWL_EVT_DISABLE (0)
  91 #define IWL_EVT_DISABLE_SIZE (1532/32)
  92
  93 /**
  94  * iwl3945_disable_events - Disable selected events in uCode event log
  95  *
  96  * Disable an event by writing "1"s into "disable"
  97  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
  98  *   Default values of 0 enable uCode events to be logged.
  99  * Use for only special debugging.  This function is just a placeholder as-is,
 100  *   you'll need to provide the special bits! ...
 101  *   ... and set IWL_EVT_DISABLE to 1. */
 102 void iwl3945_disable_events(struct iwl_priv *priv)
 103 {
 104         int i;
 105         u32 base;               /* SRAM address of event log header */
 106         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 107         u32 array_size;         /* # of u32 entries in array */
 108         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 109                 0x00000000,     /*   31 -    0  Event id numbers */
 110                 0x00000000,     /*   63 -   32 */
 111                 0x00000000,     /*   95 -   64 */
 112                 0x00000000,     /*  127 -   96 */
 113                 0x00000000,     /*  159 -  128 */
 114                 0x00000000,     /*  191 -  160 */
 115                 0x00000000,     /*  223 -  192 */
 116                 0x00000000,     /*  255 -  224 */
 117                 0x00000000,     /*  287 -  256 */
 118                 0x00000000,     /*  319 -  288 */
 119                 0x00000000,     /*  351 -  320 */
 120                 0x00000000,     /*  383 -  352 */
 121                 0x00000000,     /*  415 -  384 */
 122                 0x00000000,     /*  447 -  416 */
 123                 0x00000000,     /*  479 -  448 */
 124                 0x00000000,     /*  511 -  480 */
 125                 0x00000000,     /*  543 -  512 */
 126                 0x00000000,     /*  575 -  544 */
 127                 0x00000000,     /*  607 -  576 */
 128                 0x00000000,     /*  639 -  608 */
 129                 0x00000000,     /*  671 -  640 */
 130                 0x00000000,     /*  703 -  672 */
 131                 0x00000000,     /*  735 -  704 */
 132                 0x00000000,     /*  767 -  736 */
 133                 0x00000000,     /*  799 -  768 */
 134                 0x00000000,     /*  831 -  800 */
 135                 0x00000000,     /*  863 -  832 */
 136                 0x00000000,     /*  895 -  864 */
 137                 0x00000000,     /*  927 -  896 */
 138                 0x00000000,     /*  959 -  928 */
 139                 0x00000000,     /*  991 -  960 */
 140                 0x00000000,     /* 1023 -  992 */
 141                 0x00000000,     /* 1055 - 1024 */
 142                 0x00000000,     /* 1087 - 1056 */
 143                 0x00000000,     /* 1119 - 1088 */
 144                 0x00000000,     /* 1151 - 1120 */
 145                 0x00000000,     /* 1183 - 1152 */
 146                 0x00000000,     /* 1215 - 1184 */
 147                 0x00000000,     /* 1247 - 1216 */
 148                 0x00000000,     /* 1279 - 1248 */
 149                 0x00000000,     /* 1311 - 1280 */
 150                 0x00000000,     /* 1343 - 1312 */
 151                 0x00000000,     /* 1375 - 1344 */
 152                 0x00000000,     /* 1407 - 1376 */
 153                 0x00000000,     /* 1439 - 1408 */
 154                 0x00000000,     /* 1471 - 1440 */
 155                 0x00000000,     /* 1503 - 1472 */
 156         };
 157
 158         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 159         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 160                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
 161                 return;
 162         }
 163
 164         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
 165         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
 166
 167         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 168                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
 169                                disable_ptr);
 170                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 171                         iwl_write_targ_mem(priv,
 172                                            disable_ptr + (i * sizeof(u32)),
 173                                            evt_disable[i]);
 174
 175         } else {
 176                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
 177                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
 178                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
 179                                disable_ptr, array_size);
 180         }
 181
 182 }
 183
 184 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 185 {
 186         int idx;
 187
 188         for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
 189                 if (iwl3945_rates[idx].plcp == plcp)
 190                         return idx;
 191         return -1;
 192 }
 193
 194 #ifdef CONFIG_IWLWIFI_DEBUG
 195 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
 196
 197 static const char *iwl3945_get_tx_fail_reason(u32 status)
 198 {
 199         switch (status & TX_STATUS_MSK) {
 200         case TX_3945_STATUS_SUCCESS:
 201                 return "SUCCESS";
 202                 TX_STATUS_ENTRY(SHORT_LIMIT);
 203                 TX_STATUS_ENTRY(LONG_LIMIT);
 204                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 205                 TX_STATUS_ENTRY(MGMNT_ABORT);
 206                 TX_STATUS_ENTRY(NEXT_FRAG);
 207                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 208                 TX_STATUS_ENTRY(DEST_PS);
 209                 TX_STATUS_ENTRY(ABORTED);
 210                 TX_STATUS_ENTRY(BT_RETRY);
 211                 TX_STATUS_ENTRY(STA_INVALID);
 212                 TX_STATUS_ENTRY(FRAG_DROPPED);
 213                 TX_STATUS_ENTRY(TID_DISABLE);
 214                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 215                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 216                 TX_STATUS_ENTRY(TX_LOCKED);
 217                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 218         }
 219
 220         return "UNKNOWN";
 221 }
 222 #else
 223 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 224 {
 225         return "";
 226 }
 227 #endif
 228
 229 /*
 230  * get ieee prev rate from rate scale table.
 231  * for A and B mode we need to overright prev
 232  * value
 233  */
 234 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
 235 {
 236         int next_rate = iwl3945_get_prev_ieee_rate(rate);
 237
 238         switch (priv->band) {
 239         case IEEE80211_BAND_5GHZ:
 240                 if (rate == IWL_RATE_12M_INDEX)
 241                         next_rate = IWL_RATE_9M_INDEX;
 242                 else if (rate == IWL_RATE_6M_INDEX)
 243                         next_rate = IWL_RATE_6M_INDEX;
 244                 break;
 245         case IEEE80211_BAND_2GHZ:
 246                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
 247                     iwl_is_associated(priv)) {
 248                         if (rate == IWL_RATE_11M_INDEX)
 249                                 next_rate = IWL_RATE_5M_INDEX;
 250                 }
 251                 break;
 252
 253         default:
 254                 break;
 255         }
 256
 257         return next_rate;
 258 }
 259
 260
 261 /**
 262  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 263  *
 264  * When FW advances 'R' index, all entries between old and new 'R' index
 265  * need to be reclaimed. As result, some free space forms. If there is
 266  * enough free space (> low mark), wake the stack that feeds us.
 267  */
 268 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
 269                                      int txq_id, int index)
 270 {
 271         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 272         struct iwl_queue *q = &txq->q;
 273         struct iwl_tx_info *tx_info;
 274
 275         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
 276
 277         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 278                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 279
 280                 tx_info = &txq->txb[txq->q.read_ptr];
 281                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
 282                 tx_info->skb[0] = NULL;
 283                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
 284         }
 285
 286         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 287                         (txq_id != IWL_CMD_QUEUE_NUM) &&
 288                         priv->mac80211_registered)
 289                 iwl_wake_queue(priv, txq_id);
 290 }
 291
 292 /**
 293  * iwl3945_rx_reply_tx - Handle Tx response
 294  */
 295 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
 296                             struct iwl_rx_mem_buffer *rxb)
 297 {
 298         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 299         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 300         int txq_id = SEQ_TO_QUEUE(sequence);
 301         int index = SEQ_TO_INDEX(sequence);
 302         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 303         struct ieee80211_tx_info *info;
 304         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 305         u32  status = le32_to_cpu(tx_resp->status);
 306         int rate_idx;
 307         int fail;
 308
 309         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 310                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 311                           "is out of range [0-%d] %d %d\n", txq_id,
 312                           index, txq->q.n_bd, txq->q.write_ptr,
 313                           txq->q.read_ptr);
 314                 return;
 315         }
 316
 317         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
 318         ieee80211_tx_info_clear_status(info);
 319
 320         /* Fill the MRR chain with some info about on-chip retransmissions */
 321         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 322         if (info->band == IEEE80211_BAND_5GHZ)
 323                 rate_idx -= IWL_FIRST_OFDM_RATE;
 324
 325         fail = tx_resp->failure_frame;
 326
 327         info->status.rates[0].idx = rate_idx;
 328         info->status.rates[0].count = fail + 1; /* add final attempt */
 329
 330         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 331         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 332                                 IEEE80211_TX_STAT_ACK : 0;
 333
 334         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 335                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 336                         tx_resp->rate, tx_resp->failure_frame);
 337
 338         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
 339         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 340
 341         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 342                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 343 }
 344
 345
 346
 347 /*****************************************************************************
 348  *
 349  * Intel PRO/Wireless 3945ABG/BG Network Connection
 350  *
 351  *  RX handler implementations
 352  *
 353  *****************************************************************************/
 354
 355 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
 356                 struct iwl_rx_mem_buffer *rxb)
 357 {
 358         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 359         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
 360                      (int)sizeof(struct iwl3945_notif_statistics),
 361                      le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
 362
 363         memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
 364 }
 365
 366 /******************************************************************************
 367  *
 368  * Misc. internal state and helper functions
 369  *
 370  ******************************************************************************/
 371 #ifdef CONFIG_IWLWIFI_DEBUG
 372
 373 /**
 374  * iwl3945_report_frame - dump frame to syslog during debug sessions
 375  *
 376  * You may hack this function to show different aspects of received frames,
 377  * including selective frame dumps.
 378  * group100 parameter selects whether to show 1 out of 100 good frames.
 379  */
 380 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
 381                       struct iwl_rx_packet *pkt,
 382                       struct ieee80211_hdr *header, int group100)
 383 {
 384         u32 to_us;
 385         u32 print_summary = 0;
 386         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
 387         u32 hundred = 0;
 388         u32 dataframe = 0;
 389         __le16 fc;
 390         u16 seq_ctl;
 391         u16 channel;
 392         u16 phy_flags;
 393         u16 length;
 394         u16 status;
 395         u16 bcn_tmr;
 396         u32 tsf_low;
 397         u64 tsf;
 398         u8 rssi;
 399         u8 agc;
 400         u16 sig_avg;
 401         u16 noise_diff;
 402         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 403         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 404         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 405         u8 *data = IWL_RX_DATA(pkt);
 406
 407         /* MAC header */
 408         fc = header->frame_control;
 409         seq_ctl = le16_to_cpu(header->seq_ctrl);
 410
 411         /* metadata */
 412         channel = le16_to_cpu(rx_hdr->channel);
 413         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
 414         length = le16_to_cpu(rx_hdr->len);
 415
 416         /* end-of-frame status and timestamp */
 417         status = le32_to_cpu(rx_end->status);
 418         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
 419         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
 420         tsf = le64_to_cpu(rx_end->timestamp);
 421
 422         /* signal statistics */
 423         rssi = rx_stats->rssi;
 424         agc = rx_stats->agc;
 425         sig_avg = le16_to_cpu(rx_stats->sig_avg);
 426         noise_diff = le16_to_cpu(rx_stats->noise_diff);
 427
 428         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
 429
 430         /* if data frame is to us and all is good,
 431          *   (optionally) print summary for only 1 out of every 100 */
 432         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
 433             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
 434                 dataframe = 1;
 435                 if (!group100)
 436                         print_summary = 1;      /* print each frame */
 437                 else if (priv->framecnt_to_us < 100) {
 438                         priv->framecnt_to_us++;
 439                         print_summary = 0;
 440                 } else {
 441                         priv->framecnt_to_us = 0;
 442                         print_summary = 1;
 443                         hundred = 1;
 444                 }
 445         } else {
 446                 /* print summary for all other frames */
 447                 print_summary = 1;
 448         }
 449
 450         if (print_summary) {
 451                 char *title;
 452                 int rate;
 453
 454                 if (hundred)
 455                         title = "100Frames";
 456                 else if (ieee80211_has_retry(fc))
 457                         title = "Retry";
 458                 else if (ieee80211_is_assoc_resp(fc))
 459                         title = "AscRsp";
 460                 else if (ieee80211_is_reassoc_resp(fc))
 461                         title = "RasRsp";
 462                 else if (ieee80211_is_probe_resp(fc)) {
 463                         title = "PrbRsp";
 464                         print_dump = 1; /* dump frame contents */
 465                 } else if (ieee80211_is_beacon(fc)) {
 466                         title = "Beacon";
 467                         print_dump = 1; /* dump frame contents */
 468                 } else if (ieee80211_is_atim(fc))
 469                         title = "ATIM";
 470                 else if (ieee80211_is_auth(fc))
 471                         title = "Auth";
 472                 else if (ieee80211_is_deauth(fc))
 473                         title = "DeAuth";
 474                 else if (ieee80211_is_disassoc(fc))
 475                         title = "DisAssoc";
 476                 else
 477                         title = "Frame";
 478
 479                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 480                 if (rate == -1)
 481                         rate = 0;
 482                 else
 483                         rate = iwl3945_rates[rate].ieee / 2;
 484
 485                 /* print frame summary.
 486                  * MAC addresses show just the last byte (for brevity),
 487                  *    but you can hack it to show more, if you'd like to. */
 488                 if (dataframe)
 489                         IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
 490                                      "len=%u, rssi=%d, chnl=%d, rate=%d,\n",
 491                                      title, le16_to_cpu(fc), header->addr1[5],
 492                                      length, rssi, channel, rate);
 493                 else {
 494                         /* src/dst addresses assume managed mode */
 495                         IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
 496                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
 497                                      "phy=0x%02x, chnl=%d\n",
 498                                      title, le16_to_cpu(fc), header->addr1[5],
 499                                      header->addr3[5], rssi,
 500                                      tsf_low - priv->scan_start_tsf,
 501                                      phy_flags, channel);
 502                 }
 503         }
 504         if (print_dump)
 505                 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
 506 }
 507
 508 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 509                       struct iwl_rx_packet *pkt,
 510                       struct ieee80211_hdr *header, int group100)
 511 {
 512         if (iwl_get_debug_level(priv) & IWL_DL_RX)
 513                 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
 514 }
 515
 516 #else
 517 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 518                       struct iwl_rx_packet *pkt,
 519                       struct ieee80211_hdr *header, int group100)
 520 {
 521 }
 522 #endif
 523
 524 /* This is necessary only for a number of statistics, see the caller. */
 525 static int iwl3945_is_network_packet(struct iwl_priv *priv,
 526                 struct ieee80211_hdr *header)
 527 {
 528         /* Filter incoming packets to determine if they are targeted toward
 529          * this network, discarding packets coming from ourselves */
 530         switch (priv->iw_mode) {
 531         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 532                 /* packets to our IBSS update information */
 533                 return !compare_ether_addr(header->addr3, priv->bssid);
 534         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 535                 /* packets to our IBSS update information */
 536                 return !compare_ether_addr(header->addr2, priv->bssid);
 537         default:
 538                 return 1;
 539         }
 540 }
 541
 542 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
 543                                    struct iwl_rx_mem_buffer *rxb,
 544                                    struct ieee80211_rx_status *stats)
 545 {
 546         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 547         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 548         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 549         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 550         u16 len = le16_to_cpu(rx_hdr->len);
 551         struct sk_buff *skb;
 552         __le16 fc = hdr->frame_control;
 553
 554         /* We received data from the HW, so stop the watchdog */
 555         if (unlikely(len + IWL39_RX_FRAME_SIZE >
 556                      PAGE_SIZE << priv->hw_params.rx_page_order)) {
 557                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
 558                 return;
 559         }
 560
 561         /* We only process data packets if the interface is open */
 562         if (unlikely(!priv->is_open)) {
 563                 IWL_DEBUG_DROP_LIMIT(priv,
 564                         "Dropping packet while interface is not open.\n");
 565                 return;
 566         }
 567
 568         skb = dev_alloc_skb(128);
 569         if (!skb) {
 570                 IWL_ERR(priv, "dev_alloc_skb failed\n");
 571                 return;
 572         }
 573
 574         if (!iwl3945_mod_params.sw_crypto)
 575                 iwl_set_decrypted_flag(priv,
 576                                        (struct ieee80211_hdr *)rxb_addr(rxb),
 577                                        le32_to_cpu(rx_end->status), stats);
 578
 579         skb_add_rx_frag(skb, 0, rxb->page,
 580                         (void *)rx_hdr->payload - (void *)pkt, len);
 581
 582         iwl_update_stats(priv, false, fc, len);
 583         memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
 584
 585         ieee80211_rx(priv->hw, skb);
 586         priv->alloc_rxb_page--;
 587         rxb->page = NULL;
 588 }
 589
 590 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 591
 592 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
 593                                 struct iwl_rx_mem_buffer *rxb)
 594 {
 595         struct ieee80211_hdr *header;
 596         struct ieee80211_rx_status rx_status;
 597         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 598         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 599         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 600         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 601         u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
 602         u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
 603         u8 network_packet;
 604
 605         rx_status.flag = 0;
 606         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 607         rx_status.freq =
 608                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 609         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 610                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 611
 612         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 613         if (rx_status.band == IEEE80211_BAND_5GHZ)
 614                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 615
 616         rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
 617                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 618
 619         /* set the preamble flag if appropriate */
 620         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 621                 rx_status.flag |= RX_FLAG_SHORTPRE;
 622
 623         if ((unlikely(rx_stats->phy_count > 20))) {
 624                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
 625                                 rx_stats->phy_count);
 626                 return;
 627         }
 628
 629         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 630             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 631                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 632                 return;
 633         }
 634
 635
 636
 637         /* Convert 3945's rssi indicator to dBm */
 638         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
 639
 640         IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
 641                         rx_status.signal, rx_stats_sig_avg,
 642                         rx_stats_noise_diff);
 643
 644         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 645
 646         network_packet = iwl3945_is_network_packet(priv, header);
 647
 648         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
 649                               network_packet ? '*' : ' ',
 650                               le16_to_cpu(rx_hdr->channel),
 651                               rx_status.signal, rx_status.signal,
 652                               rx_status.rate_idx);
 653
 654         /* Set "1" to report good data frames in groups of 100 */
 655         iwl3945_dbg_report_frame(priv, pkt, header, 1);
 656         iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
 657
 658         if (network_packet) {
 659                 priv->_3945.last_beacon_time =
 660                         le32_to_cpu(rx_end->beacon_timestamp);
 661                 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
 662                 priv->_3945.last_rx_rssi = rx_status.signal;
 663         }
 664
 665         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 666 }
 667
 668 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 669                                      struct iwl_tx_queue *txq,
 670                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
 671 {
 672         int count;
 673         struct iwl_queue *q;
 674         struct iwl3945_tfd *tfd, *tfd_tmp;
 675
 676         q = &txq->q;
 677         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 678         tfd = &tfd_tmp[q->write_ptr];
 679
 680         if (reset)
 681                 memset(tfd, 0, sizeof(*tfd));
 682
 683         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 684
 685         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 686                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 687                           NUM_TFD_CHUNKS);
 688                 return -EINVAL;
 689         }
 690
 691         tfd->tbs[count].addr = cpu_to_le32(addr);
 692         tfd->tbs[count].len = cpu_to_le32(len);
 693
 694         count++;
 695
 696         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 697                                          TFD_CTL_PAD_SET(pad));
 698
 699         return 0;
 700 }
 701
 702 /**
 703  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 704  *
 705  * Does NOT advance any indexes
 706  */
 707 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 708 {
 709         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 710         int index = txq->q.read_ptr;
 711         struct iwl3945_tfd *tfd = &tfd_tmp[index];
 712         struct pci_dev *dev = priv->pci_dev;
 713         int i;
 714         int counter;
 715
 716         /* sanity check */
 717         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 718         if (counter > NUM_TFD_CHUNKS) {
 719                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
 720                 /* @todo issue fatal error, it is quite serious situation */
 721                 return;
 722         }
 723
 724         /* Unmap tx_cmd */
 725         if (counter)
 726                 pci_unmap_single(dev,
 727                                 pci_unmap_addr(&txq->meta[index], mapping),
 728                                 pci_unmap_len(&txq->meta[index], len),
 729                                 PCI_DMA_TODEVICE);
 730
 731         /* unmap chunks if any */
 732
 733         for (i = 1; i < counter; i++) {
 734                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
 735                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
 736                 if (txq->txb[txq->q.read_ptr].skb[0]) {
 737                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
 738                         if (txq->txb[txq->q.read_ptr].skb[0]) {
 739                                 /* Can be called from interrupt context */
 740                                 dev_kfree_skb_any(skb);
 741                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
 742                         }
 743                 }
 744         }
 745         return ;
 746 }
 747
 748 /**
 749  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 750  *
 751 */
 752 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
 753                                   struct iwl_device_cmd *cmd,
 754                                   struct ieee80211_tx_info *info,
 755                                   struct ieee80211_hdr *hdr,
 756                                   int sta_id, int tx_id)
 757 {
 758         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 759         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
 760         u16 rate_mask;
 761         int rate;
 762         u8 rts_retry_limit;
 763         u8 data_retry_limit;
 764         __le32 tx_flags;
 765         __le16 fc = hdr->frame_control;
 766         struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
 767
 768         rate = iwl3945_rates[rate_index].plcp;
 769         tx_flags = tx_cmd->tx_flags;
 770
 771         /* We need to figure out how to get the sta->supp_rates while
 772          * in this running context */
 773         rate_mask = IWL_RATES_MASK;
 774
 775
 776         /* Set retry limit on DATA packets and Probe Responses*/
 777         if (ieee80211_is_probe_resp(fc))
 778                 data_retry_limit = 3;
 779         else
 780                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 781         tx_cmd->data_retry_limit = data_retry_limit;
 782
 783         if (tx_id >= IWL_CMD_QUEUE_NUM)
 784                 rts_retry_limit = 3;
 785         else
 786                 rts_retry_limit = 7;
 787
 788         if (data_retry_limit < rts_retry_limit)
 789                 rts_retry_limit = data_retry_limit;
 790         tx_cmd->rts_retry_limit = rts_retry_limit;
 791
 792         if (ieee80211_is_mgmt(fc)) {
 793                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 794                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
 795                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 796                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 797                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 798                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
 799                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 800                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
 801                         }
 802                         break;
 803                 default:
 804                         break;
 805                 }
 806         }
 807
 808         tx_cmd->rate = rate;
 809         tx_cmd->tx_flags = tx_flags;
 810
 811         /* OFDM */
 812         tx_cmd->supp_rates[0] =
 813            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 814
 815         /* CCK */
 816         tx_cmd->supp_rates[1] = (rate_mask & 0xF);
 817
 818         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 819                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 820                        tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
 821                        tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
 822 }
 823
 824 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
 825 {
 826         unsigned long flags_spin;
 827         struct iwl_station_entry *station;
 828
 829         if (sta_id == IWL_INVALID_STATION)
 830                 return IWL_INVALID_STATION;
 831
 832         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 833         station = &priv->stations[sta_id];
 834
 835         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 836         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 837         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 838
 839         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 840
 841         iwl_send_add_sta(priv, &station->sta, flags);
 842         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
 843                         sta_id, tx_rate);
 844         return sta_id;
 845 }
 846
 847 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 848 {
 849         if (src == IWL_PWR_SRC_VAUX) {
 850                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
 851                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 852                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 853                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 854
 855                         iwl_poll_bit(priv, CSR_GPIO_IN,
 856                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 857                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 858                 }
 859         } else {
 860                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 861                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 862                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 863
 864                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 865                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 866         }
 867
 868         return 0;
 869 }
 870
 871 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 872 {
 873         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
 874         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
 875         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
 876         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
 877                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 878                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 879                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 880                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 881                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 882                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 883                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 884                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 885
 886         /* fake read to flush all prev I/O */
 887         iwl_read_direct32(priv, FH39_RSSR_CTRL);
 888
 889         return 0;
 890 }
 891
 892 static int iwl3945_tx_reset(struct iwl_priv *priv)
 893 {
 894
 895         /* bypass mode */
 896         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
 897
 898         /* RA 0 is active */
 899         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
 900
 901         /* all 6 fifo are active */
 902         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
 903
 904         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
 905         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
 906         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
 907         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
 908
 909         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
 910                              priv->_3945.shared_phys);
 911
 912         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
 913                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
 914                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
 915                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
 916                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
 917                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
 918                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
 919                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
 920
 921
 922         return 0;
 923 }
 924
 925 /**
 926  * iwl3945_txq_ctx_reset - Reset TX queue context
 927  *
 928  * Destroys all DMA structures and initialize them again
 929  */
 930 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
 931 {
 932         int rc;
 933         int txq_id, slots_num;
 934
 935         iwl3945_hw_txq_ctx_free(priv);
 936
 937         /* allocate tx queue structure */
 938         rc = iwl_alloc_txq_mem(priv);
 939         if (rc)
 940                 return rc;
 941
 942         /* Tx CMD queue */
 943         rc = iwl3945_tx_reset(priv);
 944         if (rc)
 945                 goto error;
 946
 947         /* Tx queue(s) */
 948         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
 949                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
 950                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 951                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
 952                                        txq_id);
 953                 if (rc) {
 954                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
 955                         goto error;
 956                 }
 957         }
 958
 959         return rc;
 960
 961  error:
 962         iwl3945_hw_txq_ctx_free(priv);
 963         return rc;
 964 }
 965
 966
 967 /*
 968  * Start up 3945's basic functionality after it has been reset
 969  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 970  * NOTE:  This does not load uCode nor start the embedded processor
 971  */
 972 static int iwl3945_apm_init(struct iwl_priv *priv)
 973 {
 974         int ret = iwl_apm_init(priv);
 975
 976         /* Clear APMG (NIC's internal power management) interrupts */
 977         iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
 978         iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
 979
 980         /* Reset radio chip */
 981         iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
 982         udelay(5);
 983         iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
 984
 985         return ret;
 986 }
 987
 988 static void iwl3945_nic_config(struct iwl_priv *priv)
 989 {
 990         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
 991         unsigned long flags;
 992         u8 rev_id = 0;
 993
 994         spin_lock_irqsave(&priv->lock, flags);
 995
 996         /* Determine HW type */
 997         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
 998
 999         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1000
1001         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1002                 IWL_DEBUG_INFO(priv, "RTP type\n");
1003         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1004                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1005                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1006                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1007         } else {
1008                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1009                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1010                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1011         }
1012
1013         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1014                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1015                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1016                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1017         } else
1018                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1019
1020         if ((eeprom->board_revision & 0xF0) == 0xD0) {
1021                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1022                                eeprom->board_revision);
1023                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1024                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1025         } else {
1026                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1027                                eeprom->board_revision);
1028                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1029                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1030         }
1031
1032         if (eeprom->almgor_m_version <= 1) {
1033                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1034                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1035                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1036                                eeprom->almgor_m_version);
1037         } else {
1038                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1039                                eeprom->almgor_m_version);
1040                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1041                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1042         }
1043         spin_unlock_irqrestore(&priv->lock, flags);
1044
1045         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1046                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1047
1048         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1049                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1050 }
1051
1052 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1053 {
1054         int rc;
1055         unsigned long flags;
1056         struct iwl_rx_queue *rxq = &priv->rxq;
1057
1058         spin_lock_irqsave(&priv->lock, flags);
1059         priv->cfg->ops->lib->apm_ops.init(priv);
1060         spin_unlock_irqrestore(&priv->lock, flags);
1061
1062         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1063         if (rc)
1064                 return rc;
1065
1066         priv->cfg->ops->lib->apm_ops.config(priv);
1067
1068         /* Allocate the RX queue, or reset if it is already allocated */
1069         if (!rxq->bd) {
1070                 rc = iwl_rx_queue_alloc(priv);
1071                 if (rc) {
1072                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1073                         return -ENOMEM;
1074                 }
1075         } else
1076                 iwl3945_rx_queue_reset(priv, rxq);
1077
1078         iwl3945_rx_replenish(priv);
1079
1080         iwl3945_rx_init(priv, rxq);
1081
1082
1083         /* Look at using this instead:
1084         rxq->need_update = 1;
1085         iwl_rx_queue_update_write_ptr(priv, rxq);
1086         */
1087
1088         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1089
1090         rc = iwl3945_txq_ctx_reset(priv);
1091         if (rc)
1092                 return rc;
1093
1094         set_bit(STATUS_INIT, &priv->status);
1095
1096         return 0;
1097 }
1098
1099 /**
1100  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1101  *
1102  * Destroy all TX DMA queues and structures
1103  */
1104 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1105 {
1106         int txq_id;
1107
1108         /* Tx queues */
1109         if (priv->txq)
1110                 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1111                      txq_id++)
1112                         if (txq_id == IWL_CMD_QUEUE_NUM)
1113                                 iwl_cmd_queue_free(priv);
1114                         else
1115                                 iwl_tx_queue_free(priv, txq_id);
1116
1117         /* free tx queue structure */
1118         iwl_free_txq_mem(priv);
1119 }
1120
1121 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1122 {
1123         int txq_id;
1124
1125         /* stop SCD */
1126         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1127         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1128
1129         /* reset TFD queues */
1130         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1131                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1132                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1133                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1134                                 1000);
1135         }
1136
1137         iwl3945_hw_txq_ctx_free(priv);
1138 }
1139
1140 /**
1141  * iwl3945_hw_reg_adjust_power_by_temp
1142  * return index delta into power gain settings table
1143 */
1144 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1145 {
1146         return (new_reading - old_reading) * (-11) / 100;
1147 }
1148
1149 /**
1150  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1151  */
1152 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1153 {
1154         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1155 }
1156
1157 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1158 {
1159         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1160 }
1161
1162 /**
1163  * iwl3945_hw_reg_txpower_get_temperature
1164  * get the current temperature by reading from NIC
1165 */
1166 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1167 {
1168         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1169         int temperature;
1170
1171         temperature = iwl3945_hw_get_temperature(priv);
1172
1173         /* driver's okay range is -260 to +25.
1174          *   human readable okay range is 0 to +285 */
1175         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1176
1177         /* handle insane temp reading */
1178         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1179                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1180
1181                 /* if really really hot(?),
1182                  *   substitute the 3rd band/group's temp measured at factory */
1183                 if (priv->last_temperature > 100)
1184                         temperature = eeprom->groups[2].temperature;
1185                 else /* else use most recent "sane" value from driver */
1186                         temperature = priv->last_temperature;
1187         }
1188
1189         return temperature;     /* raw, not "human readable" */
1190 }
1191
1192 /* Adjust Txpower only if temperature variance is greater than threshold.
1193  *
1194  * Both are lower than older versions' 9 degrees */
1195 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1196
1197 /**
1198  * is_temp_calib_needed - determines if new calibration is needed
1199  *
1200  * records new temperature in tx_mgr->temperature.
1201  * replaces tx_mgr->last_temperature *only* if calib needed
1202  *    (assumes caller will actually do the calibration!). */
1203 static int is_temp_calib_needed(struct iwl_priv *priv)
1204 {
1205         int temp_diff;
1206
1207         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1208         temp_diff = priv->temperature - priv->last_temperature;
1209
1210         /* get absolute value */
1211         if (temp_diff < 0) {
1212                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1213                 temp_diff = -temp_diff;
1214         } else if (temp_diff == 0)
1215                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1216         else
1217                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1218
1219         /* if we don't need calibration, *don't* update last_temperature */
1220         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1221                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1222                 return 0;
1223         }
1224
1225         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1226
1227         /* assume that caller will actually do calib ...
1228          *   update the "last temperature" value */
1229         priv->last_temperature = priv->temperature;
1230         return 1;
1231 }
1232
1233 #define IWL_MAX_GAIN_ENTRIES 78
1234 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1235 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1236
1237 /* radio and DSP power table, each step is 1/2 dB.
1238  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1239 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1240         {
1241          {251, 127},            /* 2.4 GHz, highest power */
1242          {251, 127},
1243          {251, 127},
1244          {251, 127},
1245          {251, 125},
1246          {251, 110},
1247          {251, 105},
1248          {251, 98},
1249          {187, 125},
1250          {187, 115},
1251          {187, 108},
1252          {187, 99},
1253          {243, 119},
1254          {243, 111},
1255          {243, 105},
1256          {243, 97},
1257          {243, 92},
1258          {211, 106},
1259          {211, 100},
1260          {179, 120},
1261          {179, 113},
1262          {179, 107},
1263          {147, 125},
1264          {147, 119},
1265          {147, 112},
1266          {147, 106},
1267          {147, 101},
1268          {147, 97},
1269          {147, 91},
1270          {115, 107},
1271          {235, 121},
1272          {235, 115},
1273          {235, 109},
1274          {203, 127},
1275          {203, 121},
1276          {203, 115},
1277          {203, 108},
1278          {203, 102},
1279          {203, 96},
1280          {203, 92},
1281          {171, 110},
1282          {171, 104},
1283          {171, 98},
1284          {139, 116},
1285          {227, 125},
1286          {227, 119},
1287          {227, 113},
1288          {227, 107},
1289          {227, 101},
1290          {227, 96},
1291          {195, 113},
1292          {195, 106},
1293          {195, 102},
1294          {195, 95},
1295          {163, 113},
1296          {163, 106},
1297          {163, 102},
1298          {163, 95},
1299          {131, 113},
1300          {131, 106},
1301          {131, 102},
1302          {131, 95},
1303          {99, 113},
1304          {99, 106},
1305          {99, 102},
1306          {99, 95},
1307          {67, 113},
1308          {67, 106},
1309          {67, 102},
1310          {67, 95},
1311          {35, 113},
1312          {35, 106},
1313          {35, 102},
1314          {35, 95},
1315          {3, 113},
1316          {3, 106},
1317          {3, 102},
1318          {3, 95} },             /* 2.4 GHz, lowest power */
1319         {
1320          {251, 127},            /* 5.x GHz, highest power */
1321          {251, 120},
1322          {251, 114},
1323          {219, 119},
1324          {219, 101},
1325          {187, 113},
1326          {187, 102},
1327          {155, 114},
1328          {155, 103},
1329          {123, 117},
1330          {123, 107},
1331          {123, 99},
1332          {123, 92},
1333          {91, 108},
1334          {59, 125},
1335          {59, 118},
1336          {59, 109},
1337          {59, 102},
1338          {59, 96},
1339          {59, 90},
1340          {27, 104},
1341          {27, 98},
1342          {27, 92},
1343          {115, 118},
1344          {115, 111},
1345          {115, 104},
1346          {83, 126},
1347          {83, 121},
1348          {83, 113},
1349          {83, 105},
1350          {83, 99},
1351          {51, 118},
1352          {51, 111},
1353          {51, 104},
1354          {51, 98},
1355          {19, 116},
1356          {19, 109},
1357          {19, 102},
1358          {19, 98},
1359          {19, 93},
1360          {171, 113},
1361          {171, 107},
1362          {171, 99},
1363          {139, 120},
1364          {139, 113},
1365          {139, 107},
1366          {139, 99},
1367          {107, 120},
1368          {107, 113},
1369          {107, 107},
1370          {107, 99},
1371          {75, 120},
1372          {75, 113},
1373          {75, 107},
1374          {75, 99},
1375          {43, 120},
1376          {43, 113},
1377          {43, 107},
1378          {43, 99},
1379          {11, 120},
1380          {11, 113},
1381          {11, 107},
1382          {11, 99},
1383          {131, 107},
1384          {131, 99},
1385          {99, 120},
1386          {99, 113},
1387          {99, 107},
1388          {99, 99},
1389          {67, 120},
1390          {67, 113},
1391          {67, 107},
1392          {67, 99},
1393          {35, 120},
1394          {35, 113},
1395          {35, 107},
1396          {35, 99},
1397          {3, 120} }             /* 5.x GHz, lowest power */
1398 };
1399
1400 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1401 {
1402         if (index < 0)
1403                 return 0;
1404         if (index >= IWL_MAX_GAIN_ENTRIES)
1405                 return IWL_MAX_GAIN_ENTRIES - 1;
1406         return (u8) index;
1407 }
1408
1409 /* Kick off thermal recalibration check every 60 seconds */
1410 #define REG_RECALIB_PERIOD (60)
1411
1412 /**
1413  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1414  *
1415  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1416  * or 6 Mbit (OFDM) rates.
1417  */
1418 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1419                                s32 rate_index, const s8 *clip_pwrs,
1420                                struct iwl_channel_info *ch_info,
1421                                int band_index)
1422 {
1423         struct iwl3945_scan_power_info *scan_power_info;
1424         s8 power;
1425         u8 power_index;
1426
1427         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1428
1429         /* use this channel group's 6Mbit clipping/saturation pwr,
1430          *   but cap at regulatory scan power restriction (set during init
1431          *   based on eeprom channel data) for this channel.  */
1432         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1433
1434         /* further limit to user's max power preference.
1435          * FIXME:  Other spectrum management power limitations do not
1436          *   seem to apply?? */
1437         power = min(power, priv->tx_power_user_lmt);
1438         scan_power_info->requested_power = power;
1439
1440         /* find difference between new scan *power* and current "normal"
1441          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1442          *   current "normal" temperature-compensated Tx power *index* for
1443          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1444          *   *index*. */
1445         power_index = ch_info->power_info[rate_index].power_table_index
1446             - (power - ch_info->power_info
1447                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1448
1449         /* store reference index that we use when adjusting *all* scan
1450          *   powers.  So we can accommodate user (all channel) or spectrum
1451          *   management (single channel) power changes "between" temperature
1452          *   feedback compensation procedures.
1453          * don't force fit this reference index into gain table; it may be a
1454          *   negative number.  This will help avoid errors when we're at
1455          *   the lower bounds (highest gains, for warmest temperatures)
1456          *   of the table. */
1457
1458         /* don't exceed table bounds for "real" setting */
1459         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1460
1461         scan_power_info->power_table_index = power_index;
1462         scan_power_info->tpc.tx_gain =
1463             power_gain_table[band_index][power_index].tx_gain;
1464         scan_power_info->tpc.dsp_atten =
1465             power_gain_table[band_index][power_index].dsp_atten;
1466 }
1467
1468 /**
1469  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1470  *
1471  * Configures power settings for all rates for the current channel,
1472  * using values from channel info struct, and send to NIC
1473  */
1474 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1475 {
1476         int rate_idx, i;
1477         const struct iwl_channel_info *ch_info = NULL;
1478         struct iwl3945_txpowertable_cmd txpower = {
1479                 .channel = priv->active_rxon.channel,
1480         };
1481
1482         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1483         ch_info = iwl_get_channel_info(priv,
1484                                        priv->band,
1485                                        le16_to_cpu(priv->active_rxon.channel));
1486         if (!ch_info) {
1487                 IWL_ERR(priv,
1488                         "Failed to get channel info for channel %d [%d]\n",
1489                         le16_to_cpu(priv->active_rxon.channel), priv->band);
1490                 return -EINVAL;
1491         }
1492
1493         if (!is_channel_valid(ch_info)) {
1494                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1495                                 "non-Tx channel.\n");
1496                 return 0;
1497         }
1498
1499         /* fill cmd with power settings for all rates for current channel */
1500         /* Fill OFDM rate */
1501         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1502              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1503
1504                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1505                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1506
1507                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1508                                 le16_to_cpu(txpower.channel),
1509                                 txpower.band,
1510                                 txpower.power[i].tpc.tx_gain,
1511                                 txpower.power[i].tpc.dsp_atten,
1512                                 txpower.power[i].rate);
1513         }
1514         /* Fill CCK rates */
1515         for (rate_idx = IWL_FIRST_CCK_RATE;
1516              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1517                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1518                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1519
1520                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1521                                 le16_to_cpu(txpower.channel),
1522                                 txpower.band,
1523                                 txpower.power[i].tpc.tx_gain,
1524                                 txpower.power[i].tpc.dsp_atten,
1525                                 txpower.power[i].rate);
1526         }
1527
1528         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1529                                 sizeof(struct iwl3945_txpowertable_cmd),
1530                                 &txpower);
1531
1532 }
1533
1534 /**
1535  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1536  * @ch_info: Channel to update.  Uses power_info.requested_power.
1537  *
1538  * Replace requested_power and base_power_index ch_info fields for
1539  * one channel.
1540  *
1541  * Called if user or spectrum management changes power preferences.
1542  * Takes into account h/w and modulation limitations (clip power).
1543  *
1544  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1545  *
1546  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1547  *       properly fill out the scan powers, and actual h/w gain settings,
1548  *       and send changes to NIC
1549  */
1550 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1551                              struct iwl_channel_info *ch_info)
1552 {
1553         struct iwl3945_channel_power_info *power_info;
1554         int power_changed = 0;
1555         int i;
1556         const s8 *clip_pwrs;
1557         int power;
1558
1559         /* Get this chnlgrp's rate-to-max/clip-powers table */
1560         clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1561
1562         /* Get this channel's rate-to-current-power settings table */
1563         power_info = ch_info->power_info;
1564
1565         /* update OFDM Txpower settings */
1566         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1567              i++, ++power_info) {
1568                 int delta_idx;
1569
1570                 /* limit new power to be no more than h/w capability */
1571                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1572                 if (power == power_info->requested_power)
1573                         continue;
1574
1575                 /* find difference between old and new requested powers,
1576                  *    update base (non-temp-compensated) power index */
1577                 delta_idx = (power - power_info->requested_power) * 2;
1578                 power_info->base_power_index -= delta_idx;
1579
1580                 /* save new requested power value */
1581                 power_info->requested_power = power;
1582
1583                 power_changed = 1;
1584         }
1585
1586         /* update CCK Txpower settings, based on OFDM 12M setting ...
1587          *    ... all CCK power settings for a given channel are the *same*. */
1588         if (power_changed) {
1589                 power =
1590                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1591                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1592
1593                 /* do all CCK rates' iwl3945_channel_power_info structures */
1594                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1595                         power_info->requested_power = power;
1596                         power_info->base_power_index =
1597                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1598                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1599                         ++power_info;
1600                 }
1601         }
1602
1603         return 0;
1604 }
1605
1606 /**
1607  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1608  *
1609  * NOTE: Returned power limit may be less (but not more) than requested,
1610  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1611  *       (no consideration for h/w clipping limitations).
1612  */
1613 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1614 {
1615         s8 max_power;
1616
1617 #if 0
1618         /* if we're using TGd limits, use lower of TGd or EEPROM */
1619         if (ch_info->tgd_data.max_power != 0)
1620                 max_power = min(ch_info->tgd_data.max_power,
1621                                 ch_info->eeprom.max_power_avg);
1622
1623         /* else just use EEPROM limits */
1624         else
1625 #endif
1626                 max_power = ch_info->eeprom.max_power_avg;
1627
1628         return min(max_power, ch_info->max_power_avg);
1629 }
1630
1631 /**
1632  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1633  *
1634  * Compensate txpower settings of *all* channels for temperature.
1635  * This only accounts for the difference between current temperature
1636  *   and the factory calibration temperatures, and bases the new settings
1637  *   on the channel's base_power_index.
1638  *
1639  * If RxOn is "associated", this sends the new Txpower to NIC!
1640  */
1641 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1642 {
1643         struct iwl_channel_info *ch_info = NULL;
1644         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1645         int delta_index;
1646         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1647         u8 a_band;
1648         u8 rate_index;
1649         u8 scan_tbl_index;
1650         u8 i;
1651         int ref_temp;
1652         int temperature = priv->temperature;
1653
1654         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1655         for (i = 0; i < priv->channel_count; i++) {
1656                 ch_info = &priv->channel_info[i];
1657                 a_band = is_channel_a_band(ch_info);
1658
1659                 /* Get this chnlgrp's factory calibration temperature */
1660                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1661                     temperature;
1662
1663                 /* get power index adjustment based on current and factory
1664                  * temps */
1665                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1666                                                               ref_temp);
1667
1668                 /* set tx power value for all rates, OFDM and CCK */
1669                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1670                      rate_index++) {
1671                         int power_idx =
1672                             ch_info->power_info[rate_index].base_power_index;
1673
1674                         /* temperature compensate */
1675                         power_idx += delta_index;
1676
1677                         /* stay within table range */
1678                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1679                         ch_info->power_info[rate_index].
1680                             power_table_index = (u8) power_idx;
1681                         ch_info->power_info[rate_index].tpc =
1682                             power_gain_table[a_band][power_idx];
1683                 }
1684
1685                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1686                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1687
1688                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1689                 for (scan_tbl_index = 0;
1690                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1691                         s32 actual_index = (scan_tbl_index == 0) ?
1692                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1693                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1694                                            actual_index, clip_pwrs,
1695                                            ch_info, a_band);
1696                 }
1697         }
1698
1699         /* send Txpower command for current channel to ucode */
1700         return priv->cfg->ops->lib->send_tx_power(priv);
1701 }
1702
1703 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1704 {
1705         struct iwl_channel_info *ch_info;
1706         s8 max_power;
1707         u8 a_band;
1708         u8 i;
1709
1710         if (priv->tx_power_user_lmt == power) {
1711                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1712                                 "limit: %ddBm.\n", power);
1713                 return 0;
1714         }
1715
1716         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1717         priv->tx_power_user_lmt = power;
1718
1719         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1720
1721         for (i = 0; i < priv->channel_count; i++) {
1722                 ch_info = &priv->channel_info[i];
1723                 a_band = is_channel_a_band(ch_info);
1724
1725                 /* find minimum power of all user and regulatory constraints
1726                  *    (does not consider h/w clipping limitations) */
1727                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1728                 max_power = min(power, max_power);
1729                 if (max_power != ch_info->curr_txpow) {
1730                         ch_info->curr_txpow = max_power;
1731
1732                         /* this considers the h/w clipping limitations */
1733                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1734                 }
1735         }
1736
1737         /* update txpower settings for all channels,
1738          *   send to NIC if associated. */
1739         is_temp_calib_needed(priv);
1740         iwl3945_hw_reg_comp_txpower_temp(priv);
1741
1742         return 0;
1743 }
1744
1745 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1746 {
1747         int rc = 0;
1748         struct iwl_rx_packet *pkt;
1749         struct iwl3945_rxon_assoc_cmd rxon_assoc;
1750         struct iwl_host_cmd cmd = {
1751                 .id = REPLY_RXON_ASSOC,
1752                 .len = sizeof(rxon_assoc),
1753                 .flags = CMD_WANT_SKB,
1754                 .data = &rxon_assoc,
1755         };
1756         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1757         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1758
1759         if ((rxon1->flags == rxon2->flags) &&
1760             (rxon1->filter_flags == rxon2->filter_flags) &&
1761             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1762             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1763                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1764                 return 0;
1765         }
1766
1767         rxon_assoc.flags = priv->staging_rxon.flags;
1768         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1769         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1770         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1771         rxon_assoc.reserved = 0;
1772
1773         rc = iwl_send_cmd_sync(priv, &cmd);
1774         if (rc)
1775                 return rc;
1776
1777         pkt = (struct iwl_rx_packet *)cmd.reply_page;
1778         if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1779                 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1780                 rc = -EIO;
1781         }
1782
1783         iwl_free_pages(priv, cmd.reply_page);
1784
1785         return rc;
1786 }
1787
1788 /**
1789  * iwl3945_commit_rxon - commit staging_rxon to hardware
1790  *
1791  * The RXON command in staging_rxon is committed to the hardware and
1792  * the active_rxon structure is updated with the new data.  This
1793  * function correctly transitions out of the RXON_ASSOC_MSK state if
1794  * a HW tune is required based on the RXON structure changes.
1795  */
1796 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1797 {
1798         /* cast away the const for active_rxon in this function */
1799         struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1800         struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1801         int rc = 0;
1802         bool new_assoc =
1803                 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1804
1805         if (!iwl_is_alive(priv))
1806                 return -1;
1807
1808         /* always get timestamp with Rx frame */
1809         staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1810
1811         /* select antenna */
1812         staging_rxon->flags &=
1813             ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1814         staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1815
1816         rc = iwl_check_rxon_cmd(priv);
1817         if (rc) {
1818                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
1819                 return -EINVAL;
1820         }
1821
1822         /* If we don't need to send a full RXON, we can use
1823          * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1824          * and other flags for the current radio configuration. */
1825         if (!iwl_full_rxon_required(priv)) {
1826                 rc = iwl_send_rxon_assoc(priv);
1827                 if (rc) {
1828                         IWL_ERR(priv, "Error setting RXON_ASSOC "
1829                                   "configuration (%d).\n", rc);
1830                         return rc;
1831                 }
1832
1833                 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1834
1835                 return 0;
1836         }
1837
1838         /* If we are currently associated and the new config requires
1839          * an RXON_ASSOC and the new config wants the associated mask enabled,
1840          * we must clear the associated from the active configuration
1841          * before we apply the new config */
1842         if (iwl_is_associated(priv) && new_assoc) {
1843                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1844                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1845
1846                 /*
1847                  * reserved4 and 5 could have been filled by the iwlcore code.
1848                  * Let's clear them before pushing to the 3945.
1849                  */
1850                 active_rxon->reserved4 = 0;
1851                 active_rxon->reserved5 = 0;
1852                 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1853                                       sizeof(struct iwl3945_rxon_cmd),
1854                                       &priv->active_rxon);
1855
1856                 /* If the mask clearing failed then we set
1857                  * active_rxon back to what it was previously */
1858                 if (rc) {
1859                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1860                         IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1861                                   "configuration (%d).\n", rc);
1862                         return rc;
1863                 }
1864                 iwl_clear_ucode_stations(priv, false);
1865                 iwl_restore_stations(priv);
1866         }
1867
1868         IWL_DEBUG_INFO(priv, "Sending RXON\n"
1869                        "* with%s RXON_FILTER_ASSOC_MSK\n"
1870                        "* channel = %d\n"
1871                        "* bssid = %pM\n",
1872                        (new_assoc ? "" : "out"),
1873                        le16_to_cpu(staging_rxon->channel),
1874                        staging_rxon->bssid_addr);
1875
1876         /*
1877          * reserved4 and 5 could have been filled by the iwlcore code.
1878          * Let's clear them before pushing to the 3945.
1879          */
1880         staging_rxon->reserved4 = 0;
1881         staging_rxon->reserved5 = 0;
1882
1883         iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1884
1885         /* Apply the new configuration */
1886         rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1887                               sizeof(struct iwl3945_rxon_cmd),
1888                               staging_rxon);
1889         if (rc) {
1890                 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1891                 return rc;
1892         }
1893
1894         memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1895
1896         if (!new_assoc) {
1897                 iwl_clear_ucode_stations(priv, false);
1898                 iwl_restore_stations(priv);
1899         }
1900
1901         /* If we issue a new RXON command which required a tune then we must
1902          * send a new TXPOWER command or we won't be able to Tx any frames */
1903         rc = priv->cfg->ops->lib->send_tx_power(priv);
1904         if (rc) {
1905                 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1906                 return rc;
1907         }
1908
1909         /* Init the hardware's rate fallback order based on the band */
1910         rc = iwl3945_init_hw_rate_table(priv);
1911         if (rc) {
1912                 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1913                 return -EIO;
1914         }
1915
1916         return 0;
1917 }
1918
1919 /**
1920  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
1921  *
1922  * -- reset periodic timer
1923  * -- see if temp has changed enough to warrant re-calibration ... if so:
1924  *     -- correct coeffs for temp (can reset temp timer)
1925  *     -- save this temp as "last",
1926  *     -- send new set of gain settings to NIC
1927  * NOTE:  This should continue working, even when we're not associated,
1928  *   so we can keep our internal table of scan powers current. */
1929 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1930 {
1931         /* This will kick in the "brute force"
1932          * iwl3945_hw_reg_comp_txpower_temp() below */
1933         if (!is_temp_calib_needed(priv))
1934                 goto reschedule;
1935
1936         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1937          * This is based *only* on current temperature,
1938          * ignoring any previous power measurements */
1939         iwl3945_hw_reg_comp_txpower_temp(priv);
1940
1941  reschedule:
1942         queue_delayed_work(priv->workqueue,
1943                            &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
1944 }
1945
1946 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1947 {
1948         struct iwl_priv *priv = container_of(work, struct iwl_priv,
1949                                              _3945.thermal_periodic.work);
1950
1951         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1952                 return;
1953
1954         mutex_lock(&priv->mutex);
1955         iwl3945_reg_txpower_periodic(priv);
1956         mutex_unlock(&priv->mutex);
1957 }
1958
1959 /**
1960  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1961  *                                 for the channel.
1962  *
1963  * This function is used when initializing channel-info structs.
1964  *
1965  * NOTE: These channel groups do *NOT* match the bands above!
1966  *       These channel groups are based on factory-tested channels;
1967  *       on A-band, EEPROM's "group frequency" entries represent the top
1968  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
1969  */
1970 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
1971                                        const struct iwl_channel_info *ch_info)
1972 {
1973         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1974         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
1975         u8 group;
1976         u16 group_index = 0;    /* based on factory calib frequencies */
1977         u8 grp_channel;
1978
1979         /* Find the group index for the channel ... don't use index 1(?) */
1980         if (is_channel_a_band(ch_info)) {
1981                 for (group = 1; group < 5; group++) {
1982                         grp_channel = ch_grp[group].group_channel;
1983                         if (ch_info->channel <= grp_channel) {
1984                                 group_index = group;
1985                                 break;
1986                         }
1987                 }
1988                 /* group 4 has a few channels *above* its factory cal freq */
1989                 if (group == 5)
1990                         group_index = 4;
1991         } else
1992                 group_index = 0;        /* 2.4 GHz, group 0 */
1993
1994         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
1995                         group_index);
1996         return group_index;
1997 }
1998
1999 /**
2000  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2001  *
2002  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2003  *   into radio/DSP gain settings table for requested power.
2004  */
2005 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2006                                        s8 requested_power,
2007                                        s32 setting_index, s32 *new_index)
2008 {
2009         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2010         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2011         s32 index0, index1;
2012         s32 power = 2 * requested_power;
2013         s32 i;
2014         const struct iwl3945_eeprom_txpower_sample *samples;
2015         s32 gains0, gains1;
2016         s32 res;
2017         s32 denominator;
2018
2019         chnl_grp = &eeprom->groups[setting_index];
2020         samples = chnl_grp->samples;
2021         for (i = 0; i < 5; i++) {
2022                 if (power == samples[i].power) {
2023                         *new_index = samples[i].gain_index;
2024                         return 0;
2025                 }
2026         }
2027
2028         if (power > samples[1].power) {
2029                 index0 = 0;
2030                 index1 = 1;
2031         } else if (power > samples[2].power) {
2032                 index0 = 1;
2033                 index1 = 2;
2034         } else if (power > samples[3].power) {
2035                 index0 = 2;
2036                 index1 = 3;
2037         } else {
2038                 index0 = 3;
2039                 index1 = 4;
2040         }
2041
2042         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2043         if (denominator == 0)
2044                 return -EINVAL;
2045         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2046         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2047         res = gains0 + (gains1 - gains0) *
2048             ((s32) power - (s32) samples[index0].power) / denominator +
2049             (1 << 18);
2050         *new_index = res >> 19;
2051         return 0;
2052 }
2053
2054 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2055 {
2056         u32 i;
2057         s32 rate_index;
2058         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2059         const struct iwl3945_eeprom_txpower_group *group;
2060
2061         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2062
2063         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2064                 s8 *clip_pwrs;  /* table of power levels for each rate */
2065                 s8 satur_pwr;   /* saturation power for each chnl group */
2066                 group = &eeprom->groups[i];
2067
2068                 /* sanity check on factory saturation power value */
2069                 if (group->saturation_power < 40) {
2070                         IWL_WARN(priv, "Error: saturation power is %d, "
2071                                     "less than minimum expected 40\n",
2072                                     group->saturation_power);
2073                         return;
2074                 }
2075
2076                 /*
2077                  * Derive requested power levels for each rate, based on
2078                  *   hardware capabilities (saturation power for band).
2079                  * Basic value is 3dB down from saturation, with further
2080                  *   power reductions for highest 3 data rates.  These
2081                  *   backoffs provide headroom for high rate modulation
2082                  *   power peaks, without too much distortion (clipping).
2083                  */
2084                 /* we'll fill in this array with h/w max power levels */
2085                 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
2086
2087                 /* divide factory saturation power by 2 to find -3dB level */
2088                 satur_pwr = (s8) (group->saturation_power >> 1);
2089
2090                 /* fill in channel group's nominal powers for each rate */
2091                 for (rate_index = 0;
2092                      rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
2093                         switch (rate_index) {
2094                         case IWL_RATE_36M_INDEX_TABLE:
2095                                 if (i == 0)     /* B/G */
2096                                         *clip_pwrs = satur_pwr;
2097                                 else    /* A */
2098                                         *clip_pwrs = satur_pwr - 5;
2099                                 break;
2100                         case IWL_RATE_48M_INDEX_TABLE:
2101                                 if (i == 0)
2102                                         *clip_pwrs = satur_pwr - 7;
2103                                 else
2104                                         *clip_pwrs = satur_pwr - 10;
2105                                 break;
2106                         case IWL_RATE_54M_INDEX_TABLE:
2107                                 if (i == 0)
2108                                         *clip_pwrs = satur_pwr - 9;
2109                                 else
2110                                         *clip_pwrs = satur_pwr - 12;
2111                                 break;
2112                         default:
2113                                 *clip_pwrs = satur_pwr;
2114                                 break;
2115                         }
2116                 }
2117         }
2118 }
2119
2120 /**
2121  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2122  *
2123  * Second pass (during init) to set up priv->channel_info
2124  *
2125  * Set up Tx-power settings in our channel info database for each VALID
2126  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2127  * and current temperature.
2128  *
2129  * Since this is based on current temperature (at init time), these values may
2130  * not be valid for very long, but it gives us a starting/default point,
2131  * and allows us to active (i.e. using Tx) scan.
2132  *
2133  * This does *not* write values to NIC, just sets up our internal table.
2134  */
2135 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2136 {
2137         struct iwl_channel_info *ch_info = NULL;
2138         struct iwl3945_channel_power_info *pwr_info;
2139         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2140         int delta_index;
2141         u8 rate_index;
2142         u8 scan_tbl_index;
2143         const s8 *clip_pwrs;    /* array of power levels for each rate */
2144         u8 gain, dsp_atten;
2145         s8 power;
2146         u8 pwr_index, base_pwr_index, a_band;
2147         u8 i;
2148         int temperature;
2149
2150         /* save temperature reference,
2151          *   so we can determine next time to calibrate */
2152         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2153         priv->last_temperature = temperature;
2154
2155         iwl3945_hw_reg_init_channel_groups(priv);
2156
2157         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2158         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2159              i++, ch_info++) {
2160                 a_band = is_channel_a_band(ch_info);
2161                 if (!is_channel_valid(ch_info))
2162                         continue;
2163
2164                 /* find this channel's channel group (*not* "band") index */
2165                 ch_info->group_index =
2166                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2167
2168                 /* Get this chnlgrp's rate->max/clip-powers table */
2169                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
2170
2171                 /* calculate power index *adjustment* value according to
2172                  *  diff between current temperature and factory temperature */
2173                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2174                                 eeprom->groups[ch_info->group_index].
2175                                 temperature);
2176
2177                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2178                                 ch_info->channel, delta_index, temperature +
2179                                 IWL_TEMP_CONVERT);
2180
2181                 /* set tx power value for all OFDM rates */
2182                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2183                      rate_index++) {
2184                         s32 uninitialized_var(power_idx);
2185                         int rc;
2186
2187                         /* use channel group's clip-power table,
2188                          *   but don't exceed channel's max power */
2189                         s8 pwr = min(ch_info->max_power_avg,
2190                                      clip_pwrs[rate_index]);
2191
2192                         pwr_info = &ch_info->power_info[rate_index];
2193
2194                         /* get base (i.e. at factory-measured temperature)
2195                          *    power table index for this rate's power */
2196                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2197                                                          ch_info->group_index,
2198                                                          &power_idx);
2199                         if (rc) {
2200                                 IWL_ERR(priv, "Invalid power index\n");
2201                                 return rc;
2202                         }
2203                         pwr_info->base_power_index = (u8) power_idx;
2204
2205                         /* temperature compensate */
2206                         power_idx += delta_index;
2207
2208                         /* stay within range of gain table */
2209                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2210
2211                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2212                         pwr_info->requested_power = pwr;
2213                         pwr_info->power_table_index = (u8) power_idx;
2214                         pwr_info->tpc.tx_gain =
2215                             power_gain_table[a_band][power_idx].tx_gain;
2216                         pwr_info->tpc.dsp_atten =
2217                             power_gain_table[a_band][power_idx].dsp_atten;
2218                 }
2219
2220                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2221                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2222                 power = pwr_info->requested_power +
2223                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2224                 pwr_index = pwr_info->power_table_index +
2225                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2226                 base_pwr_index = pwr_info->base_power_index +
2227                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2228
2229                 /* stay within table range */
2230                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2231                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2232                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2233
2234                 /* fill each CCK rate's iwl3945_channel_power_info structure
2235                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2236                  * NOTE:  CCK rates start at end of OFDM rates! */
2237                 for (rate_index = 0;
2238                      rate_index < IWL_CCK_RATES; rate_index++) {
2239                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2240                         pwr_info->requested_power = power;
2241                         pwr_info->power_table_index = pwr_index;
2242                         pwr_info->base_power_index = base_pwr_index;
2243                         pwr_info->tpc.tx_gain = gain;
2244                         pwr_info->tpc.dsp_atten = dsp_atten;
2245                 }
2246
2247                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2248                 for (scan_tbl_index = 0;
2249                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2250                         s32 actual_index = (scan_tbl_index == 0) ?
2251                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2252                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2253                                 actual_index, clip_pwrs, ch_info, a_band);
2254                 }
2255         }
2256
2257         return 0;
2258 }
2259
2260 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2261 {
2262         int rc;
2263
2264         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2265         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2266                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2267         if (rc < 0)
2268                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2269
2270         return 0;
2271 }
2272
2273 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2274 {
2275         int txq_id = txq->q.id;
2276
2277         struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
2278
2279         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2280
2281         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2282         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2283
2284         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2285                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2286                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2287                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2288                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2289                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2290
2291         /* fake read to flush all prev. writes */
2292         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2293
2294         return 0;
2295 }
2296
2297 /*
2298  * HCMD utils
2299  */
2300 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2301 {
2302         switch (cmd_id) {
2303         case REPLY_RXON:
2304                 return sizeof(struct iwl3945_rxon_cmd);
2305         case POWER_TABLE_CMD:
2306                 return sizeof(struct iwl3945_powertable_cmd);
2307         default:
2308                 return len;
2309         }
2310 }
2311
2312
2313 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2314 {
2315         struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2316         addsta->mode = cmd->mode;
2317         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2318         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2319         addsta->station_flags = cmd->station_flags;
2320         addsta->station_flags_msk = cmd->station_flags_msk;
2321         addsta->tid_disable_tx = cpu_to_le16(0);
2322         addsta->rate_n_flags = cmd->rate_n_flags;
2323         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2324         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2325         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2326
2327         return (u16)sizeof(struct iwl3945_addsta_cmd);
2328 }
2329
2330
2331 /**
2332  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2333  */
2334 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2335 {
2336         int rc, i, index, prev_index;
2337         struct iwl3945_rate_scaling_cmd rate_cmd = {
2338                 .reserved = {0, 0, 0},
2339         };
2340         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2341
2342         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2343                 index = iwl3945_rates[i].table_rs_index;
2344
2345                 table[index].rate_n_flags =
2346                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2347                 table[index].try_cnt = priv->retry_rate;
2348                 prev_index = iwl3945_get_prev_ieee_rate(i);
2349                 table[index].next_rate_index =
2350                                 iwl3945_rates[prev_index].table_rs_index;
2351         }
2352
2353         switch (priv->band) {
2354         case IEEE80211_BAND_5GHZ:
2355                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2356                 /* If one of the following CCK rates is used,
2357                  * have it fall back to the 6M OFDM rate */
2358                 for (i = IWL_RATE_1M_INDEX_TABLE;
2359                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2360                         table[i].next_rate_index =
2361                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2362
2363                 /* Don't fall back to CCK rates */
2364                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2365                                                 IWL_RATE_9M_INDEX_TABLE;
2366
2367                 /* Don't drop out of OFDM rates */
2368                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2369                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2370                 break;
2371
2372         case IEEE80211_BAND_2GHZ:
2373                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2374                 /* If an OFDM rate is used, have it fall back to the
2375                  * 1M CCK rates */
2376
2377                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2378                     iwl_is_associated(priv)) {
2379
2380                         index = IWL_FIRST_CCK_RATE;
2381                         for (i = IWL_RATE_6M_INDEX_TABLE;
2382                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2383                                 table[i].next_rate_index =
2384                                         iwl3945_rates[index].table_rs_index;
2385
2386                         index = IWL_RATE_11M_INDEX_TABLE;
2387                         /* CCK shouldn't fall back to OFDM... */
2388                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2389                 }
2390                 break;
2391
2392         default:
2393                 WARN_ON(1);
2394                 break;
2395         }
2396
2397         /* Update the rate scaling for control frame Tx */
2398         rate_cmd.table_id = 0;
2399         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2400                               &rate_cmd);
2401         if (rc)
2402                 return rc;
2403
2404         /* Update the rate scaling for data frame Tx */
2405         rate_cmd.table_id = 1;
2406         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2407                                 &rate_cmd);
2408 }
2409
2410 /* Called when initializing driver */
2411 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2412 {
2413         memset((void *)&priv->hw_params, 0,
2414                sizeof(struct iwl_hw_params));
2415
2416         priv->_3945.shared_virt =
2417                 dma_alloc_coherent(&priv->pci_dev->dev,
2418                                    sizeof(struct iwl3945_shared),
2419                                    &priv->_3945.shared_phys, GFP_KERNEL);
2420         if (!priv->_3945.shared_virt) {
2421                 IWL_ERR(priv, "failed to allocate pci memory\n");
2422                 mutex_unlock(&priv->mutex);
2423                 return -ENOMEM;
2424         }
2425
2426         /* Assign number of Usable TX queues */
2427         priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
2428
2429         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2430         priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2431         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2432         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2433         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2434         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2435
2436         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2437         priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2438
2439         return 0;
2440 }
2441
2442 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2443                           struct iwl3945_frame *frame, u8 rate)
2444 {
2445         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2446         unsigned int frame_size;
2447
2448         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2449         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2450
2451         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2452         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2453
2454         frame_size = iwl3945_fill_beacon_frame(priv,
2455                                 tx_beacon_cmd->frame,
2456                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2457
2458         BUG_ON(frame_size > MAX_MPDU_SIZE);
2459         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2460
2461         tx_beacon_cmd->tx.rate = rate;
2462         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2463                                       TX_CMD_FLG_TSF_MSK);
2464
2465         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2466         tx_beacon_cmd->tx.supp_rates[0] =
2467                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2468
2469         tx_beacon_cmd->tx.supp_rates[1] =
2470                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2471
2472         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2473 }
2474
2475 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2476 {
2477         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2478         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2479 }
2480
2481 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2482 {
2483         INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
2484                           iwl3945_bg_reg_txpower_periodic);
2485 }
2486
2487 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2488 {
2489         cancel_delayed_work(&priv->_3945.thermal_periodic);
2490 }
2491
2492 /* check contents of special bootstrap uCode SRAM */
2493 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2494  {
2495         __le32 *image = priv->ucode_boot.v_addr;
2496         u32 len = priv->ucode_boot.len;
2497         u32 reg;
2498         u32 val;
2499
2500         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2501
2502         /* verify BSM SRAM contents */
2503         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2504         for (reg = BSM_SRAM_LOWER_BOUND;
2505              reg < BSM_SRAM_LOWER_BOUND + len;
2506              reg += sizeof(u32), image++) {
2507                 val = iwl_read_prph(priv, reg);
2508                 if (val != le32_to_cpu(*image)) {
2509                         IWL_ERR(priv, "BSM uCode verification failed at "
2510                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2511                                   BSM_SRAM_LOWER_BOUND,
2512                                   reg - BSM_SRAM_LOWER_BOUND, len,
2513                                   val, le32_to_cpu(*image));
2514                         return -EIO;
2515                 }
2516         }
2517
2518         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2519
2520         return 0;
2521 }
2522
2523
2524 /******************************************************************************
2525  *
2526  * EEPROM related functions
2527  *
2528  ******************************************************************************/
2529
2530 /*
2531  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2532  * embedded controller) as EEPROM reader; each read is a series of pulses
2533  * to/from the EEPROM chip, not a single event, so even reads could conflict
2534  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2535  * simply claims ownership, which should be safe when this function is called
2536  * (i.e. before loading uCode!).
2537  */
2538 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2539 {
2540         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2541         return 0;
2542 }
2543
2544
2545 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2546 {
2547         return;
2548 }
2549
2550  /**
2551   * iwl3945_load_bsm - Load bootstrap instructions
2552   *
2553   * BSM operation:
2554   *
2555   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2556   * in special SRAM that does not power down during RFKILL.  When powering back
2557   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2558   * the bootstrap program into the on-board processor, and starts it.
2559   *
2560   * The bootstrap program loads (via DMA) instructions and data for a new
2561   * program from host DRAM locations indicated by the host driver in the
2562   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2563   * automatically.
2564   *
2565   * When initializing the NIC, the host driver points the BSM to the
2566   * "initialize" uCode image.  This uCode sets up some internal data, then
2567   * notifies host via "initialize alive" that it is complete.
2568   *
2569   * The host then replaces the BSM_DRAM_* pointer values to point to the
2570   * normal runtime uCode instructions and a backup uCode data cache buffer
2571   * (filled initially with starting data values for the on-board processor),
2572   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2573   * which begins normal operation.
2574   *
2575   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2576   * the backup data cache in DRAM before SRAM is powered down.
2577   *
2578   * When powering back up, the BSM loads the bootstrap program.  This reloads
2579   * the runtime uCode instructions and the backup data cache into SRAM,
2580   * and re-launches the runtime uCode from where it left off.
2581   */
2582 static int iwl3945_load_bsm(struct iwl_priv *priv)
2583 {
2584         __le32 *image = priv->ucode_boot.v_addr;
2585         u32 len = priv->ucode_boot.len;
2586         dma_addr_t pinst;
2587         dma_addr_t pdata;
2588         u32 inst_len;
2589         u32 data_len;
2590         int rc;
2591         int i;
2592         u32 done;
2593         u32 reg_offset;
2594
2595         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2596
2597         /* make sure bootstrap program is no larger than BSM's SRAM size */
2598         if (len > IWL39_MAX_BSM_SIZE)
2599                 return -EINVAL;
2600
2601         /* Tell bootstrap uCode where to find the "Initialize" uCode
2602         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2603         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2604         *        after the "initialize" uCode has run, to point to
2605         *        runtime/protocol instructions and backup data cache. */
2606         pinst = priv->ucode_init.p_addr;
2607         pdata = priv->ucode_init_data.p_addr;
2608         inst_len = priv->ucode_init.len;
2609         data_len = priv->ucode_init_data.len;
2610
2611         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2612         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2613         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2614         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2615
2616         /* Fill BSM memory with bootstrap instructions */
2617         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2618              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2619              reg_offset += sizeof(u32), image++)
2620                 _iwl_write_prph(priv, reg_offset,
2621                                           le32_to_cpu(*image));
2622
2623         rc = iwl3945_verify_bsm(priv);
2624         if (rc)
2625                 return rc;
2626
2627         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2628         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2629         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2630                                  IWL39_RTC_INST_LOWER_BOUND);
2631         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2632
2633         /* Load bootstrap code into instruction SRAM now,
2634          *   to prepare to load "initialize" uCode */
2635         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2636                 BSM_WR_CTRL_REG_BIT_START);
2637
2638         /* Wait for load of bootstrap uCode to finish */
2639         for (i = 0; i < 100; i++) {
2640                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2641                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2642                         break;
2643                 udelay(10);
2644         }
2645         if (i < 100)
2646                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2647         else {
2648                 IWL_ERR(priv, "BSM write did not complete!\n");
2649                 return -EIO;
2650         }
2651
2652         /* Enable future boot loads whenever power management unit triggers it
2653          *   (e.g. when powering back up after power-save shutdown) */
2654         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2655                 BSM_WR_CTRL_REG_BIT_START_EN);
2656
2657         return 0;
2658 }
2659
2660 #define IWL3945_UCODE_GET(item)                                         \
2661 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2662                                     u32 api_ver)                        \
2663 {                                                                       \
2664         return le32_to_cpu(ucode->u.v1.item);                           \
2665 }
2666
2667 static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2668 {
2669         return UCODE_HEADER_SIZE(1);
2670 }
2671 static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2672                                    u32 api_ver)
2673 {
2674         return 0;
2675 }
2676 static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2677                                   u32 api_ver)
2678 {
2679         return (u8 *) ucode->u.v1.data;
2680 }
2681
2682 IWL3945_UCODE_GET(inst_size);
2683 IWL3945_UCODE_GET(data_size);
2684 IWL3945_UCODE_GET(init_size);
2685 IWL3945_UCODE_GET(init_data_size);
2686 IWL3945_UCODE_GET(boot_size);
2687
2688 static struct iwl_hcmd_ops iwl3945_hcmd = {
2689         .rxon_assoc = iwl3945_send_rxon_assoc,
2690         .commit_rxon = iwl3945_commit_rxon,
2691         .send_bt_config = iwl_send_bt_config,
2692 };
2693
2694 static struct iwl_ucode_ops iwl3945_ucode = {
2695         .get_header_size = iwl3945_ucode_get_header_size,
2696         .get_build = iwl3945_ucode_get_build,
2697         .get_inst_size = iwl3945_ucode_get_inst_size,
2698         .get_data_size = iwl3945_ucode_get_data_size,
2699         .get_init_size = iwl3945_ucode_get_init_size,
2700         .get_init_data_size = iwl3945_ucode_get_init_data_size,
2701         .get_boot_size = iwl3945_ucode_get_boot_size,
2702         .get_data = iwl3945_ucode_get_data,
2703 };
2704
2705 static struct iwl_lib_ops iwl3945_lib = {
2706         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2707         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2708         .txq_init = iwl3945_hw_tx_queue_init,
2709         .load_ucode = iwl3945_load_bsm,
2710         .dump_nic_event_log = iwl3945_dump_nic_event_log,
2711         .dump_nic_error_log = iwl3945_dump_nic_error_log,
2712         .apm_ops = {
2713                 .init = iwl3945_apm_init,
2714                 .stop = iwl_apm_stop,
2715                 .config = iwl3945_nic_config,
2716                 .set_pwr_src = iwl3945_set_pwr_src,
2717         },
2718         .eeprom_ops = {
2719                 .regulatory_bands = {
2720                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2721                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2722                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2723                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2724                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2725                         EEPROM_REGULATORY_BAND_NO_HT40,
2726                         EEPROM_REGULATORY_BAND_NO_HT40,
2727                 },
2728                 .verify_signature  = iwlcore_eeprom_verify_signature,
2729                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2730                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2731                 .query_addr = iwlcore_eeprom_query_addr,
2732         },
2733         .send_tx_power  = iwl3945_send_tx_power,
2734         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2735         .post_associate = iwl3945_post_associate,
2736         .isr = iwl_isr_legacy,
2737         .config_ap = iwl3945_config_ap,
2738         .add_bcast_station = iwl3945_add_bcast_station,
2739 };
2740
2741 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2742         .get_hcmd_size = iwl3945_get_hcmd_size,
2743         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2744         .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2745         .request_scan = iwl3945_request_scan,
2746 };
2747
2748 static const struct iwl_ops iwl3945_ops = {
2749         .ucode = &iwl3945_ucode,
2750         .lib = &iwl3945_lib,
2751         .hcmd = &iwl3945_hcmd,
2752         .utils = &iwl3945_hcmd_utils,
2753         .led = &iwl3945_led_ops,
2754 };
2755
2756 static struct iwl_cfg iwl3945_bg_cfg = {
2757         .name = "3945BG",
2758         .fw_name_pre = IWL3945_FW_PRE,
2759         .ucode_api_max = IWL3945_UCODE_API_MAX,
2760         .ucode_api_min = IWL3945_UCODE_API_MIN,
2761         .sku = IWL_SKU_G,
2762         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2763         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2764         .ops = &iwl3945_ops,
2765         .num_of_queues = IWL39_NUM_QUEUES,
2766         .mod_params = &iwl3945_mod_params,
2767         .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2768         .set_l0s = false,
2769         .use_bsm = true,
2770         .use_isr_legacy = true,
2771         .ht_greenfield_support = false,
2772         .led_compensation = 64,
2773         .broken_powersave = true,
2774         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
2775         .monitor_recover_period = IWL_MONITORING_PERIOD,
2776         .max_event_log_size = 512,
2777 };
2778
2779 static struct iwl_cfg iwl3945_abg_cfg = {
2780         .name = "3945ABG",
2781         .fw_name_pre = IWL3945_FW_PRE,
2782         .ucode_api_max = IWL3945_UCODE_API_MAX,
2783         .ucode_api_min = IWL3945_UCODE_API_MIN,
2784         .sku = IWL_SKU_A|IWL_SKU_G,
2785         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2786         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2787         .ops = &iwl3945_ops,
2788         .num_of_queues = IWL39_NUM_QUEUES,
2789         .mod_params = &iwl3945_mod_params,
2790         .use_isr_legacy = true,
2791         .ht_greenfield_support = false,
2792         .led_compensation = 64,
2793         .broken_powersave = true,
2794         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
2795         .monitor_recover_period = IWL_MONITORING_PERIOD,
2796         .max_event_log_size = 512,
2797 };
2798
2799 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
2800         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2801         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2802         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2803         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2804         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2805         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2806         {0}
2807 };
2808
2809 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);