1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2017 Intel Deutschland GmbH
9 * Copyright(c) 2018 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
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15 * This program is distributed in the hope that it will be useful, but
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17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
22 * Copyright(c) 2017 Intel Deutschland GmbH
23 * Copyright(c) 2018 Intel Corporation
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52 *****************************************************************************/
53 #include "iwl-trans.h"
55 #include "iwl-context-info.h"
56 #include "iwl-context-info-gen3.h"
60 * Start up NIC's basic functionality after it has been reset
61 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
62 * NOTE: This does not load uCode nor start the embedded processor
64 static int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
68 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
71 * Use "set_bit" below rather than "write", to preserve any hardware
72 * bits already set by default after reset.
76 * Disable L0s without affecting L1;
77 * don't wait for ICH L0s (ICH bug W/A)
79 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
80 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
82 /* Set FH wait threshold to maximum (HW error during stress W/A) */
83 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
86 * Enable HAP INTA (interrupt from management bus) to
87 * wake device's PCI Express link L1a -> L0s
89 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
90 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
92 iwl_pcie_apm_config(trans);
95 * Set "initialization complete" bit to move adapter from
96 * D0U* --> D0A* (powered-up active) state.
98 iwl_set_bit(trans, CSR_GP_CNTRL,
99 BIT(trans->cfg->csr->flag_init_done));
102 * Wait for clock stabilization; once stabilized, access to
103 * device-internal resources is supported, e.g. iwl_write_prph()
104 * and accesses to uCode SRAM.
106 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
107 BIT(trans->cfg->csr->flag_mac_clock_ready),
108 BIT(trans->cfg->csr->flag_mac_clock_ready),
111 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
115 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
120 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
122 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
125 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
126 iwl_pcie_gen2_apm_init(trans);
128 /* inform ME that we are leaving */
129 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
130 CSR_RESET_LINK_PWR_MGMT_DISABLED);
131 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
132 CSR_HW_IF_CONFIG_REG_PREPARE |
133 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
135 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
136 CSR_RESET_LINK_PWR_MGMT_DISABLED);
140 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
142 /* Stop device's DMA activity */
143 iwl_pcie_apm_stop_master(trans);
145 iwl_trans_sw_reset(trans);
148 * Clear "initialization complete" bit to move adapter from
149 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
151 iwl_clear_bit(trans, CSR_GP_CNTRL,
152 BIT(trans->cfg->csr->flag_init_done));
155 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power)
157 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
159 lockdep_assert_held(&trans_pcie->mutex);
161 if (trans_pcie->is_down)
164 trans_pcie->is_down = true;
166 /* Stop dbgc before stopping device */
167 iwl_write_prph(trans, DBGC_IN_SAMPLE, 0);
169 iwl_write_prph(trans, DBGC_OUT_CTRL, 0);
171 /* tell the device to stop sending interrupts */
172 iwl_disable_interrupts(trans);
174 /* device going down, Stop using ICT table */
175 iwl_pcie_disable_ict(trans);
178 * If a HW restart happens during firmware loading,
179 * then the firmware loading might call this function
180 * and later it might be called again due to the
181 * restart. So don't process again if the device is
184 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
185 IWL_DEBUG_INFO(trans,
186 "DEVICE_ENABLED bit was set and is now cleared\n");
187 iwl_pcie_gen2_tx_stop(trans);
188 iwl_pcie_rx_stop(trans);
191 iwl_pcie_ctxt_info_free_paging(trans);
192 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_22560)
193 iwl_pcie_ctxt_info_gen3_free(trans);
195 iwl_pcie_ctxt_info_free(trans);
197 /* Make sure (redundant) we've released our request to stay awake */
198 iwl_clear_bit(trans, CSR_GP_CNTRL,
199 BIT(trans->cfg->csr->flag_mac_access_req));
201 /* Stop the device, and put it in low power state */
202 iwl_pcie_gen2_apm_stop(trans, false);
204 iwl_trans_sw_reset(trans);
207 * Upon stop, the IVAR table gets erased, so msi-x won't
208 * work. This causes a bug in RF-KILL flows, since the interrupt
209 * that enables radio won't fire on the correct irq, and the
210 * driver won't be able to handle the interrupt.
211 * Configure the IVAR table again after reset.
213 iwl_pcie_conf_msix_hw(trans_pcie);
216 * Upon stop, the APM issues an interrupt if HW RF kill is set.
217 * This is a bug in certain verions of the hardware.
218 * Certain devices also keep sending HW RF kill interrupt all
219 * the time, unless the interrupt is ACKed even if the interrupt
220 * should be masked. Re-ACK all the interrupts here.
222 iwl_disable_interrupts(trans);
224 /* clear all status bits */
225 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
226 clear_bit(STATUS_INT_ENABLED, &trans->status);
227 clear_bit(STATUS_TPOWER_PMI, &trans->status);
230 * Even if we stop the HW, we still want the RF kill
233 iwl_enable_rfkill_int(trans);
235 /* re-take ownership to prevent other users from stealing the device */
236 iwl_pcie_prepare_card_hw(trans);
239 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power)
241 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
244 mutex_lock(&trans_pcie->mutex);
245 trans_pcie->opmode_down = true;
246 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
247 _iwl_trans_pcie_gen2_stop_device(trans, low_power);
248 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
249 mutex_unlock(&trans_pcie->mutex);
252 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
254 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
256 /* TODO: most of the logic can be removed in A0 - but not in Z0 */
257 spin_lock(&trans_pcie->irq_lock);
258 iwl_pcie_gen2_apm_init(trans);
259 spin_unlock(&trans_pcie->irq_lock);
261 iwl_op_mode_nic_config(trans->op_mode);
263 /* Allocate the RX queue, or reset if it is already allocated */
264 if (iwl_pcie_gen2_rx_init(trans))
267 /* Allocate or reset and init all Tx and Command queues */
268 if (iwl_pcie_gen2_tx_init(trans))
271 /* enable shadow regs in HW */
272 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
273 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
278 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr)
280 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
282 iwl_pcie_reset_ict(trans);
284 /* make sure all queue are not stopped/used */
285 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
286 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
288 /* now that we got alive we can free the fw image & the context info.
289 * paging memory cannot be freed included since FW will still use it
291 iwl_pcie_ctxt_info_free(trans);
294 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
295 const struct fw_img *fw, bool run_in_rfkill)
297 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
301 /* This may fail if AMT took ownership of the device */
302 if (iwl_pcie_prepare_card_hw(trans)) {
303 IWL_WARN(trans, "Exit HW not ready\n");
308 iwl_enable_rfkill_int(trans);
310 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
313 * We enabled the RF-Kill interrupt and the handler may very
314 * well be running. Disable the interrupts to make sure no other
315 * interrupt can be fired.
317 iwl_disable_interrupts(trans);
319 /* Make sure it finished running */
320 iwl_pcie_synchronize_irqs(trans);
322 mutex_lock(&trans_pcie->mutex);
324 /* If platform's RF_KILL switch is NOT set to KILL */
325 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
326 if (hw_rfkill && !run_in_rfkill) {
331 /* Someone called stop_device, don't try to start_fw */
332 if (trans_pcie->is_down) {
334 "Can't start_fw since the HW hasn't been started\n");
339 /* make sure rfkill handshake bits are cleared */
340 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
341 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
342 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
344 /* clear (again), then enable host interrupts */
345 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
347 ret = iwl_pcie_gen2_nic_init(trans);
349 IWL_ERR(trans, "Unable to init nic\n");
353 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_22560)
354 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw);
356 ret = iwl_pcie_ctxt_info_init(trans, fw);
360 /* re-check RF-Kill state since we may have missed the interrupt */
361 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
362 if (hw_rfkill && !run_in_rfkill)
366 mutex_unlock(&trans_pcie->mutex);