1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2003-2014, 2018-2020 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
7 #include <linux/sched.h>
8 #include <linux/wait.h>
14 #include "iwl-op-mode.h"
15 #include "iwl-context-info-gen3.h"
17 /******************************************************************************
21 ******************************************************************************/
24 * Rx theory of operation
26 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
27 * each of which point to Receive Buffers to be filled by the NIC. These get
28 * used not only for Rx frames, but for any command response or notification
29 * from the NIC. The driver and NIC manage the Rx buffers by means
30 * of indexes into the circular buffer.
33 * The host/firmware share two index registers for managing the Rx buffers.
35 * The READ index maps to the first position that the firmware may be writing
36 * to -- the driver can read up to (but not including) this position and get
38 * The READ index is managed by the firmware once the card is enabled.
40 * The WRITE index maps to the last position the driver has read from -- the
41 * position preceding WRITE is the last slot the firmware can place a packet.
43 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
46 * During initialization, the host sets up the READ queue position to the first
47 * INDEX position, and WRITE to the last (READ - 1 wrapped)
49 * When the firmware places a packet in a buffer, it will advance the READ index
50 * and fire the RX interrupt. The driver can then query the READ index and
51 * process as many packets as possible, moving the WRITE index forward as it
52 * resets the Rx queue buffers with new memory.
54 * The management in the driver is as follows:
55 * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free.
56 * When the interrupt handler is called, the request is processed.
57 * The page is either stolen - transferred to the upper layer
58 * or reused - added immediately to the iwl->rxq->rx_free list.
59 * + When the page is stolen - the driver updates the matching queue's used
60 * count, detaches the RBD and transfers it to the queue used list.
61 * When there are two used RBDs - they are transferred to the allocator empty
62 * list. Work is then scheduled for the allocator to start allocating
64 * When there are another 6 used RBDs - they are transferred to the allocator
65 * empty list and the driver tries to claim the pre-allocated buffers and
66 * add them to iwl->rxq->rx_free. If it fails - it continues to claim them
68 * When there are 8+ buffers in the free list - either from allocation or from
69 * 8 reused unstolen pages - restock is called to update the FW and indexes.
70 * + In order to make sure the allocator always has RBDs to use for allocation
71 * the allocator has initial pool in the size of num_queues*(8-2) - the
72 * maximum missing RBDs per allocation request (request posted with 2
73 * empty RBDs, there is no guarantee when the other 6 RBDs are supplied).
74 * The queues supplies the recycle of the rest of the RBDs.
75 * + A received packet is processed and handed to the kernel network stack,
76 * detached from the iwl->rxq. The driver 'processed' index is updated.
77 * + If there are no allocated buffers in iwl->rxq->rx_free,
78 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
79 * If there were enough free buffers and RX_STALLED is set it is cleared.
84 * iwl_rxq_alloc() Allocates rx_free
85 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls
86 * iwl_pcie_rxq_restock.
87 * Used only during initialization.
88 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx
89 * queue, updates firmware pointers, and updates
91 * iwl_pcie_rx_allocator() Background work for allocating pages.
93 * -- enable interrupts --
94 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
95 * READ INDEX, detaching the SKB from the pool.
96 * Moves the packet buffer from queue to rx_used.
97 * Posts and claims requests to the allocator.
98 * Calls iwl_pcie_rxq_restock to refill any empty
104 * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue
106 * Regular Receive interrupt:
108 * rxq.queue -> rxq.rx_used -> allocator.rbd_empty ->
109 * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue
111 * rxq.queue -> rxq.rx_free -> rxq.queue
117 * iwl_rxq_space - Return number of free slots available in queue.
119 static int iwl_rxq_space(const struct iwl_rxq *rxq)
121 /* Make sure rx queue size is a power of 2 */
122 WARN_ON(rxq->queue_size & (rxq->queue_size - 1));
125 * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
126 * between empty and completely full queues.
127 * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
128 * defined for negative dividends.
130 return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1);
134 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
136 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
138 return cpu_to_le32((u32)(dma_addr >> 8));
142 * iwl_pcie_rx_stop - stops the Rx DMA
144 int iwl_pcie_rx_stop(struct iwl_trans *trans)
146 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
147 /* TODO: remove this once fw does it */
148 iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0);
149 return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_GEN3,
150 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
151 } else if (trans->trans_cfg->mq_rx_supported) {
152 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);
153 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS,
154 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
156 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
157 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
158 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
164 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
166 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
171 lockdep_assert_held(&rxq->lock);
174 * explicitly wake up the NIC if:
175 * 1. shadow registers aren't enabled
176 * 2. there is a chance that the NIC is asleep
178 if (!trans->trans_cfg->base_params->shadow_reg_enable &&
179 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
180 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
182 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
183 IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n",
185 iwl_set_bit(trans, CSR_GP_CNTRL,
186 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
187 rxq->need_update = true;
192 rxq->write_actual = round_down(rxq->write, 8);
193 if (trans->trans_cfg->mq_rx_supported)
194 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),
197 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
200 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans)
202 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
205 for (i = 0; i < trans->num_rx_queues; i++) {
206 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
208 if (!rxq->need_update)
210 spin_lock_bh(&rxq->lock);
211 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
212 rxq->need_update = false;
213 spin_unlock_bh(&rxq->lock);
217 static void iwl_pcie_restock_bd(struct iwl_trans *trans,
219 struct iwl_rx_mem_buffer *rxb)
221 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
222 struct iwl_rx_transfer_desc *bd = rxq->bd;
224 BUILD_BUG_ON(sizeof(*bd) != 2 * sizeof(u64));
226 bd[rxq->write].addr = cpu_to_le64(rxb->page_dma);
227 bd[rxq->write].rbid = cpu_to_le16(rxb->vid);
229 __le64 *bd = rxq->bd;
231 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid);
234 IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n",
235 (u32)rxb->vid, rxq->id, rxq->write);
239 * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx
241 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans,
244 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
245 struct iwl_rx_mem_buffer *rxb;
248 * If the device isn't enabled - no need to try to add buffers...
249 * This can happen when we stop the device and still have an interrupt
250 * pending. We stop the APM before we sync the interrupts because we
251 * have to (see comment there). On the other hand, since the APM is
252 * stopped, we cannot access the HW (in particular not prph).
253 * So don't try to restock if the APM has been already stopped.
255 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
258 spin_lock_bh(&rxq->lock);
259 while (rxq->free_count) {
260 /* Get next free Rx buffer, remove from free list */
261 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
263 list_del(&rxb->list);
264 rxb->invalid = false;
265 /* some low bits are expected to be unset (depending on hw) */
266 WARN_ON(rxb->page_dma & trans_pcie->supported_dma_mask);
267 /* Point to Rx buffer via next RBD in circular buffer */
268 iwl_pcie_restock_bd(trans, rxq, rxb);
269 rxq->write = (rxq->write + 1) & (rxq->queue_size - 1);
272 spin_unlock_bh(&rxq->lock);
275 * If we've added more space for the firmware to place data, tell it.
276 * Increment device's write pointer in multiples of 8.
278 if (rxq->write_actual != (rxq->write & ~0x7)) {
279 spin_lock_bh(&rxq->lock);
280 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
281 spin_unlock_bh(&rxq->lock);
286 * iwl_pcie_rxsq_restock - restock implementation for single queue rx
288 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans,
291 struct iwl_rx_mem_buffer *rxb;
294 * If the device isn't enabled - not need to try to add buffers...
295 * This can happen when we stop the device and still have an interrupt
296 * pending. We stop the APM before we sync the interrupts because we
297 * have to (see comment there). On the other hand, since the APM is
298 * stopped, we cannot access the HW (in particular not prph).
299 * So don't try to restock if the APM has been already stopped.
301 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
304 spin_lock_bh(&rxq->lock);
305 while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
306 __le32 *bd = (__le32 *)rxq->bd;
307 /* The overwritten rxb must be a used one */
308 rxb = rxq->queue[rxq->write];
309 BUG_ON(rxb && rxb->page);
311 /* Get next free Rx buffer, remove from free list */
312 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
314 list_del(&rxb->list);
315 rxb->invalid = false;
317 /* Point to Rx buffer via next RBD in circular buffer */
318 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
319 rxq->queue[rxq->write] = rxb;
320 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
323 spin_unlock_bh(&rxq->lock);
325 /* If we've added more space for the firmware to place data, tell it.
326 * Increment device's write pointer in multiples of 8. */
327 if (rxq->write_actual != (rxq->write & ~0x7)) {
328 spin_lock_bh(&rxq->lock);
329 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
330 spin_unlock_bh(&rxq->lock);
335 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
337 * If there are slots in the RX queue that need to be restocked,
338 * and we have free pre-allocated buffers, fill the ranks as much
339 * as we can, pulling from rx_free.
341 * This moves the 'write' index forward to catch up with 'processed', and
342 * also updates the memory address in the firmware to reference the new
346 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq)
348 if (trans->trans_cfg->mq_rx_supported)
349 iwl_pcie_rxmq_restock(trans, rxq);
351 iwl_pcie_rxsq_restock(trans, rxq);
355 * iwl_pcie_rx_alloc_page - allocates and returns a page.
358 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans,
359 u32 *offset, gfp_t priority)
361 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
362 unsigned int rbsize = iwl_trans_get_rb_size(trans_pcie->rx_buf_size);
363 unsigned int allocsize = PAGE_SIZE << trans_pcie->rx_page_order;
365 gfp_t gfp_mask = priority;
367 if (trans_pcie->rx_page_order > 0)
368 gfp_mask |= __GFP_COMP;
370 if (trans_pcie->alloc_page) {
371 spin_lock_bh(&trans_pcie->alloc_page_lock);
373 if (trans_pcie->alloc_page) {
374 *offset = trans_pcie->alloc_page_used;
375 page = trans_pcie->alloc_page;
376 trans_pcie->alloc_page_used += rbsize;
377 if (trans_pcie->alloc_page_used >= allocsize)
378 trans_pcie->alloc_page = NULL;
381 spin_unlock_bh(&trans_pcie->alloc_page_lock);
384 spin_unlock_bh(&trans_pcie->alloc_page_lock);
387 /* Alloc a new receive buffer */
388 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
391 IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n",
392 trans_pcie->rx_page_order);
394 * Issue an error if we don't have enough pre-allocated
397 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit())
399 "Failed to alloc_pages\n");
403 if (2 * rbsize <= allocsize) {
404 spin_lock_bh(&trans_pcie->alloc_page_lock);
405 if (!trans_pcie->alloc_page) {
407 trans_pcie->alloc_page = page;
408 trans_pcie->alloc_page_used = rbsize;
410 spin_unlock_bh(&trans_pcie->alloc_page_lock);
418 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
420 * A used RBD is an Rx buffer that has been given to the stack. To use it again
421 * a page must be allocated and the RBD must point to the page. This function
422 * doesn't change the HW pointer but handles the list of pages that is used by
423 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
426 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
429 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
430 struct iwl_rx_mem_buffer *rxb;
436 spin_lock_bh(&rxq->lock);
437 if (list_empty(&rxq->rx_used)) {
438 spin_unlock_bh(&rxq->lock);
441 spin_unlock_bh(&rxq->lock);
443 page = iwl_pcie_rx_alloc_page(trans, &offset, priority);
447 spin_lock_bh(&rxq->lock);
449 if (list_empty(&rxq->rx_used)) {
450 spin_unlock_bh(&rxq->lock);
451 __free_pages(page, trans_pcie->rx_page_order);
454 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
456 list_del(&rxb->list);
457 spin_unlock_bh(&rxq->lock);
461 rxb->offset = offset;
462 /* Get physical address of the RB */
464 dma_map_page(trans->dev, page, rxb->offset,
465 trans_pcie->rx_buf_bytes,
467 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
469 spin_lock_bh(&rxq->lock);
470 list_add(&rxb->list, &rxq->rx_used);
471 spin_unlock_bh(&rxq->lock);
472 __free_pages(page, trans_pcie->rx_page_order);
476 spin_lock_bh(&rxq->lock);
478 list_add_tail(&rxb->list, &rxq->rx_free);
481 spin_unlock_bh(&rxq->lock);
485 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans)
487 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
490 for (i = 0; i < RX_POOL_SIZE(trans_pcie->num_rx_bufs); i++) {
491 if (!trans_pcie->rx_pool[i].page)
493 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma,
494 trans_pcie->rx_buf_bytes, DMA_FROM_DEVICE);
495 __free_pages(trans_pcie->rx_pool[i].page,
496 trans_pcie->rx_page_order);
497 trans_pcie->rx_pool[i].page = NULL;
502 * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues
504 * Allocates for each received request 8 pages
505 * Called as a scheduled work item.
507 static void iwl_pcie_rx_allocator(struct iwl_trans *trans)
509 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
510 struct iwl_rb_allocator *rba = &trans_pcie->rba;
511 struct list_head local_empty;
512 int pending = atomic_read(&rba->req_pending);
514 IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending);
516 /* If we were scheduled - there is at least one request */
517 spin_lock_bh(&rba->lock);
518 /* swap out the rba->rbd_empty to a local list */
519 list_replace_init(&rba->rbd_empty, &local_empty);
520 spin_unlock_bh(&rba->lock);
524 LIST_HEAD(local_allocated);
525 gfp_t gfp_mask = GFP_KERNEL;
527 /* Do not post a warning if there are only a few requests */
528 if (pending < RX_PENDING_WATERMARK)
529 gfp_mask |= __GFP_NOWARN;
531 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) {
532 struct iwl_rx_mem_buffer *rxb;
535 /* List should never be empty - each reused RBD is
536 * returned to the list, and initial pool covers any
537 * possible gap between the time the page is allocated
538 * to the time the RBD is added.
540 BUG_ON(list_empty(&local_empty));
541 /* Get the first rxb from the rbd list */
542 rxb = list_first_entry(&local_empty,
543 struct iwl_rx_mem_buffer, list);
546 /* Alloc a new receive buffer */
547 page = iwl_pcie_rx_alloc_page(trans, &rxb->offset,
553 /* Get physical address of the RB */
554 rxb->page_dma = dma_map_page(trans->dev, page,
556 trans_pcie->rx_buf_bytes,
558 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
560 __free_pages(page, trans_pcie->rx_page_order);
564 /* move the allocated entry to the out list */
565 list_move(&rxb->list, &local_allocated);
569 atomic_dec(&rba->req_pending);
573 pending = atomic_read(&rba->req_pending);
576 "Got more pending allocation requests = %d\n",
580 spin_lock_bh(&rba->lock);
581 /* add the allocated rbds to the allocator allocated list */
582 list_splice_tail(&local_allocated, &rba->rbd_allocated);
583 /* get more empty RBDs for current pending requests */
584 list_splice_tail_init(&rba->rbd_empty, &local_empty);
585 spin_unlock_bh(&rba->lock);
587 atomic_inc(&rba->req_ready);
591 spin_lock_bh(&rba->lock);
592 /* return unused rbds to the allocator empty list */
593 list_splice_tail(&local_empty, &rba->rbd_empty);
594 spin_unlock_bh(&rba->lock);
596 IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__);
600 * iwl_pcie_rx_allocator_get - returns the pre-allocated pages
602 .* Called by queue when the queue posted allocation request and
603 * has freed 8 RBDs in order to restock itself.
604 * This function directly moves the allocated RBs to the queue's ownership
605 * and updates the relevant counters.
607 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans,
610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
611 struct iwl_rb_allocator *rba = &trans_pcie->rba;
614 lockdep_assert_held(&rxq->lock);
617 * atomic_dec_if_positive returns req_ready - 1 for any scenario.
618 * If req_ready is 0 atomic_dec_if_positive will return -1 and this
619 * function will return early, as there are no ready requests.
620 * atomic_dec_if_positive will perofrm the *actual* decrement only if
621 * req_ready > 0, i.e. - there are ready requests and the function
622 * hands one request to the caller.
624 if (atomic_dec_if_positive(&rba->req_ready) < 0)
627 spin_lock(&rba->lock);
628 for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) {
629 /* Get next free Rx buffer, remove it from free list */
630 struct iwl_rx_mem_buffer *rxb =
631 list_first_entry(&rba->rbd_allocated,
632 struct iwl_rx_mem_buffer, list);
634 list_move(&rxb->list, &rxq->rx_free);
636 spin_unlock(&rba->lock);
638 rxq->used_count -= RX_CLAIM_REQ_ALLOC;
639 rxq->free_count += RX_CLAIM_REQ_ALLOC;
642 void iwl_pcie_rx_allocator_work(struct work_struct *data)
644 struct iwl_rb_allocator *rba_p =
645 container_of(data, struct iwl_rb_allocator, rx_alloc);
646 struct iwl_trans_pcie *trans_pcie =
647 container_of(rba_p, struct iwl_trans_pcie, rba);
649 iwl_pcie_rx_allocator(trans_pcie->trans);
652 static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td)
654 struct iwl_rx_transfer_desc *rx_td;
657 return sizeof(*rx_td);
659 return trans->trans_cfg->mq_rx_supported ? sizeof(__le64) :
663 static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans,
666 struct device *dev = trans->dev;
667 bool use_rx_td = (trans->trans_cfg->device_family >=
668 IWL_DEVICE_FAMILY_AX210);
669 int free_size = iwl_pcie_free_bd_size(trans, use_rx_td);
672 dma_free_coherent(trans->dev,
673 free_size * rxq->queue_size,
674 rxq->bd, rxq->bd_dma);
678 rxq->rb_stts_dma = 0;
682 dma_free_coherent(trans->dev,
683 (use_rx_td ? sizeof(*rxq->cd) :
684 sizeof(__le32)) * rxq->queue_size,
685 rxq->used_bd, rxq->used_bd_dma);
686 rxq->used_bd_dma = 0;
689 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
693 dma_free_coherent(dev, sizeof(__le16),
694 rxq->tr_tail, rxq->tr_tail_dma);
695 rxq->tr_tail_dma = 0;
699 dma_free_coherent(dev, sizeof(__le16),
700 rxq->cr_tail, rxq->cr_tail_dma);
701 rxq->cr_tail_dma = 0;
705 static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans,
708 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
709 struct device *dev = trans->dev;
712 bool use_rx_td = (trans->trans_cfg->device_family >=
713 IWL_DEVICE_FAMILY_AX210);
714 size_t rb_stts_size = use_rx_td ? sizeof(__le16) :
715 sizeof(struct iwl_rb_status);
717 spin_lock_init(&rxq->lock);
718 if (trans->trans_cfg->mq_rx_supported)
719 rxq->queue_size = trans->cfg->num_rbds;
721 rxq->queue_size = RX_QUEUE_SIZE;
723 free_size = iwl_pcie_free_bd_size(trans, use_rx_td);
726 * Allocate the circular buffer of Read Buffer Descriptors
729 rxq->bd = dma_alloc_coherent(dev, free_size * rxq->queue_size,
730 &rxq->bd_dma, GFP_KERNEL);
734 if (trans->trans_cfg->mq_rx_supported) {
735 rxq->used_bd = dma_alloc_coherent(dev,
736 (use_rx_td ? sizeof(*rxq->cd) : sizeof(__le32)) * rxq->queue_size,
743 rxq->rb_stts = trans_pcie->base_rb_stts + rxq->id * rb_stts_size;
745 trans_pcie->base_rb_stts_dma + rxq->id * rb_stts_size;
750 /* Allocate the driver's pointer to TR tail */
751 rxq->tr_tail = dma_alloc_coherent(dev, sizeof(__le16),
752 &rxq->tr_tail_dma, GFP_KERNEL);
756 /* Allocate the driver's pointer to CR tail */
757 rxq->cr_tail = dma_alloc_coherent(dev, sizeof(__le16),
758 &rxq->cr_tail_dma, GFP_KERNEL);
765 for (i = 0; i < trans->num_rx_queues; i++) {
766 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
768 iwl_pcie_free_rxq_dma(trans, rxq);
774 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
776 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
777 struct iwl_rb_allocator *rba = &trans_pcie->rba;
779 size_t rb_stts_size = trans->trans_cfg->device_family >=
780 IWL_DEVICE_FAMILY_AX210 ?
781 sizeof(__le16) : sizeof(struct iwl_rb_status);
783 if (WARN_ON(trans_pcie->rxq))
786 trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq),
788 trans_pcie->rx_pool = kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs),
789 sizeof(trans_pcie->rx_pool[0]),
791 trans_pcie->global_table =
792 kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs),
793 sizeof(trans_pcie->global_table[0]),
795 if (!trans_pcie->rxq || !trans_pcie->rx_pool ||
796 !trans_pcie->global_table) {
801 spin_lock_init(&rba->lock);
804 * Allocate the driver's pointer to receive buffer status.
805 * Allocate for all queues continuously (HW requirement).
807 trans_pcie->base_rb_stts =
808 dma_alloc_coherent(trans->dev,
809 rb_stts_size * trans->num_rx_queues,
810 &trans_pcie->base_rb_stts_dma,
812 if (!trans_pcie->base_rb_stts) {
817 for (i = 0; i < trans->num_rx_queues; i++) {
818 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
821 ret = iwl_pcie_alloc_rxq_dma(trans, rxq);
828 if (trans_pcie->base_rb_stts) {
829 dma_free_coherent(trans->dev,
830 rb_stts_size * trans->num_rx_queues,
831 trans_pcie->base_rb_stts,
832 trans_pcie->base_rb_stts_dma);
833 trans_pcie->base_rb_stts = NULL;
834 trans_pcie->base_rb_stts_dma = 0;
836 kfree(trans_pcie->rx_pool);
837 trans_pcie->rx_pool = NULL;
838 kfree(trans_pcie->global_table);
839 trans_pcie->global_table = NULL;
840 kfree(trans_pcie->rxq);
841 trans_pcie->rxq = NULL;
846 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
848 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
850 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
852 switch (trans_pcie->rx_buf_size) {
854 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
857 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
860 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K;
864 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
867 if (!iwl_trans_grab_nic_access(trans))
871 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
872 /* reset and flush pointers */
873 iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
874 iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
875 iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
877 /* Reset driver's Rx queue write index */
878 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
880 /* Tell device where to find RBD circular buffer in DRAM */
881 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
882 (u32)(rxq->bd_dma >> 8));
884 /* Tell device where in DRAM to update its Rx status */
885 iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
886 rxq->rb_stts_dma >> 4);
889 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
890 * the credit mechanism in 5000 HW RX FIFO
891 * Direct rx interrupts to hosts
892 * Rx buffer size 4 or 8k or 12k
896 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
897 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
898 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
899 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
901 (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
902 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
904 iwl_trans_release_nic_access(trans);
906 /* Set interrupt coalescing timer to default (2048 usecs) */
907 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
909 /* W/A for interrupt coalescing bug in 7260 and 3160 */
910 if (trans->cfg->host_interrupt_operation_mode)
911 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
914 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
916 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
917 u32 rb_size, enabled = 0;
920 switch (trans_pcie->rx_buf_size) {
922 rb_size = RFH_RXF_DMA_RB_SIZE_2K;
925 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
928 rb_size = RFH_RXF_DMA_RB_SIZE_8K;
931 rb_size = RFH_RXF_DMA_RB_SIZE_12K;
935 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
938 if (!iwl_trans_grab_nic_access(trans))
942 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);
943 /* disable free amd used rx queue operation */
944 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);
946 for (i = 0; i < trans->num_rx_queues; i++) {
947 /* Tell device where to find RBD free table in DRAM */
948 iwl_write_prph64_no_grab(trans,
949 RFH_Q_FRBDCB_BA_LSB(i),
950 trans_pcie->rxq[i].bd_dma);
951 /* Tell device where to find RBD used table in DRAM */
952 iwl_write_prph64_no_grab(trans,
953 RFH_Q_URBDCB_BA_LSB(i),
954 trans_pcie->rxq[i].used_bd_dma);
955 /* Tell device where in DRAM to update its Rx status */
956 iwl_write_prph64_no_grab(trans,
957 RFH_Q_URBD_STTS_WPTR_LSB(i),
958 trans_pcie->rxq[i].rb_stts_dma);
959 /* Reset device indice tables */
960 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);
961 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);
962 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);
964 enabled |= BIT(i) | BIT(i + 16);
969 * Rx buffer size 4 or 8k or 12k
971 * Drop frames that exceed RB size
974 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,
975 RFH_DMA_EN_ENABLE_VAL | rb_size |
976 RFH_RXF_DMA_MIN_RB_4_8 |
977 RFH_RXF_DMA_DROP_TOO_LARGE_MASK |
978 RFH_RXF_DMA_RBDCB_SIZE_512);
981 * Activate DMA snooping.
982 * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe
985 iwl_write_prph_no_grab(trans, RFH_GEN_CFG,
986 RFH_GEN_CFG_RFH_DMA_SNOOP |
987 RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) |
988 RFH_GEN_CFG_SERVICE_DMA_SNOOP |
989 RFH_GEN_CFG_VAL(RB_CHUNK_SIZE,
990 trans->trans_cfg->integrated ?
991 RFH_GEN_CFG_RB_CHUNK_SIZE_64 :
992 RFH_GEN_CFG_RB_CHUNK_SIZE_128));
993 /* Enable the relevant rx queues */
994 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
996 iwl_trans_release_nic_access(trans);
998 /* Set interrupt coalescing timer to default (2048 usecs) */
999 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
1002 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
1004 lockdep_assert_held(&rxq->lock);
1006 INIT_LIST_HEAD(&rxq->rx_free);
1007 INIT_LIST_HEAD(&rxq->rx_used);
1008 rxq->free_count = 0;
1009 rxq->used_count = 0;
1012 static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget);
1014 static int iwl_pcie_napi_poll(struct napi_struct *napi, int budget)
1016 struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi);
1017 struct iwl_trans_pcie *trans_pcie;
1018 struct iwl_trans *trans;
1021 trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev);
1022 trans = trans_pcie->trans;
1024 ret = iwl_pcie_rx_handle(trans, rxq->id, budget);
1027 spin_lock(&trans_pcie->irq_lock);
1028 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1029 _iwl_enable_interrupts(trans);
1030 spin_unlock(&trans_pcie->irq_lock);
1032 napi_complete_done(&rxq->napi, ret);
1038 static int iwl_pcie_napi_poll_msix(struct napi_struct *napi, int budget)
1040 struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi);
1041 struct iwl_trans_pcie *trans_pcie;
1042 struct iwl_trans *trans;
1045 trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev);
1046 trans = trans_pcie->trans;
1048 ret = iwl_pcie_rx_handle(trans, rxq->id, budget);
1051 spin_lock(&trans_pcie->irq_lock);
1052 iwl_pcie_clear_irq(trans, rxq->id);
1053 spin_unlock(&trans_pcie->irq_lock);
1055 napi_complete_done(&rxq->napi, ret);
1061 static int iwl_pcie_napi_poll_msix_shared(struct napi_struct *napi, int budget)
1063 struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi);
1064 struct iwl_trans_pcie *trans_pcie;
1065 struct iwl_trans *trans;
1068 trans_pcie = container_of(napi->dev, struct iwl_trans_pcie, napi_dev);
1069 trans = trans_pcie->trans;
1071 ret = iwl_pcie_rx_handle(trans, rxq->id, budget);
1074 spin_lock(&trans_pcie->irq_lock);
1075 iwl_pcie_clear_irq(trans, 0);
1076 spin_unlock(&trans_pcie->irq_lock);
1078 napi_complete_done(&rxq->napi, ret);
1084 static int _iwl_pcie_rx_init(struct iwl_trans *trans)
1086 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1087 struct iwl_rxq *def_rxq;
1088 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1089 int i, err, queue_size, allocator_pool_size, num_alloc;
1091 if (!trans_pcie->rxq) {
1092 err = iwl_pcie_rx_alloc(trans);
1096 def_rxq = trans_pcie->rxq;
1098 cancel_work_sync(&rba->rx_alloc);
1100 spin_lock_bh(&rba->lock);
1101 atomic_set(&rba->req_pending, 0);
1102 atomic_set(&rba->req_ready, 0);
1103 INIT_LIST_HEAD(&rba->rbd_allocated);
1104 INIT_LIST_HEAD(&rba->rbd_empty);
1105 spin_unlock_bh(&rba->lock);
1107 /* free all first - we might be reconfigured for a different size */
1108 iwl_pcie_free_rbs_pool(trans);
1110 for (i = 0; i < RX_QUEUE_SIZE; i++)
1111 def_rxq->queue[i] = NULL;
1113 for (i = 0; i < trans->num_rx_queues; i++) {
1114 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1116 spin_lock_bh(&rxq->lock);
1118 * Set read write pointer to reflect that we have processed
1119 * and used all buffers, but have not restocked the Rx queue
1120 * with fresh buffers
1124 rxq->write_actual = 0;
1125 memset(rxq->rb_stts, 0,
1126 (trans->trans_cfg->device_family >=
1127 IWL_DEVICE_FAMILY_AX210) ?
1128 sizeof(__le16) : sizeof(struct iwl_rb_status));
1130 iwl_pcie_rx_init_rxb_lists(rxq);
1132 spin_unlock_bh(&rxq->lock);
1134 if (!rxq->napi.poll) {
1135 int (*poll)(struct napi_struct *, int) = iwl_pcie_napi_poll;
1137 if (trans_pcie->msix_enabled) {
1138 poll = iwl_pcie_napi_poll_msix;
1140 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX &&
1142 poll = iwl_pcie_napi_poll_msix_shared;
1144 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS &&
1146 poll = iwl_pcie_napi_poll_msix_shared;
1149 netif_napi_add(&trans_pcie->napi_dev, &rxq->napi,
1150 poll, NAPI_POLL_WEIGHT);
1151 napi_enable(&rxq->napi);
1156 /* move the pool to the default queue and allocator ownerships */
1157 queue_size = trans->trans_cfg->mq_rx_supported ?
1158 trans_pcie->num_rx_bufs - 1 : RX_QUEUE_SIZE;
1159 allocator_pool_size = trans->num_rx_queues *
1160 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC);
1161 num_alloc = queue_size + allocator_pool_size;
1163 for (i = 0; i < num_alloc; i++) {
1164 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i];
1166 if (i < allocator_pool_size)
1167 list_add(&rxb->list, &rba->rbd_empty);
1169 list_add(&rxb->list, &def_rxq->rx_used);
1170 trans_pcie->global_table[i] = rxb;
1171 rxb->vid = (u16)(i + 1);
1172 rxb->invalid = true;
1175 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq);
1180 int iwl_pcie_rx_init(struct iwl_trans *trans)
1182 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1183 int ret = _iwl_pcie_rx_init(trans);
1188 if (trans->trans_cfg->mq_rx_supported)
1189 iwl_pcie_rx_mq_hw_init(trans);
1191 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq);
1193 iwl_pcie_rxq_restock(trans, trans_pcie->rxq);
1195 spin_lock_bh(&trans_pcie->rxq->lock);
1196 iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq);
1197 spin_unlock_bh(&trans_pcie->rxq->lock);
1202 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans)
1204 /* Set interrupt coalescing timer to default (2048 usecs) */
1205 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
1208 * We don't configure the RFH.
1209 * Restock will be done at alive, after firmware configured the RFH.
1211 return _iwl_pcie_rx_init(trans);
1214 void iwl_pcie_rx_free(struct iwl_trans *trans)
1216 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1217 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1219 size_t rb_stts_size = trans->trans_cfg->device_family >=
1220 IWL_DEVICE_FAMILY_AX210 ?
1221 sizeof(__le16) : sizeof(struct iwl_rb_status);
1224 * if rxq is NULL, it means that nothing has been allocated,
1227 if (!trans_pcie->rxq) {
1228 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
1232 cancel_work_sync(&rba->rx_alloc);
1234 iwl_pcie_free_rbs_pool(trans);
1236 if (trans_pcie->base_rb_stts) {
1237 dma_free_coherent(trans->dev,
1238 rb_stts_size * trans->num_rx_queues,
1239 trans_pcie->base_rb_stts,
1240 trans_pcie->base_rb_stts_dma);
1241 trans_pcie->base_rb_stts = NULL;
1242 trans_pcie->base_rb_stts_dma = 0;
1245 for (i = 0; i < trans->num_rx_queues; i++) {
1246 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1248 iwl_pcie_free_rxq_dma(trans, rxq);
1250 if (rxq->napi.poll) {
1251 napi_disable(&rxq->napi);
1252 netif_napi_del(&rxq->napi);
1255 kfree(trans_pcie->rx_pool);
1256 kfree(trans_pcie->global_table);
1257 kfree(trans_pcie->rxq);
1259 if (trans_pcie->alloc_page)
1260 __free_pages(trans_pcie->alloc_page, trans_pcie->rx_page_order);
1263 static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq,
1264 struct iwl_rb_allocator *rba)
1266 spin_lock(&rba->lock);
1267 list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty);
1268 spin_unlock(&rba->lock);
1272 * iwl_pcie_rx_reuse_rbd - Recycle used RBDs
1274 * Called when a RBD can be reused. The RBD is transferred to the allocator.
1275 * When there are 2 empty RBDs - a request for allocation is posted
1277 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans,
1278 struct iwl_rx_mem_buffer *rxb,
1279 struct iwl_rxq *rxq, bool emergency)
1281 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1282 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1284 /* Move the RBD to the used list, will be moved to allocator in batches
1285 * before claiming or posting a request*/
1286 list_add_tail(&rxb->list, &rxq->rx_used);
1288 if (unlikely(emergency))
1291 /* Count the allocator owned RBDs */
1294 /* If we have RX_POST_REQ_ALLOC new released rx buffers -
1295 * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is
1296 * used for the case we failed to claim RX_CLAIM_REQ_ALLOC,
1297 * after but we still need to post another request.
1299 if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) {
1300 /* Move the 2 RBDs to the allocator ownership.
1301 Allocator has another 6 from pool for the request completion*/
1302 iwl_pcie_rx_move_to_allocator(rxq, rba);
1304 atomic_inc(&rba->req_pending);
1305 queue_work(rba->alloc_wq, &rba->rx_alloc);
1309 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
1310 struct iwl_rxq *rxq,
1311 struct iwl_rx_mem_buffer *rxb,
1315 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1316 struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id];
1317 bool page_stolen = false;
1318 int max_len = trans_pcie->rx_buf_bytes;
1324 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
1326 while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
1327 struct iwl_rx_packet *pkt;
1330 struct iwl_rx_cmd_buffer rxcb = {
1331 ._offset = rxb->offset + offset,
1332 ._rx_page_order = trans_pcie->rx_page_order,
1334 ._page_stolen = false,
1335 .truesize = max_len,
1338 pkt = rxb_addr(&rxcb);
1340 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) {
1342 "Q %d: RB end marker at offset %d\n",
1347 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1348 FH_RSCSR_RXQ_POS != rxq->id,
1349 "frame on invalid queue - is on %d and indicates %d\n",
1351 (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1355 "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n",
1357 iwl_get_cmd_string(trans,
1358 iwl_cmd_id(pkt->hdr.cmd,
1361 pkt->hdr.group_id, pkt->hdr.cmd,
1362 le16_to_cpu(pkt->hdr.sequence));
1364 len = iwl_rx_packet_len(pkt);
1365 len += sizeof(u32); /* account for status word */
1367 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
1369 /* check that what the device tells us made sense */
1370 if (offset > max_len)
1373 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
1374 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
1376 /* Reclaim a command buffer only if this packet is a response
1377 * to a (driver-originated) command.
1378 * If the packet (e.g. Rx frame) originated from uCode,
1379 * there is no command buffer to reclaim.
1380 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1381 * but apparently a few don't get set; catch them here. */
1382 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
1383 if (reclaim && !pkt->hdr.group_id) {
1386 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
1387 if (trans_pcie->no_reclaim_cmds[i] ==
1395 if (rxq->id == trans_pcie->def_rx_queue)
1396 iwl_op_mode_rx(trans->op_mode, &rxq->napi,
1399 iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi,
1403 * After here, we should always check rxcb._page_stolen,
1404 * if it is true then one of the handlers took the page.
1408 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1409 int index = SEQ_TO_INDEX(sequence);
1410 int cmd_index = iwl_txq_get_cmd_index(txq, index);
1412 kfree_sensitive(txq->entries[cmd_index].free_buf);
1413 txq->entries[cmd_index].free_buf = NULL;
1415 /* Invoke any callbacks, transfer the buffer to caller,
1416 * and fire off the (possibly) blocking
1417 * iwl_trans_send_cmd()
1418 * as we reclaim the driver command queue */
1419 if (!rxcb._page_stolen)
1420 iwl_pcie_hcmd_complete(trans, &rxcb);
1422 IWL_WARN(trans, "Claim null rxb?\n");
1425 page_stolen |= rxcb._page_stolen;
1426 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1430 /* page was stolen from us -- free our reference */
1432 __free_pages(rxb->page, trans_pcie->rx_page_order);
1436 /* Reuse the page if possible. For notification packets and
1437 * SKBs that fail to Rx correctly, add them back into the
1438 * rx_free list for reuse later. */
1439 if (rxb->page != NULL) {
1441 dma_map_page(trans->dev, rxb->page, rxb->offset,
1442 trans_pcie->rx_buf_bytes,
1444 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
1446 * free the page(s) as well to not break
1447 * the invariant that the items on the used
1448 * list have no page(s)
1450 __free_pages(rxb->page, trans_pcie->rx_page_order);
1452 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1454 list_add_tail(&rxb->list, &rxq->rx_free);
1458 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1461 static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans,
1462 struct iwl_rxq *rxq, int i,
1465 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1466 struct iwl_rx_mem_buffer *rxb;
1469 BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc) != 32);
1471 if (!trans->trans_cfg->mq_rx_supported) {
1472 rxb = rxq->queue[i];
1473 rxq->queue[i] = NULL;
1477 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1478 vid = le16_to_cpu(rxq->cd[i].rbid);
1479 *join = rxq->cd[i].flags & IWL_RX_CD_FLAGS_FRAGMENTED;
1481 vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF; /* 12-bit VID */
1484 if (!vid || vid > RX_POOL_SIZE(trans_pcie->num_rx_bufs))
1487 rxb = trans_pcie->global_table[vid - 1];
1491 IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid);
1493 rxb->invalid = true;
1498 WARN(1, "Invalid rxb from HW %u\n", (u32)vid);
1499 iwl_force_nmi(trans);
1504 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
1506 static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget)
1508 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1509 struct iwl_rxq *rxq;
1510 u32 r, i, count = 0, handled = 0;
1511 bool emergency = false;
1513 if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd))
1516 rxq = &trans_pcie->rxq[queue];
1519 spin_lock(&rxq->lock);
1520 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1521 * buffer that the driver may process (last buffer filled by ucode). */
1522 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
1525 /* W/A 9000 device step A0 wrap-around bug */
1526 r &= (rxq->queue_size - 1);
1528 /* Rx interrupt, but nothing sent from uCode */
1530 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r);
1532 while (i != r && ++handled < budget) {
1533 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1534 struct iwl_rx_mem_buffer *rxb;
1535 /* number of RBDs still waiting for page allocation */
1536 u32 rb_pending_alloc =
1537 atomic_read(&trans_pcie->rba.req_pending) *
1541 if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 &&
1543 iwl_pcie_rx_move_to_allocator(rxq, rba);
1545 IWL_DEBUG_TPT(trans,
1546 "RX path is in emergency. Pending allocations %d\n",
1550 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i);
1552 rxb = iwl_pcie_get_rxb(trans, rxq, i, &join);
1556 if (unlikely(join || rxq->next_rb_is_fragment)) {
1557 rxq->next_rb_is_fragment = join;
1559 * We can only get a multi-RB in the following cases:
1560 * - firmware issue, sending a too big notification
1561 * - sniffer mode with a large A-MSDU
1562 * - large MTU frames (>2k)
1563 * since the multi-RB functionality is limited to newer
1564 * hardware that cannot put multiple entries into a
1567 * Right now, the higher layers aren't set up to deal
1568 * with that, so discard all of these.
1570 list_add_tail(&rxb->list, &rxq->rx_free);
1573 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i);
1576 i = (i + 1) & (rxq->queue_size - 1);
1579 * If we have RX_CLAIM_REQ_ALLOC released rx buffers -
1580 * try to claim the pre-allocated buffers from the allocator.
1581 * If not ready - will try to reclaim next time.
1582 * There is no need to reschedule work - allocator exits only
1585 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC)
1586 iwl_pcie_rx_allocator_get(trans, rxq);
1588 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) {
1589 /* Add the remaining empty RBDs for allocator use */
1590 iwl_pcie_rx_move_to_allocator(rxq, rba);
1591 } else if (emergency) {
1595 if (rb_pending_alloc < rxq->queue_size / 3) {
1596 IWL_DEBUG_TPT(trans,
1597 "RX path exited emergency. Pending allocations %d\n",
1603 spin_unlock(&rxq->lock);
1604 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1605 iwl_pcie_rxq_restock(trans, rxq);
1611 /* Backtrack one entry */
1613 /* update cr tail with the rxq read pointer */
1614 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1615 *rxq->cr_tail = cpu_to_le16(r);
1616 spin_unlock(&rxq->lock);
1619 * handle a case where in emergency there are some unallocated RBDs.
1620 * those RBDs are in the used list, but are not tracked by the queue's
1621 * used_count which counts allocator owned RBDs.
1622 * unallocated emergency RBDs must be allocated on exit, otherwise
1623 * when called again the function may not be in emergency mode and
1624 * they will be handed to the allocator with no tracking in the RBD
1625 * allocator counters, which will lead to them never being claimed back
1627 * by allocating them here, they are now in the queue free list, and
1628 * will be restocked by the next call of iwl_pcie_rxq_restock.
1630 if (unlikely(emergency && count))
1631 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1633 iwl_pcie_rxq_restock(trans, rxq);
1638 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry)
1640 u8 queue = entry->entry;
1641 struct msix_entry *entries = entry - queue;
1643 return container_of(entries, struct iwl_trans_pcie, msix_entries[0]);
1647 * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw
1648 * This interrupt handler should be used with RSS queue only.
1650 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id)
1652 struct msix_entry *entry = dev_id;
1653 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
1654 struct iwl_trans *trans = trans_pcie->trans;
1655 struct iwl_rxq *rxq = &trans_pcie->rxq[entry->entry];
1657 trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0);
1659 if (WARN_ON(entry->entry >= trans->num_rx_queues))
1662 if (WARN_ONCE(!rxq, "Got MSI-X interrupt before we have Rx queues"))
1665 lock_map_acquire(&trans->sync_cmd_lockdep_map);
1668 if (napi_schedule_prep(&rxq->napi))
1669 __napi_schedule(&rxq->napi);
1671 iwl_pcie_clear_irq(trans, entry->entry);
1674 lock_map_release(&trans->sync_cmd_lockdep_map);
1680 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
1682 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
1686 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
1687 if (trans->cfg->internal_wimax_coex &&
1688 !trans->cfg->apmg_not_supported &&
1689 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
1690 APMS_CLK_VAL_MRB_FUNC_MODE) ||
1691 (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
1692 APMG_PS_CTRL_VAL_RESET_REQ))) {
1693 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1694 iwl_op_mode_wimax_active(trans->op_mode);
1695 wake_up(&trans->wait_command_queue);
1699 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
1700 if (!trans->txqs.txq[i])
1702 del_timer(&trans->txqs.txq[i]->stuck_timer);
1705 /* The STATUS_FW_ERROR bit is set in this function. This must happen
1706 * before we wake up the command caller, to ensure a proper cleanup. */
1707 iwl_trans_fw_error(trans);
1709 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1710 wake_up(&trans->wait_command_queue);
1713 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)
1717 lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock);
1719 trace_iwlwifi_dev_irq(trans->dev);
1721 /* Discover which interrupts are active/pending */
1722 inta = iwl_read32(trans, CSR_INT);
1724 /* the thread will service interrupts and re-enable them */
1728 /* a device (PCI-E) page is 4096 bytes long */
1729 #define ICT_SHIFT 12
1730 #define ICT_SIZE (1 << ICT_SHIFT)
1731 #define ICT_COUNT (ICT_SIZE / sizeof(u32))
1733 /* interrupt handler using ict table, with this interrupt driver will
1734 * stop using INTA register to get device's interrupt, reading this register
1735 * is expensive, device will write interrupts in ICT dram table, increment
1736 * index then will fire interrupt to driver, driver will OR all ICT table
1737 * entries from current index up to table entry with 0 value. the result is
1738 * the interrupt we need to service, driver will set the entries back to 0 and
1741 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans)
1743 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1748 trace_iwlwifi_dev_irq(trans->dev);
1750 /* Ignore interrupt if there's nothing in NIC to service.
1751 * This may be due to IRQ shared with another device,
1752 * or due to sporadic interrupts thrown from our NIC. */
1753 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1754 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1759 * Collect all entries up to the first 0, starting from ict_index;
1760 * note we already read at ict_index.
1764 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1765 trans_pcie->ict_index, read);
1766 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1767 trans_pcie->ict_index =
1768 ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1));
1770 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1771 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1775 /* We should not get this value, just ignore it. */
1776 if (val == 0xffffffff)
1780 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1781 * (bit 15 before shifting it to 31) to clear when using interrupt
1782 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1783 * so we use them to decide on the real state of the Rx bit.
1784 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1789 inta = (0xff & val) | ((0xff00 & val) << 16);
1793 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans)
1795 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1796 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1797 bool hw_rfkill, prev, report;
1799 mutex_lock(&trans_pcie->mutex);
1800 prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1801 hw_rfkill = iwl_is_rfkill_set(trans);
1803 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1804 set_bit(STATUS_RFKILL_HW, &trans->status);
1806 if (trans_pcie->opmode_down)
1809 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1811 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1812 hw_rfkill ? "disable radio" : "enable radio");
1814 isr_stats->rfkill++;
1817 iwl_trans_pcie_rf_kill(trans, report);
1818 mutex_unlock(&trans_pcie->mutex);
1821 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE,
1823 IWL_DEBUG_RF_KILL(trans,
1824 "Rfkill while SYNC HCMD in flight\n");
1825 wake_up(&trans->wait_command_queue);
1827 clear_bit(STATUS_RFKILL_HW, &trans->status);
1828 if (trans_pcie->opmode_down)
1829 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1833 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
1835 struct iwl_trans *trans = dev_id;
1836 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1837 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1840 bool polling = false;
1842 lock_map_acquire(&trans->sync_cmd_lockdep_map);
1844 spin_lock_bh(&trans_pcie->irq_lock);
1846 /* dram interrupt table not set yet,
1847 * use legacy interrupt.
1849 if (likely(trans_pcie->use_ict))
1850 inta = iwl_pcie_int_cause_ict(trans);
1852 inta = iwl_pcie_int_cause_non_ict(trans);
1854 if (iwl_have_debug_level(IWL_DL_ISR)) {
1855 IWL_DEBUG_ISR(trans,
1856 "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
1857 inta, trans_pcie->inta_mask,
1858 iwl_read32(trans, CSR_INT_MASK),
1859 iwl_read32(trans, CSR_FH_INT_STATUS));
1860 if (inta & (~trans_pcie->inta_mask))
1861 IWL_DEBUG_ISR(trans,
1862 "We got a masked interrupt (0x%08x)\n",
1863 inta & (~trans_pcie->inta_mask));
1866 inta &= trans_pcie->inta_mask;
1869 * Ignore interrupt if there's nothing in NIC to service.
1870 * This may be due to IRQ shared with another device,
1871 * or due to sporadic interrupts thrown from our NIC.
1873 if (unlikely(!inta)) {
1874 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1876 * Re-enable interrupts here since we don't
1877 * have anything to service
1879 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1880 _iwl_enable_interrupts(trans);
1881 spin_unlock_bh(&trans_pcie->irq_lock);
1882 lock_map_release(&trans->sync_cmd_lockdep_map);
1886 if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1888 * Hardware disappeared. It might have
1889 * already raised an interrupt.
1891 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1892 spin_unlock_bh(&trans_pcie->irq_lock);
1896 /* Ack/clear/reset pending uCode interrupts.
1897 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1899 /* There is a hardware bug in the interrupt mask function that some
1900 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1901 * they are disabled in the CSR_INT_MASK register. Furthermore the
1902 * ICT interrupt handling mechanism has another bug that might cause
1903 * these unmasked interrupts fail to be detected. We workaround the
1904 * hardware bugs here by ACKing all the possible interrupts so that
1905 * interrupt coalescing can still be achieved.
1907 iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
1909 if (iwl_have_debug_level(IWL_DL_ISR))
1910 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
1911 inta, iwl_read32(trans, CSR_INT_MASK));
1913 spin_unlock_bh(&trans_pcie->irq_lock);
1915 /* Now service all interrupt bits discovered above. */
1916 if (inta & CSR_INT_BIT_HW_ERR) {
1917 IWL_ERR(trans, "Hardware error detected. Restarting.\n");
1919 /* Tell the device to stop sending interrupts */
1920 iwl_disable_interrupts(trans);
1923 iwl_pcie_irq_handle_error(trans);
1925 handled |= CSR_INT_BIT_HW_ERR;
1930 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1931 if (inta & CSR_INT_BIT_SCD) {
1932 IWL_DEBUG_ISR(trans,
1933 "Scheduler finished to transmit the frame/frames.\n");
1937 /* Alive notification via Rx interrupt will do the real work */
1938 if (inta & CSR_INT_BIT_ALIVE) {
1939 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1941 if (trans->trans_cfg->gen2) {
1943 * We can restock, since firmware configured
1946 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
1949 handled |= CSR_INT_BIT_ALIVE;
1952 /* Safely ignore these bits for debug checks below */
1953 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1955 /* HW RF KILL switch toggled */
1956 if (inta & CSR_INT_BIT_RF_KILL) {
1957 iwl_pcie_handle_rfkill_irq(trans);
1958 handled |= CSR_INT_BIT_RF_KILL;
1961 /* Chip got too hot and stopped itself */
1962 if (inta & CSR_INT_BIT_CT_KILL) {
1963 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1964 isr_stats->ctkill++;
1965 handled |= CSR_INT_BIT_CT_KILL;
1968 /* Error detected by uCode */
1969 if (inta & CSR_INT_BIT_SW_ERR) {
1970 IWL_ERR(trans, "Microcode SW error detected. "
1971 " Restarting 0x%X.\n", inta);
1973 iwl_pcie_irq_handle_error(trans);
1974 handled |= CSR_INT_BIT_SW_ERR;
1977 /* uCode wakes up after power-down sleep */
1978 if (inta & CSR_INT_BIT_WAKEUP) {
1979 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1980 iwl_pcie_rxq_check_wrptr(trans);
1981 iwl_pcie_txq_check_wrptrs(trans);
1983 isr_stats->wakeup++;
1985 handled |= CSR_INT_BIT_WAKEUP;
1988 /* All uCode command responses, including Tx command responses,
1989 * Rx "responses" (frame-received notification), and other
1990 * notifications from uCode come through here*/
1991 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1992 CSR_INT_BIT_RX_PERIODIC)) {
1993 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1994 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1995 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1996 iwl_write32(trans, CSR_FH_INT_STATUS,
1997 CSR_FH_INT_RX_MASK);
1999 if (inta & CSR_INT_BIT_RX_PERIODIC) {
2000 handled |= CSR_INT_BIT_RX_PERIODIC;
2002 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
2004 /* Sending RX interrupt require many steps to be done in the
2006 * 1- write interrupt to current index in ICT table.
2008 * 3- update RX shared data to indicate last write index.
2009 * 4- send interrupt.
2010 * This could lead to RX race, driver could receive RX interrupt
2011 * but the shared data changes does not reflect this;
2012 * periodic interrupt will detect any dangling Rx activity.
2015 /* Disable periodic interrupt; we use it as just a one-shot. */
2016 iwl_write8(trans, CSR_INT_PERIODIC_REG,
2017 CSR_INT_PERIODIC_DIS);
2020 * Enable periodic interrupt in 8 msec only if we received
2021 * real RX interrupt (instead of just periodic int), to catch
2022 * any dangling Rx interrupt. If it was just the periodic
2023 * interrupt, there was no dangling Rx activity, and no need
2024 * to extend the periodic interrupt; one-shot is enough.
2026 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
2027 iwl_write8(trans, CSR_INT_PERIODIC_REG,
2028 CSR_INT_PERIODIC_ENA);
2033 if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) {
2035 __napi_schedule(&trans_pcie->rxq[0].napi);
2040 /* This "Tx" DMA channel is used only for loading uCode */
2041 if (inta & CSR_INT_BIT_FH_TX) {
2042 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
2043 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
2045 handled |= CSR_INT_BIT_FH_TX;
2046 /* Wake up uCode load routine, now that load is complete */
2047 trans_pcie->ucode_write_complete = true;
2048 wake_up(&trans_pcie->ucode_write_waitq);
2051 if (inta & ~handled) {
2052 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
2053 isr_stats->unhandled++;
2056 if (inta & ~(trans_pcie->inta_mask)) {
2057 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
2058 inta & ~trans_pcie->inta_mask);
2062 spin_lock_bh(&trans_pcie->irq_lock);
2063 /* only Re-enable all interrupt if disabled by irq */
2064 if (test_bit(STATUS_INT_ENABLED, &trans->status))
2065 _iwl_enable_interrupts(trans);
2066 /* we are loading the firmware, enable FH_TX interrupt only */
2067 else if (handled & CSR_INT_BIT_FH_TX)
2068 iwl_enable_fw_load_int(trans);
2069 /* Re-enable RF_KILL if it occurred */
2070 else if (handled & CSR_INT_BIT_RF_KILL)
2071 iwl_enable_rfkill_int(trans);
2072 /* Re-enable the ALIVE / Rx interrupt if it occurred */
2073 else if (handled & (CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX))
2074 iwl_enable_fw_load_int_ctx_info(trans);
2075 spin_unlock_bh(&trans_pcie->irq_lock);
2079 lock_map_release(&trans->sync_cmd_lockdep_map);
2083 /******************************************************************************
2087 ******************************************************************************/
2089 /* Free dram table */
2090 void iwl_pcie_free_ict(struct iwl_trans *trans)
2092 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2094 if (trans_pcie->ict_tbl) {
2095 dma_free_coherent(trans->dev, ICT_SIZE,
2096 trans_pcie->ict_tbl,
2097 trans_pcie->ict_tbl_dma);
2098 trans_pcie->ict_tbl = NULL;
2099 trans_pcie->ict_tbl_dma = 0;
2104 * allocate dram shared table, it is an aligned memory
2105 * block of ICT_SIZE.
2106 * also reset all data related to ICT table interrupt.
2108 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
2110 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2112 trans_pcie->ict_tbl =
2113 dma_alloc_coherent(trans->dev, ICT_SIZE,
2114 &trans_pcie->ict_tbl_dma, GFP_KERNEL);
2115 if (!trans_pcie->ict_tbl)
2118 /* just an API sanity check ... it is guaranteed to be aligned */
2119 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
2120 iwl_pcie_free_ict(trans);
2127 /* Device is going up inform it about using ICT interrupt table,
2128 * also we need to tell the driver to start using ICT interrupt.
2130 void iwl_pcie_reset_ict(struct iwl_trans *trans)
2132 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2135 if (!trans_pcie->ict_tbl)
2138 spin_lock_bh(&trans_pcie->irq_lock);
2139 _iwl_disable_interrupts(trans);
2141 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
2143 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
2145 val |= CSR_DRAM_INT_TBL_ENABLE |
2146 CSR_DRAM_INIT_TBL_WRAP_CHECK |
2147 CSR_DRAM_INIT_TBL_WRITE_POINTER;
2149 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
2151 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
2152 trans_pcie->use_ict = true;
2153 trans_pcie->ict_index = 0;
2154 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
2155 _iwl_enable_interrupts(trans);
2156 spin_unlock_bh(&trans_pcie->irq_lock);
2159 /* Device is going down disable ict interrupt usage */
2160 void iwl_pcie_disable_ict(struct iwl_trans *trans)
2162 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2164 spin_lock_bh(&trans_pcie->irq_lock);
2165 trans_pcie->use_ict = false;
2166 spin_unlock_bh(&trans_pcie->irq_lock);
2169 irqreturn_t iwl_pcie_isr(int irq, void *data)
2171 struct iwl_trans *trans = data;
2176 /* Disable (but don't clear!) interrupts here to avoid
2177 * back-to-back ISRs and sporadic interrupts from our NIC.
2178 * If we have something to service, the tasklet will re-enable ints.
2179 * If we *don't* have something, we'll re-enable before leaving here.
2181 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
2183 return IRQ_WAKE_THREAD;
2186 irqreturn_t iwl_pcie_msix_isr(int irq, void *data)
2188 return IRQ_WAKE_THREAD;
2191 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)
2193 struct msix_entry *entry = dev_id;
2194 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
2195 struct iwl_trans *trans = trans_pcie->trans;
2196 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2197 u32 inta_fh, inta_hw;
2198 bool polling = false;
2200 lock_map_acquire(&trans->sync_cmd_lockdep_map);
2202 spin_lock_bh(&trans_pcie->irq_lock);
2203 inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
2204 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
2206 * Clear causes registers to avoid being handling the same cause.
2208 iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh);
2209 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
2210 spin_unlock_bh(&trans_pcie->irq_lock);
2212 trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw);
2214 if (unlikely(!(inta_fh | inta_hw))) {
2215 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
2216 lock_map_release(&trans->sync_cmd_lockdep_map);
2220 if (iwl_have_debug_level(IWL_DL_ISR)) {
2221 IWL_DEBUG_ISR(trans,
2222 "ISR inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
2223 inta_fh, trans_pcie->fh_mask,
2224 iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD));
2225 if (inta_fh & ~trans_pcie->fh_mask)
2226 IWL_DEBUG_ISR(trans,
2227 "We got a masked interrupt (0x%08x)\n",
2228 inta_fh & ~trans_pcie->fh_mask);
2231 inta_fh &= trans_pcie->fh_mask;
2233 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) &&
2234 inta_fh & MSIX_FH_INT_CAUSES_Q0) {
2236 if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) {
2238 __napi_schedule(&trans_pcie->rxq[0].napi);
2243 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) &&
2244 inta_fh & MSIX_FH_INT_CAUSES_Q1) {
2246 if (napi_schedule_prep(&trans_pcie->rxq[1].napi)) {
2248 __napi_schedule(&trans_pcie->rxq[1].napi);
2253 /* This "Tx" DMA channel is used only for loading uCode */
2254 if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) {
2255 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
2258 * Wake up uCode load routine,
2259 * now that load is complete
2261 trans_pcie->ucode_write_complete = true;
2262 wake_up(&trans_pcie->ucode_write_waitq);
2265 /* Error detected by uCode */
2266 if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) ||
2267 (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR)) {
2269 "Microcode SW error detected. Restarting 0x%X.\n",
2272 iwl_pcie_irq_handle_error(trans);
2275 /* After checking FH register check HW register */
2276 if (iwl_have_debug_level(IWL_DL_ISR)) {
2277 IWL_DEBUG_ISR(trans,
2278 "ISR inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
2279 inta_hw, trans_pcie->hw_mask,
2280 iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD));
2281 if (inta_hw & ~trans_pcie->hw_mask)
2282 IWL_DEBUG_ISR(trans,
2283 "We got a masked interrupt 0x%08x\n",
2284 inta_hw & ~trans_pcie->hw_mask);
2287 inta_hw &= trans_pcie->hw_mask;
2289 /* Alive notification via Rx interrupt will do the real work */
2290 if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) {
2291 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
2293 if (trans->trans_cfg->gen2) {
2294 /* We can restock, since firmware configured the RFH */
2295 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
2299 if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) {
2301 le32_to_cpu(trans_pcie->prph_info->sleep_notif);
2302 if (sleep_notif == IWL_D3_SLEEP_STATUS_SUSPEND ||
2303 sleep_notif == IWL_D3_SLEEP_STATUS_RESUME) {
2304 IWL_DEBUG_ISR(trans,
2305 "Sx interrupt: sleep notification = 0x%x\n",
2307 trans_pcie->sx_complete = true;
2308 wake_up(&trans_pcie->sx_waitq);
2310 /* uCode wakes up after power-down sleep */
2311 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
2312 iwl_pcie_rxq_check_wrptr(trans);
2313 iwl_pcie_txq_check_wrptrs(trans);
2315 isr_stats->wakeup++;
2319 /* Chip got too hot and stopped itself */
2320 if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) {
2321 IWL_ERR(trans, "Microcode CT kill error detected.\n");
2322 isr_stats->ctkill++;
2325 /* HW RF KILL switch toggled */
2326 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL)
2327 iwl_pcie_handle_rfkill_irq(trans);
2329 if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) {
2331 "Hardware error detected. Restarting.\n");
2334 trans->dbg.hw_error = true;
2335 iwl_pcie_irq_handle_error(trans);
2338 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE) {
2339 IWL_DEBUG_ISR(trans, "Reset flow completed\n");
2340 trans_pcie->fw_reset_done = true;
2341 wake_up(&trans_pcie->fw_reset_waitq);
2345 iwl_pcie_clear_irq(trans, entry->entry);
2347 lock_map_release(&trans->sync_cmd_lockdep_map);