drivers/net/wireless/intel/iwlwifi/pcie/rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   4  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
   5  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
   6  * Copyright(c) 2018 Intel Corporation
   7  *
   8  * Portions of this file are derived from the ipw3945 project, as well
   9  * as portions of the ieee80211 subsystem header files.
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program.
  22  *
  23  * The full GNU General Public License is included in this distribution in the
  24  * file called LICENSE.
  25  *
  26  * Contact Information:
  27  *  Intel Linux Wireless <linuxwifi@intel.com>
  28  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  29  *
  30  *****************************************************************************/
  31 #include <linux/sched.h>
  32 #include <linux/wait.h>
  33 #include <linux/gfp.h>
  34
  35 #include "iwl-prph.h"
  36 #include "iwl-io.h"
  37 #include "internal.h"
  38 #include "iwl-op-mode.h"
  39 #include "iwl-context-info-gen3.h"
  40
  41 /******************************************************************************
  42  *
  43  * RX path functions
  44  *
  45  ******************************************************************************/
  46
  47 /*
  48  * Rx theory of operation
  49  *
  50  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  51  * each of which point to Receive Buffers to be filled by the NIC.  These get
  52  * used not only for Rx frames, but for any command response or notification
  53  * from the NIC.  The driver and NIC manage the Rx buffers by means
  54  * of indexes into the circular buffer.
  55  *
  56  * Rx Queue Indexes
  57  * The host/firmware share two index registers for managing the Rx buffers.
  58  *
  59  * The READ index maps to the first position that the firmware may be writing
  60  * to -- the driver can read up to (but not including) this position and get
  61  * good data.
  62  * The READ index is managed by the firmware once the card is enabled.
  63  *
  64  * The WRITE index maps to the last position the driver has read from -- the
  65  * position preceding WRITE is the last slot the firmware can place a packet.
  66  *
  67  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  68  * WRITE = READ.
  69  *
  70  * During initialization, the host sets up the READ queue position to the first
  71  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  72  *
  73  * When the firmware places a packet in a buffer, it will advance the READ index
  74  * and fire the RX interrupt.  The driver can then query the READ index and
  75  * process as many packets as possible, moving the WRITE index forward as it
  76  * resets the Rx queue buffers with new memory.
  77  *
  78  * The management in the driver is as follows:
  79  * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free.
  80  *   When the interrupt handler is called, the request is processed.
  81  *   The page is either stolen - transferred to the upper layer
  82  *   or reused - added immediately to the iwl->rxq->rx_free list.
  83  * + When the page is stolen - the driver updates the matching queue's used
  84  *   count, detaches the RBD and transfers it to the queue used list.
  85  *   When there are two used RBDs - they are transferred to the allocator empty
  86  *   list. Work is then scheduled for the allocator to start allocating
  87  *   eight buffers.
  88  *   When there are another 6 used RBDs - they are transferred to the allocator
  89  *   empty list and the driver tries to claim the pre-allocated buffers and
  90  *   add them to iwl->rxq->rx_free. If it fails - it continues to claim them
  91  *   until ready.
  92  *   When there are 8+ buffers in the free list - either from allocation or from
  93  *   8 reused unstolen pages - restock is called to update the FW and indexes.
  94  * + In order to make sure the allocator always has RBDs to use for allocation
  95  *   the allocator has initial pool in the size of num_queues*(8-2) - the
  96  *   maximum missing RBDs per allocation request (request posted with 2
  97  *    empty RBDs, there is no guarantee when the other 6 RBDs are supplied).
  98  *   The queues supplies the recycle of the rest of the RBDs.
  99  * + A received packet is processed and handed to the kernel network stack,
 100  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
 101  * + If there are no allocated buffers in iwl->rxq->rx_free,
 102  *   the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
 103  *   If there were enough free buffers and RX_STALLED is set it is cleared.
 104  *
 105  *
 106  * Driver sequence:
 107  *
 108  * iwl_rxq_alloc()            Allocates rx_free
 109  * iwl_pcie_rx_replenish()    Replenishes rx_free list from rx_used, and calls
 110  *                            iwl_pcie_rxq_restock.
 111  *                            Used only during initialization.
 112  * iwl_pcie_rxq_restock()     Moves available buffers from rx_free into Rx
 113  *                            queue, updates firmware pointers, and updates
 114  *                            the WRITE index.
 115  * iwl_pcie_rx_allocator()     Background work for allocating pages.
 116  *
 117  * -- enable interrupts --
 118  * ISR - iwl_rx()             Detach iwl_rx_mem_buffers from pool up to the
 119  *                            READ INDEX, detaching the SKB from the pool.
 120  *                            Moves the packet buffer from queue to rx_used.
 121  *                            Posts and claims requests to the allocator.
 122  *                            Calls iwl_pcie_rxq_restock to refill any empty
 123  *                            slots.
 124  *
 125  * RBD life-cycle:
 126  *
 127  * Init:
 128  * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue
 129  *
 130  * Regular Receive interrupt:
 131  * Page Stolen:
 132  * rxq.queue -> rxq.rx_used -> allocator.rbd_empty ->
 133  * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue
 134  * Page not Stolen:
 135  * rxq.queue -> rxq.rx_free -> rxq.queue
 136  * ...
 137  *
 138  */
 139
 140 /*
 141  * iwl_rxq_space - Return number of free slots available in queue.
 142  */
 143 static int iwl_rxq_space(const struct iwl_rxq *rxq)
 144 {
 145         /* Make sure rx queue size is a power of 2 */
 146         WARN_ON(rxq->queue_size & (rxq->queue_size - 1));
 147
 148         /*
 149          * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
 150          * between empty and completely full queues.
 151          * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
 152          * defined for negative dividends.
 153          */
 154         return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1);
 155 }
 156
 157 /*
 158  * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 159  */
 160 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 161 {
 162         return cpu_to_le32((u32)(dma_addr >> 8));
 163 }
 164
 165 /*
 166  * iwl_pcie_rx_stop - stops the Rx DMA
 167  */
 168 int iwl_pcie_rx_stop(struct iwl_trans *trans)
 169 {
 170         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) {
 171                 /* TODO: remove this for 22560 once fw does it */
 172                 iwl_write_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0);
 173                 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS_GEN3,
 174                                          RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
 175         } else if (trans->cfg->mq_rx_supported) {
 176                 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);
 177                 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS,
 178                                            RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
 179         } else {
 180                 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 181                 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 182                                            FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
 183                                            1000);
 184         }
 185 }
 186
 187 /*
 188  * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
 189  */
 190 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
 191                                     struct iwl_rxq *rxq)
 192 {
 193         u32 reg;
 194
 195         lockdep_assert_held(&rxq->lock);
 196
 197         /*
 198          * explicitly wake up the NIC if:
 199          * 1. shadow registers aren't enabled
 200          * 2. there is a chance that the NIC is asleep
 201          */
 202         if (!trans->cfg->base_params->shadow_reg_enable &&
 203             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 204                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 205
 206                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 207                         IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n",
 208                                        reg);
 209                         iwl_set_bit(trans, CSR_GP_CNTRL,
 210                                     BIT(trans->cfg->csr->flag_mac_access_req));
 211                         rxq->need_update = true;
 212                         return;
 213                 }
 214         }
 215
 216         rxq->write_actual = round_down(rxq->write, 8);
 217         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
 218                 iwl_write32(trans, HBUS_TARG_WRPTR,
 219                             (rxq->write_actual |
 220                              ((FIRST_RX_QUEUE + rxq->id) << 16)));
 221         else if (trans->cfg->mq_rx_supported)
 222                 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),
 223                             rxq->write_actual);
 224         else
 225                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
 226 }
 227
 228 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans)
 229 {
 230         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 231         int i;
 232
 233         for (i = 0; i < trans->num_rx_queues; i++) {
 234                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 235
 236                 if (!rxq->need_update)
 237                         continue;
 238                 spin_lock(&rxq->lock);
 239                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 240                 rxq->need_update = false;
 241                 spin_unlock(&rxq->lock);
 242         }
 243 }
 244
 245 static void iwl_pcie_restock_bd(struct iwl_trans *trans,
 246                                 struct iwl_rxq *rxq,
 247                                 struct iwl_rx_mem_buffer *rxb)
 248 {
 249         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) {
 250                 struct iwl_rx_transfer_desc *bd = rxq->bd;
 251
 252                 bd[rxq->write].type_n_size =
 253                         cpu_to_le32((IWL_RX_TD_TYPE & IWL_RX_TD_TYPE_MSK) |
 254                         ((IWL_RX_TD_SIZE_2K >> 8) & IWL_RX_TD_SIZE_MSK));
 255                 bd[rxq->write].addr = cpu_to_le64(rxb->page_dma);
 256                 bd[rxq->write].rbid = cpu_to_le16(rxb->vid);
 257         } else {
 258                 __le64 *bd = rxq->bd;
 259
 260                 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid);
 261         }
 262 }
 263
 264 /*
 265  * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx
 266  */
 267 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans,
 268                                   struct iwl_rxq *rxq)
 269 {
 270         struct iwl_rx_mem_buffer *rxb;
 271
 272         /*
 273          * If the device isn't enabled - no need to try to add buffers...
 274          * This can happen when we stop the device and still have an interrupt
 275          * pending. We stop the APM before we sync the interrupts because we
 276          * have to (see comment there). On the other hand, since the APM is
 277          * stopped, we cannot access the HW (in particular not prph).
 278          * So don't try to restock if the APM has been already stopped.
 279          */
 280         if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 281                 return;
 282
 283         spin_lock(&rxq->lock);
 284         while (rxq->free_count) {
 285                 /* Get next free Rx buffer, remove from free list */
 286                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 287                                        list);
 288                 list_del(&rxb->list);
 289                 rxb->invalid = false;
 290                 /* 12 first bits are expected to be empty */
 291                 WARN_ON(rxb->page_dma & DMA_BIT_MASK(12));
 292                 /* Point to Rx buffer via next RBD in circular buffer */
 293                 iwl_pcie_restock_bd(trans, rxq, rxb);
 294                 rxq->write = (rxq->write + 1) & MQ_RX_TABLE_MASK;
 295                 rxq->free_count--;
 296         }
 297         spin_unlock(&rxq->lock);
 298
 299         /*
 300          * If we've added more space for the firmware to place data, tell it.
 301          * Increment device's write pointer in multiples of 8.
 302          */
 303         if (rxq->write_actual != (rxq->write & ~0x7)) {
 304                 spin_lock(&rxq->lock);
 305                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 306                 spin_unlock(&rxq->lock);
 307         }
 308 }
 309
 310 /*
 311  * iwl_pcie_rxsq_restock - restock implementation for single queue rx
 312  */
 313 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans,
 314                                   struct iwl_rxq *rxq)
 315 {
 316         struct iwl_rx_mem_buffer *rxb;
 317
 318         /*
 319          * If the device isn't enabled - not need to try to add buffers...
 320          * This can happen when we stop the device and still have an interrupt
 321          * pending. We stop the APM before we sync the interrupts because we
 322          * have to (see comment there). On the other hand, since the APM is
 323          * stopped, we cannot access the HW (in particular not prph).
 324          * So don't try to restock if the APM has been already stopped.
 325          */
 326         if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 327                 return;
 328
 329         spin_lock(&rxq->lock);
 330         while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
 331                 __le32 *bd = (__le32 *)rxq->bd;
 332                 /* The overwritten rxb must be a used one */
 333                 rxb = rxq->queue[rxq->write];
 334                 BUG_ON(rxb && rxb->page);
 335
 336                 /* Get next free Rx buffer, remove from free list */
 337                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 338                                        list);
 339                 list_del(&rxb->list);
 340                 rxb->invalid = false;
 341
 342                 /* Point to Rx buffer via next RBD in circular buffer */
 343                 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
 344                 rxq->queue[rxq->write] = rxb;
 345                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 346                 rxq->free_count--;
 347         }
 348         spin_unlock(&rxq->lock);
 349
 350         /* If we've added more space for the firmware to place data, tell it.
 351          * Increment device's write pointer in multiples of 8. */
 352         if (rxq->write_actual != (rxq->write & ~0x7)) {
 353                 spin_lock(&rxq->lock);
 354                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 355                 spin_unlock(&rxq->lock);
 356         }
 357 }
 358
 359 /*
 360  * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
 361  *
 362  * If there are slots in the RX queue that need to be restocked,
 363  * and we have free pre-allocated buffers, fill the ranks as much
 364  * as we can, pulling from rx_free.
 365  *
 366  * This moves the 'write' index forward to catch up with 'processed', and
 367  * also updates the memory address in the firmware to reference the new
 368  * target buffer.
 369  */
 370 static
 371 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq)
 372 {
 373         if (trans->cfg->mq_rx_supported)
 374                 iwl_pcie_rxmq_restock(trans, rxq);
 375         else
 376                 iwl_pcie_rxsq_restock(trans, rxq);
 377 }
 378
 379 /*
 380  * iwl_pcie_rx_alloc_page - allocates and returns a page.
 381  *
 382  */
 383 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans,
 384                                            gfp_t priority)
 385 {
 386         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 387         struct page *page;
 388         gfp_t gfp_mask = priority;
 389
 390         if (trans_pcie->rx_page_order > 0)
 391                 gfp_mask |= __GFP_COMP;
 392
 393         /* Alloc a new receive buffer */
 394         page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
 395         if (!page) {
 396                 if (net_ratelimit())
 397                         IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n",
 398                                        trans_pcie->rx_page_order);
 399                 /*
 400                  * Issue an error if we don't have enough pre-allocated
 401                   * buffers.
 402 `                */
 403                 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit())
 404                         IWL_CRIT(trans,
 405                                  "Failed to alloc_pages\n");
 406                 return NULL;
 407         }
 408         return page;
 409 }
 410
 411 /*
 412  * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
 413  *
 414  * A used RBD is an Rx buffer that has been given to the stack. To use it again
 415  * a page must be allocated and the RBD must point to the page. This function
 416  * doesn't change the HW pointer but handles the list of pages that is used by
 417  * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
 418  * allocated buffers.
 419  */
 420 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
 421                             struct iwl_rxq *rxq)
 422 {
 423         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 424         struct iwl_rx_mem_buffer *rxb;
 425         struct page *page;
 426
 427         while (1) {
 428                 spin_lock(&rxq->lock);
 429                 if (list_empty(&rxq->rx_used)) {
 430                         spin_unlock(&rxq->lock);
 431                         return;
 432                 }
 433                 spin_unlock(&rxq->lock);
 434
 435                 /* Alloc a new receive buffer */
 436                 page = iwl_pcie_rx_alloc_page(trans, priority);
 437                 if (!page)
 438                         return;
 439
 440                 spin_lock(&rxq->lock);
 441
 442                 if (list_empty(&rxq->rx_used)) {
 443                         spin_unlock(&rxq->lock);
 444                         __free_pages(page, trans_pcie->rx_page_order);
 445                         return;
 446                 }
 447                 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
 448                                        list);
 449                 list_del(&rxb->list);
 450                 spin_unlock(&rxq->lock);
 451
 452                 BUG_ON(rxb->page);
 453                 rxb->page = page;
 454                 /* Get physical address of the RB */
 455                 rxb->page_dma =
 456                         dma_map_page(trans->dev, page, 0,
 457                                      PAGE_SIZE << trans_pcie->rx_page_order,
 458                                      DMA_FROM_DEVICE);
 459                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 460                         rxb->page = NULL;
 461                         spin_lock(&rxq->lock);
 462                         list_add(&rxb->list, &rxq->rx_used);
 463                         spin_unlock(&rxq->lock);
 464                         __free_pages(page, trans_pcie->rx_page_order);
 465                         return;
 466                 }
 467
 468                 spin_lock(&rxq->lock);
 469
 470                 list_add_tail(&rxb->list, &rxq->rx_free);
 471                 rxq->free_count++;
 472
 473                 spin_unlock(&rxq->lock);
 474         }
 475 }
 476
 477 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans)
 478 {
 479         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 480         int i;
 481
 482         for (i = 0; i < RX_POOL_SIZE; i++) {
 483                 if (!trans_pcie->rx_pool[i].page)
 484                         continue;
 485                 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma,
 486                                PAGE_SIZE << trans_pcie->rx_page_order,
 487                                DMA_FROM_DEVICE);
 488                 __free_pages(trans_pcie->rx_pool[i].page,
 489                              trans_pcie->rx_page_order);
 490                 trans_pcie->rx_pool[i].page = NULL;
 491         }
 492 }
 493
 494 /*
 495  * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues
 496  *
 497  * Allocates for each received request 8 pages
 498  * Called as a scheduled work item.
 499  */
 500 static void iwl_pcie_rx_allocator(struct iwl_trans *trans)
 501 {
 502         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 503         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 504         struct list_head local_empty;
 505         int pending = atomic_read(&rba->req_pending);
 506
 507         IWL_DEBUG_RX(trans, "Pending allocation requests = %d\n", pending);
 508
 509         /* If we were scheduled - there is at least one request */
 510         spin_lock(&rba->lock);
 511         /* swap out the rba->rbd_empty to a local list */
 512         list_replace_init(&rba->rbd_empty, &local_empty);
 513         spin_unlock(&rba->lock);
 514
 515         while (pending) {
 516                 int i;
 517                 LIST_HEAD(local_allocated);
 518                 gfp_t gfp_mask = GFP_KERNEL;
 519
 520                 /* Do not post a warning if there are only a few requests */
 521                 if (pending < RX_PENDING_WATERMARK)
 522                         gfp_mask |= __GFP_NOWARN;
 523
 524                 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) {
 525                         struct iwl_rx_mem_buffer *rxb;
 526                         struct page *page;
 527
 528                         /* List should never be empty - each reused RBD is
 529                          * returned to the list, and initial pool covers any
 530                          * possible gap between the time the page is allocated
 531                          * to the time the RBD is added.
 532                          */
 533                         BUG_ON(list_empty(&local_empty));
 534                         /* Get the first rxb from the rbd list */
 535                         rxb = list_first_entry(&local_empty,
 536                                                struct iwl_rx_mem_buffer, list);
 537                         BUG_ON(rxb->page);
 538
 539                         /* Alloc a new receive buffer */
 540                         page = iwl_pcie_rx_alloc_page(trans, gfp_mask);
 541                         if (!page)
 542                                 continue;
 543                         rxb->page = page;
 544
 545                         /* Get physical address of the RB */
 546                         rxb->page_dma = dma_map_page(trans->dev, page, 0,
 547                                         PAGE_SIZE << trans_pcie->rx_page_order,
 548                                         DMA_FROM_DEVICE);
 549                         if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 550                                 rxb->page = NULL;
 551                                 __free_pages(page, trans_pcie->rx_page_order);
 552                                 continue;
 553                         }
 554
 555                         /* move the allocated entry to the out list */
 556                         list_move(&rxb->list, &local_allocated);
 557                         i++;
 558                 }
 559
 560                 atomic_dec(&rba->req_pending);
 561                 pending--;
 562
 563                 if (!pending) {
 564                         pending = atomic_read(&rba->req_pending);
 565                         IWL_DEBUG_RX(trans,
 566                                      "Got more pending allocation requests = %d\n",
 567                                      pending);
 568                 }
 569
 570                 spin_lock(&rba->lock);
 571                 /* add the allocated rbds to the allocator allocated list */
 572                 list_splice_tail(&local_allocated, &rba->rbd_allocated);
 573                 /* get more empty RBDs for current pending requests */
 574                 list_splice_tail_init(&rba->rbd_empty, &local_empty);
 575                 spin_unlock(&rba->lock);
 576
 577                 atomic_inc(&rba->req_ready);
 578
 579         }
 580
 581         spin_lock(&rba->lock);
 582         /* return unused rbds to the allocator empty list */
 583         list_splice_tail(&local_empty, &rba->rbd_empty);
 584         spin_unlock(&rba->lock);
 585
 586         IWL_DEBUG_RX(trans, "%s, exit.\n", __func__);
 587 }
 588
 589 /*
 590  * iwl_pcie_rx_allocator_get - returns the pre-allocated pages
 591 .*
 592 .* Called by queue when the queue posted allocation request and
 593  * has freed 8 RBDs in order to restock itself.
 594  * This function directly moves the allocated RBs to the queue's ownership
 595  * and updates the relevant counters.
 596  */
 597 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans,
 598                                       struct iwl_rxq *rxq)
 599 {
 600         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 601         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 602         int i;
 603
 604         lockdep_assert_held(&rxq->lock);
 605
 606         /*
 607          * atomic_dec_if_positive returns req_ready - 1 for any scenario.
 608          * If req_ready is 0 atomic_dec_if_positive will return -1 and this
 609          * function will return early, as there are no ready requests.
 610          * atomic_dec_if_positive will perofrm the *actual* decrement only if
 611          * req_ready > 0, i.e. - there are ready requests and the function
 612          * hands one request to the caller.
 613          */
 614         if (atomic_dec_if_positive(&rba->req_ready) < 0)
 615                 return;
 616
 617         spin_lock(&rba->lock);
 618         for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) {
 619                 /* Get next free Rx buffer, remove it from free list */
 620                 struct iwl_rx_mem_buffer *rxb =
 621                         list_first_entry(&rba->rbd_allocated,
 622                                          struct iwl_rx_mem_buffer, list);
 623
 624                 list_move(&rxb->list, &rxq->rx_free);
 625         }
 626         spin_unlock(&rba->lock);
 627
 628         rxq->used_count -= RX_CLAIM_REQ_ALLOC;
 629         rxq->free_count += RX_CLAIM_REQ_ALLOC;
 630 }
 631
 632 void iwl_pcie_rx_allocator_work(struct work_struct *data)
 633 {
 634         struct iwl_rb_allocator *rba_p =
 635                 container_of(data, struct iwl_rb_allocator, rx_alloc);
 636         struct iwl_trans_pcie *trans_pcie =
 637                 container_of(rba_p, struct iwl_trans_pcie, rba);
 638
 639         iwl_pcie_rx_allocator(trans_pcie->trans);
 640 }
 641
 642 static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td)
 643 {
 644         struct iwl_rx_transfer_desc *rx_td;
 645
 646         if (use_rx_td)
 647                 return sizeof(*rx_td);
 648         else
 649                 return trans->cfg->mq_rx_supported ? sizeof(__le64) :
 650                         sizeof(__le32);
 651 }
 652
 653 static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans,
 654                                   struct iwl_rxq *rxq)
 655 {
 656         struct device *dev = trans->dev;
 657         bool use_rx_td = (trans->cfg->device_family >=
 658                           IWL_DEVICE_FAMILY_22560);
 659         int free_size = iwl_pcie_free_bd_size(trans, use_rx_td);
 660
 661         if (rxq->bd)
 662                 dma_free_coherent(trans->dev,
 663                                   free_size * rxq->queue_size,
 664                                   rxq->bd, rxq->bd_dma);
 665         rxq->bd_dma = 0;
 666         rxq->bd = NULL;
 667
 668         if (rxq->rb_stts)
 669                 dma_free_coherent(trans->dev,
 670                                   use_rx_td ? sizeof(__le16) :
 671                                   sizeof(struct iwl_rb_status),
 672                                   rxq->rb_stts, rxq->rb_stts_dma);
 673         rxq->rb_stts_dma = 0;
 674         rxq->rb_stts = NULL;
 675
 676         if (rxq->used_bd)
 677                 dma_free_coherent(trans->dev,
 678                                   (use_rx_td ? sizeof(*rxq->cd) :
 679                                    sizeof(__le32)) * rxq->queue_size,
 680                                   rxq->used_bd, rxq->used_bd_dma);
 681         rxq->used_bd_dma = 0;
 682         rxq->used_bd = NULL;
 683
 684         if (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560)
 685                 return;
 686
 687         if (rxq->tr_tail)
 688                 dma_free_coherent(dev, sizeof(__le16),
 689                                   rxq->tr_tail, rxq->tr_tail_dma);
 690         rxq->tr_tail_dma = 0;
 691         rxq->tr_tail = NULL;
 692
 693         if (rxq->cr_tail)
 694                 dma_free_coherent(dev, sizeof(__le16),
 695                                   rxq->cr_tail, rxq->cr_tail_dma);
 696         rxq->cr_tail_dma = 0;
 697         rxq->cr_tail = NULL;
 698 }
 699
 700 static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans,
 701                                   struct iwl_rxq *rxq)
 702 {
 703         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 704         struct device *dev = trans->dev;
 705         int i;
 706         int free_size;
 707         bool use_rx_td = (trans->cfg->device_family >=
 708                           IWL_DEVICE_FAMILY_22560);
 709
 710         spin_lock_init(&rxq->lock);
 711         if (trans->cfg->mq_rx_supported)
 712                 rxq->queue_size = MQ_RX_TABLE_SIZE;
 713         else
 714                 rxq->queue_size = RX_QUEUE_SIZE;
 715
 716         free_size = iwl_pcie_free_bd_size(trans, use_rx_td);
 717
 718         /*
 719          * Allocate the circular buffer of Read Buffer Descriptors
 720          * (RBDs)
 721          */
 722         rxq->bd = dma_zalloc_coherent(dev,
 723                                       free_size * rxq->queue_size,
 724                                       &rxq->bd_dma, GFP_KERNEL);
 725         if (!rxq->bd)
 726                 goto err;
 727
 728         if (trans->cfg->mq_rx_supported) {
 729                 rxq->used_bd = dma_zalloc_coherent(dev,
 730                                                    (use_rx_td ?
 731                                                    sizeof(*rxq->cd) :
 732                                                    sizeof(__le32)) *
 733                                                    rxq->queue_size,
 734                                                    &rxq->used_bd_dma,
 735                                                    GFP_KERNEL);
 736                 if (!rxq->used_bd)
 737                         goto err;
 738         }
 739
 740         /* Allocate the driver's pointer to receive buffer status */
 741         rxq->rb_stts = dma_zalloc_coherent(dev, use_rx_td ?
 742                                            sizeof(__le16) :
 743                                            sizeof(struct iwl_rb_status),
 744                                            &rxq->rb_stts_dma,
 745                                            GFP_KERNEL);
 746         if (!rxq->rb_stts)
 747                 goto err;
 748
 749         if (!use_rx_td)
 750                 return 0;
 751
 752         /* Allocate the driver's pointer to TR tail */
 753         rxq->tr_tail = dma_zalloc_coherent(dev, sizeof(__le16),
 754                                            &rxq->tr_tail_dma,
 755                                            GFP_KERNEL);
 756         if (!rxq->tr_tail)
 757                 goto err;
 758
 759         /* Allocate the driver's pointer to CR tail */
 760         rxq->cr_tail = dma_zalloc_coherent(dev, sizeof(__le16),
 761                                            &rxq->cr_tail_dma,
 762                                            GFP_KERNEL);
 763         if (!rxq->cr_tail)
 764                 goto err;
 765         /*
 766          * W/A 22560 device step Z0 must be non zero bug
 767          * TODO: remove this when stop supporting Z0
 768          */
 769         *rxq->cr_tail = cpu_to_le16(500);
 770
 771         return 0;
 772
 773 err:
 774         for (i = 0; i < trans->num_rx_queues; i++) {
 775                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 776
 777                 iwl_pcie_free_rxq_dma(trans, rxq);
 778         }
 779         kfree(trans_pcie->rxq);
 780
 781         return -ENOMEM;
 782 }
 783
 784 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
 785 {
 786         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 787         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 788         int i, ret;
 789
 790         if (WARN_ON(trans_pcie->rxq))
 791                 return -EINVAL;
 792
 793         trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq),
 794                                   GFP_KERNEL);
 795         if (!trans_pcie->rxq)
 796                 return -EINVAL;
 797
 798         spin_lock_init(&rba->lock);
 799
 800         for (i = 0; i < trans->num_rx_queues; i++) {
 801                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 802
 803                 ret = iwl_pcie_alloc_rxq_dma(trans, rxq);
 804                 if (ret)
 805                         return ret;
 806         }
 807         return 0;
 808 }
 809
 810 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
 811 {
 812         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 813         u32 rb_size;
 814         unsigned long flags;
 815         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 816
 817         switch (trans_pcie->rx_buf_size) {
 818         case IWL_AMSDU_4K:
 819                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 820                 break;
 821         case IWL_AMSDU_8K:
 822                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 823                 break;
 824         case IWL_AMSDU_12K:
 825                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K;
 826                 break;
 827         default:
 828                 WARN_ON(1);
 829                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 830         }
 831
 832         if (!iwl_trans_grab_nic_access(trans, &flags))
 833                 return;
 834
 835         /* Stop Rx DMA */
 836         iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 837         /* reset and flush pointers */
 838         iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
 839         iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
 840         iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
 841
 842         /* Reset driver's Rx queue write index */
 843         iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 844
 845         /* Tell device where to find RBD circular buffer in DRAM */
 846         iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 847                     (u32)(rxq->bd_dma >> 8));
 848
 849         /* Tell device where in DRAM to update its Rx status */
 850         iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 851                     rxq->rb_stts_dma >> 4);
 852
 853         /* Enable Rx DMA
 854          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 855          *      the credit mechanism in 5000 HW RX FIFO
 856          * Direct rx interrupts to hosts
 857          * Rx buffer size 4 or 8k or 12k
 858          * RB timeout 0x10
 859          * 256 RBDs
 860          */
 861         iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 862                     FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 863                     FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 864                     FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 865                     rb_size |
 866                     (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
 867                     (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 868
 869         iwl_trans_release_nic_access(trans, &flags);
 870
 871         /* Set interrupt coalescing timer to default (2048 usecs) */
 872         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 873
 874         /* W/A for interrupt coalescing bug in 7260 and 3160 */
 875         if (trans->cfg->host_interrupt_operation_mode)
 876                 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
 877 }
 878
 879 void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable)
 880 {
 881         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_9000)
 882                 return;
 883
 884         if (CSR_HW_REV_STEP(trans->hw_rev) != SILICON_A_STEP)
 885                 return;
 886
 887         if (!trans->cfg->integrated)
 888                 return;
 889
 890         /*
 891          * Turn on the chicken-bits that cause MAC wakeup for RX-related
 892          * values.
 893          * This costs some power, but needed for W/A 9000 integrated A-step
 894          * bug where shadow registers are not in the retention list and their
 895          * value is lost when NIC powers down
 896          */
 897         iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
 898                     CSR_MAC_SHADOW_REG_CTRL_RX_WAKE);
 899         iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTL2,
 900                     CSR_MAC_SHADOW_REG_CTL2_RX_WAKE);
 901 }
 902
 903 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
 904 {
 905         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 906         u32 rb_size, enabled = 0;
 907         unsigned long flags;
 908         int i;
 909
 910         switch (trans_pcie->rx_buf_size) {
 911         case IWL_AMSDU_2K:
 912                 rb_size = RFH_RXF_DMA_RB_SIZE_2K;
 913                 break;
 914         case IWL_AMSDU_4K:
 915                 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
 916                 break;
 917         case IWL_AMSDU_8K:
 918                 rb_size = RFH_RXF_DMA_RB_SIZE_8K;
 919                 break;
 920         case IWL_AMSDU_12K:
 921                 rb_size = RFH_RXF_DMA_RB_SIZE_12K;
 922                 break;
 923         default:
 924                 WARN_ON(1);
 925                 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
 926         }
 927
 928         if (!iwl_trans_grab_nic_access(trans, &flags))
 929                 return;
 930
 931         /* Stop Rx DMA */
 932         iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);
 933         /* disable free amd used rx queue operation */
 934         iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);
 935
 936         for (i = 0; i < trans->num_rx_queues; i++) {
 937                 /* Tell device where to find RBD free table in DRAM */
 938                 iwl_write_prph64_no_grab(trans,
 939                                          RFH_Q_FRBDCB_BA_LSB(i),
 940                                          trans_pcie->rxq[i].bd_dma);
 941                 /* Tell device where to find RBD used table in DRAM */
 942                 iwl_write_prph64_no_grab(trans,
 943                                          RFH_Q_URBDCB_BA_LSB(i),
 944                                          trans_pcie->rxq[i].used_bd_dma);
 945                 /* Tell device where in DRAM to update its Rx status */
 946                 iwl_write_prph64_no_grab(trans,
 947                                          RFH_Q_URBD_STTS_WPTR_LSB(i),
 948                                          trans_pcie->rxq[i].rb_stts_dma);
 949                 /* Reset device indice tables */
 950                 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);
 951                 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);
 952                 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);
 953
 954                 enabled |= BIT(i) | BIT(i + 16);
 955         }
 956
 957         /*
 958          * Enable Rx DMA
 959          * Rx buffer size 4 or 8k or 12k
 960          * Min RB size 4 or 8
 961          * Drop frames that exceed RB size
 962          * 512 RBDs
 963          */
 964         iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,
 965                                RFH_DMA_EN_ENABLE_VAL | rb_size |
 966                                RFH_RXF_DMA_MIN_RB_4_8 |
 967                                RFH_RXF_DMA_DROP_TOO_LARGE_MASK |
 968                                RFH_RXF_DMA_RBDCB_SIZE_512);
 969
 970         /*
 971          * Activate DMA snooping.
 972          * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe
 973          * Default queue is 0
 974          */
 975         iwl_write_prph_no_grab(trans, RFH_GEN_CFG,
 976                                RFH_GEN_CFG_RFH_DMA_SNOOP |
 977                                RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) |
 978                                RFH_GEN_CFG_SERVICE_DMA_SNOOP |
 979                                RFH_GEN_CFG_VAL(RB_CHUNK_SIZE,
 980                                                trans->cfg->integrated ?
 981                                                RFH_GEN_CFG_RB_CHUNK_SIZE_64 :
 982                                                RFH_GEN_CFG_RB_CHUNK_SIZE_128));
 983         /* Enable the relevant rx queues */
 984         iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
 985
 986         iwl_trans_release_nic_access(trans, &flags);
 987
 988         /* Set interrupt coalescing timer to default (2048 usecs) */
 989         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 990
 991         iwl_pcie_enable_rx_wake(trans, true);
 992 }
 993
 994 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
 995 {
 996         lockdep_assert_held(&rxq->lock);
 997
 998         INIT_LIST_HEAD(&rxq->rx_free);
 999         INIT_LIST_HEAD(&rxq->rx_used);
1000         rxq->free_count = 0;
1001         rxq->used_count = 0;
1002 }
1003
1004 int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1005 {
1006         WARN_ON(1);
1007         return 0;
1008 }
1009
1010 static int _iwl_pcie_rx_init(struct iwl_trans *trans)
1011 {
1012         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1013         struct iwl_rxq *def_rxq;
1014         struct iwl_rb_allocator *rba = &trans_pcie->rba;
1015         int i, err, queue_size, allocator_pool_size, num_alloc;
1016
1017         if (!trans_pcie->rxq) {
1018                 err = iwl_pcie_rx_alloc(trans);
1019                 if (err)
1020                         return err;
1021         }
1022         def_rxq = trans_pcie->rxq;
1023
1024         cancel_work_sync(&rba->rx_alloc);
1025
1026         spin_lock(&rba->lock);
1027         atomic_set(&rba->req_pending, 0);
1028         atomic_set(&rba->req_ready, 0);
1029         INIT_LIST_HEAD(&rba->rbd_allocated);
1030         INIT_LIST_HEAD(&rba->rbd_empty);
1031         spin_unlock(&rba->lock);
1032
1033         /* free all first - we might be reconfigured for a different size */
1034         iwl_pcie_free_rbs_pool(trans);
1035
1036         for (i = 0; i < RX_QUEUE_SIZE; i++)
1037                 def_rxq->queue[i] = NULL;
1038
1039         for (i = 0; i < trans->num_rx_queues; i++) {
1040                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1041
1042                 rxq->id = i;
1043
1044                 spin_lock(&rxq->lock);
1045                 /*
1046                  * Set read write pointer to reflect that we have processed
1047                  * and used all buffers, but have not restocked the Rx queue
1048                  * with fresh buffers
1049                  */
1050                 rxq->read = 0;
1051                 rxq->write = 0;
1052                 rxq->write_actual = 0;
1053                 memset(rxq->rb_stts, 0,
1054                        (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) ?
1055                        sizeof(__le16) : sizeof(struct iwl_rb_status));
1056
1057                 iwl_pcie_rx_init_rxb_lists(rxq);
1058
1059                 if (!rxq->napi.poll)
1060                         netif_napi_add(&trans_pcie->napi_dev, &rxq->napi,
1061                                        iwl_pcie_dummy_napi_poll, 64);
1062
1063                 spin_unlock(&rxq->lock);
1064         }
1065
1066         /* move the pool to the default queue and allocator ownerships */
1067         queue_size = trans->cfg->mq_rx_supported ?
1068                      MQ_RX_NUM_RBDS : RX_QUEUE_SIZE;
1069         allocator_pool_size = trans->num_rx_queues *
1070                 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC);
1071         num_alloc = queue_size + allocator_pool_size;
1072         BUILD_BUG_ON(ARRAY_SIZE(trans_pcie->global_table) !=
1073                      ARRAY_SIZE(trans_pcie->rx_pool));
1074         for (i = 0; i < num_alloc; i++) {
1075                 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i];
1076
1077                 if (i < allocator_pool_size)
1078                         list_add(&rxb->list, &rba->rbd_empty);
1079                 else
1080                         list_add(&rxb->list, &def_rxq->rx_used);
1081                 trans_pcie->global_table[i] = rxb;
1082                 rxb->vid = (u16)(i + 1);
1083                 rxb->invalid = true;
1084         }
1085
1086         iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq);
1087
1088         return 0;
1089 }
1090
1091 int iwl_pcie_rx_init(struct iwl_trans *trans)
1092 {
1093         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1094         int ret = _iwl_pcie_rx_init(trans);
1095
1096         if (ret)
1097                 return ret;
1098
1099         if (trans->cfg->mq_rx_supported)
1100                 iwl_pcie_rx_mq_hw_init(trans);
1101         else
1102                 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq);
1103
1104         iwl_pcie_rxq_restock(trans, trans_pcie->rxq);
1105
1106         spin_lock(&trans_pcie->rxq->lock);
1107         iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq);
1108         spin_unlock(&trans_pcie->rxq->lock);
1109
1110         return 0;
1111 }
1112
1113 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans)
1114 {
1115         /*
1116          * We don't configure the RFH.
1117          * Restock will be done at alive, after firmware configured the RFH.
1118          */
1119         return _iwl_pcie_rx_init(trans);
1120 }
1121
1122 void iwl_pcie_rx_free(struct iwl_trans *trans)
1123 {
1124         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1125         struct iwl_rb_allocator *rba = &trans_pcie->rba;
1126         int i;
1127
1128         /*
1129          * if rxq is NULL, it means that nothing has been allocated,
1130          * exit now
1131          */
1132         if (!trans_pcie->rxq) {
1133                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
1134                 return;
1135         }
1136
1137         cancel_work_sync(&rba->rx_alloc);
1138
1139         iwl_pcie_free_rbs_pool(trans);
1140
1141         for (i = 0; i < trans->num_rx_queues; i++) {
1142                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1143
1144                 iwl_pcie_free_rxq_dma(trans, rxq);
1145
1146                 if (rxq->napi.poll)
1147                         netif_napi_del(&rxq->napi);
1148         }
1149         kfree(trans_pcie->rxq);
1150 }
1151
1152 static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq,
1153                                           struct iwl_rb_allocator *rba)
1154 {
1155         spin_lock(&rba->lock);
1156         list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty);
1157         spin_unlock(&rba->lock);
1158 }
1159
1160 /*
1161  * iwl_pcie_rx_reuse_rbd - Recycle used RBDs
1162  *
1163  * Called when a RBD can be reused. The RBD is transferred to the allocator.
1164  * When there are 2 empty RBDs - a request for allocation is posted
1165  */
1166 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans,
1167                                   struct iwl_rx_mem_buffer *rxb,
1168                                   struct iwl_rxq *rxq, bool emergency)
1169 {
1170         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1171         struct iwl_rb_allocator *rba = &trans_pcie->rba;
1172
1173         /* Move the RBD to the used list, will be moved to allocator in batches
1174          * before claiming or posting a request*/
1175         list_add_tail(&rxb->list, &rxq->rx_used);
1176
1177         if (unlikely(emergency))
1178                 return;
1179
1180         /* Count the allocator owned RBDs */
1181         rxq->used_count++;
1182
1183         /* If we have RX_POST_REQ_ALLOC new released rx buffers -
1184          * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is
1185          * used for the case we failed to claim RX_CLAIM_REQ_ALLOC,
1186          * after but we still need to post another request.
1187          */
1188         if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) {
1189                 /* Move the 2 RBDs to the allocator ownership.
1190                  Allocator has another 6 from pool for the request completion*/
1191                 iwl_pcie_rx_move_to_allocator(rxq, rba);
1192
1193                 atomic_inc(&rba->req_pending);
1194                 queue_work(rba->alloc_wq, &rba->rx_alloc);
1195         }
1196 }
1197
1198 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
1199                                 struct iwl_rxq *rxq,
1200                                 struct iwl_rx_mem_buffer *rxb,
1201                                 bool emergency)
1202 {
1203         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1204         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1205         bool page_stolen = false;
1206         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
1207         u32 offset = 0;
1208
1209         if (WARN_ON(!rxb))
1210                 return;
1211
1212         dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
1213
1214         while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
1215                 struct iwl_rx_packet *pkt;
1216                 u16 sequence;
1217                 bool reclaim;
1218                 int index, cmd_index, len;
1219                 struct iwl_rx_cmd_buffer rxcb = {
1220                         ._offset = offset,
1221                         ._rx_page_order = trans_pcie->rx_page_order,
1222                         ._page = rxb->page,
1223                         ._page_stolen = false,
1224                         .truesize = max_len,
1225                 };
1226
1227                 pkt = rxb_addr(&rxcb);
1228
1229                 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) {
1230                         IWL_DEBUG_RX(trans,
1231                                      "Q %d: RB end marker at offset %d\n",
1232                                      rxq->id, offset);
1233                         break;
1234                 }
1235
1236                 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1237                         FH_RSCSR_RXQ_POS != rxq->id,
1238                      "frame on invalid queue - is on %d and indicates %d\n",
1239                      rxq->id,
1240                      (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1241                         FH_RSCSR_RXQ_POS);
1242
1243                 IWL_DEBUG_RX(trans,
1244                              "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n",
1245                              rxq->id, offset,
1246                              iwl_get_cmd_string(trans,
1247                                                 iwl_cmd_id(pkt->hdr.cmd,
1248                                                            pkt->hdr.group_id,
1249                                                            0)),
1250                              pkt->hdr.group_id, pkt->hdr.cmd,
1251                              le16_to_cpu(pkt->hdr.sequence));
1252
1253                 len = iwl_rx_packet_len(pkt);
1254                 len += sizeof(u32); /* account for status word */
1255                 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
1256                 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
1257
1258                 /* Reclaim a command buffer only if this packet is a response
1259                  *   to a (driver-originated) command.
1260                  * If the packet (e.g. Rx frame) originated from uCode,
1261                  *   there is no command buffer to reclaim.
1262                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1263                  *   but apparently a few don't get set; catch them here. */
1264                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
1265                 if (reclaim && !pkt->hdr.group_id) {
1266                         int i;
1267
1268                         for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
1269                                 if (trans_pcie->no_reclaim_cmds[i] ==
1270                                                         pkt->hdr.cmd) {
1271                                         reclaim = false;
1272                                         break;
1273                                 }
1274                         }
1275                 }
1276
1277                 sequence = le16_to_cpu(pkt->hdr.sequence);
1278                 index = SEQ_TO_INDEX(sequence);
1279                 cmd_index = iwl_pcie_get_cmd_index(txq, index);
1280
1281                 if (rxq->id == 0)
1282                         iwl_op_mode_rx(trans->op_mode, &rxq->napi,
1283                                        &rxcb);
1284                 else
1285                         iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi,
1286                                            &rxcb, rxq->id);
1287
1288                 if (reclaim) {
1289                         kzfree(txq->entries[cmd_index].free_buf);
1290                         txq->entries[cmd_index].free_buf = NULL;
1291                 }
1292
1293                 /*
1294                  * After here, we should always check rxcb._page_stolen,
1295                  * if it is true then one of the handlers took the page.
1296                  */
1297
1298                 if (reclaim) {
1299                         /* Invoke any callbacks, transfer the buffer to caller,
1300                          * and fire off the (possibly) blocking
1301                          * iwl_trans_send_cmd()
1302                          * as we reclaim the driver command queue */
1303                         if (!rxcb._page_stolen)
1304                                 iwl_pcie_hcmd_complete(trans, &rxcb);
1305                         else
1306                                 IWL_WARN(trans, "Claim null rxb?\n");
1307                 }
1308
1309                 page_stolen |= rxcb._page_stolen;
1310                 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1311                         break;
1312                 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
1313         }
1314
1315         /* page was stolen from us -- free our reference */
1316         if (page_stolen) {
1317                 __free_pages(rxb->page, trans_pcie->rx_page_order);
1318                 rxb->page = NULL;
1319         }
1320
1321         /* Reuse the page if possible. For notification packets and
1322          * SKBs that fail to Rx correctly, add them back into the
1323          * rx_free list for reuse later. */
1324         if (rxb->page != NULL) {
1325                 rxb->page_dma =
1326                         dma_map_page(trans->dev, rxb->page, 0,
1327                                      PAGE_SIZE << trans_pcie->rx_page_order,
1328                                      DMA_FROM_DEVICE);
1329                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
1330                         /*
1331                          * free the page(s) as well to not break
1332                          * the invariant that the items on the used
1333                          * list have no page(s)
1334                          */
1335                         __free_pages(rxb->page, trans_pcie->rx_page_order);
1336                         rxb->page = NULL;
1337                         iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1338                 } else {
1339                         list_add_tail(&rxb->list, &rxq->rx_free);
1340                         rxq->free_count++;
1341                 }
1342         } else
1343                 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1344 }
1345
1346 static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans,
1347                                                   struct iwl_rxq *rxq, int i)
1348 {
1349         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1350         struct iwl_rx_mem_buffer *rxb;
1351         u16 vid;
1352
1353         if (!trans->cfg->mq_rx_supported) {
1354                 rxb = rxq->queue[i];
1355                 rxq->queue[i] = NULL;
1356                 return rxb;
1357         }
1358
1359         /* used_bd is a 32/16 bit but only 12 are used to retrieve the vid */
1360         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1361                 vid = le16_to_cpu(rxq->cd[i].rbid) & 0x0FFF;
1362         else
1363                 vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF;
1364
1365         if (!vid || vid > ARRAY_SIZE(trans_pcie->global_table))
1366                 goto out_err;
1367
1368         rxb = trans_pcie->global_table[vid - 1];
1369         if (rxb->invalid)
1370                 goto out_err;
1371
1372         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1373                 rxb->size = le32_to_cpu(rxq->cd[i].size) & IWL_RX_CD_SIZE;
1374
1375         rxb->invalid = true;
1376
1377         return rxb;
1378
1379 out_err:
1380         WARN(1, "Invalid rxb from HW %u\n", (u32)vid);
1381         iwl_force_nmi(trans);
1382         return NULL;
1383 }
1384
1385 /*
1386  * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
1387  */
1388 static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue)
1389 {
1390         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1391         struct iwl_rxq *rxq;
1392         u32 r, i, count = 0;
1393         bool emergency = false;
1394
1395         if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd))
1396                 return;
1397
1398         rxq = &trans_pcie->rxq[queue];
1399
1400 restart:
1401         spin_lock(&rxq->lock);
1402         /* uCode's read index (stored in shared DRAM) indicates the last Rx
1403          * buffer that the driver may process (last buffer filled by ucode). */
1404         r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
1405         i = rxq->read;
1406
1407         /* W/A 9000 device step A0 wrap-around bug */
1408         r &= (rxq->queue_size - 1);
1409
1410         /* Rx interrupt, but nothing sent from uCode */
1411         if (i == r)
1412                 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r);
1413
1414         while (i != r) {
1415                 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1416                 struct iwl_rx_mem_buffer *rxb;
1417                 /* number of RBDs still waiting for page allocation */
1418                 u32 rb_pending_alloc =
1419                         atomic_read(&trans_pcie->rba.req_pending) *
1420                         RX_CLAIM_REQ_ALLOC;
1421
1422                 if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 &&
1423                              !emergency)) {
1424                         iwl_pcie_rx_move_to_allocator(rxq, rba);
1425                         emergency = true;
1426                 }
1427
1428                 rxb = iwl_pcie_get_rxb(trans, rxq, i);
1429                 if (!rxb)
1430                         goto out;
1431
1432                 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i);
1433                 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency);
1434
1435                 i = (i + 1) & (rxq->queue_size - 1);
1436
1437                 /*
1438                  * If we have RX_CLAIM_REQ_ALLOC released rx buffers -
1439                  * try to claim the pre-allocated buffers from the allocator.
1440                  * If not ready - will try to reclaim next time.
1441                  * There is no need to reschedule work - allocator exits only
1442                  * on success
1443                  */
1444                 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC)
1445                         iwl_pcie_rx_allocator_get(trans, rxq);
1446
1447                 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) {
1448                         /* Add the remaining empty RBDs for allocator use */
1449                         iwl_pcie_rx_move_to_allocator(rxq, rba);
1450                 } else if (emergency) {
1451                         count++;
1452                         if (count == 8) {
1453                                 count = 0;
1454                                 if (rb_pending_alloc < rxq->queue_size / 3)
1455                                         emergency = false;
1456
1457                                 rxq->read = i;
1458                                 spin_unlock(&rxq->lock);
1459                                 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1460                                 iwl_pcie_rxq_restock(trans, rxq);
1461                                 goto restart;
1462                         }
1463                 }
1464         }
1465 out:
1466         /* Backtrack one entry */
1467         rxq->read = i;
1468         /* update cr tail with the rxq read pointer */
1469         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1470                 *rxq->cr_tail = cpu_to_le16(r);
1471         spin_unlock(&rxq->lock);
1472
1473         /*
1474          * handle a case where in emergency there are some unallocated RBDs.
1475          * those RBDs are in the used list, but are not tracked by the queue's
1476          * used_count which counts allocator owned RBDs.
1477          * unallocated emergency RBDs must be allocated on exit, otherwise
1478          * when called again the function may not be in emergency mode and
1479          * they will be handed to the allocator with no tracking in the RBD
1480          * allocator counters, which will lead to them never being claimed back
1481          * by the queue.
1482          * by allocating them here, they are now in the queue free list, and
1483          * will be restocked by the next call of iwl_pcie_rxq_restock.
1484          */
1485         if (unlikely(emergency && count))
1486                 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1487
1488         if (rxq->napi.poll)
1489                 napi_gro_flush(&rxq->napi, false);
1490
1491         iwl_pcie_rxq_restock(trans, rxq);
1492 }
1493
1494 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry)
1495 {
1496         u8 queue = entry->entry;
1497         struct msix_entry *entries = entry - queue;
1498
1499         return container_of(entries, struct iwl_trans_pcie, msix_entries[0]);
1500 }
1501
1502 /*
1503  * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw
1504  * This interrupt handler should be used with RSS queue only.
1505  */
1506 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id)
1507 {
1508         struct msix_entry *entry = dev_id;
1509         struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
1510         struct iwl_trans *trans = trans_pcie->trans;
1511
1512         trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0);
1513
1514         if (WARN_ON(entry->entry >= trans->num_rx_queues))
1515                 return IRQ_NONE;
1516
1517         lock_map_acquire(&trans->sync_cmd_lockdep_map);
1518
1519         local_bh_disable();
1520         iwl_pcie_rx_handle(trans, entry->entry);
1521         local_bh_enable();
1522
1523         iwl_pcie_clear_irq(trans, entry);
1524
1525         lock_map_release(&trans->sync_cmd_lockdep_map);
1526
1527         return IRQ_HANDLED;
1528 }
1529
1530 /*
1531  * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
1532  */
1533 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
1534 {
1535         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1536         int i;
1537
1538         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
1539         if (trans->cfg->internal_wimax_coex &&
1540             !trans->cfg->apmg_not_supported &&
1541             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
1542                              APMS_CLK_VAL_MRB_FUNC_MODE) ||
1543              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
1544                             APMG_PS_CTRL_VAL_RESET_REQ))) {
1545                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1546                 iwl_op_mode_wimax_active(trans->op_mode);
1547                 wake_up(&trans_pcie->wait_command_queue);
1548                 return;
1549         }
1550
1551         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1552                 if (!trans_pcie->txq[i])
1553                         continue;
1554                 del_timer(&trans_pcie->txq[i]->stuck_timer);
1555         }
1556
1557         /* The STATUS_FW_ERROR bit is set in this function. This must happen
1558          * before we wake up the command caller, to ensure a proper cleanup. */
1559         iwl_trans_fw_error(trans);
1560
1561         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1562         wake_up(&trans_pcie->wait_command_queue);
1563 }
1564
1565 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)
1566 {
1567         u32 inta;
1568
1569         lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock);
1570
1571         trace_iwlwifi_dev_irq(trans->dev);
1572
1573         /* Discover which interrupts are active/pending */
1574         inta = iwl_read32(trans, CSR_INT);
1575
1576         /* the thread will service interrupts and re-enable them */
1577         return inta;
1578 }
1579
1580 /* a device (PCI-E) page is 4096 bytes long */
1581 #define ICT_SHIFT       12
1582 #define ICT_SIZE        (1 << ICT_SHIFT)
1583 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
1584
1585 /* interrupt handler using ict table, with this interrupt driver will
1586  * stop using INTA register to get device's interrupt, reading this register
1587  * is expensive, device will write interrupts in ICT dram table, increment
1588  * index then will fire interrupt to driver, driver will OR all ICT table
1589  * entries from current index up to table entry with 0 value. the result is
1590  * the interrupt we need to service, driver will set the entries back to 0 and
1591  * set index.
1592  */
1593 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans)
1594 {
1595         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1596         u32 inta;
1597         u32 val = 0;
1598         u32 read;
1599
1600         trace_iwlwifi_dev_irq(trans->dev);
1601
1602         /* Ignore interrupt if there's nothing in NIC to service.
1603          * This may be due to IRQ shared with another device,
1604          * or due to sporadic interrupts thrown from our NIC. */
1605         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1606         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1607         if (!read)
1608                 return 0;
1609
1610         /*
1611          * Collect all entries up to the first 0, starting from ict_index;
1612          * note we already read at ict_index.
1613          */
1614         do {
1615                 val |= read;
1616                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1617                                 trans_pcie->ict_index, read);
1618                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1619                 trans_pcie->ict_index =
1620                         ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1));
1621
1622                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1623                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1624                                            read);
1625         } while (read);
1626
1627         /* We should not get this value, just ignore it. */
1628         if (val == 0xffffffff)
1629                 val = 0;
1630
1631         /*
1632          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1633          * (bit 15 before shifting it to 31) to clear when using interrupt
1634          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1635          * so we use them to decide on the real state of the Rx bit.
1636          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1637          */
1638         if (val & 0xC0000)
1639                 val |= 0x8000;
1640
1641         inta = (0xff & val) | ((0xff00 & val) << 16);
1642         return inta;
1643 }
1644
1645 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans)
1646 {
1647         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1648         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1649         bool hw_rfkill, prev, report;
1650
1651         mutex_lock(&trans_pcie->mutex);
1652         prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1653         hw_rfkill = iwl_is_rfkill_set(trans);
1654         if (hw_rfkill) {
1655                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1656                 set_bit(STATUS_RFKILL_HW, &trans->status);
1657         }
1658         if (trans_pcie->opmode_down)
1659                 report = hw_rfkill;
1660         else
1661                 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1662
1663         IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1664                  hw_rfkill ? "disable radio" : "enable radio");
1665
1666         isr_stats->rfkill++;
1667
1668         if (prev != report)
1669                 iwl_trans_pcie_rf_kill(trans, report);
1670         mutex_unlock(&trans_pcie->mutex);
1671
1672         if (hw_rfkill) {
1673                 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE,
1674                                        &trans->status))
1675                         IWL_DEBUG_RF_KILL(trans,
1676                                           "Rfkill while SYNC HCMD in flight\n");
1677                 wake_up(&trans_pcie->wait_command_queue);
1678         } else {
1679                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1680                 if (trans_pcie->opmode_down)
1681                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1682         }
1683 }
1684
1685 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
1686 {
1687         struct iwl_trans *trans = dev_id;
1688         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1689         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1690         u32 inta = 0;
1691         u32 handled = 0;
1692
1693         lock_map_acquire(&trans->sync_cmd_lockdep_map);
1694
1695         spin_lock(&trans_pcie->irq_lock);
1696
1697         /* dram interrupt table not set yet,
1698          * use legacy interrupt.
1699          */
1700         if (likely(trans_pcie->use_ict))
1701                 inta = iwl_pcie_int_cause_ict(trans);
1702         else
1703                 inta = iwl_pcie_int_cause_non_ict(trans);
1704
1705         if (iwl_have_debug_level(IWL_DL_ISR)) {
1706                 IWL_DEBUG_ISR(trans,
1707                               "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
1708                               inta, trans_pcie->inta_mask,
1709                               iwl_read32(trans, CSR_INT_MASK),
1710                               iwl_read32(trans, CSR_FH_INT_STATUS));
1711                 if (inta & (~trans_pcie->inta_mask))
1712                         IWL_DEBUG_ISR(trans,
1713                                       "We got a masked interrupt (0x%08x)\n",
1714                                       inta & (~trans_pcie->inta_mask));
1715         }
1716
1717         inta &= trans_pcie->inta_mask;
1718
1719         /*
1720          * Ignore interrupt if there's nothing in NIC to service.
1721          * This may be due to IRQ shared with another device,
1722          * or due to sporadic interrupts thrown from our NIC.
1723          */
1724         if (unlikely(!inta)) {
1725                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1726                 /*
1727                  * Re-enable interrupts here since we don't
1728                  * have anything to service
1729                  */
1730                 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1731                         _iwl_enable_interrupts(trans);
1732                 spin_unlock(&trans_pcie->irq_lock);
1733                 lock_map_release(&trans->sync_cmd_lockdep_map);
1734                 return IRQ_NONE;
1735         }
1736
1737         if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1738                 /*
1739                  * Hardware disappeared. It might have
1740                  * already raised an interrupt.
1741                  */
1742                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1743                 spin_unlock(&trans_pcie->irq_lock);
1744                 goto out;
1745         }
1746
1747         /* Ack/clear/reset pending uCode interrupts.
1748          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1749          */
1750         /* There is a hardware bug in the interrupt mask function that some
1751          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1752          * they are disabled in the CSR_INT_MASK register. Furthermore the
1753          * ICT interrupt handling mechanism has another bug that might cause
1754          * these unmasked interrupts fail to be detected. We workaround the
1755          * hardware bugs here by ACKing all the possible interrupts so that
1756          * interrupt coalescing can still be achieved.
1757          */
1758         iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
1759
1760         if (iwl_have_debug_level(IWL_DL_ISR))
1761                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
1762                               inta, iwl_read32(trans, CSR_INT_MASK));
1763
1764         spin_unlock(&trans_pcie->irq_lock);
1765
1766         /* Now service all interrupt bits discovered above. */
1767         if (inta & CSR_INT_BIT_HW_ERR) {
1768                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
1769
1770                 /* Tell the device to stop sending interrupts */
1771                 iwl_disable_interrupts(trans);
1772
1773                 isr_stats->hw++;
1774                 iwl_pcie_irq_handle_error(trans);
1775
1776                 handled |= CSR_INT_BIT_HW_ERR;
1777
1778                 goto out;
1779         }
1780
1781         /* NIC fires this, but we don't use it, redundant with WAKEUP */
1782         if (inta & CSR_INT_BIT_SCD) {
1783                 IWL_DEBUG_ISR(trans,
1784                               "Scheduler finished to transmit the frame/frames.\n");
1785                 isr_stats->sch++;
1786         }
1787
1788         /* Alive notification via Rx interrupt will do the real work */
1789         if (inta & CSR_INT_BIT_ALIVE) {
1790                 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1791                 isr_stats->alive++;
1792                 if (trans->cfg->gen2) {
1793                         /*
1794                          * We can restock, since firmware configured
1795                          * the RFH
1796                          */
1797                         iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
1798                 }
1799
1800                 handled |= CSR_INT_BIT_ALIVE;
1801         }
1802
1803         /* Safely ignore these bits for debug checks below */
1804         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1805
1806         /* HW RF KILL switch toggled */
1807         if (inta & CSR_INT_BIT_RF_KILL) {
1808                 iwl_pcie_handle_rfkill_irq(trans);
1809                 handled |= CSR_INT_BIT_RF_KILL;
1810         }
1811
1812         /* Chip got too hot and stopped itself */
1813         if (inta & CSR_INT_BIT_CT_KILL) {
1814                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1815                 isr_stats->ctkill++;
1816                 handled |= CSR_INT_BIT_CT_KILL;
1817         }
1818
1819         /* Error detected by uCode */
1820         if (inta & CSR_INT_BIT_SW_ERR) {
1821                 IWL_ERR(trans, "Microcode SW error detected. "
1822                         " Restarting 0x%X.\n", inta);
1823                 isr_stats->sw++;
1824                 iwl_pcie_irq_handle_error(trans);
1825                 handled |= CSR_INT_BIT_SW_ERR;
1826         }
1827
1828         /* uCode wakes up after power-down sleep */
1829         if (inta & CSR_INT_BIT_WAKEUP) {
1830                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1831                 iwl_pcie_rxq_check_wrptr(trans);
1832                 iwl_pcie_txq_check_wrptrs(trans);
1833
1834                 isr_stats->wakeup++;
1835
1836                 handled |= CSR_INT_BIT_WAKEUP;
1837         }
1838
1839         /* All uCode command responses, including Tx command responses,
1840          * Rx "responses" (frame-received notification), and other
1841          * notifications from uCode come through here*/
1842         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1843                     CSR_INT_BIT_RX_PERIODIC)) {
1844                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1845                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1846                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1847                         iwl_write32(trans, CSR_FH_INT_STATUS,
1848                                         CSR_FH_INT_RX_MASK);
1849                 }
1850                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1851                         handled |= CSR_INT_BIT_RX_PERIODIC;
1852                         iwl_write32(trans,
1853                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1854                 }
1855                 /* Sending RX interrupt require many steps to be done in the
1856                  * the device:
1857                  * 1- write interrupt to current index in ICT table.
1858                  * 2- dma RX frame.
1859                  * 3- update RX shared data to indicate last write index.
1860                  * 4- send interrupt.
1861                  * This could lead to RX race, driver could receive RX interrupt
1862                  * but the shared data changes does not reflect this;
1863                  * periodic interrupt will detect any dangling Rx activity.
1864                  */
1865
1866                 /* Disable periodic interrupt; we use it as just a one-shot. */
1867                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1868                             CSR_INT_PERIODIC_DIS);
1869
1870                 /*
1871                  * Enable periodic interrupt in 8 msec only if we received
1872                  * real RX interrupt (instead of just periodic int), to catch
1873                  * any dangling Rx interrupt.  If it was just the periodic
1874                  * interrupt, there was no dangling Rx activity, and no need
1875                  * to extend the periodic interrupt; one-shot is enough.
1876                  */
1877                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1878                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
1879                                    CSR_INT_PERIODIC_ENA);
1880
1881                 isr_stats->rx++;
1882
1883                 local_bh_disable();
1884                 iwl_pcie_rx_handle(trans, 0);
1885                 local_bh_enable();
1886         }
1887
1888         /* This "Tx" DMA channel is used only for loading uCode */
1889         if (inta & CSR_INT_BIT_FH_TX) {
1890                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1891                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1892                 isr_stats->tx++;
1893                 handled |= CSR_INT_BIT_FH_TX;
1894                 /* Wake up uCode load routine, now that load is complete */
1895                 trans_pcie->ucode_write_complete = true;
1896                 wake_up(&trans_pcie->ucode_write_waitq);
1897         }
1898
1899         if (inta & ~handled) {
1900                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1901                 isr_stats->unhandled++;
1902         }
1903
1904         if (inta & ~(trans_pcie->inta_mask)) {
1905                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1906                          inta & ~trans_pcie->inta_mask);
1907         }
1908
1909         spin_lock(&trans_pcie->irq_lock);
1910         /* only Re-enable all interrupt if disabled by irq */
1911         if (test_bit(STATUS_INT_ENABLED, &trans->status))
1912                 _iwl_enable_interrupts(trans);
1913         /* we are loading the firmware, enable FH_TX interrupt only */
1914         else if (handled & CSR_INT_BIT_FH_TX)
1915                 iwl_enable_fw_load_int(trans);
1916         /* Re-enable RF_KILL if it occurred */
1917         else if (handled & CSR_INT_BIT_RF_KILL)
1918                 iwl_enable_rfkill_int(trans);
1919         /* Re-enable the ALIVE / Rx interrupt if it occurred */
1920         else if (handled & (CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX))
1921                 iwl_enable_fw_load_int_ctx_info(trans);
1922         spin_unlock(&trans_pcie->irq_lock);
1923
1924 out:
1925         lock_map_release(&trans->sync_cmd_lockdep_map);
1926         return IRQ_HANDLED;
1927 }
1928
1929 /******************************************************************************
1930  *
1931  * ICT functions
1932  *
1933  ******************************************************************************/
1934
1935 /* Free dram table */
1936 void iwl_pcie_free_ict(struct iwl_trans *trans)
1937 {
1938         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1939
1940         if (trans_pcie->ict_tbl) {
1941                 dma_free_coherent(trans->dev, ICT_SIZE,
1942                                   trans_pcie->ict_tbl,
1943                                   trans_pcie->ict_tbl_dma);
1944                 trans_pcie->ict_tbl = NULL;
1945                 trans_pcie->ict_tbl_dma = 0;
1946         }
1947 }
1948
1949 /*
1950  * allocate dram shared table, it is an aligned memory
1951  * block of ICT_SIZE.
1952  * also reset all data related to ICT table interrupt.
1953  */
1954 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
1955 {
1956         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1957
1958         trans_pcie->ict_tbl =
1959                 dma_zalloc_coherent(trans->dev, ICT_SIZE,
1960                                    &trans_pcie->ict_tbl_dma,
1961                                    GFP_KERNEL);
1962         if (!trans_pcie->ict_tbl)
1963                 return -ENOMEM;
1964
1965         /* just an API sanity check ... it is guaranteed to be aligned */
1966         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1967                 iwl_pcie_free_ict(trans);
1968                 return -EINVAL;
1969         }
1970
1971         return 0;
1972 }
1973
1974 /* Device is going up inform it about using ICT interrupt table,
1975  * also we need to tell the driver to start using ICT interrupt.
1976  */
1977 void iwl_pcie_reset_ict(struct iwl_trans *trans)
1978 {
1979         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1980         u32 val;
1981
1982         if (!trans_pcie->ict_tbl)
1983                 return;
1984
1985         spin_lock(&trans_pcie->irq_lock);
1986         _iwl_disable_interrupts(trans);
1987
1988         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1989
1990         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1991
1992         val |= CSR_DRAM_INT_TBL_ENABLE |
1993                CSR_DRAM_INIT_TBL_WRAP_CHECK |
1994                CSR_DRAM_INIT_TBL_WRITE_POINTER;
1995
1996         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1997
1998         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1999         trans_pcie->use_ict = true;
2000         trans_pcie->ict_index = 0;
2001         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
2002         _iwl_enable_interrupts(trans);
2003         spin_unlock(&trans_pcie->irq_lock);
2004 }
2005
2006 /* Device is going down disable ict interrupt usage */
2007 void iwl_pcie_disable_ict(struct iwl_trans *trans)
2008 {
2009         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2010
2011         spin_lock(&trans_pcie->irq_lock);
2012         trans_pcie->use_ict = false;
2013         spin_unlock(&trans_pcie->irq_lock);
2014 }
2015
2016 irqreturn_t iwl_pcie_isr(int irq, void *data)
2017 {
2018         struct iwl_trans *trans = data;
2019
2020         if (!trans)
2021                 return IRQ_NONE;
2022
2023         /* Disable (but don't clear!) interrupts here to avoid
2024          * back-to-back ISRs and sporadic interrupts from our NIC.
2025          * If we have something to service, the tasklet will re-enable ints.
2026          * If we *don't* have something, we'll re-enable before leaving here.
2027          */
2028         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
2029
2030         return IRQ_WAKE_THREAD;
2031 }
2032
2033 irqreturn_t iwl_pcie_msix_isr(int irq, void *data)
2034 {
2035         return IRQ_WAKE_THREAD;
2036 }
2037
2038 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)
2039 {
2040         struct msix_entry *entry = dev_id;
2041         struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
2042         struct iwl_trans *trans = trans_pcie->trans;
2043         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2044         u32 inta_fh, inta_hw;
2045
2046         lock_map_acquire(&trans->sync_cmd_lockdep_map);
2047
2048         spin_lock(&trans_pcie->irq_lock);
2049         inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
2050         inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
2051         /*
2052          * Clear causes registers to avoid being handling the same cause.
2053          */
2054         iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh);
2055         iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
2056         spin_unlock(&trans_pcie->irq_lock);
2057
2058         trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw);
2059
2060         if (unlikely(!(inta_fh | inta_hw))) {
2061                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
2062                 lock_map_release(&trans->sync_cmd_lockdep_map);
2063                 return IRQ_NONE;
2064         }
2065
2066         if (iwl_have_debug_level(IWL_DL_ISR)) {
2067                 IWL_DEBUG_ISR(trans,
2068                               "ISR inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
2069                               inta_fh, trans_pcie->fh_mask,
2070                               iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD));
2071                 if (inta_fh & ~trans_pcie->fh_mask)
2072                         IWL_DEBUG_ISR(trans,
2073                                       "We got a masked interrupt (0x%08x)\n",
2074                                       inta_fh & ~trans_pcie->fh_mask);
2075         }
2076
2077         inta_fh &= trans_pcie->fh_mask;
2078
2079         if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) &&
2080             inta_fh & MSIX_FH_INT_CAUSES_Q0) {
2081                 local_bh_disable();
2082                 iwl_pcie_rx_handle(trans, 0);
2083                 local_bh_enable();
2084         }
2085
2086         if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) &&
2087             inta_fh & MSIX_FH_INT_CAUSES_Q1) {
2088                 local_bh_disable();
2089                 iwl_pcie_rx_handle(trans, 1);
2090                 local_bh_enable();
2091         }
2092
2093         /* This "Tx" DMA channel is used only for loading uCode */
2094         if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) {
2095                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
2096                 isr_stats->tx++;
2097                 /*
2098                  * Wake up uCode load routine,
2099                  * now that load is complete
2100                  */
2101                 trans_pcie->ucode_write_complete = true;
2102                 wake_up(&trans_pcie->ucode_write_waitq);
2103         }
2104
2105         /* Error detected by uCode */
2106         if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) ||
2107             (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR) ||
2108             (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR_V2)) {
2109                 IWL_ERR(trans,
2110                         "Microcode SW error detected. Restarting 0x%X.\n",
2111                         inta_fh);
2112                 isr_stats->sw++;
2113                 iwl_pcie_irq_handle_error(trans);
2114         }
2115
2116         /* After checking FH register check HW register */
2117         if (iwl_have_debug_level(IWL_DL_ISR)) {
2118                 IWL_DEBUG_ISR(trans,
2119                               "ISR inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
2120                               inta_hw, trans_pcie->hw_mask,
2121                               iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD));
2122                 if (inta_hw & ~trans_pcie->hw_mask)
2123                         IWL_DEBUG_ISR(trans,
2124                                       "We got a masked interrupt 0x%08x\n",
2125                                       inta_hw & ~trans_pcie->hw_mask);
2126         }
2127
2128         inta_hw &= trans_pcie->hw_mask;
2129
2130         /* Alive notification via Rx interrupt will do the real work */
2131         if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) {
2132                 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
2133                 isr_stats->alive++;
2134                 if (trans->cfg->gen2) {
2135                         /* We can restock, since firmware configured the RFH */
2136                         iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
2137                 }
2138         }
2139
2140         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560 &&
2141             inta_hw & MSIX_HW_INT_CAUSES_REG_IPC) {
2142                 /* Reflect IML transfer status */
2143                 int res = iwl_read32(trans, CSR_IML_RESP_ADDR);
2144
2145                 IWL_DEBUG_ISR(trans, "IML transfer status: %d\n", res);
2146                 if (res == IWL_IMAGE_RESP_FAIL) {
2147                         isr_stats->sw++;
2148                         iwl_pcie_irq_handle_error(trans);
2149                 }
2150         } else if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) {
2151                 /* uCode wakes up after power-down sleep */
2152                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
2153                 iwl_pcie_rxq_check_wrptr(trans);
2154                 iwl_pcie_txq_check_wrptrs(trans);
2155
2156                 isr_stats->wakeup++;
2157         }
2158
2159         /* Chip got too hot and stopped itself */
2160         if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) {
2161                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
2162                 isr_stats->ctkill++;
2163         }
2164
2165         /* HW RF KILL switch toggled */
2166         if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL)
2167                 iwl_pcie_handle_rfkill_irq(trans);
2168
2169         if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) {
2170                 IWL_ERR(trans,
2171                         "Hardware error detected. Restarting.\n");
2172
2173                 isr_stats->hw++;
2174                 iwl_pcie_irq_handle_error(trans);
2175         }
2176
2177         iwl_pcie_clear_irq(trans, entry);
2178
2179         lock_map_release(&trans->sync_cmd_lockdep_map);
2180
2181         return IRQ_HANDLED;
2182 }