1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
7 #ifndef __iwl_trans_h__
8 #define __iwl_trans_h__
10 #include <linux/ieee80211.h>
11 #include <linux/mm.h> /* for page_address */
12 #include <linux/lockdep.h>
13 #include <linux/kernel.h>
15 #include "iwl-debug.h"
16 #include "iwl-config.h"
18 #include "iwl-op-mode.h"
19 #include <linux/firmware.h>
20 #include "fw/api/cmdhdr.h"
21 #include "fw/api/txq.h"
22 #include "fw/api/dbg-tlv.h"
23 #include "iwl-dbg-tlv.h"
26 * DOC: Transport layer - what is it ?
28 * The transport layer is the layer that deals with the HW directly. It provides
29 * an abstraction of the underlying HW to the upper layer. The transport layer
30 * doesn't provide any policy, algorithm or anything of this kind, but only
31 * mechanisms to make the HW do something. It is not completely stateless but
33 * We will have an implementation for each different supported bus.
37 * DOC: Life cycle of the transport layer
39 * The transport layer has a very precise life cycle.
41 * 1) A helper function is called during the module initialization and
42 * registers the bus driver's ops with the transport's alloc function.
43 * 2) Bus's probe calls to the transport layer's allocation functions.
44 * Of course this function is bus specific.
45 * 3) This allocation functions will spawn the upper layer which will
48 * 4) At some point (i.e. mac80211's start call), the op_mode will call
49 * the following sequence:
53 * 5) Then when finished (or reset):
56 * 6) Eventually, the free function will be called.
59 #define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON
61 #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */
62 #define FH_RSCSR_FRAME_INVALID 0x55550000
63 #define FH_RSCSR_FRAME_ALIGN 0x40
64 #define FH_RSCSR_RPA_EN BIT(25)
65 #define FH_RSCSR_RADA_EN BIT(26)
66 #define FH_RSCSR_RXQ_POS 16
67 #define FH_RSCSR_RXQ_MASK 0x3F0000
69 struct iwl_rx_packet {
71 * The first 4 bytes of the RX frame header contain both the RX frame
72 * size and some flags.
74 * 31: flag flush RB request
75 * 30: flag ignore TC (terminal counter) request
76 * 29: flag fast IRQ request
82 * 22: Checksum enabled
85 * 13-00: RX frame size
88 struct iwl_cmd_header hdr;
92 static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt)
94 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
97 static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt)
99 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr);
103 * enum CMD_MODE - how to send the host commands ?
105 * @CMD_ASYNC: Return right away and don't wait for the response
106 * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of
107 * the response. The caller needs to call iwl_free_resp when done.
108 * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be
109 * called after this command completes. Valid only with CMD_ASYNC.
110 * @CMD_SEND_IN_D3: Allow the command to be sent in D3 mode, relevant to
111 * SUSPEND and RESUME commands. We are in D3 mode when we set
112 * trans->system_pm_mode to IWL_PLAT_PM_MODE_D3.
116 CMD_WANT_SKB = BIT(1),
117 CMD_SEND_IN_RFKILL = BIT(2),
118 CMD_WANT_ASYNC_CALLBACK = BIT(3),
119 CMD_SEND_IN_D3 = BIT(4),
122 #define DEF_CMD_PAYLOAD_SIZE 320
125 * struct iwl_device_cmd
127 * For allocation of the command and tx queues, this establishes the overall
128 * size of the largest command we send to uCode, except for commands that
129 * aren't fully copied and use other TFD space.
131 struct iwl_device_cmd {
134 struct iwl_cmd_header hdr; /* uCode API */
135 u8 payload[DEF_CMD_PAYLOAD_SIZE];
138 struct iwl_cmd_header_wide hdr_wide;
139 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE -
140 sizeof(struct iwl_cmd_header_wide) +
141 sizeof(struct iwl_cmd_header)];
147 * struct iwl_device_tx_cmd - buffer for TX command
149 * @payload: the payload placeholder
151 * The actual structure is sized dynamically according to need.
153 struct iwl_device_tx_cmd {
154 struct iwl_cmd_header hdr;
158 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
161 * number of transfer buffers (fragments) per transmit frame descriptor;
162 * this is just the driver's idea, the hardware supports 20
164 #define IWL_MAX_CMD_TBS_PER_TFD 2
166 /* We need 2 entries for the TX command and header, and another one might
167 * be needed for potential data in the SKB's head. The remaining ones can
170 #define IWL_TRANS_MAX_FRAGS(trans) ((trans)->txqs.tfd.max_tbs - 3)
173 * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command
175 * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's
176 * ring. The transport layer doesn't map the command's buffer to DMA, but
177 * rather copies it to a previously allocated DMA buffer. This flag tells
178 * the transport layer not to copy the command, but to map the existing
179 * buffer (that is passed in) instead. This saves the memcpy and allows
180 * commands that are bigger than the fixed buffer to be submitted.
181 * Note that a TFD entry after a NOCOPY one cannot be a normal copied one.
182 * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this
183 * chunk internally and free it again after the command completes. This
184 * can (currently) be used only once per command.
185 * Note that a TFD entry after a DUP one cannot be a normal copied one.
187 enum iwl_hcmd_dataflag {
188 IWL_HCMD_DFL_NOCOPY = BIT(0),
189 IWL_HCMD_DFL_DUP = BIT(1),
192 enum iwl_error_event_table_status {
193 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0),
194 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1),
195 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2),
196 IWL_ERROR_EVENT_TABLE_TCM1 = BIT(3),
197 IWL_ERROR_EVENT_TABLE_TCM2 = BIT(4),
198 IWL_ERROR_EVENT_TABLE_RCM1 = BIT(5),
199 IWL_ERROR_EVENT_TABLE_RCM2 = BIT(6),
203 * struct iwl_host_cmd - Host command to the uCode
205 * @data: array of chunks that composes the data of the host command
206 * @resp_pkt: response packet, if %CMD_WANT_SKB was set
207 * @_rx_page_order: (internally used to free response packet)
208 * @_rx_page_addr: (internally used to free response packet)
209 * @flags: can be CMD_*
210 * @len: array of the lengths of the chunks in data
211 * @dataflags: IWL_HCMD_DFL_*
212 * @id: command id of the host command, for wide commands encoding the
213 * version and group as well
215 struct iwl_host_cmd {
216 const void *data[IWL_MAX_CMD_TBS_PER_TFD];
217 struct iwl_rx_packet *resp_pkt;
218 unsigned long _rx_page_addr;
223 u16 len[IWL_MAX_CMD_TBS_PER_TFD];
224 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD];
227 static inline void iwl_free_resp(struct iwl_host_cmd *cmd)
229 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order);
232 struct iwl_rx_cmd_buffer {
237 unsigned int truesize;
240 static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r)
242 return (void *)((unsigned long)page_address(r->_page) + r->_offset);
245 static inline int rxb_offset(struct iwl_rx_cmd_buffer *r)
250 static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r)
252 r->_page_stolen = true;
257 static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r)
259 __free_pages(r->_page, r->_rx_page_order);
262 #define MAX_NO_RECLAIM_CMDS 6
264 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
267 * Maximum number of HW queues the transport layer
270 #define IWL_MAX_HW_QUEUES 32
271 #define IWL_MAX_TVQM_QUEUES 512
273 #define IWL_MAX_TID_COUNT 8
274 #define IWL_MGMT_TID 15
275 #define IWL_FRAME_LIMIT 64
276 #define IWL_MAX_RX_HW_QUEUES 16
277 #define IWL_9000_MAX_RX_HW_QUEUES 6
280 * enum iwl_wowlan_status - WoWLAN image/device status
281 * @IWL_D3_STATUS_ALIVE: firmware is still running after resume
282 * @IWL_D3_STATUS_RESET: device was reset while suspended
290 * enum iwl_trans_status: transport status flags
291 * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed
292 * @STATUS_DEVICE_ENABLED: APM is enabled
293 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)
294 * @STATUS_INT_ENABLED: interrupts are enabled
295 * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch
296 * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode
297 * @STATUS_FW_ERROR: the fw is in error state
298 * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands
300 * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent
301 * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation
302 * @STATUS_SUPPRESS_CMD_ERROR_ONCE: suppress "FW error in SYNC CMD" once,
305 enum iwl_trans_status {
306 STATUS_SYNC_HCMD_ACTIVE,
307 STATUS_DEVICE_ENABLED,
311 STATUS_RFKILL_OPMODE,
313 STATUS_TRANS_GOING_IDLE,
316 STATUS_SUPPRESS_CMD_ERROR_ONCE,
320 iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size)
324 return get_order(2 * 1024);
326 return get_order(4 * 1024);
328 return get_order(8 * 1024);
330 return get_order(16 * 1024);
338 iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size)
355 struct iwl_hcmd_names {
357 const char *const cmd_name;
360 #define HCMD_NAME(x) \
361 { .cmd_id = x, .cmd_name = #x }
363 struct iwl_hcmd_arr {
364 const struct iwl_hcmd_names *arr;
368 #define HCMD_ARR(x) \
369 { .arr = x, .size = ARRAY_SIZE(x) }
372 * struct iwl_dump_sanitize_ops - dump sanitization operations
373 * @frob_txf: Scrub the TX FIFO data
374 * @frob_hcmd: Scrub a host command, the %hcmd pointer is to the header
375 * but that might be short or long (&struct iwl_cmd_header or
376 * &struct iwl_cmd_header_wide)
377 * @frob_mem: Scrub memory data
379 struct iwl_dump_sanitize_ops {
380 void (*frob_txf)(void *ctx, void *buf, size_t buflen);
381 void (*frob_hcmd)(void *ctx, void *hcmd, size_t buflen);
382 void (*frob_mem)(void *ctx, u32 mem_addr, void *mem, size_t buflen);
386 * struct iwl_trans_config - transport configuration
388 * @op_mode: pointer to the upper layer.
389 * @cmd_queue: the index of the command queue.
390 * Must be set before start_fw.
391 * @cmd_fifo: the fifo for host commands
392 * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue.
393 * @no_reclaim_cmds: Some devices erroneously don't set the
394 * SEQ_RX_FRAME bit on some notifications, this is the
395 * list of such notifications to filter. Max length is
396 * %MAX_NO_RECLAIM_CMDS.
397 * @n_no_reclaim_cmds: # of commands in list
398 * @rx_buf_size: RX buffer size needed for A-MSDUs
399 * if unset 4k will be the RX buffer size
400 * @bc_table_dword: set to true if the BC table expects the byte count to be
401 * in DWORD (as opposed to bytes)
402 * @scd_set_active: should the transport configure the SCD for HCMD queue
403 * @command_groups: array of command groups, each member is an array of the
404 * commands in the group; for debugging only
405 * @command_groups_size: number of command groups, to avoid illegal access
406 * @cb_data_offs: offset inside skb->cb to store transport data at, must have
407 * space for at least two pointers
408 * @fw_reset_handshake: firmware supports reset flow handshake
409 * @queue_alloc_cmd_ver: queue allocation command version, set to 0
410 * for using the older SCD_QUEUE_CFG, set to the version of
411 * SCD_QUEUE_CONFIG_CMD otherwise.
413 struct iwl_trans_config {
414 struct iwl_op_mode *op_mode;
418 unsigned int cmd_q_wdg_timeout;
419 const u8 *no_reclaim_cmds;
420 unsigned int n_no_reclaim_cmds;
422 enum iwl_amsdu_size rx_buf_size;
425 const struct iwl_hcmd_arr *command_groups;
426 int command_groups_size;
429 bool fw_reset_handshake;
430 u8 queue_alloc_cmd_ver;
433 struct iwl_trans_dump_data {
440 struct iwl_trans_txq_scd_cfg {
449 * struct iwl_trans_rxq_dma_data - RX queue DMA data
450 * @fr_bd_cb: DMA address of free BD cyclic buffer
451 * @fr_bd_wid: Initial write index of the free BD cyclic buffer
452 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr
453 * @ur_bd_cb: DMA address of used BD cyclic buffer
455 struct iwl_trans_rxq_dma_data {
462 /* maximal number of DRAM MAP entries supported by FW */
463 #define IPC_DRAM_MAP_ENTRY_NUM_MAX 64
466 * struct iwl_pnvm_image - contains info about the parsed pnvm image
467 * @chunks: array of pointers to pnvm payloads and their sizes
468 * @n_chunks: the number of the pnvm payloads.
469 * @version: the version of the loaded PNVM image
471 struct iwl_pnvm_image {
475 } chunks[IPC_DRAM_MAP_ENTRY_NUM_MAX];
481 * struct iwl_trans_ops - transport specific operations
483 * All the handlers MUST be implemented
485 * @start_hw: starts the HW. From that point on, the HW can send interrupts.
487 * @op_mode_leave: Turn off the HW RF kill indication if on
489 * @start_fw: allocates and inits all the resources for the transport
490 * layer. Also kick a fw image.
492 * @fw_alive: called when the fw sends alive notification. If the fw provides
493 * the SCD base address in SRAM, then provide it here, or 0 otherwise.
495 * @stop_device: stops the whole device (embedded CPU put to reset) and stops
496 * the HW. From that point on, the HW will be stopped but will still issue
497 * an interrupt if the HW RF kill switch is triggered.
498 * This callback must do the right thing and not crash even if %start_hw()
499 * was called but not &start_fw(). May sleep.
500 * @d3_suspend: put the device into the correct mode for WoWLAN during
501 * suspend. This is optional, if not implemented WoWLAN will not be
502 * supported. This callback may sleep.
503 * @d3_resume: resume the device after WoWLAN, enabling the opmode to
504 * talk to the WoWLAN image to get its status. This is optional, if not
505 * implemented WoWLAN will not be supported. This callback may sleep.
506 * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted.
507 * If RFkill is asserted in the middle of a SYNC host command, it must
508 * return -ERFKILL straight away.
509 * May sleep only if CMD_ASYNC is not set
510 * @tx: send an skb. The transport relies on the op_mode to zero the
511 * the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all
512 * the CSUM will be taken care of (TCP CSUM and IP header in case of
513 * IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP
514 * header if it is IPv4.
516 * @reclaim: free packet until ssn. Returns a list of freed packets.
518 * @txq_enable: setup a queue. To setup an AC queue, use the
519 * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before
520 * this one. The op_mode must not configure the HCMD queue. The scheduler
521 * configuration may be %NULL, in which case the hardware will not be
522 * configured. If true is returned, the operation mode needs to increment
523 * the sequence number of the packets routed to this queue because of a
524 * hardware scheduler bug. May sleep.
525 * @txq_disable: de-configure a Tx queue to send AMPDUs
527 * @txq_set_shared_mode: change Tx queue shared/unshared marking
528 * @wait_tx_queues_empty: wait until tx queues are empty. May sleep.
529 * @wait_txq_empty: wait until specific tx queue is empty. May sleep.
530 * @freeze_txq_timer: prevents the timer of the queue from firing until the
531 * queue is set to awake. Must be atomic.
532 * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note
533 * that the transport needs to refcount the calls since this function
534 * will be called several times with block = true, and then the queues
535 * need to be unblocked only after the same number of calls with
537 * @write8: write a u8 to a register at offset ofs from the BAR
538 * @write32: write a u32 to a register at offset ofs from the BAR
539 * @read32: read a u32 register at offset ofs from the BAR
540 * @read_prph: read a DWORD from a periphery register
541 * @write_prph: write a DWORD to a periphery register
542 * @read_mem: read device's SRAM in DWORD
543 * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory
545 * @read_config32: read a u32 value from the device's config space at
547 * @configure: configure parameters required by the transport layer from
548 * the op_mode. May be called several times before start_fw, can't be
550 * @set_pmi: set the power pmi state
551 * @grab_nic_access: wake the NIC to be able to access non-HBUS regs.
552 * Sleeping is not allowed between grab_nic_access and
553 * release_nic_access.
554 * @release_nic_access: let the NIC go to sleep. The "flags" parameter
555 * must be the same one that was sent before to the grab_nic_access.
556 * @set_bits_mask - set SRAM register according to value and mask.
557 * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last
558 * TX'ed commands and similar. The buffer will be vfree'd by the caller.
559 * Note that the transport must fill in the proper file headers.
560 * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup
561 * of the trans debugfs
562 * @load_pnvm: save the pnvm data in DRAM
563 * @set_pnvm: set the pnvm data in the prph scratch buffer, inside the
565 * @load_reduce_power: copy reduce power table to the corresponding DRAM memory
566 * @set_reduce_power: set reduce power table addresses in the sratch buffer
567 * @interrupts: disable/enable interrupts to transport
569 struct iwl_trans_ops {
571 int (*start_hw)(struct iwl_trans *iwl_trans);
572 void (*op_mode_leave)(struct iwl_trans *iwl_trans);
573 int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw,
575 void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr);
576 void (*stop_device)(struct iwl_trans *trans);
578 int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset);
579 int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status,
580 bool test, bool reset);
582 int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
584 int (*tx)(struct iwl_trans *trans, struct sk_buff *skb,
585 struct iwl_device_tx_cmd *dev_cmd, int queue);
586 void (*reclaim)(struct iwl_trans *trans, int queue, int ssn,
587 struct sk_buff_head *skbs);
589 void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr);
591 bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn,
592 const struct iwl_trans_txq_scd_cfg *cfg,
593 unsigned int queue_wdg_timeout);
594 void (*txq_disable)(struct iwl_trans *trans, int queue,
596 /* 22000 functions */
597 int (*txq_alloc)(struct iwl_trans *trans, u32 flags,
598 u32 sta_mask, u8 tid,
599 int size, unsigned int queue_wdg_timeout);
600 void (*txq_free)(struct iwl_trans *trans, int queue);
601 int (*rxq_dma_data)(struct iwl_trans *trans, int queue,
602 struct iwl_trans_rxq_dma_data *data);
604 void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id,
607 int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm);
608 int (*wait_txq_empty)(struct iwl_trans *trans, int queue);
609 void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs,
611 void (*block_txq_ptrs)(struct iwl_trans *trans, bool block);
613 void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val);
614 void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val);
615 u32 (*read32)(struct iwl_trans *trans, u32 ofs);
616 u32 (*read_prph)(struct iwl_trans *trans, u32 ofs);
617 void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val);
618 int (*read_mem)(struct iwl_trans *trans, u32 addr,
619 void *buf, int dwords);
620 int (*write_mem)(struct iwl_trans *trans, u32 addr,
621 const void *buf, int dwords);
622 int (*read_config32)(struct iwl_trans *trans, u32 ofs, u32 *val);
623 void (*configure)(struct iwl_trans *trans,
624 const struct iwl_trans_config *trans_cfg);
625 void (*set_pmi)(struct iwl_trans *trans, bool state);
626 int (*sw_reset)(struct iwl_trans *trans, bool retake_ownership);
627 bool (*grab_nic_access)(struct iwl_trans *trans);
628 void (*release_nic_access)(struct iwl_trans *trans);
629 void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask,
632 struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans,
634 const struct iwl_dump_sanitize_ops *sanitize_ops,
636 void (*debugfs_cleanup)(struct iwl_trans *trans);
637 void (*sync_nmi)(struct iwl_trans *trans);
638 int (*load_pnvm)(struct iwl_trans *trans,
639 const struct iwl_pnvm_image *pnvm_payloads,
640 const struct iwl_ucode_capabilities *capa);
641 void (*set_pnvm)(struct iwl_trans *trans,
642 const struct iwl_ucode_capabilities *capa);
643 int (*load_reduce_power)(struct iwl_trans *trans,
644 const struct iwl_pnvm_image *payloads,
645 const struct iwl_ucode_capabilities *capa);
646 void (*set_reduce_power)(struct iwl_trans *trans,
647 const struct iwl_ucode_capabilities *capa);
649 void (*interrupts)(struct iwl_trans *trans, bool enable);
650 int (*imr_dma_data)(struct iwl_trans *trans,
651 u32 dst_addr, u64 src_addr,
657 * enum iwl_trans_state - state of the transport layer
659 * @IWL_TRANS_NO_FW: firmware wasn't started yet, or crashed
660 * @IWL_TRANS_FW_STARTED: FW was started, but not alive yet
661 * @IWL_TRANS_FW_ALIVE: FW has sent an alive response
663 enum iwl_trans_state {
665 IWL_TRANS_FW_STARTED,
670 * DOC: Platform power management
672 * In system-wide power management the entire platform goes into a low
673 * power state (e.g. idle or suspend to RAM) at the same time and the
674 * device is configured as a wakeup source for the entire platform.
675 * This is usually triggered by userspace activity (e.g. the user
676 * presses the suspend button or a power management daemon decides to
677 * put the platform in low power mode). The device's behavior in this
678 * mode is dictated by the wake-on-WLAN configuration.
680 * The terms used for the device's behavior are as follows:
682 * - D0: the device is fully powered and the host is awake;
683 * - D3: the device is in low power mode and only reacts to
684 * specific events (e.g. magic-packet received or scan
687 * These terms reflect the power modes in the firmware and are not to
688 * be confused with the physical device power state.
692 * enum iwl_plat_pm_mode - platform power management mode
694 * This enumeration describes the device's platform power management
695 * behavior when in system-wide suspend (i.e WoWLAN).
697 * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this
698 * device. In system-wide suspend mode, it means that the all
699 * connections will be closed automatically by mac80211 before
700 * the platform is suspended.
701 * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN).
703 enum iwl_plat_pm_mode {
704 IWL_PLAT_PM_MODE_DISABLED,
709 * enum iwl_ini_cfg_state
710 * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given
711 * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded
712 * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs
713 * are corrupted. The rest of the debug TLVs will still be used
715 enum iwl_ini_cfg_state {
716 IWL_INI_CFG_STATE_NOT_LOADED,
717 IWL_INI_CFG_STATE_LOADED,
718 IWL_INI_CFG_STATE_CORRUPTED,
721 /* Max time to wait for nmi interrupt */
722 #define IWL_TRANS_NMI_TIMEOUT (HZ / 4)
725 * struct iwl_dram_data
726 * @physical: page phy pointer
727 * @block: pointer to the allocated block/page
728 * @size: size of the block/page
730 struct iwl_dram_data {
737 * @drams: array of several DRAM areas that contains the pnvm and power
738 * reduction table payloads.
739 * @n_regions: number of DRAM regions that were allocated
740 * @prph_scratch_mem_desc: points to a structure allocated in dram,
741 * designed to show FW where all the payloads are.
743 struct iwl_dram_regions {
744 struct iwl_dram_data drams[IPC_DRAM_MAP_ENTRY_NUM_MAX];
745 struct iwl_dram_data prph_scratch_mem_desc;
750 * struct iwl_fw_mon - fw monitor per allocation id
751 * @num_frags: number of fragments
752 * @frags: an array of DRAM buffer fragments
756 struct iwl_dram_data *frags;
760 * struct iwl_self_init_dram - dram data used by self init process
761 * @fw: lmac and umac dram data
762 * @fw_cnt: total number of items in array
763 * @paging: paging dram data
764 * @paging_cnt: total number of items in array
766 struct iwl_self_init_dram {
767 struct iwl_dram_data *fw;
769 struct iwl_dram_data *paging;
774 * struct iwl_imr_data - imr dram data used during debug process
775 * @imr_enable: imr enable status received from fw
776 * @imr_size: imr dram size received from fw
777 * @sram_addr: sram address from debug tlv
778 * @sram_size: sram size from debug tlv
779 * @imr2sram_remainbyte`: size remained after each dma transfer
780 * @imr_curr_addr: current dst address used during dma transfer
781 * @imr_base_addr: imr address received from fw
783 struct iwl_imr_data {
788 u32 imr2sram_remainbyte;
790 __le64 imr_base_addr;
793 #define IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES 32
796 * struct iwl_pc_data - program counter details
798 * @pc_address: cpu program counter
801 u8 pc_name[IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES];
806 * struct iwl_trans_debug - transport debug related data
808 * @n_dest_reg: num of reg_ops in %dbg_dest_tlv
809 * @rec_on: true iff there is a fw debug recording currently active
810 * @dest_tlv: points to the destination TLV for debug
811 * @conf_tlv: array of pointers to configuration TLVs for debug
812 * @trigger_tlv: array of pointers to triggers TLVs for debug
813 * @lmac_error_event_table: addrs of lmacs error tables
814 * @umac_error_event_table: addr of umac error table
815 * @tcm_error_event_table: address(es) of TCM error table(s)
816 * @rcm_error_event_table: address(es) of RCM error table(s)
817 * @error_event_table_tlv_status: bitmap that indicates what error table
818 * pointers was recevied via TLV. uses enum &iwl_error_event_table_status
819 * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state
820 * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state
821 * @fw_mon_cfg: debug buffer allocation configuration
822 * @fw_mon_ini: DRAM buffer fragments per allocation id
823 * @fw_mon: DRAM buffer for firmware monitor
824 * @hw_error: equals true if hw error interrupt was received from the FW
825 * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location
826 * @active_regions: active regions
827 * @debug_info_tlv_list: list of debug info TLVs
828 * @time_point: array of debug time points
829 * @periodic_trig_list: periodic triggers list
830 * @domains_bitmap: bitmap of active domains other than &IWL_FW_INI_DOMAIN_ALWAYS_ON
831 * @ucode_preset: preset based on ucode
832 * @dump_file_name_ext: dump file name extension
833 * @dump_file_name_ext_valid: dump file name extension if valid or not
834 * @num_pc: number of program counter for cpu
835 * @pc_data: details of the program counter
837 struct iwl_trans_debug {
841 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv;
842 const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX];
843 struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv;
845 u32 lmac_error_event_table[2];
846 u32 umac_error_event_table;
847 u32 tcm_error_event_table[2];
848 u32 rcm_error_event_table[2];
849 unsigned int error_event_table_tlv_status;
851 enum iwl_ini_cfg_state internal_ini_cfg;
852 enum iwl_ini_cfg_state external_ini_cfg;
854 struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM];
855 struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM];
857 struct iwl_dram_data fw_mon;
860 enum iwl_fw_ini_buffer_location ini_dest;
862 u64 unsupported_region_msk;
863 struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID];
864 struct list_head debug_info_tlv_list;
865 struct iwl_dbg_tlv_time_point_data
866 time_point[IWL_FW_INI_TIME_POINT_NUM];
867 struct list_head periodic_trig_list;
871 bool restart_required;
873 struct iwl_imr_data imr_data;
874 u8 dump_file_name_ext[IWL_FW_INI_MAX_NAME];
875 bool dump_file_name_ext_valid;
877 struct iwl_pc_data *pc_data;
886 struct iwl_cmd_meta {
887 /* only for SYNC commands, iff the reply skb is wanted */
888 struct iwl_host_cmd *source;
894 * The FH will write back to the first TB only, so we need to copy some data
895 * into the buffer regardless of whether it should be mapped or not.
896 * This indicates how big the first TB must be to include the scratch buffer
897 * and the assigned PN.
898 * Since PN location is 8 bytes at offset 12, it's 20 now.
899 * If we make it bigger then allocations will be bigger and copy slower, so
900 * that's probably not useful.
902 #define IWL_FIRST_TB_SIZE 20
903 #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64)
905 struct iwl_pcie_txq_entry {
908 /* buffer to free after command completes */
909 const void *free_buf;
910 struct iwl_cmd_meta meta;
913 struct iwl_pcie_first_tb_buf {
914 u8 buf[IWL_FIRST_TB_SIZE_ALIGN];
918 * struct iwl_txq - Tx Queue for DMA
919 * @q: generic Rx/Tx queue descriptor
920 * @tfds: transmit frame descriptors (DMA memory)
921 * @first_tb_bufs: start of command headers, including scratch buffers, for
922 * the writeback -- this is DMA memory and an array holding one buffer
923 * for each command on the queue
924 * @first_tb_dma: DMA address for the first_tb_bufs start
925 * @entries: transmit entries (driver state)
927 * @stuck_timer: timer that fires if queue gets stuck
928 * @trans: pointer back to transport (for timer)
929 * @need_update: indicates need to update read/write index
930 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID
931 * @wd_timeout: queue watchdog timeout (jiffies) - per queue
932 * @frozen: tx stuck queue timer is frozen
933 * @frozen_expiry_remainder: remember how long until the timer fires
934 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport)
935 * @write_ptr: 1-st empty entry (index) host_w
936 * @read_ptr: last used entry (index) host_r
937 * @dma_addr: physical addr for BD's
938 * @n_window: safe queue window
940 * @low_mark: low watermark, resume queue if free space more than this
941 * @high_mark: high watermark, stop queue if free space less than this
943 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
944 * descriptors) and required locking structures.
946 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware
947 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless
948 * there might be HW changes in the future). For the normal TX
949 * queues, n_window, which is the size of the software queue data
950 * is also 256; however, for the command queue, n_window is only
951 * 32 since we don't need so many commands pending. Since the HW
952 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256.
953 * This means that we end up with the following:
954 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
955 * SW entries: | 0 | ... | 31 |
956 * where N is a number between 0 and 7. This means that the SW
957 * data is a window overlayed over the HW queue.
961 struct iwl_pcie_first_tb_buf *first_tb_bufs;
962 dma_addr_t first_tb_dma;
963 struct iwl_pcie_txq_entry *entries;
964 /* lock for syncing changes on the queue */
966 unsigned long frozen_expiry_remainder;
967 struct timer_list stuck_timer;
968 struct iwl_trans *trans;
973 unsigned long wd_timeout;
974 struct sk_buff_head overflow_q;
975 struct iwl_dma_ptr bc_tbl;
989 * struct iwl_trans_txqs - transport tx queues data
991 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
992 * @page_offs: offset from skb->cb to mac header page pointer
993 * @dev_cmd_offs: offset from skb->cb to iwl_device_tx_cmd pointer
994 * @queue_used - bit mask of used queues
995 * @queue_stopped - bit mask of stopped queues
996 * @scd_bc_tbls: gen1 pointer to the byte count table of the scheduler
997 * @queue_alloc_cmd_ver: queue allocation command version
999 struct iwl_trans_txqs {
1000 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
1001 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
1002 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES];
1003 struct dma_pool *bc_pool;
1005 bool bc_table_dword;
1008 struct iwl_tso_hdr_page __percpu *tso_hdr_page;
1013 unsigned int wdg_timeout;
1022 struct iwl_dma_ptr scd_bc_tbls;
1024 u8 queue_alloc_cmd_ver;
1028 * struct iwl_trans - transport common data
1030 * @csme_own - true if we couldn't get ownership on the device
1031 * @ops - pointer to iwl_trans_ops
1032 * @op_mode - pointer to the op_mode
1033 * @trans_cfg: the trans-specific configuration part
1034 * @cfg - pointer to the configuration
1035 * @drv - pointer to iwl_drv
1036 * @status: a bit-mask of transport status flags
1037 * @dev - pointer to struct device * that represents the device
1038 * @max_skb_frags: maximum number of fragments an SKB can have when transmitted.
1039 * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported.
1040 * @hw_rf_id a u32 with the device RF ID
1041 * @hw_crf_id a u32 with the device CRF ID
1042 * @hw_wfpm_id a u32 with the device wfpm ID
1043 * @hw_id: a u32 with the ID of the device / sub-device.
1044 * Set during transport allocation.
1045 * @hw_id_str: a string with info about HW ID. Set during transport allocation.
1046 * @hw_rev_step: The mac step of the HW
1047 * @pm_support: set to true in start_hw if link pm is supported
1048 * @ltr_enabled: set to true if the LTR is enabled
1049 * @fail_to_parse_pnvm_image: set to true if pnvm parsing failed
1050 * @failed_to_load_reduce_power_image: set to true if pnvm loading failed
1051 * @wide_cmd_header: true when ucode supports wide command header format
1052 * @wait_command_queue: wait queue for sync commands
1053 * @num_rx_queues: number of RX queues allocated by the transport;
1054 * the transport must set this before calling iwl_drv_start()
1055 * @iml_len: the length of the image loader
1056 * @iml: a pointer to the image loader itself
1057 * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only.
1058 * The user should use iwl_trans_{alloc,free}_tx_cmd.
1059 * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before
1060 * starting the firmware, used for tracing
1061 * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the
1062 * start of the 802.11 header in the @rx_mpdu_cmd
1063 * @dflt_pwr_limit: default power limit fetched from the platform (ACPI)
1064 * @system_pm_mode: the system-wide power management mode in use.
1065 * This mode is set dynamically, depending on the WoWLAN values
1066 * configured from the userspace at runtime.
1067 * @iwl_trans_txqs: transport tx queues data.
1068 * @mbx_addr_0_step: step address data 0
1069 * @mbx_addr_1_step: step address data 1
1070 * @pcie_link_speed: current PCIe link speed (%PCI_EXP_LNKSTA_CLS_*),
1071 * only valid for discrete (not integrated) NICs
1075 const struct iwl_trans_ops *ops;
1076 struct iwl_op_mode *op_mode;
1077 const struct iwl_cfg_trans_params *trans_cfg;
1078 const struct iwl_cfg *cfg;
1079 struct iwl_drv *drv;
1080 enum iwl_trans_state state;
1081 unsigned long status;
1095 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;
1100 u8 fail_to_parse_pnvm_image:1;
1101 u8 reduce_power_loaded:1;
1102 u8 failed_to_load_reduce_power_image:1;
1104 const struct iwl_hcmd_arr *command_groups;
1105 int command_groups_size;
1106 bool wide_cmd_header;
1108 wait_queue_head_t wait_command_queue;
1114 /* The following fields are internal only */
1115 struct kmem_cache *dev_cmd_pool;
1116 char dev_cmd_pool_name[50];
1118 struct dentry *dbgfs_dir;
1120 #ifdef CONFIG_LOCKDEP
1121 struct lockdep_map sync_cmd_lockdep_map;
1124 struct iwl_trans_debug dbg;
1125 struct iwl_self_init_dram init_dram;
1127 enum iwl_plat_pm_mode system_pm_mode;
1130 struct iwl_trans_txqs txqs;
1131 u32 mbx_addr_0_step;
1132 u32 mbx_addr_1_step;
1136 /* pointer to trans specific struct */
1137 /*Ensure that this pointer will always be aligned to sizeof pointer */
1138 char trans_specific[] __aligned(sizeof(void *));
1141 const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id);
1142 int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans);
1144 static inline void iwl_trans_configure(struct iwl_trans *trans,
1145 const struct iwl_trans_config *trans_cfg)
1147 trans->op_mode = trans_cfg->op_mode;
1149 trans->ops->configure(trans, trans_cfg);
1150 WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg));
1153 static inline int iwl_trans_start_hw(struct iwl_trans *trans)
1157 return trans->ops->start_hw(trans);
1160 static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans)
1164 if (trans->ops->op_mode_leave)
1165 trans->ops->op_mode_leave(trans);
1167 trans->op_mode = NULL;
1169 trans->state = IWL_TRANS_NO_FW;
1172 static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1176 trans->state = IWL_TRANS_FW_ALIVE;
1178 trans->ops->fw_alive(trans, scd_addr);
1181 static inline int iwl_trans_start_fw(struct iwl_trans *trans,
1182 const struct fw_img *fw,
1189 WARN_ON_ONCE(!trans->rx_mpdu_cmd);
1191 clear_bit(STATUS_FW_ERROR, &trans->status);
1192 ret = trans->ops->start_fw(trans, fw, run_in_rfkill);
1194 trans->state = IWL_TRANS_FW_STARTED;
1199 static inline void iwl_trans_stop_device(struct iwl_trans *trans)
1203 trans->ops->stop_device(trans);
1205 trans->state = IWL_TRANS_NO_FW;
1208 static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test,
1212 if (!trans->ops->d3_suspend)
1215 return trans->ops->d3_suspend(trans, test, reset);
1218 static inline int iwl_trans_d3_resume(struct iwl_trans *trans,
1219 enum iwl_d3_status *status,
1220 bool test, bool reset)
1223 if (!trans->ops->d3_resume)
1226 return trans->ops->d3_resume(trans, status, test, reset);
1229 static inline struct iwl_trans_dump_data *
1230 iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask,
1231 const struct iwl_dump_sanitize_ops *sanitize_ops,
1234 if (!trans->ops->dump_data)
1236 return trans->ops->dump_data(trans, dump_mask,
1237 sanitize_ops, sanitize_ctx);
1240 static inline struct iwl_device_tx_cmd *
1241 iwl_trans_alloc_tx_cmd(struct iwl_trans *trans)
1243 return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC);
1246 int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
1248 static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans,
1249 struct iwl_device_tx_cmd *dev_cmd)
1251 kmem_cache_free(trans->dev_cmd_pool, dev_cmd);
1254 static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb,
1255 struct iwl_device_tx_cmd *dev_cmd, int queue)
1257 if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status)))
1260 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1261 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1265 return trans->ops->tx(trans, skb, dev_cmd, queue);
1268 static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue,
1269 int ssn, struct sk_buff_head *skbs)
1271 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1272 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1276 trans->ops->reclaim(trans, queue, ssn, skbs);
1279 static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue,
1282 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1283 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1287 trans->ops->set_q_ptrs(trans, queue, ptr);
1290 static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue,
1293 trans->ops->txq_disable(trans, queue, configure_scd);
1297 iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn,
1298 const struct iwl_trans_txq_scd_cfg *cfg,
1299 unsigned int queue_wdg_timeout)
1303 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1304 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1308 return trans->ops->txq_enable(trans, queue, ssn,
1309 cfg, queue_wdg_timeout);
1313 iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue,
1314 struct iwl_trans_rxq_dma_data *data)
1316 if (WARN_ON_ONCE(!trans->ops->rxq_dma_data))
1319 return trans->ops->rxq_dma_data(trans, queue, data);
1323 iwl_trans_txq_free(struct iwl_trans *trans, int queue)
1325 if (WARN_ON_ONCE(!trans->ops->txq_free))
1328 trans->ops->txq_free(trans, queue);
1332 iwl_trans_txq_alloc(struct iwl_trans *trans,
1333 u32 flags, u32 sta_mask, u8 tid,
1334 int size, unsigned int wdg_timeout)
1338 if (WARN_ON_ONCE(!trans->ops->txq_alloc))
1341 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1342 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1346 return trans->ops->txq_alloc(trans, flags, sta_mask, tid,
1350 static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans,
1351 int queue, bool shared_mode)
1353 if (trans->ops->txq_set_shared_mode)
1354 trans->ops->txq_set_shared_mode(trans, queue, shared_mode);
1357 static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue,
1358 int fifo, int sta_id, int tid,
1359 int frame_limit, u16 ssn,
1360 unsigned int queue_wdg_timeout)
1362 struct iwl_trans_txq_scd_cfg cfg = {
1366 .frame_limit = frame_limit,
1367 .aggregate = sta_id >= 0,
1370 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout);
1374 void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo,
1375 unsigned int queue_wdg_timeout)
1377 struct iwl_trans_txq_scd_cfg cfg = {
1380 .tid = IWL_MAX_TID_COUNT,
1381 .frame_limit = IWL_FRAME_LIMIT,
1385 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout);
1388 static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans,
1392 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1393 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1397 if (trans->ops->freeze_txq_timer)
1398 trans->ops->freeze_txq_timer(trans, txqs, freeze);
1401 static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans,
1404 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1405 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1409 if (trans->ops->block_txq_ptrs)
1410 trans->ops->block_txq_ptrs(trans, block);
1413 static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans,
1416 if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty))
1419 /* No need to wait if the firmware is not alive */
1420 if (trans->state != IWL_TRANS_FW_ALIVE) {
1421 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1425 return trans->ops->wait_tx_queues_empty(trans, txqs);
1428 static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue)
1430 if (WARN_ON_ONCE(!trans->ops->wait_txq_empty))
1433 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1434 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1438 return trans->ops->wait_txq_empty(trans, queue);
1441 static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1443 trans->ops->write8(trans, ofs, val);
1446 static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1448 trans->ops->write32(trans, ofs, val);
1451 static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs)
1453 return trans->ops->read32(trans, ofs);
1456 static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs)
1458 return trans->ops->read_prph(trans, ofs);
1461 static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs,
1464 return trans->ops->write_prph(trans, ofs, val);
1467 static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr,
1468 void *buf, int dwords)
1470 return trans->ops->read_mem(trans, addr, buf, dwords);
1473 #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \
1475 if (__builtin_constant_p(bufsize)) \
1476 BUILD_BUG_ON((bufsize) % sizeof(u32)); \
1477 iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\
1480 static inline int iwl_trans_write_imr_mem(struct iwl_trans *trans,
1481 u32 dst_addr, u64 src_addr,
1484 if (trans->ops->imr_dma_data)
1485 return trans->ops->imr_dma_data(trans, dst_addr, src_addr, byte_cnt);
1489 static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr)
1493 if (iwl_trans_read_mem(trans, addr, &value, 1))
1499 static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr,
1500 const void *buf, int dwords)
1502 return trans->ops->write_mem(trans, addr, buf, dwords);
1505 static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr,
1508 return iwl_trans_write_mem(trans, addr, &val, 1);
1511 static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state)
1513 if (trans->ops->set_pmi)
1514 trans->ops->set_pmi(trans, state);
1517 static inline int iwl_trans_sw_reset(struct iwl_trans *trans,
1518 bool retake_ownership)
1520 if (trans->ops->sw_reset)
1521 return trans->ops->sw_reset(trans, retake_ownership);
1526 iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value)
1528 trans->ops->set_bits_mask(trans, reg, mask, value);
1531 #define iwl_trans_grab_nic_access(trans) \
1532 __cond_lock(nic_access, \
1533 likely((trans)->ops->grab_nic_access(trans)))
1535 static inline void __releases(nic_access)
1536 iwl_trans_release_nic_access(struct iwl_trans *trans)
1538 trans->ops->release_nic_access(trans);
1539 __release(nic_access);
1542 static inline void iwl_trans_fw_error(struct iwl_trans *trans, bool sync)
1544 if (WARN_ON_ONCE(!trans->op_mode))
1547 /* prevent double restarts due to the same erroneous FW */
1548 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) {
1549 iwl_op_mode_nic_error(trans->op_mode, sync);
1550 trans->state = IWL_TRANS_NO_FW;
1554 static inline bool iwl_trans_fw_running(struct iwl_trans *trans)
1556 return trans->state == IWL_TRANS_FW_ALIVE;
1559 static inline void iwl_trans_sync_nmi(struct iwl_trans *trans)
1561 if (trans->ops->sync_nmi)
1562 trans->ops->sync_nmi(trans);
1565 void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr,
1568 static inline int iwl_trans_load_pnvm(struct iwl_trans *trans,
1569 const struct iwl_pnvm_image *pnvm_data,
1570 const struct iwl_ucode_capabilities *capa)
1572 return trans->ops->load_pnvm(trans, pnvm_data, capa);
1575 static inline void iwl_trans_set_pnvm(struct iwl_trans *trans,
1576 const struct iwl_ucode_capabilities *capa)
1578 if (trans->ops->set_pnvm)
1579 trans->ops->set_pnvm(trans, capa);
1582 static inline int iwl_trans_load_reduce_power
1583 (struct iwl_trans *trans,
1584 const struct iwl_pnvm_image *payloads,
1585 const struct iwl_ucode_capabilities *capa)
1587 return trans->ops->load_reduce_power(trans, payloads, capa);
1591 iwl_trans_set_reduce_power(struct iwl_trans *trans,
1592 const struct iwl_ucode_capabilities *capa)
1594 if (trans->ops->set_reduce_power)
1595 trans->ops->set_reduce_power(trans, capa);
1598 static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans)
1600 return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED ||
1601 trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED;
1604 static inline void iwl_trans_interrupts(struct iwl_trans *trans, bool enable)
1606 if (trans->ops->interrupts)
1607 trans->ops->interrupts(trans, enable);
1610 /*****************************************************
1611 * transport helper functions
1612 *****************************************************/
1613 struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
1615 const struct iwl_trans_ops *ops,
1616 const struct iwl_cfg_trans_params *cfg_trans);
1617 int iwl_trans_init(struct iwl_trans *trans);
1618 void iwl_trans_free(struct iwl_trans *trans);
1620 static inline bool iwl_trans_is_hw_error_value(u32 val)
1622 return ((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50);
1625 /*****************************************************
1626 * driver (transport) register/unregister functions
1627 ******************************************************/
1628 int __must_check iwl_pci_register_driver(void);
1629 void iwl_pci_unregister_driver(void);
1630 void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan);
1632 #endif /* __iwl_trans_h__ */