1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2015-2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2023 Intel Corporation
6 #include <linux/module.h>
7 #include <linux/stringify.h>
8 #include "iwl-config.h"
10 #include "fw/api/txq.h"
12 /* Highest firmware API version supported */
13 #define IWL_22000_UCODE_API_MAX 81
14 #define IWL_22500_UCODE_API_MAX 77
16 /* Lowest firmware API version supported */
17 #define IWL_22000_UCODE_API_MIN 39
20 #define IWL_22000_NVM_VERSION 0x0a1d
22 /* Memory offsets and lengths */
23 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */
24 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */
25 #define IWL_22000_DCCM2_OFFSET 0x880000
26 #define IWL_22000_DCCM2_LEN 0x8000
27 #define IWL_22000_SMEM_OFFSET 0x400000
28 #define IWL_22000_SMEM_LEN 0xD0000
30 #define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-"
31 #define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-"
32 #define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-"
33 #define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-"
34 #define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-"
35 #define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-"
36 #define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-"
37 #define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-"
38 #define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-"
39 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-"
40 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-"
41 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-"
42 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-"
43 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-"
44 #define IWL_SO_A_MR_A_FW_PRE "iwlwifi-so-a0-mr-a0-"
45 #define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-"
46 #define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-"
47 #define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-"
48 #define IWL_SNJ_A_JF_B_FW_PRE "iwlwifi-SoSnj-a0-jf-b0-"
49 #define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0-"
50 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-"
51 #define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0-"
52 #define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-"
53 #define IWL_MA_A_FM_A_FW_PRE "iwlwifi-ma-a0-fm-a0-"
54 #define IWL_MA_B_HR_B_FW_PRE "iwlwifi-ma-b0-hr-b0-"
55 #define IWL_MA_B_GF_A_FW_PRE "iwlwifi-ma-b0-gf-a0-"
56 #define IWL_MA_B_GF4_A_FW_PRE "iwlwifi-ma-b0-gf4-a0-"
57 #define IWL_MA_B_MR_A_FW_PRE "iwlwifi-ma-b0-mr-a0-"
58 #define IWL_MA_B_FM_A_FW_PRE "iwlwifi-ma-b0-fm-a0-"
59 #define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-"
60 #define IWL_BZ_A_HR_A_FW_PRE "iwlwifi-bz-a0-hr-b0-"
61 #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0-"
62 #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0-"
63 #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0-"
64 #define IWL_BZ_A_MR_A_FW_PRE "iwlwifi-bz-a0-mr-a0-"
65 #define IWL_BZ_A_FM_A_FW_PRE "iwlwifi-bz-a0-fm-a0-"
66 #define IWL_BZ_A_FM4_A_FW_PRE "iwlwifi-bz-a0-fm4-a0-"
67 #define IWL_BZ_A_FM_B_FW_PRE "iwlwifi-bz-a0-fm-b0-"
68 #define IWL_BZ_A_FM_C_FW_PRE "iwlwifi-bz-a0-fm-c0-"
69 #define IWL_BZ_A_FM4_B_FW_PRE "iwlwifi-bz-a0-fm4-b0-"
70 #define IWL_BZ_B_GF_A_FW_PRE "iwlwifi-bz-b0-gf-a0-"
71 #define IWL_BZ_B_GF4_A_FW_PRE "iwlwifi-bz-b0-gf4-a0-"
72 #define IWL_BZ_B_FM_B_FW_PRE "iwlwifi-bz-b0-fm-b0-"
73 #define IWL_BZ_B_FM4_B_FW_PRE "iwlwifi-bz-b0-fm4-b0-"
74 #define IWL_GL_A_FM_A_FW_PRE "iwlwifi-gl-a0-fm-a0-"
75 #define IWL_GL_B_FM_B_FW_PRE "iwlwifi-gl-b0-fm-b0-"
76 #define IWL_GL_C_FM_C_FW_PRE "iwlwifi-gl-c0-fm-c0-"
78 #define IWL_BZ_Z_GF_A_FW_PRE "iwlwifi-bz-z0-gf-a0-"
79 #define IWL_BNJ_A_FM_A_FW_PRE "iwlwifi-BzBnj-a0-fm-a0-"
80 #define IWL_BNJ_A_FM4_A_FW_PRE "iwlwifi-BzBnj-a0-fm4-a0-"
81 #define IWL_BNJ_B_FM4_B_FW_PRE "iwlwifi-BzBnj-b0-fm4-b0-"
82 #define IWL_BNJ_A_GF_A_FW_PRE "iwlwifi-BzBnj-a0-gf-a0-"
83 #define IWL_BNJ_B_GF_A_FW_PRE "iwlwifi-BzBnj-b0-gf-a0-"
84 #define IWL_BNJ_A_GF4_A_FW_PRE "iwlwifi-BzBnj-a0-gf4-a0-"
85 #define IWL_BNJ_B_GF4_A_FW_PRE "iwlwifi-BzBnj-b0-gf4-a0-"
86 #define IWL_BNJ_A_HR_A_FW_PRE "iwlwifi-BzBnj-a0-hr-b0-"
87 #define IWL_BNJ_A_HR_B_FW_PRE "iwlwifi-BzBnj-a0-hr-b0-"
88 #define IWL_BNJ_B_HR_A_FW_PRE "iwlwifi-BzBnj-b0-hr-b0-"
89 #define IWL_BNJ_B_HR_B_FW_PRE "iwlwifi-BzBnj-b0-hr-b0-"
90 #define IWL_BNJ_B_FM_B_FW_PRE "iwlwifi-BzBnj-b0-fm-b0-"
93 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \
94 IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode"
95 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \
96 IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode"
97 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \
98 IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
99 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \
100 IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode"
101 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \
102 IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode"
103 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \
104 IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode"
105 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \
106 IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode"
107 #define IWL_CC_A_MODULE_FIRMWARE(api) \
108 IWL_CC_A_FW_PRE __stringify(api) ".ucode"
109 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \
110 IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode"
111 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \
112 IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode"
113 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \
114 IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode"
115 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \
116 IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode"
117 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \
118 IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
119 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \
120 IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
121 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \
122 IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
123 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \
124 IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode"
125 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \
126 IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode"
127 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \
128 IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode"
129 #define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api) \
130 IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode"
131 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \
132 IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode"
133 #define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api) \
134 IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode"
135 #define IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(api) \
136 IWL_MA_B_HR_B_FW_PRE __stringify(api) ".ucode"
137 #define IWL_MA_B_GF_A_FW_MODULE_FIRMWARE(api) \
138 IWL_MA_B_GF_A_FW_PRE __stringify(api) ".ucode"
139 #define IWL_MA_B_GF4_A_FW_MODULE_FIRMWARE(api) \
140 IWL_MA_B_GF4_A_FW_PRE __stringify(api) ".ucode"
141 #define IWL_MA_B_MR_A_FW_MODULE_FIRMWARE(api) \
142 IWL_MA_B_MR_A_FW_PRE __stringify(api) ".ucode"
143 #define IWL_MA_B_FM_A_FW_MODULE_FIRMWARE(api) \
144 IWL_MA_B_FM_A_FW_PRE __stringify(api) ".ucode"
145 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \
146 IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode"
147 #define IWL_BZ_A_HR_A_MODULE_FIRMWARE(api) \
148 IWL_BZ_A_HR_A_FW_PRE __stringify(api) ".ucode"
149 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \
150 IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
151 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \
152 IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode"
153 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \
154 IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
155 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \
156 IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode"
157 #define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \
158 IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode"
159 #define IWL_BZ_A_FM4_A_MODULE_FIRMWARE(api) \
160 IWL_BZ_A_FM4_A_FW_PRE __stringify(api) ".ucode"
161 #define IWL_BZ_A_FM_B_MODULE_FIRMWARE(api) \
162 IWL_BZ_A_FM_B_FW_PRE __stringify(api) ".ucode"
163 #define IWL_BZ_A_FM_C_MODULE_FIRMWARE(api) \
164 IWL_BZ_A_FM_C_FW_PRE __stringify(api) ".ucode"
165 #define IWL_BZ_A_FM4_B_MODULE_FIRMWARE(api) \
166 IWL_BZ_A_FM4_B_FW_PRE __stringify(api) ".ucode"
167 #define IWL_BZ_B_GF_A_MODULE_FIRMWARE(api) \
168 IWL_BZ_B_GF_A_FW_PRE __stringify(api) ".ucode"
169 #define IWL_BZ_B_GF4_A_MODULE_FIRMWARE(api) \
170 IWL_BZ_B_GF4_A_FW_PRE __stringify(api) ".ucode"
171 #define IWL_BZ_B_FM_B_MODULE_FIRMWARE(api) \
172 IWL_BZ_B_FM_B_FW_PRE __stringify(api) ".ucode"
173 #define IWL_BZ_B_FM4_B_MODULE_FIRMWARE(api) \
174 IWL_BZ_B_FM4_B_FW_PRE __stringify(api) ".ucode"
175 #define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \
176 IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode"
177 #define IWL_GL_B_FM_B_MODULE_FIRMWARE(api) \
178 IWL_GL_B_FM_B_FW_PRE __stringify(api) ".ucode"
179 #define IWL_GL_C_FM_C_MODULE_FIRMWARE(api) \
180 IWL_GL_C_FM_C_FW_PRE __stringify(api) ".ucode"
181 #define IWL_BNJ_A_FM_A_MODULE_FIRMWARE(api) \
182 IWL_BNJ_A_FM_A_FW_PRE __stringify(api) ".ucode"
183 #define IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(api) \
184 IWL_BNJ_A_FM4_A_FW_PRE __stringify(api) ".ucode"
185 #define IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(api) \
186 IWL_BNJ_B_FM4_B_FW_PRE __stringify(api) ".ucode"
187 #define IWL_BNJ_A_GF_A_MODULE_FIRMWARE(api) \
188 IWL_BNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
189 #define IWL_BNJ_B_GF_A_MODULE_FIRMWARE(api) \
190 IWL_BNJ_B_GF_A_FW_PRE __stringify(api) ".ucode"
191 #define IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(api) \
192 IWL_BNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
193 #define IWL_BNJ_B_GF4_A_MODULE_FIRMWARE(api) \
194 IWL_BNJ_B_GF4_A_FW_PRE __stringify(api) ".ucode"
196 #define IWL_BNJ_A_HR_A_MODULE_FIRMWARE(api) \
197 IWL_BNJ_A_HR_A_FW_PRE __stringify(api) ".ucode"
198 #define IWL_BNJ_A_HR_B_MODULE_FIRMWARE(api) \
199 IWL_BNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
200 #define IWL_BNJ_B_HR_A_MODULE_FIRMWARE(api) \
201 IWL_BNJ_B_HR_A_FW_PRE __stringify(api) ".ucode"
202 #define IWL_BNJ_B_HR_B_MODULE_FIRMWARE(api) \
203 IWL_BNJ_B_HR_B_FW_PRE __stringify(api) ".ucode"
204 #define IWL_BNJ_B_FM_B_MODULE_FIRMWARE(api) \
205 IWL_BNJ_B_FM_B_FW_PRE __stringify(api) ".ucode"
207 static const struct iwl_base_params iwl_22000_base_params = {
208 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
209 .num_of_queues = 512,
210 .max_tfd_queue_size = 256,
211 .shadow_ram_support = true,
212 .led_compensation = 57,
213 .wd_timeout = IWL_LONG_WD_TIMEOUT,
214 .max_event_log_size = 512,
215 .shadow_reg_enable = true,
216 .pcie_l1_allowed = true,
219 static const struct iwl_base_params iwl_ax210_base_params = {
220 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
221 .num_of_queues = 512,
222 .max_tfd_queue_size = 65536,
223 .shadow_ram_support = true,
224 .led_compensation = 57,
225 .wd_timeout = IWL_LONG_WD_TIMEOUT,
226 .max_event_log_size = 512,
227 .shadow_reg_enable = true,
228 .pcie_l1_allowed = true,
231 static const struct iwl_ht_params iwl_22000_ht_params = {
234 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
235 BIT(NL80211_BAND_6GHZ),
238 static const struct iwl_ht_params iwl_gl_a_ht_params = {
239 .stbc = false, /* we explicitly disable STBC for GL step A */
241 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
242 BIT(NL80211_BAND_6GHZ),
245 #define IWL_DEVICE_22000_COMMON \
246 .ucode_api_min = IWL_22000_UCODE_API_MIN, \
247 .led_mode = IWL_LED_RF_STATE, \
248 .nvm_hw_section_num = 10, \
249 .non_shared_ant = ANT_B, \
250 .dccm_offset = IWL_22000_DCCM_OFFSET, \
251 .dccm_len = IWL_22000_DCCM_LEN, \
252 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \
253 .dccm2_len = IWL_22000_DCCM2_LEN, \
254 .smem_offset = IWL_22000_SMEM_OFFSET, \
255 .smem_len = IWL_22000_SMEM_LEN, \
256 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \
257 .apmg_not_supported = true, \
258 .trans.mq_rx_supported = true, \
259 .vht_mu_mimo_supported = true, \
260 .mac_addr_from_csr = 0x380, \
261 .ht_params = &iwl_22000_ht_params, \
262 .nvm_ver = IWL_22000_NVM_VERSION, \
263 .trans.use_tfh = true, \
264 .trans.rf_id = true, \
265 .trans.gen2 = true, \
266 .nvm_type = IWL_NVM_EXT, \
267 .dbgc_supported = true, \
268 .min_umac_error_event_table = 0x400000, \
269 .d3_debug_data_base_addr = 0x401000, \
270 .d3_debug_data_length = 60 * 1024, \
273 .addr = LDBG_M2S_BUF_WPTR, \
274 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \
277 .addr = LDBG_M2S_BUF_WRAP_CNT, \
278 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \
282 #define IWL_DEVICE_22500 \
283 IWL_DEVICE_22000_COMMON, \
284 .ucode_api_max = IWL_22500_UCODE_API_MAX, \
285 .trans.device_family = IWL_DEVICE_FAMILY_22000, \
286 .trans.base_params = &iwl_22000_base_params, \
287 .gp2_reg_addr = 0xa02c68, \
290 .addr = MON_BUFF_WRPTR_VER2, \
291 .mask = 0xffffffff, \
294 .addr = MON_BUFF_CYCLE_CNT_VER2, \
295 .mask = 0xffffffff, \
299 #define IWL_DEVICE_AX210 \
300 IWL_DEVICE_22000_COMMON, \
301 .ucode_api_max = IWL_22000_UCODE_API_MAX, \
302 .trans.umac_prph_offset = 0x300000, \
303 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \
304 .trans.base_params = &iwl_ax210_base_params, \
305 .min_txq_size = 128, \
306 .gp2_reg_addr = 0xd02c68, \
307 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE, \
310 .addr = DBGC_CUR_DBGBUF_STATUS, \
311 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \
314 .addr = DBGC_DBGBUF_WRAP_AROUND, \
315 .mask = 0xffffffff, \
318 .addr = DBGC_CUR_DBGBUF_STATUS, \
319 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \
323 #define IWL_DEVICE_BZ_COMMON \
324 .ucode_api_max = IWL_22000_UCODE_API_MAX, \
325 .ucode_api_min = IWL_22000_UCODE_API_MIN, \
326 .led_mode = IWL_LED_RF_STATE, \
327 .nvm_hw_section_num = 10, \
328 .non_shared_ant = ANT_B, \
329 .dccm_offset = IWL_22000_DCCM_OFFSET, \
330 .dccm_len = IWL_22000_DCCM_LEN, \
331 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \
332 .dccm2_len = IWL_22000_DCCM2_LEN, \
333 .smem_offset = IWL_22000_SMEM_OFFSET, \
334 .smem_len = IWL_22000_SMEM_LEN, \
335 .apmg_not_supported = true, \
336 .trans.mq_rx_supported = true, \
337 .vht_mu_mimo_supported = true, \
338 .mac_addr_from_csr = 0x30, \
339 .nvm_ver = IWL_22000_NVM_VERSION, \
340 .trans.use_tfh = true, \
341 .trans.rf_id = true, \
342 .trans.gen2 = true, \
343 .nvm_type = IWL_NVM_EXT, \
344 .dbgc_supported = true, \
345 .min_umac_error_event_table = 0xD0000, \
346 .d3_debug_data_base_addr = 0x401000, \
347 .d3_debug_data_length = 60 * 1024, \
350 .addr = LDBG_M2S_BUF_WPTR, \
351 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \
354 .addr = LDBG_M2S_BUF_WRAP_CNT, \
355 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \
358 .trans.umac_prph_offset = 0x300000, \
359 .trans.device_family = IWL_DEVICE_FAMILY_BZ, \
360 .trans.base_params = &iwl_ax210_base_params, \
361 .min_txq_size = 128, \
362 .gp2_reg_addr = 0xd02c68, \
363 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \
366 .addr = DBGC_CUR_DBGBUF_STATUS, \
367 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \
370 .addr = DBGC_DBGBUF_WRAP_AROUND, \
371 .mask = 0xffffffff, \
374 .addr = DBGC_CUR_DBGBUF_STATUS, \
375 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \
380 .addr = DBGI_SRAM_FIFO_POINTERS, \
381 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \
385 #define IWL_DEVICE_BZ \
386 IWL_DEVICE_BZ_COMMON, \
387 .ht_params = &iwl_22000_ht_params
389 #define IWL_DEVICE_GL_A \
390 IWL_DEVICE_BZ_COMMON, \
391 .ht_params = &iwl_gl_a_ht_params
393 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = {
394 .mq_rx_supported = true,
398 .device_family = IWL_DEVICE_FAMILY_22000,
399 .base_params = &iwl_22000_base_params,
402 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = {
403 .mq_rx_supported = true,
407 .device_family = IWL_DEVICE_FAMILY_22000,
408 .base_params = &iwl_22000_base_params,
411 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
414 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = {
415 .mq_rx_supported = true,
419 .device_family = IWL_DEVICE_FAMILY_22000,
420 .base_params = &iwl_22000_base_params,
422 .xtal_latency = 1820,
423 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US,
426 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = {
427 .mq_rx_supported = true,
431 .device_family = IWL_DEVICE_FAMILY_22000,
432 .base_params = &iwl_22000_base_params,
434 .xtal_latency = 12000,
435 .low_latency_xtal = true,
436 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
439 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = {
440 .mq_rx_supported = true,
444 .device_family = IWL_DEVICE_FAMILY_AX210,
445 .base_params = &iwl_ax210_base_params,
446 .umac_prph_offset = 0x300000,
449 const struct iwl_cfg_trans_params iwl_so_trans_cfg = {
450 .mq_rx_supported = true,
454 .device_family = IWL_DEVICE_FAMILY_AX210,
455 .base_params = &iwl_ax210_base_params,
456 .umac_prph_offset = 0x300000,
458 /* TODO: the following values need to be checked */
460 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
463 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = {
464 .mq_rx_supported = true,
468 .device_family = IWL_DEVICE_FAMILY_AX210,
469 .base_params = &iwl_ax210_base_params,
470 .umac_prph_offset = 0x300000,
472 .low_latency_xtal = true,
473 .xtal_latency = 12000,
474 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
477 const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = {
478 .mq_rx_supported = true,
482 .device_family = IWL_DEVICE_FAMILY_AX210,
483 .base_params = &iwl_ax210_base_params,
484 .umac_prph_offset = 0x300000,
486 .low_latency_xtal = true,
487 .xtal_latency = 12000,
488 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
493 * If the device doesn't support HE, no need to have that many buffers.
494 * 22000 devices can split multiple frames into a single RB, so fewer are
495 * needed; AX210 cannot (but use smaller RBs by default) - these sizes
496 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with
497 * additional overhead to account for processing time.
499 #define IWL_NUM_RBDS_NON_HE 512
500 #define IWL_NUM_RBDS_22000_HE 2048
501 #define IWL_NUM_RBDS_AX210_HE 4096
504 * All JF radio modules are part of the 9000 series, but the MAC part
505 * looks more like 22000. That's why this device is here, but called
508 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = {
509 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
511 .num_rbds = IWL_NUM_RBDS_NON_HE,
514 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = {
515 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE,
517 .num_rbds = IWL_NUM_RBDS_NON_HE,
520 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = {
521 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE,
524 * This device doesn't support receiving BlockAck with a large bitmap
525 * so we need to restrict the size of transmitted aggregation to the
526 * HT size; mac80211 would otherwise pick the HE max (256) by default.
528 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
529 .num_rbds = IWL_NUM_RBDS_NON_HE,
532 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = {
533 .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE,
536 * This device doesn't support receiving BlockAck with a large bitmap
537 * so we need to restrict the size of transmitted aggregation to the
538 * HT size; mac80211 would otherwise pick the HE max (256) by default.
540 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
541 .num_rbds = IWL_NUM_RBDS_NON_HE,
544 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = {
545 .device_family = IWL_DEVICE_FAMILY_22000,
546 .base_params = &iwl_22000_base_params,
547 .mq_rx_supported = true,
551 .bisr_workaround = 1,
554 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = {
555 .device_family = IWL_DEVICE_FAMILY_AX210,
556 .base_params = &iwl_ax210_base_params,
557 .mq_rx_supported = true,
562 .umac_prph_offset = 0x300000
565 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = {
566 .device_family = IWL_DEVICE_FAMILY_BZ,
567 .base_params = &iwl_ax210_base_params,
568 .mq_rx_supported = true,
573 .umac_prph_offset = 0x300000,
574 .xtal_latency = 12000,
575 .low_latency_xtal = true,
576 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
579 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101";
580 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz";
581 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz";
582 const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203";
583 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz";
584 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz";
585 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz";
586 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz";
587 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz";
588 const char iwl_bz_name[] = "Intel(R) TBD Bz device";
590 const char iwl_ax200_killer_1650w_name[] =
591 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)";
592 const char iwl_ax200_killer_1650x_name[] =
593 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)";
594 const char iwl_ax201_killer_1650s_name[] =
595 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)";
596 const char iwl_ax201_killer_1650i_name[] =
597 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)";
598 const char iwl_ax210_killer_1675w_name[] =
599 "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)";
600 const char iwl_ax210_killer_1675x_name[] =
601 "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)";
602 const char iwl_ax211_killer_1675s_name[] =
603 "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)";
604 const char iwl_ax211_killer_1675i_name[] =
605 "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)";
606 const char iwl_ax411_killer_1690s_name[] =
607 "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)";
608 const char iwl_ax411_killer_1690i_name[] =
609 "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)";
611 const struct iwl_cfg iwl_qu_b0_hr1_b0 = {
612 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
615 * This device doesn't support receiving BlockAck with a large bitmap
616 * so we need to restrict the size of transmitted aggregation to the
617 * HT size; mac80211 would otherwise pick the HE max (256) by default.
619 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
620 .tx_with_siso_diversity = true,
621 .num_rbds = IWL_NUM_RBDS_22000_HE,
624 const struct iwl_cfg iwl_qu_b0_hr_b0 = {
625 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
628 * This device doesn't support receiving BlockAck with a large bitmap
629 * so we need to restrict the size of transmitted aggregation to the
630 * HT size; mac80211 would otherwise pick the HE max (256) by default.
632 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
633 .num_rbds = IWL_NUM_RBDS_22000_HE,
636 const struct iwl_cfg iwl_ax201_cfg_qu_hr = {
637 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
638 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
641 * This device doesn't support receiving BlockAck with a large bitmap
642 * so we need to restrict the size of transmitted aggregation to the
643 * HT size; mac80211 would otherwise pick the HE max (256) by default.
645 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
646 .num_rbds = IWL_NUM_RBDS_22000_HE,
649 const struct iwl_cfg iwl_qu_c0_hr1_b0 = {
650 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
653 * This device doesn't support receiving BlockAck with a large bitmap
654 * so we need to restrict the size of transmitted aggregation to the
655 * HT size; mac80211 would otherwise pick the HE max (256) by default.
657 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
658 .tx_with_siso_diversity = true,
659 .num_rbds = IWL_NUM_RBDS_22000_HE,
662 const struct iwl_cfg iwl_qu_c0_hr_b0 = {
663 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
666 * This device doesn't support receiving BlockAck with a large bitmap
667 * so we need to restrict the size of transmitted aggregation to the
668 * HT size; mac80211 would otherwise pick the HE max (256) by default.
670 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
671 .num_rbds = IWL_NUM_RBDS_22000_HE,
674 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = {
675 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
676 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
679 * This device doesn't support receiving BlockAck with a large bitmap
680 * so we need to restrict the size of transmitted aggregation to the
681 * HT size; mac80211 would otherwise pick the HE max (256) by default.
683 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
684 .num_rbds = IWL_NUM_RBDS_22000_HE,
687 const struct iwl_cfg iwl_quz_a0_hr1_b0 = {
688 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
691 * This device doesn't support receiving BlockAck with a large bitmap
692 * so we need to restrict the size of transmitted aggregation to the
693 * HT size; mac80211 would otherwise pick the HE max (256) by default.
695 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
696 .tx_with_siso_diversity = true,
697 .num_rbds = IWL_NUM_RBDS_22000_HE,
700 const struct iwl_cfg iwl_ax201_cfg_quz_hr = {
701 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
702 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
705 * This device doesn't support receiving BlockAck with a large bitmap
706 * so we need to restrict the size of transmitted aggregation to the
707 * HT size; mac80211 would otherwise pick the HE max (256) by default.
709 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
710 .num_rbds = IWL_NUM_RBDS_22000_HE,
713 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = {
714 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)",
715 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
718 * This device doesn't support receiving BlockAck with a large bitmap
719 * so we need to restrict the size of transmitted aggregation to the
720 * HT size; mac80211 would otherwise pick the HE max (256) by default.
722 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
723 .num_rbds = IWL_NUM_RBDS_22000_HE,
726 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = {
727 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)",
728 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
731 * This device doesn't support receiving BlockAck with a large bitmap
732 * so we need to restrict the size of transmitted aggregation to the
733 * HT size; mac80211 would otherwise pick the HE max (256) by default.
735 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
736 .num_rbds = IWL_NUM_RBDS_22000_HE,
739 const struct iwl_cfg iwl_ax200_cfg_cc = {
740 .fw_name_pre = IWL_CC_A_FW_PRE,
743 * This device doesn't support receiving BlockAck with a large bitmap
744 * so we need to restrict the size of transmitted aggregation to the
745 * HT size; mac80211 would otherwise pick the HE max (256) by default.
747 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
748 .num_rbds = IWL_NUM_RBDS_22000_HE,
751 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = {
752 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)",
753 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
756 * This device doesn't support receiving BlockAck with a large bitmap
757 * so we need to restrict the size of transmitted aggregation to the
758 * HT size; mac80211 would otherwise pick the HE max (256) by default.
760 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
761 .num_rbds = IWL_NUM_RBDS_22000_HE,
764 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = {
765 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)",
766 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
769 * This device doesn't support receiving BlockAck with a large bitmap
770 * so we need to restrict the size of transmitted aggregation to the
771 * HT size; mac80211 would otherwise pick the HE max (256) by default.
773 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
774 .num_rbds = IWL_NUM_RBDS_22000_HE,
777 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = {
778 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)",
779 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
782 * This device doesn't support receiving BlockAck with a large bitmap
783 * so we need to restrict the size of transmitted aggregation to the
784 * HT size; mac80211 would otherwise pick the HE max (256) by default.
786 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
787 .num_rbds = IWL_NUM_RBDS_22000_HE,
790 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = {
791 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)",
792 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
795 * This device doesn't support receiving BlockAck with a large bitmap
796 * so we need to restrict the size of transmitted aggregation to the
797 * HT size; mac80211 would otherwise pick the HE max (256) by default.
799 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
800 .num_rbds = IWL_NUM_RBDS_22000_HE,
803 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = {
804 .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE,
807 * This device doesn't support receiving BlockAck with a large bitmap
808 * so we need to restrict the size of transmitted aggregation to the
809 * HT size; mac80211 would otherwise pick the HE max (256) by default.
811 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
812 .num_rbds = IWL_NUM_RBDS_22000_HE,
815 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = {
816 .name = "Intel(R) Wireless-AC 9560 160MHz",
817 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE,
819 .num_rbds = IWL_NUM_RBDS_NON_HE,
822 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = {
823 .name = iwl_ax211_name,
824 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
825 .uhb_supported = true,
827 .num_rbds = IWL_NUM_RBDS_AX210_HE,
830 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = {
831 .name = iwl_ax211_name,
832 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
833 .uhb_supported = true,
835 .num_rbds = IWL_NUM_RBDS_AX210_HE,
836 .trans.xtal_latency = 12000,
837 .trans.low_latency_xtal = true,
840 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = {
841 .name = "Intel(R) Wi-Fi 6 AX210 160MHz",
842 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE,
843 .uhb_supported = true,
845 .num_rbds = IWL_NUM_RBDS_AX210_HE,
848 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = {
849 .name = iwl_ax411_name,
850 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
851 .uhb_supported = true,
853 .num_rbds = IWL_NUM_RBDS_AX210_HE,
856 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = {
857 .name = iwl_ax411_name,
858 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
859 .uhb_supported = true,
861 .num_rbds = IWL_NUM_RBDS_AX210_HE,
862 .trans.xtal_latency = 12000,
863 .trans.low_latency_xtal = true,
866 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = {
867 .name = iwl_ax411_name,
868 .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE,
869 .uhb_supported = true,
871 .num_rbds = IWL_NUM_RBDS_AX210_HE,
874 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = {
875 .name = iwl_ax211_name,
876 .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE,
877 .uhb_supported = true,
879 .num_rbds = IWL_NUM_RBDS_AX210_HE,
882 const struct iwl_cfg iwl_cfg_snj_hr_b0 = {
883 .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE,
884 .uhb_supported = true,
886 .num_rbds = IWL_NUM_RBDS_AX210_HE,
889 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = {
890 .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE,
891 .uhb_supported = true,
893 .num_rbds = IWL_NUM_RBDS_AX210_HE,
896 const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = {
897 .fw_name_pre = IWL_MA_A_HR_B_FW_PRE,
898 .uhb_supported = true,
900 .num_rbds = IWL_NUM_RBDS_AX210_HE,
903 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = {
904 .fw_name_pre = IWL_MA_A_GF_A_FW_PRE,
905 .uhb_supported = true,
907 .num_rbds = IWL_NUM_RBDS_AX210_HE,
910 const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = {
911 .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE,
912 .uhb_supported = true,
914 .num_rbds = IWL_NUM_RBDS_AX210_HE,
917 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = {
918 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
919 .uhb_supported = true,
921 .num_rbds = IWL_NUM_RBDS_AX210_HE,
924 const struct iwl_cfg iwl_cfg_ma_a0_ms_a0 = {
925 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
926 .uhb_supported = false,
928 .num_rbds = IWL_NUM_RBDS_AX210_HE,
931 const struct iwl_cfg iwl_cfg_ma_b0_fm_a0 = {
932 .fw_name_pre = IWL_MA_B_FM_A_FW_PRE,
933 .uhb_supported = true,
935 .num_rbds = IWL_NUM_RBDS_AX210_HE,
938 const struct iwl_cfg iwl_cfg_ma_b0_hr_b0 = {
939 .fw_name_pre = IWL_MA_B_HR_B_FW_PRE,
940 .uhb_supported = true,
942 .num_rbds = IWL_NUM_RBDS_AX210_HE,
945 const struct iwl_cfg iwl_cfg_ma_b0_gf_a0 = {
946 .fw_name_pre = IWL_MA_B_GF_A_FW_PRE,
947 .uhb_supported = true,
949 .num_rbds = IWL_NUM_RBDS_AX210_HE,
952 const struct iwl_cfg iwl_cfg_ma_b0_gf4_a0 = {
953 .fw_name_pre = IWL_MA_B_GF4_A_FW_PRE,
954 .uhb_supported = true,
956 .num_rbds = IWL_NUM_RBDS_AX210_HE,
959 const struct iwl_cfg iwl_cfg_ma_b0_mr_a0 = {
960 .fw_name_pre = IWL_MA_B_MR_A_FW_PRE,
961 .uhb_supported = true,
963 .num_rbds = IWL_NUM_RBDS_AX210_HE,
966 const struct iwl_cfg iwl_cfg_so_a0_ms_a0 = {
967 .fw_name_pre = IWL_SO_A_MR_A_FW_PRE,
968 .uhb_supported = false,
970 .num_rbds = IWL_NUM_RBDS_AX210_HE,
973 const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = {
974 .fw_name_pre = IWL_MA_A_FM_A_FW_PRE,
975 .uhb_supported = true,
977 .num_rbds = IWL_NUM_RBDS_AX210_HE,
980 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = {
981 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
982 .uhb_supported = true,
984 .num_rbds = IWL_NUM_RBDS_AX210_HE,
987 const struct iwl_cfg iwl_cfg_snj_a0_ms_a0 = {
988 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
989 .uhb_supported = false,
991 .num_rbds = IWL_NUM_RBDS_AX210_HE,
994 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = {
995 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE,
997 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1000 const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = {
1001 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
1004 * This device doesn't support receiving BlockAck with a large bitmap
1005 * so we need to restrict the size of transmitted aggregation to the
1006 * HT size; mac80211 would otherwise pick the HE max (256) by default.
1008 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
1009 .num_rbds = IWL_NUM_RBDS_22000_HE,
1012 const struct iwl_cfg iwl_cfg_bz_a0_hr_a0 = {
1013 .fw_name_pre = IWL_BZ_A_HR_A_FW_PRE,
1014 .uhb_supported = true,
1016 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1017 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1020 const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = {
1021 .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE,
1022 .uhb_supported = true,
1024 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1025 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1028 const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = {
1029 .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE,
1030 .uhb_supported = true,
1032 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1033 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1036 const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = {
1037 .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE,
1038 .uhb_supported = true,
1040 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1041 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1044 const struct iwl_cfg iwl_cfg_bz_b0_gf_a0 = {
1045 .fw_name_pre = IWL_BZ_B_GF_A_FW_PRE,
1046 .uhb_supported = true,
1048 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1049 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1052 const struct iwl_cfg iwl_cfg_bz_b0_gf4_a0 = {
1053 .fw_name_pre = IWL_BZ_B_GF4_A_FW_PRE,
1054 .uhb_supported = true,
1056 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1057 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1060 const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = {
1061 .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE,
1062 .uhb_supported = true,
1064 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1065 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1068 const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = {
1069 .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE,
1070 .uhb_supported = true,
1072 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1073 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1076 const struct iwl_cfg iwl_cfg_bz_a0_fm4_a0 = {
1077 .fw_name_pre = IWL_BZ_A_FM4_A_FW_PRE,
1078 .uhb_supported = true,
1080 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1081 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1084 const struct iwl_cfg iwl_cfg_bz_a0_fm_b0 = {
1085 .fw_name_pre = IWL_BZ_A_FM_B_FW_PRE,
1086 .uhb_supported = true,
1088 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1089 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1092 const struct iwl_cfg iwl_cfg_bz_a0_fm_c0 = {
1093 .fw_name_pre = IWL_BZ_A_FM_C_FW_PRE,
1094 .uhb_supported = true,
1096 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1097 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1100 const struct iwl_cfg iwl_cfg_bz_a0_fm4_b0 = {
1101 .fw_name_pre = IWL_BZ_A_FM4_B_FW_PRE,
1102 .uhb_supported = true,
1104 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1105 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1108 const struct iwl_cfg iwl_cfg_bz_b0_fm_b0 = {
1109 .fw_name_pre = IWL_BZ_B_FM_B_FW_PRE,
1110 .uhb_supported = true,
1112 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1113 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1116 const struct iwl_cfg iwl_cfg_bz_b0_fm4_b0 = {
1117 .fw_name_pre = IWL_BZ_B_FM4_B_FW_PRE,
1118 .uhb_supported = true,
1120 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1121 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1124 const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = {
1125 .fw_name_pre = IWL_GL_A_FM_A_FW_PRE,
1126 .uhb_supported = true,
1128 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1129 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1132 const struct iwl_cfg iwl_cfg_gl_b0_fm_b0 = {
1133 .fw_name_pre = IWL_GL_B_FM_B_FW_PRE,
1134 .uhb_supported = true,
1136 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1137 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1140 const struct iwl_cfg iwl_cfg_gl_c0_fm_c0 = {
1141 .fw_name_pre = IWL_GL_C_FM_C_FW_PRE,
1142 .uhb_supported = true,
1144 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1145 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1148 const struct iwl_cfg iwl_cfg_bz_z0_gf_a0 = {
1149 .fw_name_pre = IWL_BZ_Z_GF_A_FW_PRE,
1150 .uhb_supported = true,
1152 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1153 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1156 const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0 = {
1157 .fw_name_pre = IWL_BNJ_A_FM_A_FW_PRE,
1158 .uhb_supported = true,
1160 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1161 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1164 const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0 = {
1165 .fw_name_pre = IWL_BNJ_A_FM4_A_FW_PRE,
1166 .uhb_supported = true,
1168 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1169 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1172 const struct iwl_cfg iwl_cfg_bnj_b0_fm4_b0 = {
1173 .fw_name_pre = IWL_BNJ_B_FM4_B_FW_PRE,
1174 .uhb_supported = true,
1176 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1177 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1180 const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0 = {
1181 .fw_name_pre = IWL_BNJ_A_GF_A_FW_PRE,
1182 .uhb_supported = true,
1184 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1185 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1188 const struct iwl_cfg iwl_cfg_bnj_b0_gf_a0 = {
1189 .fw_name_pre = IWL_BNJ_B_GF_A_FW_PRE,
1190 .uhb_supported = true,
1192 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1193 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1196 const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0 = {
1197 .fw_name_pre = IWL_BNJ_A_GF4_A_FW_PRE,
1198 .uhb_supported = true,
1200 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1201 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1204 const struct iwl_cfg iwl_cfg_bnj_b0_gf4_a0 = {
1205 .fw_name_pre = IWL_BNJ_B_GF4_A_FW_PRE,
1206 .uhb_supported = true,
1208 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1209 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1212 const struct iwl_cfg iwl_cfg_bnj_a0_hr_a0 = {
1213 .fw_name_pre = IWL_BNJ_A_HR_A_FW_PRE,
1214 .uhb_supported = true,
1216 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1217 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1220 const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0 = {
1221 .fw_name_pre = IWL_BNJ_A_HR_B_FW_PRE,
1222 .uhb_supported = true,
1224 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1225 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1228 const struct iwl_cfg iwl_cfg_bnj_b0_hr_a0 = {
1229 .fw_name_pre = IWL_BNJ_B_HR_A_FW_PRE,
1230 .uhb_supported = true,
1232 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1233 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1236 const struct iwl_cfg iwl_cfg_bnj_b0_hr_b0 = {
1237 .fw_name_pre = IWL_BNJ_B_HR_B_FW_PRE,
1238 .uhb_supported = true,
1240 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1241 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1244 const struct iwl_cfg iwl_cfg_bnj_b0_fm_b0 = {
1245 .fw_name_pre = IWL_BNJ_B_FM_B_FW_PRE,
1246 .uhb_supported = true,
1248 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1249 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1252 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1253 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1254 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1255 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1256 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1257 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1258 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1259 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1260 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1261 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1262 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1263 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1264 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1265 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1266 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1267 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1268 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1269 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1270 MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1271 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1272 MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1273 MODULE_FIRMWARE(IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1274 MODULE_FIRMWARE(IWL_MA_B_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1275 MODULE_FIRMWARE(IWL_MA_B_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1276 MODULE_FIRMWARE(IWL_MA_B_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1277 MODULE_FIRMWARE(IWL_MA_B_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1278 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1279 MODULE_FIRMWARE(IWL_BZ_A_HR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1280 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1281 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1282 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1283 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1284 MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1285 MODULE_FIRMWARE(IWL_BZ_A_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1286 MODULE_FIRMWARE(IWL_BZ_A_FM_C_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1287 MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1288 MODULE_FIRMWARE(IWL_BNJ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1289 MODULE_FIRMWARE(IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1290 MODULE_FIRMWARE(IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1291 MODULE_FIRMWARE(IWL_BNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1292 MODULE_FIRMWARE(IWL_BNJ_B_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1293 MODULE_FIRMWARE(IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1294 MODULE_FIRMWARE(IWL_BNJ_B_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1295 MODULE_FIRMWARE(IWL_BNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1296 MODULE_FIRMWARE(IWL_BNJ_B_HR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1297 MODULE_FIRMWARE(IWL_BNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1298 MODULE_FIRMWARE(IWL_BZ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1299 MODULE_FIRMWARE(IWL_BZ_A_FM4_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1300 MODULE_FIRMWARE(IWL_GL_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1301 MODULE_FIRMWARE(IWL_GL_C_FM_C_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1302 MODULE_FIRMWARE(IWL_BNJ_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));