drivers/net/wireless/intel/iwlwifi/cfg/22000.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2015-2017 Intel Deutschland GmbH
   4  * Copyright (C) 2018-2022 Intel Corporation
   5  */
   6 #include <linux/module.h>
   7 #include <linux/stringify.h>
   8 #include "iwl-config.h"
   9 #include "iwl-prph.h"
  10 #include "fw/api/txq.h"
  11
  12 /* Highest firmware API version supported */
  13 #define IWL_22000_UCODE_API_MAX 78
  14
  15 /* Lowest firmware API version supported */
  16 #define IWL_22000_UCODE_API_MIN 39
  17
  18 /* NVM versions */
  19 #define IWL_22000_NVM_VERSION           0x0a1d
  20
  21 /* Memory offsets and lengths */
  22 #define IWL_22000_DCCM_OFFSET           0x800000 /* LMAC1 */
  23 #define IWL_22000_DCCM_LEN              0x10000 /* LMAC1 */
  24 #define IWL_22000_DCCM2_OFFSET          0x880000
  25 #define IWL_22000_DCCM2_LEN             0x8000
  26 #define IWL_22000_SMEM_OFFSET           0x400000
  27 #define IWL_22000_SMEM_LEN              0xD0000
  28
  29 #define IWL_QU_B_HR_B_FW_PRE            "iwlwifi-Qu-b0-hr-b0-"
  30 #define IWL_QNJ_B_HR_B_FW_PRE           "iwlwifi-QuQnj-b0-hr-b0-"
  31 #define IWL_QU_C_HR_B_FW_PRE            "iwlwifi-Qu-c0-hr-b0-"
  32 #define IWL_QU_B_JF_B_FW_PRE            "iwlwifi-Qu-b0-jf-b0-"
  33 #define IWL_QU_C_JF_B_FW_PRE            "iwlwifi-Qu-c0-jf-b0-"
  34 #define IWL_QUZ_A_HR_B_FW_PRE           "iwlwifi-QuZ-a0-hr-b0-"
  35 #define IWL_QUZ_A_JF_B_FW_PRE           "iwlwifi-QuZ-a0-jf-b0-"
  36 #define IWL_QNJ_B_JF_B_FW_PRE           "iwlwifi-QuQnj-b0-jf-b0-"
  37 #define IWL_CC_A_FW_PRE                 "iwlwifi-cc-a0-"
  38 #define IWL_SO_A_JF_B_FW_PRE            "iwlwifi-so-a0-jf-b0-"
  39 #define IWL_SO_A_HR_B_FW_PRE            "iwlwifi-so-a0-hr-b0-"
  40 #define IWL_SO_A_GF_A_FW_PRE            "iwlwifi-so-a0-gf-a0-"
  41 #define IWL_TY_A_GF_A_FW_PRE            "iwlwifi-ty-a0-gf-a0-"
  42 #define IWL_SO_A_GF4_A_FW_PRE           "iwlwifi-so-a0-gf4-a0-"
  43 #define IWL_SO_A_MR_A_FW_PRE            "iwlwifi-so-a0-mr-a0-"
  44 #define IWL_SNJ_A_GF4_A_FW_PRE          "iwlwifi-SoSnj-a0-gf4-a0-"
  45 #define IWL_SNJ_A_GF_A_FW_PRE           "iwlwifi-SoSnj-a0-gf-a0-"
  46 #define IWL_SNJ_A_HR_B_FW_PRE           "iwlwifi-SoSnj-a0-hr-b0-"
  47 #define IWL_SNJ_A_JF_B_FW_PRE           "iwlwifi-SoSnj-a0-jf-b0-"
  48 #define IWL_MA_A_HR_B_FW_PRE            "iwlwifi-ma-a0-hr-b0-"
  49 #define IWL_MA_A_GF_A_FW_PRE            "iwlwifi-ma-a0-gf-a0-"
  50 #define IWL_MA_A_GF4_A_FW_PRE           "iwlwifi-ma-a0-gf4-a0-"
  51 #define IWL_MA_A_MR_A_FW_PRE            "iwlwifi-ma-a0-mr-a0-"
  52 #define IWL_MA_A_FM_A_FW_PRE            "iwlwifi-ma-a0-fm-a0-"
  53 #define IWL_MA_B_HR_B_FW_PRE            "iwlwifi-ma-b0-hr-b0-"
  54 #define IWL_MA_B_GF_A_FW_PRE            "iwlwifi-ma-b0-gf-a0-"
  55 #define IWL_MA_B_GF4_A_FW_PRE           "iwlwifi-ma-b0-gf4-a0-"
  56 #define IWL_MA_B_MR_A_FW_PRE            "iwlwifi-ma-b0-mr-a0-"
  57 #define IWL_MA_B_FM_A_FW_PRE            "iwlwifi-ma-b0-fm-a0-"
  58 #define IWL_SNJ_A_MR_A_FW_PRE           "iwlwifi-SoSnj-a0-mr-a0-"
  59 #define IWL_BZ_A_HR_A_FW_PRE            "iwlwifi-bz-a0-hr-b0-"
  60 #define IWL_BZ_A_HR_B_FW_PRE            "iwlwifi-bz-a0-hr-b0-"
  61 #define IWL_BZ_A_GF_A_FW_PRE            "iwlwifi-bz-a0-gf-a0-"
  62 #define IWL_BZ_A_GF4_A_FW_PRE           "iwlwifi-bz-a0-gf4-a0-"
  63 #define IWL_BZ_A_MR_A_FW_PRE            "iwlwifi-bz-a0-mr-a0-"
  64 #define IWL_BZ_A_FM_A_FW_PRE            "iwlwifi-bz-a0-fm-a0-"
  65 #define IWL_BZ_A_FM4_A_FW_PRE           "iwlwifi-bz-a0-fm4-a0-"
  66 #define IWL_BZ_A_FM_B_FW_PRE            "iwlwifi-bz-a0-fm-b0-"
  67 #define IWL_BZ_A_FM4_B_FW_PRE           "iwlwifi-bz-a0-fm4-b0-"
  68 #define IWL_GL_A_FM_A_FW_PRE            "iwlwifi-gl-a0-fm-a0-"
  69 #define IWL_GL_B_FM_B_FW_PRE            "iwlwifi-gl-b0-fm-b0-"
  70 #define IWL_BZ_Z_GF_A_FW_PRE            "iwlwifi-bz-z0-gf-a0-"
  71 #define IWL_BNJ_A_FM_A_FW_PRE           "iwlwifi-BzBnj-a0-fm-a0-"
  72 #define IWL_BNJ_A_FM4_A_FW_PRE          "iwlwifi-BzBnj-a0-fm4-a0-"
  73 #define IWL_BNJ_B_FM4_B_FW_PRE          "iwlwifi-BzBnj-b0-fm4-b0-"
  74 #define IWL_BNJ_A_GF_A_FW_PRE           "iwlwifi-BzBnj-a0-gf-a0-"
  75 #define IWL_BNJ_B_GF_A_FW_PRE           "iwlwifi-BzBnj-b0-gf-a0-"
  76 #define IWL_BNJ_A_GF4_A_FW_PRE          "iwlwifi-BzBnj-a0-gf4-a0-"
  77 #define IWL_BNJ_B_GF4_A_FW_PRE          "iwlwifi-BzBnj-b0-gf4-a0-"
  78 #define IWL_BNJ_A_HR_A_FW_PRE           "iwlwifi-BzBnj-a0-hr-b0-"
  79 #define IWL_BNJ_A_HR_B_FW_PRE           "iwlwifi-BzBnj-a0-hr-b0-"
  80 #define IWL_BNJ_B_HR_A_FW_PRE           "iwlwifi-BzBnj-b0-hr-b0-"
  81 #define IWL_BNJ_B_HR_B_FW_PRE           "iwlwifi-BzBnj-b0-hr-b0-"
  82 #define IWL_BNJ_B_FM_B_FW_PRE           "iwlwifi-BzBnj-b0-fm-b0-"
  83
  84
  85 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \
  86         IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode"
  87 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api)     \
  88         IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode"
  89 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \
  90         IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
  91 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \
  92         IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode"
  93 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \
  94         IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode"
  95 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \
  96         IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode"
  97 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api)             \
  98         IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode"
  99 #define IWL_CC_A_MODULE_FIRMWARE(api)                   \
 100         IWL_CC_A_FW_PRE __stringify(api) ".ucode"
 101 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \
 102         IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode"
 103 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \
 104         IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode"
 105 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \
 106         IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode"
 107 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \
 108         IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode"
 109 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \
 110         IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
 111 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \
 112         IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
 113 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \
 114         IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
 115 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \
 116         IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode"
 117 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api)           \
 118         IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode"
 119 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api)           \
 120         IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode"
 121 #define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api)          \
 122         IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode"
 123 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \
 124         IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode"
 125 #define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api)           \
 126         IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode"
 127 #define IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(api)           \
 128         IWL_MA_B_HR_B_FW_PRE __stringify(api) ".ucode"
 129 #define IWL_MA_B_GF_A_FW_MODULE_FIRMWARE(api)           \
 130         IWL_MA_B_GF_A_FW_PRE __stringify(api) ".ucode"
 131 #define IWL_MA_B_GF4_A_FW_MODULE_FIRMWARE(api)          \
 132         IWL_MA_B_GF4_A_FW_PRE __stringify(api) ".ucode"
 133 #define IWL_MA_B_MR_A_FW_MODULE_FIRMWARE(api) \
 134         IWL_MA_B_MR_A_FW_PRE __stringify(api) ".ucode"
 135 #define IWL_MA_B_FM_A_FW_MODULE_FIRMWARE(api)           \
 136         IWL_MA_B_FM_A_FW_PRE __stringify(api) ".ucode"
 137 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \
 138         IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode"
 139 #define IWL_BZ_A_HR_A_MODULE_FIRMWARE(api) \
 140         IWL_BZ_A_HR_A_FW_PRE __stringify(api) ".ucode"
 141 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \
 142         IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
 143 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \
 144         IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode"
 145 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \
 146         IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
 147 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \
 148         IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode"
 149 #define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \
 150         IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode"
 151 #define IWL_BZ_A_FM4_A_MODULE_FIRMWARE(api) \
 152         IWL_BZ_A_FM4_A_FW_PRE __stringify(api) ".ucode"
 153 #define IWL_BZ_A_FM_B_MODULE_FIRMWARE(api) \
 154         IWL_BZ_A_FM_B_FW_PRE __stringify(api) ".ucode"
 155 #define IWL_BZ_A_FM4_B_MODULE_FIRMWARE(api) \
 156         IWL_BZ_A_FM4_B_FW_PRE __stringify(api) ".ucode"
 157 #define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \
 158         IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode"
 159 #define IWL_GL_B_FM_B_MODULE_FIRMWARE(api) \
 160         IWL_GL_B_FM_B_FW_PRE __stringify(api) ".ucode"
 161 #define IWL_BNJ_A_FM_A_MODULE_FIRMWARE(api) \
 162         IWL_BNJ_A_FM_A_FW_PRE __stringify(api) ".ucode"
 163 #define IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(api) \
 164         IWL_BNJ_A_FM4_A_FW_PRE __stringify(api) ".ucode"
 165 #define IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(api) \
 166         IWL_BNJ_B_FM4_B_FW_PRE __stringify(api) ".ucode"
 167 #define IWL_BNJ_A_GF_A_MODULE_FIRMWARE(api) \
 168         IWL_BNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
 169 #define IWL_BNJ_B_GF_A_MODULE_FIRMWARE(api) \
 170         IWL_BNJ_B_GF_A_FW_PRE __stringify(api) ".ucode"
 171 #define IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(api) \
 172         IWL_BNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
 173 #define IWL_BNJ_B_GF4_A_MODULE_FIRMWARE(api) \
 174         IWL_BNJ_B_GF4_A_FW_PRE __stringify(api) ".ucode"
 175 #define IWL_BNJ_A_HR_A_MODULE_FIRMWARE(api) \
 176         IWL_BNJ_A_HR_A_FW_PRE __stringify(api) ".ucode"
 177 #define IWL_BNJ_A_HR_B_MODULE_FIRMWARE(api) \
 178         IWL_BNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
 179 #define IWL_BNJ_B_HR_A_MODULE_FIRMWARE(api) \
 180         IWL_BNJ_B_HR_A_FW_PRE __stringify(api) ".ucode"
 181 #define IWL_BNJ_B_HR_B_MODULE_FIRMWARE(api) \
 182         IWL_BNJ_B_HR_B_FW_PRE __stringify(api) ".ucode"
 183 #define IWL_BNJ_B_FM_B_MODULE_FIRMWARE(api) \
 184         IWL_BNJ_B_FM_B_FW_PRE __stringify(api) ".ucode"
 185
 186 static const struct iwl_base_params iwl_22000_base_params = {
 187         .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
 188         .num_of_queues = 512,
 189         .max_tfd_queue_size = 256,
 190         .shadow_ram_support = true,
 191         .led_compensation = 57,
 192         .wd_timeout = IWL_LONG_WD_TIMEOUT,
 193         .max_event_log_size = 512,
 194         .shadow_reg_enable = true,
 195         .pcie_l1_allowed = true,
 196 };
 197
 198 static const struct iwl_base_params iwl_ax210_base_params = {
 199         .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
 200         .num_of_queues = 512,
 201         .max_tfd_queue_size = 65536,
 202         .shadow_ram_support = true,
 203         .led_compensation = 57,
 204         .wd_timeout = IWL_LONG_WD_TIMEOUT,
 205         .max_event_log_size = 512,
 206         .shadow_reg_enable = true,
 207         .pcie_l1_allowed = true,
 208 };
 209
 210 static const struct iwl_ht_params iwl_22000_ht_params = {
 211         .stbc = true,
 212         .ldpc = true,
 213         .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
 214                       BIT(NL80211_BAND_6GHZ),
 215 };
 216
 217 static const struct iwl_ht_params iwl_gl_a_ht_params = {
 218         .stbc = false, /* we explicitly disable STBC for GL step A */
 219         .ldpc = true,
 220         .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
 221                       BIT(NL80211_BAND_6GHZ),
 222 };
 223
 224 #define IWL_DEVICE_22000_COMMON                                         \
 225         .ucode_api_max = IWL_22000_UCODE_API_MAX,                       \
 226         .ucode_api_min = IWL_22000_UCODE_API_MIN,                       \
 227         .led_mode = IWL_LED_RF_STATE,                                   \
 228         .nvm_hw_section_num = 10,                                       \
 229         .non_shared_ant = ANT_B,                                        \
 230         .dccm_offset = IWL_22000_DCCM_OFFSET,                           \
 231         .dccm_len = IWL_22000_DCCM_LEN,                                 \
 232         .dccm2_offset = IWL_22000_DCCM2_OFFSET,                         \
 233         .dccm2_len = IWL_22000_DCCM2_LEN,                               \
 234         .smem_offset = IWL_22000_SMEM_OFFSET,                           \
 235         .smem_len = IWL_22000_SMEM_LEN,                                 \
 236         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,           \
 237         .apmg_not_supported = true,                                     \
 238         .trans.mq_rx_supported = true,                                  \
 239         .vht_mu_mimo_supported = true,                                  \
 240         .mac_addr_from_csr = 0x380,                                     \
 241         .ht_params = &iwl_22000_ht_params,                              \
 242         .nvm_ver = IWL_22000_NVM_VERSION,                               \
 243         .trans.use_tfh = true,                                          \
 244         .trans.rf_id = true,                                            \
 245         .trans.gen2 = true,                                             \
 246         .nvm_type = IWL_NVM_EXT,                                        \
 247         .dbgc_supported = true,                                         \
 248         .min_umac_error_event_table = 0x400000,                         \
 249         .d3_debug_data_base_addr = 0x401000,                            \
 250         .d3_debug_data_length = 60 * 1024,                              \
 251         .mon_smem_regs = {                                              \
 252                 .write_ptr = {                                          \
 253                         .addr = LDBG_M2S_BUF_WPTR,                      \
 254                         .mask = LDBG_M2S_BUF_WPTR_VAL_MSK,              \
 255         },                                                              \
 256                 .cycle_cnt = {                                          \
 257                         .addr = LDBG_M2S_BUF_WRAP_CNT,                  \
 258                         .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK,          \
 259                 },                                                      \
 260         }
 261
 262 #define IWL_DEVICE_22500                                                \
 263         IWL_DEVICE_22000_COMMON,                                        \
 264         .trans.device_family = IWL_DEVICE_FAMILY_22000,                 \
 265         .trans.base_params = &iwl_22000_base_params,                    \
 266         .gp2_reg_addr = 0xa02c68,                                       \
 267         .mon_dram_regs = {                                              \
 268                 .write_ptr = {                                          \
 269                         .addr = MON_BUFF_WRPTR_VER2,                    \
 270                         .mask = 0xffffffff,                             \
 271                 },                                                      \
 272                 .cycle_cnt = {                                          \
 273                         .addr = MON_BUFF_CYCLE_CNT_VER2,                \
 274                         .mask = 0xffffffff,                             \
 275                 },                                                      \
 276         }
 277
 278 #define IWL_DEVICE_AX210                                                \
 279         IWL_DEVICE_22000_COMMON,                                        \
 280         .trans.umac_prph_offset = 0x300000,                             \
 281         .trans.device_family = IWL_DEVICE_FAMILY_AX210,                 \
 282         .trans.base_params = &iwl_ax210_base_params,                    \
 283         .min_txq_size = 128,                                            \
 284         .gp2_reg_addr = 0xd02c68,                                       \
 285         .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE,           \
 286         .mon_dram_regs = {                                              \
 287                 .write_ptr = {                                          \
 288                         .addr = DBGC_CUR_DBGBUF_STATUS,                 \
 289                         .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK,      \
 290                 },                                                      \
 291                 .cycle_cnt = {                                          \
 292                         .addr = DBGC_DBGBUF_WRAP_AROUND,                \
 293                         .mask = 0xffffffff,                             \
 294                 },                                                      \
 295                 .cur_frag = {                                           \
 296                         .addr = DBGC_CUR_DBGBUF_STATUS,                 \
 297                         .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK,         \
 298                 },                                                      \
 299         }
 300
 301 #define IWL_DEVICE_BZ_COMMON                                            \
 302         .ucode_api_max = IWL_22000_UCODE_API_MAX,                       \
 303         .ucode_api_min = IWL_22000_UCODE_API_MIN,                       \
 304         .led_mode = IWL_LED_RF_STATE,                                   \
 305         .nvm_hw_section_num = 10,                                       \
 306         .non_shared_ant = ANT_B,                                        \
 307         .dccm_offset = IWL_22000_DCCM_OFFSET,                           \
 308         .dccm_len = IWL_22000_DCCM_LEN,                                 \
 309         .dccm2_offset = IWL_22000_DCCM2_OFFSET,                         \
 310         .dccm2_len = IWL_22000_DCCM2_LEN,                               \
 311         .smem_offset = IWL_22000_SMEM_OFFSET,                           \
 312         .smem_len = IWL_22000_SMEM_LEN,                                 \
 313         .apmg_not_supported = true,                                     \
 314         .trans.mq_rx_supported = true,                                  \
 315         .vht_mu_mimo_supported = true,                                  \
 316         .mac_addr_from_csr = 0x30,                                      \
 317         .nvm_ver = IWL_22000_NVM_VERSION,                               \
 318         .trans.use_tfh = true,                                          \
 319         .trans.rf_id = true,                                            \
 320         .trans.gen2 = true,                                             \
 321         .nvm_type = IWL_NVM_EXT,                                        \
 322         .dbgc_supported = true,                                         \
 323         .min_umac_error_event_table = 0xD0000,                          \
 324         .d3_debug_data_base_addr = 0x401000,                            \
 325         .d3_debug_data_length = 60 * 1024,                              \
 326         .mon_smem_regs = {                                              \
 327                 .write_ptr = {                                          \
 328                         .addr = LDBG_M2S_BUF_WPTR,                      \
 329                         .mask = LDBG_M2S_BUF_WPTR_VAL_MSK,              \
 330         },                                                              \
 331                 .cycle_cnt = {                                          \
 332                         .addr = LDBG_M2S_BUF_WRAP_CNT,                  \
 333                         .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK,          \
 334                 },                                                      \
 335         },                                                              \
 336         .trans.umac_prph_offset = 0x300000,                             \
 337         .trans.device_family = IWL_DEVICE_FAMILY_BZ,                    \
 338         .trans.base_params = &iwl_ax210_base_params,                    \
 339         .min_txq_size = 128,                                            \
 340         .gp2_reg_addr = 0xd02c68,                                       \
 341         .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT,                  \
 342         .mon_dram_regs = {                                              \
 343                 .write_ptr = {                                          \
 344                         .addr = DBGC_CUR_DBGBUF_STATUS,                 \
 345                         .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK,      \
 346                 },                                                      \
 347                 .cycle_cnt = {                                          \
 348                         .addr = DBGC_DBGBUF_WRAP_AROUND,                \
 349                         .mask = 0xffffffff,                             \
 350                 },                                                      \
 351                 .cur_frag = {                                           \
 352                         .addr = DBGC_CUR_DBGBUF_STATUS,                 \
 353                         .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK,         \
 354                 },                                                      \
 355         },                                                              \
 356         .mon_dbgi_regs = {                                              \
 357                 .write_ptr = {                                          \
 358                         .addr = DBGI_SRAM_FIFO_POINTERS,                \
 359                         .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK,     \
 360                 },                                                      \
 361         }
 362
 363 #define IWL_DEVICE_BZ                                                   \
 364         IWL_DEVICE_BZ_COMMON,                                           \
 365         .ht_params = &iwl_22000_ht_params
 366
 367 #define IWL_DEVICE_GL_A                                                 \
 368         IWL_DEVICE_BZ_COMMON,                                           \
 369         .ht_params = &iwl_gl_a_ht_params
 370
 371 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = {
 372         .mq_rx_supported = true,
 373         .use_tfh = true,
 374         .rf_id = true,
 375         .gen2 = true,
 376         .device_family = IWL_DEVICE_FAMILY_22000,
 377         .base_params = &iwl_22000_base_params,
 378 };
 379
 380 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = {
 381         .mq_rx_supported = true,
 382         .use_tfh = true,
 383         .rf_id = true,
 384         .gen2 = true,
 385         .device_family = IWL_DEVICE_FAMILY_22000,
 386         .base_params = &iwl_22000_base_params,
 387         .integrated = true,
 388         .xtal_latency = 500,
 389         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
 390 };
 391
 392 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = {
 393         .mq_rx_supported = true,
 394         .use_tfh = true,
 395         .rf_id = true,
 396         .gen2 = true,
 397         .device_family = IWL_DEVICE_FAMILY_22000,
 398         .base_params = &iwl_22000_base_params,
 399         .integrated = true,
 400         .xtal_latency = 1820,
 401         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US,
 402 };
 403
 404 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = {
 405         .mq_rx_supported = true,
 406         .use_tfh = true,
 407         .rf_id = true,
 408         .gen2 = true,
 409         .device_family = IWL_DEVICE_FAMILY_22000,
 410         .base_params = &iwl_22000_base_params,
 411         .integrated = true,
 412         .xtal_latency = 12000,
 413         .low_latency_xtal = true,
 414         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
 415 };
 416
 417 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = {
 418         .mq_rx_supported = true,
 419         .use_tfh = true,
 420         .rf_id = true,
 421         .gen2 = true,
 422         .device_family = IWL_DEVICE_FAMILY_AX210,
 423         .base_params = &iwl_ax210_base_params,
 424         .umac_prph_offset = 0x300000,
 425 };
 426
 427 const struct iwl_cfg_trans_params iwl_so_trans_cfg = {
 428         .mq_rx_supported = true,
 429         .use_tfh = true,
 430         .rf_id = true,
 431         .gen2 = true,
 432         .device_family = IWL_DEVICE_FAMILY_AX210,
 433         .base_params = &iwl_ax210_base_params,
 434         .umac_prph_offset = 0x300000,
 435         .integrated = true,
 436         /* TODO: the following values need to be checked */
 437         .xtal_latency = 500,
 438         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
 439 };
 440
 441 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = {
 442         .mq_rx_supported = true,
 443         .use_tfh = true,
 444         .rf_id = true,
 445         .gen2 = true,
 446         .device_family = IWL_DEVICE_FAMILY_AX210,
 447         .base_params = &iwl_ax210_base_params,
 448         .umac_prph_offset = 0x300000,
 449         .integrated = true,
 450         .low_latency_xtal = true,
 451         .xtal_latency = 12000,
 452         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
 453 };
 454
 455 const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = {
 456         .mq_rx_supported = true,
 457         .use_tfh = true,
 458         .rf_id = true,
 459         .gen2 = true,
 460         .device_family = IWL_DEVICE_FAMILY_AX210,
 461         .base_params = &iwl_ax210_base_params,
 462         .umac_prph_offset = 0x300000,
 463         .integrated = true,
 464         .low_latency_xtal = true,
 465         .xtal_latency = 12000,
 466         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
 467         .imr_enabled = true,
 468 };
 469
 470 /*
 471  * If the device doesn't support HE, no need to have that many buffers.
 472  * 22000 devices can split multiple frames into a single RB, so fewer are
 473  * needed; AX210 cannot (but use smaller RBs by default) - these sizes
 474  * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with
 475  * additional overhead to account for processing time.
 476  */
 477 #define IWL_NUM_RBDS_NON_HE             512
 478 #define IWL_NUM_RBDS_22000_HE           2048
 479 #define IWL_NUM_RBDS_AX210_HE           4096
 480
 481 /*
 482  * All JF radio modules are part of the 9000 series, but the MAC part
 483  * looks more like 22000.  That's why this device is here, but called
 484  * 9560 nevertheless.
 485  */
 486 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = {
 487         .fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
 488         IWL_DEVICE_22500,
 489         .num_rbds = IWL_NUM_RBDS_NON_HE,
 490 };
 491
 492 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = {
 493         .fw_name_pre = IWL_QU_C_JF_B_FW_PRE,
 494         IWL_DEVICE_22500,
 495         .num_rbds = IWL_NUM_RBDS_NON_HE,
 496 };
 497
 498 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = {
 499         .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE,
 500         IWL_DEVICE_22500,
 501         /*
 502          * This device doesn't support receiving BlockAck with a large bitmap
 503          * so we need to restrict the size of transmitted aggregation to the
 504          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 505          */
 506         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 507         .num_rbds = IWL_NUM_RBDS_NON_HE,
 508 };
 509
 510 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = {
 511         .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE,
 512         IWL_DEVICE_22500,
 513         /*
 514          * This device doesn't support receiving BlockAck with a large bitmap
 515          * so we need to restrict the size of transmitted aggregation to the
 516          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 517          */
 518         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 519         .num_rbds = IWL_NUM_RBDS_NON_HE,
 520 };
 521
 522 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = {
 523         .device_family = IWL_DEVICE_FAMILY_22000,
 524         .base_params = &iwl_22000_base_params,
 525         .mq_rx_supported = true,
 526         .use_tfh = true,
 527         .rf_id = true,
 528         .gen2 = true,
 529         .bisr_workaround = 1,
 530 };
 531
 532 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = {
 533         .device_family = IWL_DEVICE_FAMILY_AX210,
 534         .base_params = &iwl_ax210_base_params,
 535         .mq_rx_supported = true,
 536         .use_tfh = true,
 537         .rf_id = true,
 538         .gen2 = true,
 539         .integrated = true,
 540         .umac_prph_offset = 0x300000
 541 };
 542
 543 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = {
 544         .device_family = IWL_DEVICE_FAMILY_BZ,
 545         .base_params = &iwl_ax210_base_params,
 546         .mq_rx_supported = true,
 547         .use_tfh = true,
 548         .rf_id = true,
 549         .gen2 = true,
 550         .integrated = true,
 551         .umac_prph_offset = 0x300000,
 552         .xtal_latency = 12000,
 553         .low_latency_xtal = true,
 554         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
 555 };
 556
 557 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101";
 558 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz";
 559 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz";
 560 const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203";
 561 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz";
 562 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz";
 563 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz";
 564 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz";
 565 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz";
 566 const char iwl_bz_name[] = "Intel(R) TBD Bz device";
 567
 568 const char iwl_ax200_killer_1650w_name[] =
 569         "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)";
 570 const char iwl_ax200_killer_1650x_name[] =
 571         "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)";
 572 const char iwl_ax201_killer_1650s_name[] =
 573         "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)";
 574 const char iwl_ax201_killer_1650i_name[] =
 575         "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)";
 576 const char iwl_ax210_killer_1675w_name[] =
 577         "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)";
 578 const char iwl_ax210_killer_1675x_name[] =
 579         "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)";
 580 const char iwl_ax211_killer_1675s_name[] =
 581         "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)";
 582 const char iwl_ax211_killer_1675i_name[] =
 583         "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)";
 584 const char iwl_ax411_killer_1690s_name[] =
 585         "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)";
 586 const char iwl_ax411_killer_1690i_name[] =
 587         "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)";
 588
 589 const struct iwl_cfg iwl_qu_b0_hr1_b0 = {
 590         .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
 591         IWL_DEVICE_22500,
 592         /*
 593          * This device doesn't support receiving BlockAck with a large bitmap
 594          * so we need to restrict the size of transmitted aggregation to the
 595          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 596          */
 597         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 598         .tx_with_siso_diversity = true,
 599         .num_rbds = IWL_NUM_RBDS_22000_HE,
 600 };
 601
 602 const struct iwl_cfg iwl_qu_b0_hr_b0 = {
 603         .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
 604         IWL_DEVICE_22500,
 605         /*
 606          * This device doesn't support receiving BlockAck with a large bitmap
 607          * so we need to restrict the size of transmitted aggregation to the
 608          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 609          */
 610         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 611         .num_rbds = IWL_NUM_RBDS_22000_HE,
 612 };
 613
 614 const struct iwl_cfg iwl_ax201_cfg_qu_hr = {
 615         .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
 616         .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
 617         IWL_DEVICE_22500,
 618         /*
 619          * This device doesn't support receiving BlockAck with a large bitmap
 620          * so we need to restrict the size of transmitted aggregation to the
 621          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 622          */
 623         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 624         .num_rbds = IWL_NUM_RBDS_22000_HE,
 625 };
 626
 627 const struct iwl_cfg iwl_qu_c0_hr1_b0 = {
 628         .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
 629         IWL_DEVICE_22500,
 630         /*
 631          * This device doesn't support receiving BlockAck with a large bitmap
 632          * so we need to restrict the size of transmitted aggregation to the
 633          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 634          */
 635         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 636         .tx_with_siso_diversity = true,
 637         .num_rbds = IWL_NUM_RBDS_22000_HE,
 638 };
 639
 640 const struct iwl_cfg iwl_qu_c0_hr_b0 = {
 641         .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
 642         IWL_DEVICE_22500,
 643         /*
 644          * This device doesn't support receiving BlockAck with a large bitmap
 645          * so we need to restrict the size of transmitted aggregation to the
 646          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 647          */
 648         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 649         .num_rbds = IWL_NUM_RBDS_22000_HE,
 650 };
 651
 652 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = {
 653         .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
 654         .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
 655         IWL_DEVICE_22500,
 656         /*
 657          * This device doesn't support receiving BlockAck with a large bitmap
 658          * so we need to restrict the size of transmitted aggregation to the
 659          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 660          */
 661         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 662         .num_rbds = IWL_NUM_RBDS_22000_HE,
 663 };
 664
 665 const struct iwl_cfg iwl_quz_a0_hr1_b0 = {
 666         .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
 667         IWL_DEVICE_22500,
 668         /*
 669          * This device doesn't support receiving BlockAck with a large bitmap
 670          * so we need to restrict the size of transmitted aggregation to the
 671          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 672          */
 673         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 674         .tx_with_siso_diversity = true,
 675         .num_rbds = IWL_NUM_RBDS_22000_HE,
 676 };
 677
 678 const struct iwl_cfg iwl_ax201_cfg_quz_hr = {
 679         .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
 680         .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
 681         IWL_DEVICE_22500,
 682         /*
 683          * This device doesn't support receiving BlockAck with a large bitmap
 684          * so we need to restrict the size of transmitted aggregation to the
 685          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 686          */
 687         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 688         .num_rbds = IWL_NUM_RBDS_22000_HE,
 689 };
 690
 691 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = {
 692         .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)",
 693         .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
 694         IWL_DEVICE_22500,
 695         /*
 696          * This device doesn't support receiving BlockAck with a large bitmap
 697          * so we need to restrict the size of transmitted aggregation to the
 698          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 699          */
 700         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 701         .num_rbds = IWL_NUM_RBDS_22000_HE,
 702 };
 703
 704 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = {
 705         .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)",
 706         .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
 707         IWL_DEVICE_22500,
 708         /*
 709          * This device doesn't support receiving BlockAck with a large bitmap
 710          * so we need to restrict the size of transmitted aggregation to the
 711          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 712          */
 713         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 714         .num_rbds = IWL_NUM_RBDS_22000_HE,
 715 };
 716
 717 const struct iwl_cfg iwl_ax200_cfg_cc = {
 718         .fw_name_pre = IWL_CC_A_FW_PRE,
 719         IWL_DEVICE_22500,
 720         /*
 721          * This device doesn't support receiving BlockAck with a large bitmap
 722          * so we need to restrict the size of transmitted aggregation to the
 723          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 724          */
 725         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 726         .num_rbds = IWL_NUM_RBDS_22000_HE,
 727 };
 728
 729 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = {
 730         .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)",
 731         .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
 732         IWL_DEVICE_22500,
 733         /*
 734          * This device doesn't support receiving BlockAck with a large bitmap
 735          * so we need to restrict the size of transmitted aggregation to the
 736          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 737          */
 738         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 739         .num_rbds = IWL_NUM_RBDS_22000_HE,
 740 };
 741
 742 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = {
 743         .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)",
 744         .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
 745         IWL_DEVICE_22500,
 746         /*
 747          * This device doesn't support receiving BlockAck with a large bitmap
 748          * so we need to restrict the size of transmitted aggregation to the
 749          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 750          */
 751         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 752         .num_rbds = IWL_NUM_RBDS_22000_HE,
 753 };
 754
 755 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = {
 756         .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)",
 757         .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
 758         IWL_DEVICE_22500,
 759         /*
 760          * This device doesn't support receiving BlockAck with a large bitmap
 761          * so we need to restrict the size of transmitted aggregation to the
 762          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 763          */
 764         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 765         .num_rbds = IWL_NUM_RBDS_22000_HE,
 766 };
 767
 768 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = {
 769         .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)",
 770         .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
 771         IWL_DEVICE_22500,
 772         /*
 773          * This device doesn't support receiving BlockAck with a large bitmap
 774          * so we need to restrict the size of transmitted aggregation to the
 775          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 776          */
 777         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 778         .num_rbds = IWL_NUM_RBDS_22000_HE,
 779 };
 780
 781 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = {
 782         .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE,
 783         IWL_DEVICE_22500,
 784         /*
 785          * This device doesn't support receiving BlockAck with a large bitmap
 786          * so we need to restrict the size of transmitted aggregation to the
 787          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 788          */
 789         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 790         .num_rbds = IWL_NUM_RBDS_22000_HE,
 791 };
 792
 793 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = {
 794         .name = "Intel(R) Wireless-AC 9560 160MHz",
 795         .fw_name_pre = IWL_SO_A_JF_B_FW_PRE,
 796         IWL_DEVICE_AX210,
 797         .num_rbds = IWL_NUM_RBDS_NON_HE,
 798 };
 799
 800 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = {
 801         .name = iwl_ax211_name,
 802         .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
 803         .uhb_supported = true,
 804         IWL_DEVICE_AX210,
 805         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 806 };
 807
 808 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = {
 809         .name = iwl_ax211_name,
 810         .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
 811         .uhb_supported = true,
 812         IWL_DEVICE_AX210,
 813         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 814         .trans.xtal_latency = 12000,
 815         .trans.low_latency_xtal = true,
 816 };
 817
 818 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = {
 819         .name = "Intel(R) Wi-Fi 6 AX210 160MHz",
 820         .fw_name_pre = IWL_TY_A_GF_A_FW_PRE,
 821         .uhb_supported = true,
 822         IWL_DEVICE_AX210,
 823         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 824 };
 825
 826 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = {
 827         .name = iwl_ax411_name,
 828         .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
 829         .uhb_supported = true,
 830         IWL_DEVICE_AX210,
 831         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 832 };
 833
 834 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = {
 835         .name = iwl_ax411_name,
 836         .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
 837         .uhb_supported = true,
 838         IWL_DEVICE_AX210,
 839         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 840         .trans.xtal_latency = 12000,
 841         .trans.low_latency_xtal = true,
 842 };
 843
 844 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = {
 845         .name = iwl_ax411_name,
 846         .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE,
 847         .uhb_supported = true,
 848         IWL_DEVICE_AX210,
 849         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 850 };
 851
 852 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = {
 853         .name = iwl_ax211_name,
 854         .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE,
 855         .uhb_supported = true,
 856         IWL_DEVICE_AX210,
 857         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 858 };
 859
 860 const struct iwl_cfg iwl_cfg_snj_hr_b0 = {
 861         .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE,
 862         .uhb_supported = true,
 863         IWL_DEVICE_AX210,
 864         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 865 };
 866
 867 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = {
 868         .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE,
 869         .uhb_supported = true,
 870         IWL_DEVICE_AX210,
 871         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 872 };
 873
 874 const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = {
 875         .fw_name_pre = IWL_MA_A_HR_B_FW_PRE,
 876         .uhb_supported = true,
 877         IWL_DEVICE_AX210,
 878         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 879 };
 880
 881 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = {
 882         .fw_name_pre = IWL_MA_A_GF_A_FW_PRE,
 883         .uhb_supported = true,
 884         IWL_DEVICE_AX210,
 885         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 886 };
 887
 888 const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = {
 889         .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE,
 890         .uhb_supported = true,
 891         IWL_DEVICE_AX210,
 892         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 893 };
 894
 895 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = {
 896         .fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
 897         .uhb_supported = true,
 898         IWL_DEVICE_AX210,
 899         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 900 };
 901
 902 const struct iwl_cfg iwl_cfg_ma_a0_ms_a0 = {
 903         .fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
 904         .uhb_supported = false,
 905         IWL_DEVICE_AX210,
 906         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 907 };
 908
 909 const struct iwl_cfg iwl_cfg_ma_b0_fm_a0 = {
 910         .fw_name_pre = IWL_MA_B_FM_A_FW_PRE,
 911         .uhb_supported = true,
 912         IWL_DEVICE_AX210,
 913         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 914 };
 915
 916 const struct iwl_cfg iwl_cfg_ma_b0_hr_b0 = {
 917         .fw_name_pre = IWL_MA_B_HR_B_FW_PRE,
 918         .uhb_supported = true,
 919         IWL_DEVICE_AX210,
 920         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 921 };
 922
 923 const struct iwl_cfg iwl_cfg_ma_b0_gf_a0 = {
 924         .fw_name_pre = IWL_MA_B_GF_A_FW_PRE,
 925         .uhb_supported = true,
 926         IWL_DEVICE_AX210,
 927         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 928 };
 929
 930 const struct iwl_cfg iwl_cfg_ma_b0_gf4_a0 = {
 931         .fw_name_pre = IWL_MA_B_GF4_A_FW_PRE,
 932         .uhb_supported = true,
 933         IWL_DEVICE_AX210,
 934         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 935 };
 936
 937 const struct iwl_cfg iwl_cfg_ma_b0_mr_a0 = {
 938         .fw_name_pre = IWL_MA_B_MR_A_FW_PRE,
 939         .uhb_supported = true,
 940         IWL_DEVICE_AX210,
 941         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 942 };
 943
 944 const struct iwl_cfg iwl_cfg_so_a0_ms_a0 = {
 945         .fw_name_pre = IWL_SO_A_MR_A_FW_PRE,
 946         .uhb_supported = false,
 947         IWL_DEVICE_AX210,
 948         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 949 };
 950
 951 const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = {
 952         .fw_name_pre = IWL_MA_A_FM_A_FW_PRE,
 953         .uhb_supported = true,
 954         IWL_DEVICE_AX210,
 955         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 956 };
 957
 958 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = {
 959         .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
 960         .uhb_supported = true,
 961         IWL_DEVICE_AX210,
 962         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 963 };
 964
 965 const struct iwl_cfg iwl_cfg_snj_a0_ms_a0 = {
 966         .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
 967         .uhb_supported = false,
 968         IWL_DEVICE_AX210,
 969         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 970 };
 971
 972 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = {
 973         .fw_name_pre = IWL_SO_A_HR_B_FW_PRE,
 974         IWL_DEVICE_AX210,
 975         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 976 };
 977
 978 const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = {
 979         .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
 980         IWL_DEVICE_22500,
 981         /*
 982          * This device doesn't support receiving BlockAck with a large bitmap
 983          * so we need to restrict the size of transmitted aggregation to the
 984          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 985          */
 986         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 987         .num_rbds = IWL_NUM_RBDS_22000_HE,
 988 };
 989
 990 const struct iwl_cfg iwl_cfg_bz_a0_hr_a0 = {
 991         .fw_name_pre = IWL_BZ_A_HR_A_FW_PRE,
 992         .uhb_supported = true,
 993         IWL_DEVICE_BZ,
 994         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
 995         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 996 };
 997
 998 const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = {
 999         .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE,
1000         .uhb_supported = true,
1001         IWL_DEVICE_BZ,
1002         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1003         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1004 };
1005
1006 const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = {
1007         .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE,
1008         .uhb_supported = true,
1009         IWL_DEVICE_BZ,
1010         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1011         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1012 };
1013
1014 const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = {
1015         .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE,
1016         .uhb_supported = true,
1017         IWL_DEVICE_BZ,
1018         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1019         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1020 };
1021
1022 const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = {
1023         .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE,
1024         .uhb_supported = true,
1025         IWL_DEVICE_BZ,
1026         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1027         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1028 };
1029
1030 const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = {
1031         .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE,
1032         .uhb_supported = true,
1033         IWL_DEVICE_BZ,
1034         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1035         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1036 };
1037
1038 const struct iwl_cfg iwl_cfg_bz_a0_fm4_a0 = {
1039         .fw_name_pre = IWL_BZ_A_FM4_A_FW_PRE,
1040         .uhb_supported = true,
1041         IWL_DEVICE_BZ,
1042         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1043         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1044 };
1045
1046 const struct iwl_cfg iwl_cfg_bz_a0_fm_b0 = {
1047         .fw_name_pre = IWL_BZ_A_FM_B_FW_PRE,
1048         .uhb_supported = true,
1049         IWL_DEVICE_BZ,
1050         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1051         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1052 };
1053
1054 const struct iwl_cfg iwl_cfg_bz_a0_fm4_b0 = {
1055         .fw_name_pre = IWL_BZ_A_FM4_B_FW_PRE,
1056         .uhb_supported = true,
1057         IWL_DEVICE_BZ,
1058         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1059         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1060 };
1061
1062 const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = {
1063         .fw_name_pre = IWL_GL_A_FM_A_FW_PRE,
1064         .uhb_supported = true,
1065         IWL_DEVICE_GL_A,
1066         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1067         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1068 };
1069
1070 const struct iwl_cfg iwl_cfg_gl_b0_fm_b0 = {
1071         .fw_name_pre = IWL_GL_B_FM_B_FW_PRE,
1072         .uhb_supported = true,
1073         IWL_DEVICE_BZ,
1074         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1075         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1076 };
1077
1078 const struct iwl_cfg iwl_cfg_bz_z0_gf_a0 = {
1079         .fw_name_pre = IWL_BZ_Z_GF_A_FW_PRE,
1080         .uhb_supported = true,
1081         IWL_DEVICE_BZ,
1082         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1083         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1084 };
1085
1086 const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0 = {
1087         .fw_name_pre = IWL_BNJ_A_FM_A_FW_PRE,
1088         .uhb_supported = true,
1089         IWL_DEVICE_BZ,
1090         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1091         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1092 };
1093
1094 const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0 = {
1095         .fw_name_pre = IWL_BNJ_A_FM4_A_FW_PRE,
1096         .uhb_supported = true,
1097         IWL_DEVICE_BZ,
1098         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1099         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1100 };
1101
1102 const struct iwl_cfg iwl_cfg_bnj_b0_fm4_b0 = {
1103         .fw_name_pre = IWL_BNJ_B_FM4_B_FW_PRE,
1104         .uhb_supported = true,
1105         IWL_DEVICE_BZ,
1106         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1107         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1108 };
1109
1110 const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0 = {
1111         .fw_name_pre = IWL_BNJ_A_GF_A_FW_PRE,
1112         .uhb_supported = true,
1113         IWL_DEVICE_BZ,
1114         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1115         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1116 };
1117
1118 const struct iwl_cfg iwl_cfg_bnj_b0_gf_a0 = {
1119         .fw_name_pre = IWL_BNJ_B_GF_A_FW_PRE,
1120         .uhb_supported = true,
1121         IWL_DEVICE_BZ,
1122         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1123         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1124 };
1125
1126 const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0 = {
1127         .fw_name_pre = IWL_BNJ_A_GF4_A_FW_PRE,
1128         .uhb_supported = true,
1129         IWL_DEVICE_BZ,
1130         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1131         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1132 };
1133
1134 const struct iwl_cfg iwl_cfg_bnj_b0_gf4_a0 = {
1135         .fw_name_pre = IWL_BNJ_B_GF4_A_FW_PRE,
1136         .uhb_supported = true,
1137         IWL_DEVICE_BZ,
1138         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1139         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1140 };
1141
1142 const struct iwl_cfg iwl_cfg_bnj_a0_hr_a0 = {
1143         .fw_name_pre = IWL_BNJ_A_HR_A_FW_PRE,
1144         .uhb_supported = true,
1145         IWL_DEVICE_BZ,
1146         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1147         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1148 };
1149
1150 const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0 = {
1151         .fw_name_pre = IWL_BNJ_A_HR_B_FW_PRE,
1152         .uhb_supported = true,
1153         IWL_DEVICE_BZ,
1154         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1155         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1156 };
1157
1158 const struct iwl_cfg iwl_cfg_bnj_b0_hr_a0 = {
1159         .fw_name_pre = IWL_BNJ_B_HR_A_FW_PRE,
1160         .uhb_supported = true,
1161         IWL_DEVICE_BZ,
1162         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1163         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1164 };
1165
1166 const struct iwl_cfg iwl_cfg_bnj_b0_hr_b0 = {
1167         .fw_name_pre = IWL_BNJ_B_HR_B_FW_PRE,
1168         .uhb_supported = true,
1169         IWL_DEVICE_BZ,
1170         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1171         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1172 };
1173
1174 const struct iwl_cfg iwl_cfg_bnj_b0_fm_b0 = {
1175         .fw_name_pre = IWL_BNJ_B_FM_B_FW_PRE,
1176         .uhb_supported = true,
1177         IWL_DEVICE_BZ,
1178         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1179         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1180 };
1181 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1182 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1183 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1184 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1185 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1186 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1187 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1188 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1189 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1190 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1191 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1192 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1193 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1194 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1195 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1196 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1197 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1198 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1199 MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1200 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1201 MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1202 MODULE_FIRMWARE(IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1203 MODULE_FIRMWARE(IWL_MA_B_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1204 MODULE_FIRMWARE(IWL_MA_B_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1205 MODULE_FIRMWARE(IWL_MA_B_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1206 MODULE_FIRMWARE(IWL_MA_B_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1207 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1208 MODULE_FIRMWARE(IWL_BZ_A_HR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1209 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1210 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1211 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1212 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1213 MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1214 MODULE_FIRMWARE(IWL_BZ_A_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1215 MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1216 MODULE_FIRMWARE(IWL_BNJ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1217 MODULE_FIRMWARE(IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1218 MODULE_FIRMWARE(IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1219 MODULE_FIRMWARE(IWL_BNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1220 MODULE_FIRMWARE(IWL_BNJ_B_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1221 MODULE_FIRMWARE(IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1222 MODULE_FIRMWARE(IWL_BNJ_B_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1223 MODULE_FIRMWARE(IWL_BNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1224 MODULE_FIRMWARE(IWL_BNJ_B_HR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1225 MODULE_FIRMWARE(IWL_BNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1226 MODULE_FIRMWARE(IWL_BZ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1227 MODULE_FIRMWARE(IWL_BZ_A_FM4_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1228 MODULE_FIRMWARE(IWL_GL_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1229 MODULE_FIRMWARE(IWL_BNJ_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));