drivers/net/wireless/intel/iwlwifi/cfg/22000.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2015-2017 Intel Deutschland GmbH
   4  * Copyright (C) 2018-2022 Intel Corporation
   5  */
   6 #include <linux/module.h>
   7 #include <linux/stringify.h>
   8 #include "iwl-config.h"
   9 #include "iwl-prph.h"
  10 #include "fw/api/txq.h"
  11
  12 /* Highest firmware API version supported */
  13 #define IWL_22000_UCODE_API_MAX 78
  14 #define IWL_22500_UCODE_API_MAX 77
  15
  16 /* Lowest firmware API version supported */
  17 #define IWL_22000_UCODE_API_MIN 39
  18
  19 /* NVM versions */
  20 #define IWL_22000_NVM_VERSION           0x0a1d
  21
  22 /* Memory offsets and lengths */
  23 #define IWL_22000_DCCM_OFFSET           0x800000 /* LMAC1 */
  24 #define IWL_22000_DCCM_LEN              0x10000 /* LMAC1 */
  25 #define IWL_22000_DCCM2_OFFSET          0x880000
  26 #define IWL_22000_DCCM2_LEN             0x8000
  27 #define IWL_22000_SMEM_OFFSET           0x400000
  28 #define IWL_22000_SMEM_LEN              0xD0000
  29
  30 #define IWL_QU_B_HR_B_FW_PRE            "iwlwifi-Qu-b0-hr-b0-"
  31 #define IWL_QNJ_B_HR_B_FW_PRE           "iwlwifi-QuQnj-b0-hr-b0-"
  32 #define IWL_QU_C_HR_B_FW_PRE            "iwlwifi-Qu-c0-hr-b0-"
  33 #define IWL_QU_B_JF_B_FW_PRE            "iwlwifi-Qu-b0-jf-b0-"
  34 #define IWL_QU_C_JF_B_FW_PRE            "iwlwifi-Qu-c0-jf-b0-"
  35 #define IWL_QUZ_A_HR_B_FW_PRE           "iwlwifi-QuZ-a0-hr-b0-"
  36 #define IWL_QUZ_A_JF_B_FW_PRE           "iwlwifi-QuZ-a0-jf-b0-"
  37 #define IWL_QNJ_B_JF_B_FW_PRE           "iwlwifi-QuQnj-b0-jf-b0-"
  38 #define IWL_CC_A_FW_PRE                 "iwlwifi-cc-a0-"
  39 #define IWL_SO_A_JF_B_FW_PRE            "iwlwifi-so-a0-jf-b0-"
  40 #define IWL_SO_A_HR_B_FW_PRE            "iwlwifi-so-a0-hr-b0-"
  41 #define IWL_SO_A_GF_A_FW_PRE            "iwlwifi-so-a0-gf-a0-"
  42 #define IWL_TY_A_GF_A_FW_PRE            "iwlwifi-ty-a0-gf-a0-"
  43 #define IWL_SO_A_GF4_A_FW_PRE           "iwlwifi-so-a0-gf4-a0-"
  44 #define IWL_SO_A_MR_A_FW_PRE            "iwlwifi-so-a0-mr-a0-"
  45 #define IWL_SNJ_A_GF4_A_FW_PRE          "iwlwifi-SoSnj-a0-gf4-a0-"
  46 #define IWL_SNJ_A_GF_A_FW_PRE           "iwlwifi-SoSnj-a0-gf-a0-"
  47 #define IWL_SNJ_A_HR_B_FW_PRE           "iwlwifi-SoSnj-a0-hr-b0-"
  48 #define IWL_SNJ_A_JF_B_FW_PRE           "iwlwifi-SoSnj-a0-jf-b0-"
  49 #define IWL_MA_A_HR_B_FW_PRE            "iwlwifi-ma-a0-hr-b0-"
  50 #define IWL_MA_A_GF_A_FW_PRE            "iwlwifi-ma-a0-gf-a0-"
  51 #define IWL_MA_A_GF4_A_FW_PRE           "iwlwifi-ma-a0-gf4-a0-"
  52 #define IWL_MA_A_MR_A_FW_PRE            "iwlwifi-ma-a0-mr-a0-"
  53 #define IWL_MA_A_FM_A_FW_PRE            "iwlwifi-ma-a0-fm-a0-"
  54 #define IWL_MA_B_HR_B_FW_PRE            "iwlwifi-ma-b0-hr-b0-"
  55 #define IWL_MA_B_GF_A_FW_PRE            "iwlwifi-ma-b0-gf-a0-"
  56 #define IWL_MA_B_GF4_A_FW_PRE           "iwlwifi-ma-b0-gf4-a0-"
  57 #define IWL_MA_B_MR_A_FW_PRE            "iwlwifi-ma-b0-mr-a0-"
  58 #define IWL_MA_B_FM_A_FW_PRE            "iwlwifi-ma-b0-fm-a0-"
  59 #define IWL_SNJ_A_MR_A_FW_PRE           "iwlwifi-SoSnj-a0-mr-a0-"
  60 #define IWL_BZ_A_HR_A_FW_PRE            "iwlwifi-bz-a0-hr-b0-"
  61 #define IWL_BZ_A_HR_B_FW_PRE            "iwlwifi-bz-a0-hr-b0-"
  62 #define IWL_BZ_A_GF_A_FW_PRE            "iwlwifi-bz-a0-gf-a0-"
  63 #define IWL_BZ_A_GF4_A_FW_PRE           "iwlwifi-bz-a0-gf4-a0-"
  64 #define IWL_BZ_A_MR_A_FW_PRE            "iwlwifi-bz-a0-mr-a0-"
  65 #define IWL_BZ_A_FM_A_FW_PRE            "iwlwifi-bz-a0-fm-a0-"
  66 #define IWL_BZ_A_FM4_A_FW_PRE           "iwlwifi-bz-a0-fm4-a0-"
  67 #define IWL_BZ_A_FM_B_FW_PRE            "iwlwifi-bz-a0-fm-b0-"
  68 #define IWL_BZ_A_FM4_B_FW_PRE           "iwlwifi-bz-a0-fm4-b0-"
  69 #define IWL_GL_A_FM_A_FW_PRE            "iwlwifi-gl-a0-fm-a0-"
  70 #define IWL_GL_B_FM_B_FW_PRE            "iwlwifi-gl-b0-fm-b0-"
  71 #define IWL_BZ_Z_GF_A_FW_PRE            "iwlwifi-bz-z0-gf-a0-"
  72 #define IWL_BNJ_A_FM_A_FW_PRE           "iwlwifi-BzBnj-a0-fm-a0-"
  73 #define IWL_BNJ_A_FM4_A_FW_PRE          "iwlwifi-BzBnj-a0-fm4-a0-"
  74 #define IWL_BNJ_B_FM4_B_FW_PRE          "iwlwifi-BzBnj-b0-fm4-b0-"
  75 #define IWL_BNJ_A_GF_A_FW_PRE           "iwlwifi-BzBnj-a0-gf-a0-"
  76 #define IWL_BNJ_B_GF_A_FW_PRE           "iwlwifi-BzBnj-b0-gf-a0-"
  77 #define IWL_BNJ_A_GF4_A_FW_PRE          "iwlwifi-BzBnj-a0-gf4-a0-"
  78 #define IWL_BNJ_B_GF4_A_FW_PRE          "iwlwifi-BzBnj-b0-gf4-a0-"
  79 #define IWL_BNJ_A_HR_A_FW_PRE           "iwlwifi-BzBnj-a0-hr-b0-"
  80 #define IWL_BNJ_A_HR_B_FW_PRE           "iwlwifi-BzBnj-a0-hr-b0-"
  81 #define IWL_BNJ_B_HR_A_FW_PRE           "iwlwifi-BzBnj-b0-hr-b0-"
  82 #define IWL_BNJ_B_HR_B_FW_PRE           "iwlwifi-BzBnj-b0-hr-b0-"
  83 #define IWL_BNJ_B_FM_B_FW_PRE           "iwlwifi-BzBnj-b0-fm-b0-"
  84
  85
  86 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \
  87         IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode"
  88 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api)     \
  89         IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode"
  90 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \
  91         IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
  92 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \
  93         IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode"
  94 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \
  95         IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode"
  96 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \
  97         IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode"
  98 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api)             \
  99         IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode"
 100 #define IWL_CC_A_MODULE_FIRMWARE(api)                   \
 101         IWL_CC_A_FW_PRE __stringify(api) ".ucode"
 102 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \
 103         IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode"
 104 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \
 105         IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode"
 106 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \
 107         IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode"
 108 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \
 109         IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode"
 110 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \
 111         IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
 112 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \
 113         IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
 114 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \
 115         IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
 116 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \
 117         IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode"
 118 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api)           \
 119         IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode"
 120 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api)           \
 121         IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode"
 122 #define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api)          \
 123         IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode"
 124 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \
 125         IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode"
 126 #define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api)           \
 127         IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode"
 128 #define IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(api)           \
 129         IWL_MA_B_HR_B_FW_PRE __stringify(api) ".ucode"
 130 #define IWL_MA_B_GF_A_FW_MODULE_FIRMWARE(api)           \
 131         IWL_MA_B_GF_A_FW_PRE __stringify(api) ".ucode"
 132 #define IWL_MA_B_GF4_A_FW_MODULE_FIRMWARE(api)          \
 133         IWL_MA_B_GF4_A_FW_PRE __stringify(api) ".ucode"
 134 #define IWL_MA_B_MR_A_FW_MODULE_FIRMWARE(api) \
 135         IWL_MA_B_MR_A_FW_PRE __stringify(api) ".ucode"
 136 #define IWL_MA_B_FM_A_FW_MODULE_FIRMWARE(api)           \
 137         IWL_MA_B_FM_A_FW_PRE __stringify(api) ".ucode"
 138 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \
 139         IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode"
 140 #define IWL_BZ_A_HR_A_MODULE_FIRMWARE(api) \
 141         IWL_BZ_A_HR_A_FW_PRE __stringify(api) ".ucode"
 142 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \
 143         IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
 144 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \
 145         IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode"
 146 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \
 147         IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
 148 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \
 149         IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode"
 150 #define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \
 151         IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode"
 152 #define IWL_BZ_A_FM4_A_MODULE_FIRMWARE(api) \
 153         IWL_BZ_A_FM4_A_FW_PRE __stringify(api) ".ucode"
 154 #define IWL_BZ_A_FM_B_MODULE_FIRMWARE(api) \
 155         IWL_BZ_A_FM_B_FW_PRE __stringify(api) ".ucode"
 156 #define IWL_BZ_A_FM4_B_MODULE_FIRMWARE(api) \
 157         IWL_BZ_A_FM4_B_FW_PRE __stringify(api) ".ucode"
 158 #define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \
 159         IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode"
 160 #define IWL_GL_B_FM_B_MODULE_FIRMWARE(api) \
 161         IWL_GL_B_FM_B_FW_PRE __stringify(api) ".ucode"
 162 #define IWL_BNJ_A_FM_A_MODULE_FIRMWARE(api) \
 163         IWL_BNJ_A_FM_A_FW_PRE __stringify(api) ".ucode"
 164 #define IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(api) \
 165         IWL_BNJ_A_FM4_A_FW_PRE __stringify(api) ".ucode"
 166 #define IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(api) \
 167         IWL_BNJ_B_FM4_B_FW_PRE __stringify(api) ".ucode"
 168 #define IWL_BNJ_A_GF_A_MODULE_FIRMWARE(api) \
 169         IWL_BNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
 170 #define IWL_BNJ_B_GF_A_MODULE_FIRMWARE(api) \
 171         IWL_BNJ_B_GF_A_FW_PRE __stringify(api) ".ucode"
 172 #define IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(api) \
 173         IWL_BNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
 174 #define IWL_BNJ_B_GF4_A_MODULE_FIRMWARE(api) \
 175         IWL_BNJ_B_GF4_A_FW_PRE __stringify(api) ".ucode"
 176 #define IWL_BNJ_A_HR_A_MODULE_FIRMWARE(api) \
 177         IWL_BNJ_A_HR_A_FW_PRE __stringify(api) ".ucode"
 178 #define IWL_BNJ_A_HR_B_MODULE_FIRMWARE(api) \
 179         IWL_BNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
 180 #define IWL_BNJ_B_HR_A_MODULE_FIRMWARE(api) \
 181         IWL_BNJ_B_HR_A_FW_PRE __stringify(api) ".ucode"
 182 #define IWL_BNJ_B_HR_B_MODULE_FIRMWARE(api) \
 183         IWL_BNJ_B_HR_B_FW_PRE __stringify(api) ".ucode"
 184 #define IWL_BNJ_B_FM_B_MODULE_FIRMWARE(api) \
 185         IWL_BNJ_B_FM_B_FW_PRE __stringify(api) ".ucode"
 186
 187 static const struct iwl_base_params iwl_22000_base_params = {
 188         .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
 189         .num_of_queues = 512,
 190         .max_tfd_queue_size = 256,
 191         .shadow_ram_support = true,
 192         .led_compensation = 57,
 193         .wd_timeout = IWL_LONG_WD_TIMEOUT,
 194         .max_event_log_size = 512,
 195         .shadow_reg_enable = true,
 196         .pcie_l1_allowed = true,
 197 };
 198
 199 static const struct iwl_base_params iwl_ax210_base_params = {
 200         .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
 201         .num_of_queues = 512,
 202         .max_tfd_queue_size = 65536,
 203         .shadow_ram_support = true,
 204         .led_compensation = 57,
 205         .wd_timeout = IWL_LONG_WD_TIMEOUT,
 206         .max_event_log_size = 512,
 207         .shadow_reg_enable = true,
 208         .pcie_l1_allowed = true,
 209 };
 210
 211 static const struct iwl_ht_params iwl_22000_ht_params = {
 212         .stbc = true,
 213         .ldpc = true,
 214         .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
 215                       BIT(NL80211_BAND_6GHZ),
 216 };
 217
 218 static const struct iwl_ht_params iwl_gl_a_ht_params = {
 219         .stbc = false, /* we explicitly disable STBC for GL step A */
 220         .ldpc = true,
 221         .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
 222                       BIT(NL80211_BAND_6GHZ),
 223 };
 224
 225 #define IWL_DEVICE_22000_COMMON                                         \
 226         .ucode_api_min = IWL_22000_UCODE_API_MIN,                       \
 227         .led_mode = IWL_LED_RF_STATE,                                   \
 228         .nvm_hw_section_num = 10,                                       \
 229         .non_shared_ant = ANT_B,                                        \
 230         .dccm_offset = IWL_22000_DCCM_OFFSET,                           \
 231         .dccm_len = IWL_22000_DCCM_LEN,                                 \
 232         .dccm2_offset = IWL_22000_DCCM2_OFFSET,                         \
 233         .dccm2_len = IWL_22000_DCCM2_LEN,                               \
 234         .smem_offset = IWL_22000_SMEM_OFFSET,                           \
 235         .smem_len = IWL_22000_SMEM_LEN,                                 \
 236         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,           \
 237         .apmg_not_supported = true,                                     \
 238         .trans.mq_rx_supported = true,                                  \
 239         .vht_mu_mimo_supported = true,                                  \
 240         .mac_addr_from_csr = 0x380,                                     \
 241         .ht_params = &iwl_22000_ht_params,                              \
 242         .nvm_ver = IWL_22000_NVM_VERSION,                               \
 243         .trans.use_tfh = true,                                          \
 244         .trans.rf_id = true,                                            \
 245         .trans.gen2 = true,                                             \
 246         .nvm_type = IWL_NVM_EXT,                                        \
 247         .dbgc_supported = true,                                         \
 248         .min_umac_error_event_table = 0x400000,                         \
 249         .d3_debug_data_base_addr = 0x401000,                            \
 250         .d3_debug_data_length = 60 * 1024,                              \
 251         .mon_smem_regs = {                                              \
 252                 .write_ptr = {                                          \
 253                         .addr = LDBG_M2S_BUF_WPTR,                      \
 254                         .mask = LDBG_M2S_BUF_WPTR_VAL_MSK,              \
 255         },                                                              \
 256                 .cycle_cnt = {                                          \
 257                         .addr = LDBG_M2S_BUF_WRAP_CNT,                  \
 258                         .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK,          \
 259                 },                                                      \
 260         }
 261
 262 #define IWL_DEVICE_22500                                                \
 263         IWL_DEVICE_22000_COMMON,                                        \
 264         .ucode_api_max = IWL_22500_UCODE_API_MAX,                       \
 265         .trans.device_family = IWL_DEVICE_FAMILY_22000,                 \
 266         .trans.base_params = &iwl_22000_base_params,                    \
 267         .gp2_reg_addr = 0xa02c68,                                       \
 268         .mon_dram_regs = {                                              \
 269                 .write_ptr = {                                          \
 270                         .addr = MON_BUFF_WRPTR_VER2,                    \
 271                         .mask = 0xffffffff,                             \
 272                 },                                                      \
 273                 .cycle_cnt = {                                          \
 274                         .addr = MON_BUFF_CYCLE_CNT_VER2,                \
 275                         .mask = 0xffffffff,                             \
 276                 },                                                      \
 277         }
 278
 279 #define IWL_DEVICE_AX210                                                \
 280         IWL_DEVICE_22000_COMMON,                                        \
 281         .ucode_api_max = IWL_22000_UCODE_API_MAX,                       \
 282         .trans.umac_prph_offset = 0x300000,                             \
 283         .trans.device_family = IWL_DEVICE_FAMILY_AX210,                 \
 284         .trans.base_params = &iwl_ax210_base_params,                    \
 285         .min_txq_size = 128,                                            \
 286         .gp2_reg_addr = 0xd02c68,                                       \
 287         .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE,           \
 288         .mon_dram_regs = {                                              \
 289                 .write_ptr = {                                          \
 290                         .addr = DBGC_CUR_DBGBUF_STATUS,                 \
 291                         .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK,      \
 292                 },                                                      \
 293                 .cycle_cnt = {                                          \
 294                         .addr = DBGC_DBGBUF_WRAP_AROUND,                \
 295                         .mask = 0xffffffff,                             \
 296                 },                                                      \
 297                 .cur_frag = {                                           \
 298                         .addr = DBGC_CUR_DBGBUF_STATUS,                 \
 299                         .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK,         \
 300                 },                                                      \
 301         }
 302
 303 #define IWL_DEVICE_BZ_COMMON                                            \
 304         .ucode_api_max = IWL_22000_UCODE_API_MAX,                       \
 305         .ucode_api_min = IWL_22000_UCODE_API_MIN,                       \
 306         .led_mode = IWL_LED_RF_STATE,                                   \
 307         .nvm_hw_section_num = 10,                                       \
 308         .non_shared_ant = ANT_B,                                        \
 309         .dccm_offset = IWL_22000_DCCM_OFFSET,                           \
 310         .dccm_len = IWL_22000_DCCM_LEN,                                 \
 311         .dccm2_offset = IWL_22000_DCCM2_OFFSET,                         \
 312         .dccm2_len = IWL_22000_DCCM2_LEN,                               \
 313         .smem_offset = IWL_22000_SMEM_OFFSET,                           \
 314         .smem_len = IWL_22000_SMEM_LEN,                                 \
 315         .apmg_not_supported = true,                                     \
 316         .trans.mq_rx_supported = true,                                  \
 317         .vht_mu_mimo_supported = true,                                  \
 318         .mac_addr_from_csr = 0x30,                                      \
 319         .nvm_ver = IWL_22000_NVM_VERSION,                               \
 320         .trans.use_tfh = true,                                          \
 321         .trans.rf_id = true,                                            \
 322         .trans.gen2 = true,                                             \
 323         .nvm_type = IWL_NVM_EXT,                                        \
 324         .dbgc_supported = true,                                         \
 325         .min_umac_error_event_table = 0xD0000,                          \
 326         .d3_debug_data_base_addr = 0x401000,                            \
 327         .d3_debug_data_length = 60 * 1024,                              \
 328         .mon_smem_regs = {                                              \
 329                 .write_ptr = {                                          \
 330                         .addr = LDBG_M2S_BUF_WPTR,                      \
 331                         .mask = LDBG_M2S_BUF_WPTR_VAL_MSK,              \
 332         },                                                              \
 333                 .cycle_cnt = {                                          \
 334                         .addr = LDBG_M2S_BUF_WRAP_CNT,                  \
 335                         .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK,          \
 336                 },                                                      \
 337         },                                                              \
 338         .trans.umac_prph_offset = 0x300000,                             \
 339         .trans.device_family = IWL_DEVICE_FAMILY_BZ,                    \
 340         .trans.base_params = &iwl_ax210_base_params,                    \
 341         .min_txq_size = 128,                                            \
 342         .gp2_reg_addr = 0xd02c68,                                       \
 343         .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT,                  \
 344         .mon_dram_regs = {                                              \
 345                 .write_ptr = {                                          \
 346                         .addr = DBGC_CUR_DBGBUF_STATUS,                 \
 347                         .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK,      \
 348                 },                                                      \
 349                 .cycle_cnt = {                                          \
 350                         .addr = DBGC_DBGBUF_WRAP_AROUND,                \
 351                         .mask = 0xffffffff,                             \
 352                 },                                                      \
 353                 .cur_frag = {                                           \
 354                         .addr = DBGC_CUR_DBGBUF_STATUS,                 \
 355                         .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK,         \
 356                 },                                                      \
 357         },                                                              \
 358         .mon_dbgi_regs = {                                              \
 359                 .write_ptr = {                                          \
 360                         .addr = DBGI_SRAM_FIFO_POINTERS,                \
 361                         .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK,     \
 362                 },                                                      \
 363         }
 364
 365 #define IWL_DEVICE_BZ                                                   \
 366         IWL_DEVICE_BZ_COMMON,                                           \
 367         .ht_params = &iwl_22000_ht_params
 368
 369 #define IWL_DEVICE_GL_A                                                 \
 370         IWL_DEVICE_BZ_COMMON,                                           \
 371         .ht_params = &iwl_gl_a_ht_params
 372
 373 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = {
 374         .mq_rx_supported = true,
 375         .use_tfh = true,
 376         .rf_id = true,
 377         .gen2 = true,
 378         .device_family = IWL_DEVICE_FAMILY_22000,
 379         .base_params = &iwl_22000_base_params,
 380 };
 381
 382 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = {
 383         .mq_rx_supported = true,
 384         .use_tfh = true,
 385         .rf_id = true,
 386         .gen2 = true,
 387         .device_family = IWL_DEVICE_FAMILY_22000,
 388         .base_params = &iwl_22000_base_params,
 389         .integrated = true,
 390         .xtal_latency = 500,
 391         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
 392 };
 393
 394 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = {
 395         .mq_rx_supported = true,
 396         .use_tfh = true,
 397         .rf_id = true,
 398         .gen2 = true,
 399         .device_family = IWL_DEVICE_FAMILY_22000,
 400         .base_params = &iwl_22000_base_params,
 401         .integrated = true,
 402         .xtal_latency = 1820,
 403         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US,
 404 };
 405
 406 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = {
 407         .mq_rx_supported = true,
 408         .use_tfh = true,
 409         .rf_id = true,
 410         .gen2 = true,
 411         .device_family = IWL_DEVICE_FAMILY_22000,
 412         .base_params = &iwl_22000_base_params,
 413         .integrated = true,
 414         .xtal_latency = 12000,
 415         .low_latency_xtal = true,
 416         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
 417 };
 418
 419 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = {
 420         .mq_rx_supported = true,
 421         .use_tfh = true,
 422         .rf_id = true,
 423         .gen2 = true,
 424         .device_family = IWL_DEVICE_FAMILY_AX210,
 425         .base_params = &iwl_ax210_base_params,
 426         .umac_prph_offset = 0x300000,
 427 };
 428
 429 const struct iwl_cfg_trans_params iwl_so_trans_cfg = {
 430         .mq_rx_supported = true,
 431         .use_tfh = true,
 432         .rf_id = true,
 433         .gen2 = true,
 434         .device_family = IWL_DEVICE_FAMILY_AX210,
 435         .base_params = &iwl_ax210_base_params,
 436         .umac_prph_offset = 0x300000,
 437         .integrated = true,
 438         /* TODO: the following values need to be checked */
 439         .xtal_latency = 500,
 440         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
 441 };
 442
 443 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = {
 444         .mq_rx_supported = true,
 445         .use_tfh = true,
 446         .rf_id = true,
 447         .gen2 = true,
 448         .device_family = IWL_DEVICE_FAMILY_AX210,
 449         .base_params = &iwl_ax210_base_params,
 450         .umac_prph_offset = 0x300000,
 451         .integrated = true,
 452         .low_latency_xtal = true,
 453         .xtal_latency = 12000,
 454         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
 455 };
 456
 457 const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = {
 458         .mq_rx_supported = true,
 459         .use_tfh = true,
 460         .rf_id = true,
 461         .gen2 = true,
 462         .device_family = IWL_DEVICE_FAMILY_AX210,
 463         .base_params = &iwl_ax210_base_params,
 464         .umac_prph_offset = 0x300000,
 465         .integrated = true,
 466         .low_latency_xtal = true,
 467         .xtal_latency = 12000,
 468         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
 469         .imr_enabled = true,
 470 };
 471
 472 /*
 473  * If the device doesn't support HE, no need to have that many buffers.
 474  * 22000 devices can split multiple frames into a single RB, so fewer are
 475  * needed; AX210 cannot (but use smaller RBs by default) - these sizes
 476  * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with
 477  * additional overhead to account for processing time.
 478  */
 479 #define IWL_NUM_RBDS_NON_HE             512
 480 #define IWL_NUM_RBDS_22000_HE           2048
 481 #define IWL_NUM_RBDS_AX210_HE           4096
 482
 483 /*
 484  * All JF radio modules are part of the 9000 series, but the MAC part
 485  * looks more like 22000.  That's why this device is here, but called
 486  * 9560 nevertheless.
 487  */
 488 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = {
 489         .fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
 490         IWL_DEVICE_22500,
 491         .num_rbds = IWL_NUM_RBDS_NON_HE,
 492 };
 493
 494 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = {
 495         .fw_name_pre = IWL_QU_C_JF_B_FW_PRE,
 496         IWL_DEVICE_22500,
 497         .num_rbds = IWL_NUM_RBDS_NON_HE,
 498 };
 499
 500 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = {
 501         .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE,
 502         IWL_DEVICE_22500,
 503         /*
 504          * This device doesn't support receiving BlockAck with a large bitmap
 505          * so we need to restrict the size of transmitted aggregation to the
 506          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 507          */
 508         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 509         .num_rbds = IWL_NUM_RBDS_NON_HE,
 510 };
 511
 512 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = {
 513         .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE,
 514         IWL_DEVICE_22500,
 515         /*
 516          * This device doesn't support receiving BlockAck with a large bitmap
 517          * so we need to restrict the size of transmitted aggregation to the
 518          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 519          */
 520         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 521         .num_rbds = IWL_NUM_RBDS_NON_HE,
 522 };
 523
 524 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = {
 525         .device_family = IWL_DEVICE_FAMILY_22000,
 526         .base_params = &iwl_22000_base_params,
 527         .mq_rx_supported = true,
 528         .use_tfh = true,
 529         .rf_id = true,
 530         .gen2 = true,
 531         .bisr_workaround = 1,
 532 };
 533
 534 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = {
 535         .device_family = IWL_DEVICE_FAMILY_AX210,
 536         .base_params = &iwl_ax210_base_params,
 537         .mq_rx_supported = true,
 538         .use_tfh = true,
 539         .rf_id = true,
 540         .gen2 = true,
 541         .integrated = true,
 542         .umac_prph_offset = 0x300000
 543 };
 544
 545 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = {
 546         .device_family = IWL_DEVICE_FAMILY_BZ,
 547         .base_params = &iwl_ax210_base_params,
 548         .mq_rx_supported = true,
 549         .use_tfh = true,
 550         .rf_id = true,
 551         .gen2 = true,
 552         .integrated = true,
 553         .umac_prph_offset = 0x300000,
 554         .xtal_latency = 12000,
 555         .low_latency_xtal = true,
 556         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
 557 };
 558
 559 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101";
 560 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz";
 561 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz";
 562 const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203";
 563 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz";
 564 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz";
 565 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz";
 566 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz";
 567 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz";
 568 const char iwl_bz_name[] = "Intel(R) TBD Bz device";
 569
 570 const char iwl_ax200_killer_1650w_name[] =
 571         "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)";
 572 const char iwl_ax200_killer_1650x_name[] =
 573         "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)";
 574 const char iwl_ax201_killer_1650s_name[] =
 575         "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)";
 576 const char iwl_ax201_killer_1650i_name[] =
 577         "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)";
 578 const char iwl_ax210_killer_1675w_name[] =
 579         "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)";
 580 const char iwl_ax210_killer_1675x_name[] =
 581         "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)";
 582 const char iwl_ax211_killer_1675s_name[] =
 583         "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)";
 584 const char iwl_ax211_killer_1675i_name[] =
 585         "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)";
 586 const char iwl_ax411_killer_1690s_name[] =
 587         "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)";
 588 const char iwl_ax411_killer_1690i_name[] =
 589         "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)";
 590
 591 const struct iwl_cfg iwl_qu_b0_hr1_b0 = {
 592         .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
 593         IWL_DEVICE_22500,
 594         /*
 595          * This device doesn't support receiving BlockAck with a large bitmap
 596          * so we need to restrict the size of transmitted aggregation to the
 597          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 598          */
 599         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 600         .tx_with_siso_diversity = true,
 601         .num_rbds = IWL_NUM_RBDS_22000_HE,
 602 };
 603
 604 const struct iwl_cfg iwl_qu_b0_hr_b0 = {
 605         .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
 606         IWL_DEVICE_22500,
 607         /*
 608          * This device doesn't support receiving BlockAck with a large bitmap
 609          * so we need to restrict the size of transmitted aggregation to the
 610          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 611          */
 612         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 613         .num_rbds = IWL_NUM_RBDS_22000_HE,
 614 };
 615
 616 const struct iwl_cfg iwl_ax201_cfg_qu_hr = {
 617         .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
 618         .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
 619         IWL_DEVICE_22500,
 620         /*
 621          * This device doesn't support receiving BlockAck with a large bitmap
 622          * so we need to restrict the size of transmitted aggregation to the
 623          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 624          */
 625         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 626         .num_rbds = IWL_NUM_RBDS_22000_HE,
 627 };
 628
 629 const struct iwl_cfg iwl_qu_c0_hr1_b0 = {
 630         .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
 631         IWL_DEVICE_22500,
 632         /*
 633          * This device doesn't support receiving BlockAck with a large bitmap
 634          * so we need to restrict the size of transmitted aggregation to the
 635          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 636          */
 637         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 638         .tx_with_siso_diversity = true,
 639         .num_rbds = IWL_NUM_RBDS_22000_HE,
 640 };
 641
 642 const struct iwl_cfg iwl_qu_c0_hr_b0 = {
 643         .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
 644         IWL_DEVICE_22500,
 645         /*
 646          * This device doesn't support receiving BlockAck with a large bitmap
 647          * so we need to restrict the size of transmitted aggregation to the
 648          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 649          */
 650         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 651         .num_rbds = IWL_NUM_RBDS_22000_HE,
 652 };
 653
 654 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = {
 655         .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
 656         .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
 657         IWL_DEVICE_22500,
 658         /*
 659          * This device doesn't support receiving BlockAck with a large bitmap
 660          * so we need to restrict the size of transmitted aggregation to the
 661          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 662          */
 663         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 664         .num_rbds = IWL_NUM_RBDS_22000_HE,
 665 };
 666
 667 const struct iwl_cfg iwl_quz_a0_hr1_b0 = {
 668         .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
 669         IWL_DEVICE_22500,
 670         /*
 671          * This device doesn't support receiving BlockAck with a large bitmap
 672          * so we need to restrict the size of transmitted aggregation to the
 673          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 674          */
 675         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 676         .tx_with_siso_diversity = true,
 677         .num_rbds = IWL_NUM_RBDS_22000_HE,
 678 };
 679
 680 const struct iwl_cfg iwl_ax201_cfg_quz_hr = {
 681         .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
 682         .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
 683         IWL_DEVICE_22500,
 684         /*
 685          * This device doesn't support receiving BlockAck with a large bitmap
 686          * so we need to restrict the size of transmitted aggregation to the
 687          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 688          */
 689         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 690         .num_rbds = IWL_NUM_RBDS_22000_HE,
 691 };
 692
 693 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = {
 694         .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)",
 695         .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
 696         IWL_DEVICE_22500,
 697         /*
 698          * This device doesn't support receiving BlockAck with a large bitmap
 699          * so we need to restrict the size of transmitted aggregation to the
 700          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 701          */
 702         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 703         .num_rbds = IWL_NUM_RBDS_22000_HE,
 704 };
 705
 706 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = {
 707         .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)",
 708         .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
 709         IWL_DEVICE_22500,
 710         /*
 711          * This device doesn't support receiving BlockAck with a large bitmap
 712          * so we need to restrict the size of transmitted aggregation to the
 713          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 714          */
 715         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 716         .num_rbds = IWL_NUM_RBDS_22000_HE,
 717 };
 718
 719 const struct iwl_cfg iwl_ax200_cfg_cc = {
 720         .fw_name_pre = IWL_CC_A_FW_PRE,
 721         IWL_DEVICE_22500,
 722         /*
 723          * This device doesn't support receiving BlockAck with a large bitmap
 724          * so we need to restrict the size of transmitted aggregation to the
 725          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 726          */
 727         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 728         .num_rbds = IWL_NUM_RBDS_22000_HE,
 729 };
 730
 731 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = {
 732         .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)",
 733         .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
 734         IWL_DEVICE_22500,
 735         /*
 736          * This device doesn't support receiving BlockAck with a large bitmap
 737          * so we need to restrict the size of transmitted aggregation to the
 738          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 739          */
 740         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 741         .num_rbds = IWL_NUM_RBDS_22000_HE,
 742 };
 743
 744 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = {
 745         .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)",
 746         .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
 747         IWL_DEVICE_22500,
 748         /*
 749          * This device doesn't support receiving BlockAck with a large bitmap
 750          * so we need to restrict the size of transmitted aggregation to the
 751          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 752          */
 753         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 754         .num_rbds = IWL_NUM_RBDS_22000_HE,
 755 };
 756
 757 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = {
 758         .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)",
 759         .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
 760         IWL_DEVICE_22500,
 761         /*
 762          * This device doesn't support receiving BlockAck with a large bitmap
 763          * so we need to restrict the size of transmitted aggregation to the
 764          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 765          */
 766         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 767         .num_rbds = IWL_NUM_RBDS_22000_HE,
 768 };
 769
 770 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = {
 771         .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)",
 772         .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
 773         IWL_DEVICE_22500,
 774         /*
 775          * This device doesn't support receiving BlockAck with a large bitmap
 776          * so we need to restrict the size of transmitted aggregation to the
 777          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 778          */
 779         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 780         .num_rbds = IWL_NUM_RBDS_22000_HE,
 781 };
 782
 783 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = {
 784         .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE,
 785         IWL_DEVICE_22500,
 786         /*
 787          * This device doesn't support receiving BlockAck with a large bitmap
 788          * so we need to restrict the size of transmitted aggregation to the
 789          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 790          */
 791         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 792         .num_rbds = IWL_NUM_RBDS_22000_HE,
 793 };
 794
 795 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = {
 796         .name = "Intel(R) Wireless-AC 9560 160MHz",
 797         .fw_name_pre = IWL_SO_A_JF_B_FW_PRE,
 798         IWL_DEVICE_AX210,
 799         .num_rbds = IWL_NUM_RBDS_NON_HE,
 800 };
 801
 802 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = {
 803         .name = iwl_ax211_name,
 804         .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
 805         .uhb_supported = true,
 806         IWL_DEVICE_AX210,
 807         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 808 };
 809
 810 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = {
 811         .name = iwl_ax211_name,
 812         .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
 813         .uhb_supported = true,
 814         IWL_DEVICE_AX210,
 815         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 816         .trans.xtal_latency = 12000,
 817         .trans.low_latency_xtal = true,
 818 };
 819
 820 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = {
 821         .name = "Intel(R) Wi-Fi 6 AX210 160MHz",
 822         .fw_name_pre = IWL_TY_A_GF_A_FW_PRE,
 823         .uhb_supported = true,
 824         IWL_DEVICE_AX210,
 825         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 826 };
 827
 828 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = {
 829         .name = iwl_ax411_name,
 830         .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
 831         .uhb_supported = true,
 832         IWL_DEVICE_AX210,
 833         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 834 };
 835
 836 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = {
 837         .name = iwl_ax411_name,
 838         .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
 839         .uhb_supported = true,
 840         IWL_DEVICE_AX210,
 841         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 842         .trans.xtal_latency = 12000,
 843         .trans.low_latency_xtal = true,
 844 };
 845
 846 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = {
 847         .name = iwl_ax411_name,
 848         .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE,
 849         .uhb_supported = true,
 850         IWL_DEVICE_AX210,
 851         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 852 };
 853
 854 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = {
 855         .name = iwl_ax211_name,
 856         .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE,
 857         .uhb_supported = true,
 858         IWL_DEVICE_AX210,
 859         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 860 };
 861
 862 const struct iwl_cfg iwl_cfg_snj_hr_b0 = {
 863         .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE,
 864         .uhb_supported = true,
 865         IWL_DEVICE_AX210,
 866         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 867 };
 868
 869 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = {
 870         .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE,
 871         .uhb_supported = true,
 872         IWL_DEVICE_AX210,
 873         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 874 };
 875
 876 const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = {
 877         .fw_name_pre = IWL_MA_A_HR_B_FW_PRE,
 878         .uhb_supported = true,
 879         IWL_DEVICE_AX210,
 880         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 881 };
 882
 883 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = {
 884         .fw_name_pre = IWL_MA_A_GF_A_FW_PRE,
 885         .uhb_supported = true,
 886         IWL_DEVICE_AX210,
 887         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 888 };
 889
 890 const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = {
 891         .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE,
 892         .uhb_supported = true,
 893         IWL_DEVICE_AX210,
 894         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 895 };
 896
 897 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = {
 898         .fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
 899         .uhb_supported = true,
 900         IWL_DEVICE_AX210,
 901         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 902 };
 903
 904 const struct iwl_cfg iwl_cfg_ma_a0_ms_a0 = {
 905         .fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
 906         .uhb_supported = false,
 907         IWL_DEVICE_AX210,
 908         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 909 };
 910
 911 const struct iwl_cfg iwl_cfg_ma_b0_fm_a0 = {
 912         .fw_name_pre = IWL_MA_B_FM_A_FW_PRE,
 913         .uhb_supported = true,
 914         IWL_DEVICE_AX210,
 915         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 916 };
 917
 918 const struct iwl_cfg iwl_cfg_ma_b0_hr_b0 = {
 919         .fw_name_pre = IWL_MA_B_HR_B_FW_PRE,
 920         .uhb_supported = true,
 921         IWL_DEVICE_AX210,
 922         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 923 };
 924
 925 const struct iwl_cfg iwl_cfg_ma_b0_gf_a0 = {
 926         .fw_name_pre = IWL_MA_B_GF_A_FW_PRE,
 927         .uhb_supported = true,
 928         IWL_DEVICE_AX210,
 929         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 930 };
 931
 932 const struct iwl_cfg iwl_cfg_ma_b0_gf4_a0 = {
 933         .fw_name_pre = IWL_MA_B_GF4_A_FW_PRE,
 934         .uhb_supported = true,
 935         IWL_DEVICE_AX210,
 936         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 937 };
 938
 939 const struct iwl_cfg iwl_cfg_ma_b0_mr_a0 = {
 940         .fw_name_pre = IWL_MA_B_MR_A_FW_PRE,
 941         .uhb_supported = true,
 942         IWL_DEVICE_AX210,
 943         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 944 };
 945
 946 const struct iwl_cfg iwl_cfg_so_a0_ms_a0 = {
 947         .fw_name_pre = IWL_SO_A_MR_A_FW_PRE,
 948         .uhb_supported = false,
 949         IWL_DEVICE_AX210,
 950         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 951 };
 952
 953 const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = {
 954         .fw_name_pre = IWL_MA_A_FM_A_FW_PRE,
 955         .uhb_supported = true,
 956         IWL_DEVICE_AX210,
 957         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 958 };
 959
 960 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = {
 961         .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
 962         .uhb_supported = true,
 963         IWL_DEVICE_AX210,
 964         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 965 };
 966
 967 const struct iwl_cfg iwl_cfg_snj_a0_ms_a0 = {
 968         .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
 969         .uhb_supported = false,
 970         IWL_DEVICE_AX210,
 971         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 972 };
 973
 974 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = {
 975         .fw_name_pre = IWL_SO_A_HR_B_FW_PRE,
 976         IWL_DEVICE_AX210,
 977         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 978 };
 979
 980 const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = {
 981         .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
 982         IWL_DEVICE_22500,
 983         /*
 984          * This device doesn't support receiving BlockAck with a large bitmap
 985          * so we need to restrict the size of transmitted aggregation to the
 986          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 987          */
 988         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 989         .num_rbds = IWL_NUM_RBDS_22000_HE,
 990 };
 991
 992 const struct iwl_cfg iwl_cfg_bz_a0_hr_a0 = {
 993         .fw_name_pre = IWL_BZ_A_HR_A_FW_PRE,
 994         .uhb_supported = true,
 995         IWL_DEVICE_BZ,
 996         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
 997         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 998 };
 999
1000 const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = {
1001         .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE,
1002         .uhb_supported = true,
1003         IWL_DEVICE_BZ,
1004         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1005         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1006 };
1007
1008 const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = {
1009         .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE,
1010         .uhb_supported = true,
1011         IWL_DEVICE_BZ,
1012         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1013         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1014 };
1015
1016 const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = {
1017         .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE,
1018         .uhb_supported = true,
1019         IWL_DEVICE_BZ,
1020         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1021         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1022 };
1023
1024 const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = {
1025         .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE,
1026         .uhb_supported = true,
1027         IWL_DEVICE_BZ,
1028         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1029         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1030 };
1031
1032 const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = {
1033         .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE,
1034         .uhb_supported = true,
1035         IWL_DEVICE_BZ,
1036         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1037         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1038 };
1039
1040 const struct iwl_cfg iwl_cfg_bz_a0_fm4_a0 = {
1041         .fw_name_pre = IWL_BZ_A_FM4_A_FW_PRE,
1042         .uhb_supported = true,
1043         IWL_DEVICE_BZ,
1044         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1045         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1046 };
1047
1048 const struct iwl_cfg iwl_cfg_bz_a0_fm_b0 = {
1049         .fw_name_pre = IWL_BZ_A_FM_B_FW_PRE,
1050         .uhb_supported = true,
1051         IWL_DEVICE_BZ,
1052         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1053         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1054 };
1055
1056 const struct iwl_cfg iwl_cfg_bz_a0_fm4_b0 = {
1057         .fw_name_pre = IWL_BZ_A_FM4_B_FW_PRE,
1058         .uhb_supported = true,
1059         IWL_DEVICE_BZ,
1060         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1061         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1062 };
1063
1064 const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = {
1065         .fw_name_pre = IWL_GL_A_FM_A_FW_PRE,
1066         .uhb_supported = true,
1067         IWL_DEVICE_GL_A,
1068         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1069         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1070 };
1071
1072 const struct iwl_cfg iwl_cfg_gl_b0_fm_b0 = {
1073         .fw_name_pre = IWL_GL_B_FM_B_FW_PRE,
1074         .uhb_supported = true,
1075         IWL_DEVICE_BZ,
1076         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1077         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1078 };
1079
1080 const struct iwl_cfg iwl_cfg_bz_z0_gf_a0 = {
1081         .fw_name_pre = IWL_BZ_Z_GF_A_FW_PRE,
1082         .uhb_supported = true,
1083         IWL_DEVICE_BZ,
1084         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1085         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1086 };
1087
1088 const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0 = {
1089         .fw_name_pre = IWL_BNJ_A_FM_A_FW_PRE,
1090         .uhb_supported = true,
1091         IWL_DEVICE_BZ,
1092         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1093         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1094 };
1095
1096 const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0 = {
1097         .fw_name_pre = IWL_BNJ_A_FM4_A_FW_PRE,
1098         .uhb_supported = true,
1099         IWL_DEVICE_BZ,
1100         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1101         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1102 };
1103
1104 const struct iwl_cfg iwl_cfg_bnj_b0_fm4_b0 = {
1105         .fw_name_pre = IWL_BNJ_B_FM4_B_FW_PRE,
1106         .uhb_supported = true,
1107         IWL_DEVICE_BZ,
1108         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1109         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1110 };
1111
1112 const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0 = {
1113         .fw_name_pre = IWL_BNJ_A_GF_A_FW_PRE,
1114         .uhb_supported = true,
1115         IWL_DEVICE_BZ,
1116         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1117         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1118 };
1119
1120 const struct iwl_cfg iwl_cfg_bnj_b0_gf_a0 = {
1121         .fw_name_pre = IWL_BNJ_B_GF_A_FW_PRE,
1122         .uhb_supported = true,
1123         IWL_DEVICE_BZ,
1124         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1125         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1126 };
1127
1128 const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0 = {
1129         .fw_name_pre = IWL_BNJ_A_GF4_A_FW_PRE,
1130         .uhb_supported = true,
1131         IWL_DEVICE_BZ,
1132         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1133         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1134 };
1135
1136 const struct iwl_cfg iwl_cfg_bnj_b0_gf4_a0 = {
1137         .fw_name_pre = IWL_BNJ_B_GF4_A_FW_PRE,
1138         .uhb_supported = true,
1139         IWL_DEVICE_BZ,
1140         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1141         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1142 };
1143
1144 const struct iwl_cfg iwl_cfg_bnj_a0_hr_a0 = {
1145         .fw_name_pre = IWL_BNJ_A_HR_A_FW_PRE,
1146         .uhb_supported = true,
1147         IWL_DEVICE_BZ,
1148         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1149         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1150 };
1151
1152 const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0 = {
1153         .fw_name_pre = IWL_BNJ_A_HR_B_FW_PRE,
1154         .uhb_supported = true,
1155         IWL_DEVICE_BZ,
1156         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1157         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1158 };
1159
1160 const struct iwl_cfg iwl_cfg_bnj_b0_hr_a0 = {
1161         .fw_name_pre = IWL_BNJ_B_HR_A_FW_PRE,
1162         .uhb_supported = true,
1163         IWL_DEVICE_BZ,
1164         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1165         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1166 };
1167
1168 const struct iwl_cfg iwl_cfg_bnj_b0_hr_b0 = {
1169         .fw_name_pre = IWL_BNJ_B_HR_B_FW_PRE,
1170         .uhb_supported = true,
1171         IWL_DEVICE_BZ,
1172         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1173         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1174 };
1175
1176 const struct iwl_cfg iwl_cfg_bnj_b0_fm_b0 = {
1177         .fw_name_pre = IWL_BNJ_B_FM_B_FW_PRE,
1178         .uhb_supported = true,
1179         IWL_DEVICE_BZ,
1180         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1181         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1182 };
1183 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1184 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1185 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1186 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1187 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1188 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1189 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1190 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1191 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1192 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1193 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1194 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1195 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1196 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1197 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1198 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1199 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1200 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1201 MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1202 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1203 MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1204 MODULE_FIRMWARE(IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1205 MODULE_FIRMWARE(IWL_MA_B_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1206 MODULE_FIRMWARE(IWL_MA_B_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1207 MODULE_FIRMWARE(IWL_MA_B_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1208 MODULE_FIRMWARE(IWL_MA_B_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1209 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1210 MODULE_FIRMWARE(IWL_BZ_A_HR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1211 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1212 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1213 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1214 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1215 MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1216 MODULE_FIRMWARE(IWL_BZ_A_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1217 MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1218 MODULE_FIRMWARE(IWL_BNJ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1219 MODULE_FIRMWARE(IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1220 MODULE_FIRMWARE(IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1221 MODULE_FIRMWARE(IWL_BNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1222 MODULE_FIRMWARE(IWL_BNJ_B_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1223 MODULE_FIRMWARE(IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1224 MODULE_FIRMWARE(IWL_BNJ_B_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1225 MODULE_FIRMWARE(IWL_BNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1226 MODULE_FIRMWARE(IWL_BNJ_B_HR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1227 MODULE_FIRMWARE(IWL_BNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1228 MODULE_FIRMWARE(IWL_BZ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1229 MODULE_FIRMWARE(IWL_BZ_A_FM4_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1230 MODULE_FIRMWARE(IWL_GL_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1231 MODULE_FIRMWARE(IWL_BNJ_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));