drivers/net/wireless/intel/iwlwifi/cfg/22000.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2015-2017 Intel Deutschland GmbH
   4  * Copyright (C) 2018-2023 Intel Corporation
   5  */
   6 #include <linux/module.h>
   7 #include <linux/stringify.h>
   8 #include "iwl-config.h"
   9 #include "iwl-prph.h"
  10 #include "fw/api/txq.h"
  11
  12 /* Highest firmware API version supported */
  13 #define IWL_22000_UCODE_API_MAX 81
  14 #define IWL_22500_UCODE_API_MAX 77
  15
  16 /* Lowest firmware API version supported */
  17 #define IWL_22000_UCODE_API_MIN 39
  18
  19 /* NVM versions */
  20 #define IWL_22000_NVM_VERSION           0x0a1d
  21
  22 /* Memory offsets and lengths */
  23 #define IWL_22000_DCCM_OFFSET           0x800000 /* LMAC1 */
  24 #define IWL_22000_DCCM_LEN              0x10000 /* LMAC1 */
  25 #define IWL_22000_DCCM2_OFFSET          0x880000
  26 #define IWL_22000_DCCM2_LEN             0x8000
  27 #define IWL_22000_SMEM_OFFSET           0x400000
  28 #define IWL_22000_SMEM_LEN              0xD0000
  29
  30 #define IWL_QU_B_HR_B_FW_PRE            "iwlwifi-Qu-b0-hr-b0-"
  31 #define IWL_QNJ_B_HR_B_FW_PRE           "iwlwifi-QuQnj-b0-hr-b0-"
  32 #define IWL_QU_C_HR_B_FW_PRE            "iwlwifi-Qu-c0-hr-b0-"
  33 #define IWL_QU_B_JF_B_FW_PRE            "iwlwifi-Qu-b0-jf-b0-"
  34 #define IWL_QU_C_JF_B_FW_PRE            "iwlwifi-Qu-c0-jf-b0-"
  35 #define IWL_QUZ_A_HR_B_FW_PRE           "iwlwifi-QuZ-a0-hr-b0-"
  36 #define IWL_QUZ_A_JF_B_FW_PRE           "iwlwifi-QuZ-a0-jf-b0-"
  37 #define IWL_QNJ_B_JF_B_FW_PRE           "iwlwifi-QuQnj-b0-jf-b0-"
  38 #define IWL_CC_A_FW_PRE                 "iwlwifi-cc-a0-"
  39 #define IWL_SO_A_JF_B_FW_PRE            "iwlwifi-so-a0-jf-b0-"
  40 #define IWL_SO_A_HR_B_FW_PRE            "iwlwifi-so-a0-hr-b0-"
  41 #define IWL_SO_A_GF_A_FW_PRE            "iwlwifi-so-a0-gf-a0-"
  42 #define IWL_TY_A_GF_A_FW_PRE            "iwlwifi-ty-a0-gf-a0-"
  43 #define IWL_SO_A_GF4_A_FW_PRE           "iwlwifi-so-a0-gf4-a0-"
  44 #define IWL_SO_A_MR_A_FW_PRE            "iwlwifi-so-a0-mr-a0-"
  45 #define IWL_SNJ_A_GF4_A_FW_PRE          "iwlwifi-SoSnj-a0-gf4-a0-"
  46 #define IWL_SNJ_A_GF_A_FW_PRE           "iwlwifi-SoSnj-a0-gf-a0-"
  47 #define IWL_SNJ_A_HR_B_FW_PRE           "iwlwifi-SoSnj-a0-hr-b0-"
  48 #define IWL_SNJ_A_JF_B_FW_PRE           "iwlwifi-SoSnj-a0-jf-b0-"
  49 #define IWL_MA_A_HR_B_FW_PRE            "iwlwifi-ma-a0-hr-b0-"
  50 #define IWL_MA_A_GF_A_FW_PRE            "iwlwifi-ma-a0-gf-a0-"
  51 #define IWL_MA_A_GF4_A_FW_PRE           "iwlwifi-ma-a0-gf4-a0-"
  52 #define IWL_MA_A_MR_A_FW_PRE            "iwlwifi-ma-a0-mr-a0-"
  53 #define IWL_MA_A_FM_A_FW_PRE            "iwlwifi-ma-a0-fm-a0-"
  54 #define IWL_MA_B_HR_B_FW_PRE            "iwlwifi-ma-b0-hr-b0-"
  55 #define IWL_MA_B_GF_A_FW_PRE            "iwlwifi-ma-b0-gf-a0-"
  56 #define IWL_MA_B_GF4_A_FW_PRE           "iwlwifi-ma-b0-gf4-a0-"
  57 #define IWL_MA_B_MR_A_FW_PRE            "iwlwifi-ma-b0-mr-a0-"
  58 #define IWL_MA_B_FM_A_FW_PRE            "iwlwifi-ma-b0-fm-a0-"
  59 #define IWL_SNJ_A_MR_A_FW_PRE           "iwlwifi-SoSnj-a0-mr-a0-"
  60 #define IWL_BZ_A_HR_A_FW_PRE            "iwlwifi-bz-a0-hr-b0-"
  61 #define IWL_BZ_A_HR_B_FW_PRE            "iwlwifi-bz-a0-hr-b0-"
  62 #define IWL_BZ_A_GF_A_FW_PRE            "iwlwifi-bz-a0-gf-a0-"
  63 #define IWL_BZ_A_GF4_A_FW_PRE           "iwlwifi-bz-a0-gf4-a0-"
  64 #define IWL_BZ_A_MR_A_FW_PRE            "iwlwifi-bz-a0-mr-a0-"
  65 #define IWL_BZ_A_FM_A_FW_PRE            "iwlwifi-bz-a0-fm-a0-"
  66 #define IWL_BZ_A_FM4_A_FW_PRE           "iwlwifi-bz-a0-fm4-a0-"
  67 #define IWL_BZ_A_FM_B_FW_PRE            "iwlwifi-bz-a0-fm-b0-"
  68 #define IWL_BZ_A_FM_C_FW_PRE            "iwlwifi-bz-a0-fm-c0-"
  69 #define IWL_BZ_A_FM4_B_FW_PRE           "iwlwifi-bz-a0-fm4-b0-"
  70 #define IWL_BZ_B_GF_A_FW_PRE            "iwlwifi-bz-b0-gf-a0-"
  71 #define IWL_BZ_B_GF4_A_FW_PRE           "iwlwifi-bz-b0-gf4-a0-"
  72 #define IWL_BZ_B_FM_B_FW_PRE            "iwlwifi-bz-b0-fm-b0-"
  73 #define IWL_BZ_B_FM4_B_FW_PRE           "iwlwifi-bz-b0-fm4-b0-"
  74 #define IWL_GL_A_FM_A_FW_PRE            "iwlwifi-gl-a0-fm-a0-"
  75 #define IWL_GL_B_FM_B_FW_PRE            "iwlwifi-gl-b0-fm-b0-"
  76 #define IWL_GL_C_FM_C_FW_PRE            "iwlwifi-gl-c0-fm-c0-"
  77
  78 #define IWL_BZ_Z_GF_A_FW_PRE            "iwlwifi-bz-z0-gf-a0-"
  79 #define IWL_BNJ_A_FM_A_FW_PRE           "iwlwifi-BzBnj-a0-fm-a0-"
  80 #define IWL_BNJ_A_FM4_A_FW_PRE          "iwlwifi-BzBnj-a0-fm4-a0-"
  81 #define IWL_BNJ_B_FM4_B_FW_PRE          "iwlwifi-BzBnj-b0-fm4-b0-"
  82 #define IWL_BNJ_A_GF_A_FW_PRE           "iwlwifi-BzBnj-a0-gf-a0-"
  83 #define IWL_BNJ_B_GF_A_FW_PRE           "iwlwifi-BzBnj-b0-gf-a0-"
  84 #define IWL_BNJ_A_GF4_A_FW_PRE          "iwlwifi-BzBnj-a0-gf4-a0-"
  85 #define IWL_BNJ_B_GF4_A_FW_PRE          "iwlwifi-BzBnj-b0-gf4-a0-"
  86 #define IWL_BNJ_A_HR_A_FW_PRE           "iwlwifi-BzBnj-a0-hr-b0-"
  87 #define IWL_BNJ_A_HR_B_FW_PRE           "iwlwifi-BzBnj-a0-hr-b0-"
  88 #define IWL_BNJ_B_HR_A_FW_PRE           "iwlwifi-BzBnj-b0-hr-b0-"
  89 #define IWL_BNJ_B_HR_B_FW_PRE           "iwlwifi-BzBnj-b0-hr-b0-"
  90 #define IWL_BNJ_B_FM_B_FW_PRE           "iwlwifi-BzBnj-b0-fm-b0-"
  91
  92 #define IWL_SC_A_FM_B_FW_PRE            "iwlwifi-sc-a0-fm-b0-"
  93 #define IWL_SC_A_FM_C_FW_PRE            "iwlwifi-sc-a0-fm-c0-"
  94 #define IWL_SC_A_HR_A_FW_PRE            "iwlwifi-sc-a0-hr-b0-"
  95 #define IWL_SC_A_HR_B_FW_PRE            "iwlwifi-sc-a0-hr-b0-"
  96 #define IWL_SC_A_GF_A_FW_PRE            "iwlwifi-sc-a0-gf-a0-"
  97 #define IWL_SC_A_GF4_A_FW_PRE           "iwlwifi-sc-a0-gf4-a0-"
  98 #define IWL_SC_A_WH_A_FW_PRE            "iwlwifi-sc-a0-wh-a0-"
  99
 100 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \
 101         IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode"
 102 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api)     \
 103         IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode"
 104 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \
 105         IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
 106 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \
 107         IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode"
 108 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \
 109         IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode"
 110 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \
 111         IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode"
 112 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api)             \
 113         IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode"
 114 #define IWL_CC_A_MODULE_FIRMWARE(api)                   \
 115         IWL_CC_A_FW_PRE __stringify(api) ".ucode"
 116 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \
 117         IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode"
 118 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \
 119         IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode"
 120 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \
 121         IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode"
 122 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \
 123         IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode"
 124 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \
 125         IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
 126 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \
 127         IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
 128 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \
 129         IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
 130 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \
 131         IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode"
 132 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api)           \
 133         IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode"
 134 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api)           \
 135         IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode"
 136 #define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api)          \
 137         IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode"
 138 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \
 139         IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode"
 140 #define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api)           \
 141         IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode"
 142 #define IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(api)           \
 143         IWL_MA_B_HR_B_FW_PRE __stringify(api) ".ucode"
 144 #define IWL_MA_B_GF_A_FW_MODULE_FIRMWARE(api)           \
 145         IWL_MA_B_GF_A_FW_PRE __stringify(api) ".ucode"
 146 #define IWL_MA_B_GF4_A_FW_MODULE_FIRMWARE(api)          \
 147         IWL_MA_B_GF4_A_FW_PRE __stringify(api) ".ucode"
 148 #define IWL_MA_B_MR_A_FW_MODULE_FIRMWARE(api) \
 149         IWL_MA_B_MR_A_FW_PRE __stringify(api) ".ucode"
 150 #define IWL_MA_B_FM_A_FW_MODULE_FIRMWARE(api)           \
 151         IWL_MA_B_FM_A_FW_PRE __stringify(api) ".ucode"
 152 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \
 153         IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode"
 154 #define IWL_BZ_A_HR_A_MODULE_FIRMWARE(api) \
 155         IWL_BZ_A_HR_A_FW_PRE __stringify(api) ".ucode"
 156 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \
 157         IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
 158 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \
 159         IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode"
 160 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \
 161         IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
 162 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \
 163         IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode"
 164 #define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \
 165         IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode"
 166 #define IWL_BZ_A_FM4_A_MODULE_FIRMWARE(api) \
 167         IWL_BZ_A_FM4_A_FW_PRE __stringify(api) ".ucode"
 168 #define IWL_BZ_A_FM_B_MODULE_FIRMWARE(api) \
 169         IWL_BZ_A_FM_B_FW_PRE __stringify(api) ".ucode"
 170 #define IWL_BZ_A_FM_C_MODULE_FIRMWARE(api) \
 171                 IWL_BZ_A_FM_C_FW_PRE __stringify(api) ".ucode"
 172 #define IWL_BZ_A_FM4_B_MODULE_FIRMWARE(api) \
 173         IWL_BZ_A_FM4_B_FW_PRE __stringify(api) ".ucode"
 174 #define IWL_BZ_B_GF_A_MODULE_FIRMWARE(api) \
 175         IWL_BZ_B_GF_A_FW_PRE __stringify(api) ".ucode"
 176 #define IWL_BZ_B_GF4_A_MODULE_FIRMWARE(api) \
 177         IWL_BZ_B_GF4_A_FW_PRE __stringify(api) ".ucode"
 178 #define IWL_BZ_B_FM_B_MODULE_FIRMWARE(api) \
 179         IWL_BZ_B_FM_B_FW_PRE __stringify(api) ".ucode"
 180 #define IWL_BZ_B_FM4_B_MODULE_FIRMWARE(api) \
 181         IWL_BZ_B_FM4_B_FW_PRE __stringify(api) ".ucode"
 182 #define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \
 183         IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode"
 184 #define IWL_GL_B_FM_B_MODULE_FIRMWARE(api) \
 185         IWL_GL_B_FM_B_FW_PRE __stringify(api) ".ucode"
 186 #define IWL_GL_C_FM_C_MODULE_FIRMWARE(api) \
 187         IWL_GL_C_FM_C_FW_PRE __stringify(api) ".ucode"
 188 #define IWL_BNJ_A_FM_A_MODULE_FIRMWARE(api) \
 189         IWL_BNJ_A_FM_A_FW_PRE __stringify(api) ".ucode"
 190 #define IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(api) \
 191         IWL_BNJ_A_FM4_A_FW_PRE __stringify(api) ".ucode"
 192 #define IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(api) \
 193         IWL_BNJ_B_FM4_B_FW_PRE __stringify(api) ".ucode"
 194 #define IWL_BNJ_A_GF_A_MODULE_FIRMWARE(api) \
 195         IWL_BNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
 196 #define IWL_BNJ_B_GF_A_MODULE_FIRMWARE(api) \
 197         IWL_BNJ_B_GF_A_FW_PRE __stringify(api) ".ucode"
 198 #define IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(api) \
 199         IWL_BNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
 200 #define IWL_BNJ_B_GF4_A_MODULE_FIRMWARE(api) \
 201         IWL_BNJ_B_GF4_A_FW_PRE __stringify(api) ".ucode"
 202
 203 #define IWL_BNJ_A_HR_A_MODULE_FIRMWARE(api) \
 204         IWL_BNJ_A_HR_A_FW_PRE __stringify(api) ".ucode"
 205 #define IWL_BNJ_A_HR_B_MODULE_FIRMWARE(api) \
 206         IWL_BNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
 207 #define IWL_BNJ_B_HR_A_MODULE_FIRMWARE(api) \
 208         IWL_BNJ_B_HR_A_FW_PRE __stringify(api) ".ucode"
 209 #define IWL_BNJ_B_HR_B_MODULE_FIRMWARE(api) \
 210         IWL_BNJ_B_HR_B_FW_PRE __stringify(api) ".ucode"
 211 #define IWL_BNJ_B_FM_B_MODULE_FIRMWARE(api) \
 212         IWL_BNJ_B_FM_B_FW_PRE __stringify(api) ".ucode"
 213 #define IWL_SC_A_FM_B_FW_MODULE_FIRMWARE(api) \
 214         IWL_SC_A_FM_B_FW_PRE __stringify(api) ".ucode"
 215 #define IWL_SC_A_FM_C_FW_MODULE_FIRMWARE(api) \
 216         IWL_SC_A_FM_C_FW_PRE __stringify(api) ".ucode"
 217 #define IWL_SC_A_HR_A_FW_MODULE_FIRMWARE(api) \
 218         IWL_SC_A_HR_A_FW_PRE __stringify(api) ".ucode"
 219 #define IWL_SC_A_HR_B_FW_MODULE_FIRMWARE(api) \
 220         IWL_SC_A_HR_B_FW_PRE __stringify(api) ".ucode"
 221 #define IWL_SC_A_GF_A_FW_MODULE_FIRMWARE(api) \
 222         IWL_SC_A_GF_A_FW_PRE __stringify(api) ".ucode"
 223 #define IWL_SC_A_GF4_A_FW_MODULE_FIRMWARE(api) \
 224         IWL_SC_A_GF4_A_FW_PRE __stringify(api) ".ucode"
 225 #define IWL_SC_A_WH_A_FW_MODULE_FIRMWARE(api) \
 226         IWL_SC_A_WH_A_FW_PRE __stringify(api) ".ucode"
 227
 228 static const struct iwl_base_params iwl_22000_base_params = {
 229         .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
 230         .num_of_queues = 512,
 231         .max_tfd_queue_size = 256,
 232         .shadow_ram_support = true,
 233         .led_compensation = 57,
 234         .wd_timeout = IWL_LONG_WD_TIMEOUT,
 235         .max_event_log_size = 512,
 236         .shadow_reg_enable = true,
 237         .pcie_l1_allowed = true,
 238 };
 239
 240 static const struct iwl_base_params iwl_ax210_base_params = {
 241         .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
 242         .num_of_queues = 512,
 243         .max_tfd_queue_size = 65536,
 244         .shadow_ram_support = true,
 245         .led_compensation = 57,
 246         .wd_timeout = IWL_LONG_WD_TIMEOUT,
 247         .max_event_log_size = 512,
 248         .shadow_reg_enable = true,
 249         .pcie_l1_allowed = true,
 250 };
 251
 252 static const struct iwl_ht_params iwl_22000_ht_params = {
 253         .stbc = true,
 254         .ldpc = true,
 255         .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
 256                       BIT(NL80211_BAND_6GHZ),
 257 };
 258
 259 static const struct iwl_ht_params iwl_gl_a_ht_params = {
 260         .stbc = false, /* we explicitly disable STBC for GL step A */
 261         .ldpc = true,
 262         .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
 263                       BIT(NL80211_BAND_6GHZ),
 264 };
 265
 266 #define IWL_DEVICE_22000_COMMON                                         \
 267         .ucode_api_min = IWL_22000_UCODE_API_MIN,                       \
 268         .led_mode = IWL_LED_RF_STATE,                                   \
 269         .nvm_hw_section_num = 10,                                       \
 270         .non_shared_ant = ANT_B,                                        \
 271         .dccm_offset = IWL_22000_DCCM_OFFSET,                           \
 272         .dccm_len = IWL_22000_DCCM_LEN,                                 \
 273         .dccm2_offset = IWL_22000_DCCM2_OFFSET,                         \
 274         .dccm2_len = IWL_22000_DCCM2_LEN,                               \
 275         .smem_offset = IWL_22000_SMEM_OFFSET,                           \
 276         .smem_len = IWL_22000_SMEM_LEN,                                 \
 277         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,           \
 278         .apmg_not_supported = true,                                     \
 279         .trans.mq_rx_supported = true,                                  \
 280         .vht_mu_mimo_supported = true,                                  \
 281         .mac_addr_from_csr = 0x380,                                     \
 282         .ht_params = &iwl_22000_ht_params,                              \
 283         .nvm_ver = IWL_22000_NVM_VERSION,                               \
 284         .trans.use_tfh = true,                                          \
 285         .trans.rf_id = true,                                            \
 286         .trans.gen2 = true,                                             \
 287         .nvm_type = IWL_NVM_EXT,                                        \
 288         .dbgc_supported = true,                                         \
 289         .min_umac_error_event_table = 0x400000,                         \
 290         .d3_debug_data_base_addr = 0x401000,                            \
 291         .d3_debug_data_length = 60 * 1024,                              \
 292         .mon_smem_regs = {                                              \
 293                 .write_ptr = {                                          \
 294                         .addr = LDBG_M2S_BUF_WPTR,                      \
 295                         .mask = LDBG_M2S_BUF_WPTR_VAL_MSK,              \
 296         },                                                              \
 297                 .cycle_cnt = {                                          \
 298                         .addr = LDBG_M2S_BUF_WRAP_CNT,                  \
 299                         .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK,          \
 300                 },                                                      \
 301         }
 302
 303 #define IWL_DEVICE_22500                                                \
 304         IWL_DEVICE_22000_COMMON,                                        \
 305         .ucode_api_max = IWL_22500_UCODE_API_MAX,                       \
 306         .trans.device_family = IWL_DEVICE_FAMILY_22000,                 \
 307         .trans.base_params = &iwl_22000_base_params,                    \
 308         .gp2_reg_addr = 0xa02c68,                                       \
 309         .mon_dram_regs = {                                              \
 310                 .write_ptr = {                                          \
 311                         .addr = MON_BUFF_WRPTR_VER2,                    \
 312                         .mask = 0xffffffff,                             \
 313                 },                                                      \
 314                 .cycle_cnt = {                                          \
 315                         .addr = MON_BUFF_CYCLE_CNT_VER2,                \
 316                         .mask = 0xffffffff,                             \
 317                 },                                                      \
 318         }
 319
 320 #define IWL_DEVICE_AX210                                                \
 321         IWL_DEVICE_22000_COMMON,                                        \
 322         .ucode_api_max = IWL_22000_UCODE_API_MAX,                       \
 323         .trans.umac_prph_offset = 0x300000,                             \
 324         .trans.device_family = IWL_DEVICE_FAMILY_AX210,                 \
 325         .trans.base_params = &iwl_ax210_base_params,                    \
 326         .min_txq_size = 128,                                            \
 327         .gp2_reg_addr = 0xd02c68,                                       \
 328         .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE,           \
 329         .mon_dram_regs = {                                              \
 330                 .write_ptr = {                                          \
 331                         .addr = DBGC_CUR_DBGBUF_STATUS,                 \
 332                         .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK,      \
 333                 },                                                      \
 334                 .cycle_cnt = {                                          \
 335                         .addr = DBGC_DBGBUF_WRAP_AROUND,                \
 336                         .mask = 0xffffffff,                             \
 337                 },                                                      \
 338                 .cur_frag = {                                           \
 339                         .addr = DBGC_CUR_DBGBUF_STATUS,                 \
 340                         .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK,         \
 341                 },                                                      \
 342         }
 343
 344 #define IWL_DEVICE_BZ_COMMON                                            \
 345         .ucode_api_max = IWL_22000_UCODE_API_MAX,                       \
 346         .ucode_api_min = IWL_22000_UCODE_API_MIN,                       \
 347         .led_mode = IWL_LED_RF_STATE,                                   \
 348         .nvm_hw_section_num = 10,                                       \
 349         .non_shared_ant = ANT_B,                                        \
 350         .dccm_offset = IWL_22000_DCCM_OFFSET,                           \
 351         .dccm_len = IWL_22000_DCCM_LEN,                                 \
 352         .dccm2_offset = IWL_22000_DCCM2_OFFSET,                         \
 353         .dccm2_len = IWL_22000_DCCM2_LEN,                               \
 354         .smem_offset = IWL_22000_SMEM_OFFSET,                           \
 355         .smem_len = IWL_22000_SMEM_LEN,                                 \
 356         .apmg_not_supported = true,                                     \
 357         .trans.mq_rx_supported = true,                                  \
 358         .vht_mu_mimo_supported = true,                                  \
 359         .mac_addr_from_csr = 0x30,                                      \
 360         .nvm_ver = IWL_22000_NVM_VERSION,                               \
 361         .trans.use_tfh = true,                                          \
 362         .trans.rf_id = true,                                            \
 363         .trans.gen2 = true,                                             \
 364         .nvm_type = IWL_NVM_EXT,                                        \
 365         .dbgc_supported = true,                                         \
 366         .min_umac_error_event_table = 0xD0000,                          \
 367         .d3_debug_data_base_addr = 0x401000,                            \
 368         .d3_debug_data_length = 60 * 1024,                              \
 369         .mon_smem_regs = {                                              \
 370                 .write_ptr = {                                          \
 371                         .addr = LDBG_M2S_BUF_WPTR,                      \
 372                         .mask = LDBG_M2S_BUF_WPTR_VAL_MSK,              \
 373         },                                                              \
 374                 .cycle_cnt = {                                          \
 375                         .addr = LDBG_M2S_BUF_WRAP_CNT,                  \
 376                         .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK,          \
 377                 },                                                      \
 378         },                                                              \
 379         .trans.umac_prph_offset = 0x300000,                             \
 380         .trans.device_family = IWL_DEVICE_FAMILY_BZ,                    \
 381         .trans.base_params = &iwl_ax210_base_params,                    \
 382         .min_txq_size = 128,                                            \
 383         .gp2_reg_addr = 0xd02c68,                                       \
 384         .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT,                  \
 385         .mon_dram_regs = {                                              \
 386                 .write_ptr = {                                          \
 387                         .addr = DBGC_CUR_DBGBUF_STATUS,                 \
 388                         .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK,      \
 389                 },                                                      \
 390                 .cycle_cnt = {                                          \
 391                         .addr = DBGC_DBGBUF_WRAP_AROUND,                \
 392                         .mask = 0xffffffff,                             \
 393                 },                                                      \
 394                 .cur_frag = {                                           \
 395                         .addr = DBGC_CUR_DBGBUF_STATUS,                 \
 396                         .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK,         \
 397                 },                                                      \
 398         },                                                              \
 399         .mon_dbgi_regs = {                                              \
 400                 .write_ptr = {                                          \
 401                         .addr = DBGI_SRAM_FIFO_POINTERS,                \
 402                         .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK,     \
 403                 },                                                      \
 404         }
 405
 406 #define IWL_DEVICE_BZ                                                   \
 407         IWL_DEVICE_BZ_COMMON,                                           \
 408         .ht_params = &iwl_22000_ht_params
 409
 410 #define IWL_DEVICE_GL_A                                                 \
 411         IWL_DEVICE_BZ_COMMON,                                           \
 412         .ht_params = &iwl_gl_a_ht_params
 413
 414 #define IWL_DEVICE_SC                                                   \
 415         IWL_DEVICE_BZ_COMMON,                                           \
 416         .ht_params = &iwl_22000_ht_params
 417
 418 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = {
 419         .mq_rx_supported = true,
 420         .use_tfh = true,
 421         .rf_id = true,
 422         .gen2 = true,
 423         .device_family = IWL_DEVICE_FAMILY_22000,
 424         .base_params = &iwl_22000_base_params,
 425 };
 426
 427 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = {
 428         .mq_rx_supported = true,
 429         .use_tfh = true,
 430         .rf_id = true,
 431         .gen2 = true,
 432         .device_family = IWL_DEVICE_FAMILY_22000,
 433         .base_params = &iwl_22000_base_params,
 434         .integrated = true,
 435         .xtal_latency = 500,
 436         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
 437 };
 438
 439 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = {
 440         .mq_rx_supported = true,
 441         .use_tfh = true,
 442         .rf_id = true,
 443         .gen2 = true,
 444         .device_family = IWL_DEVICE_FAMILY_22000,
 445         .base_params = &iwl_22000_base_params,
 446         .integrated = true,
 447         .xtal_latency = 1820,
 448         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US,
 449 };
 450
 451 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = {
 452         .mq_rx_supported = true,
 453         .use_tfh = true,
 454         .rf_id = true,
 455         .gen2 = true,
 456         .device_family = IWL_DEVICE_FAMILY_22000,
 457         .base_params = &iwl_22000_base_params,
 458         .integrated = true,
 459         .xtal_latency = 12000,
 460         .low_latency_xtal = true,
 461         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
 462 };
 463
 464 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = {
 465         .mq_rx_supported = true,
 466         .use_tfh = true,
 467         .rf_id = true,
 468         .gen2 = true,
 469         .device_family = IWL_DEVICE_FAMILY_AX210,
 470         .base_params = &iwl_ax210_base_params,
 471         .umac_prph_offset = 0x300000,
 472 };
 473
 474 const struct iwl_cfg_trans_params iwl_so_trans_cfg = {
 475         .mq_rx_supported = true,
 476         .use_tfh = true,
 477         .rf_id = true,
 478         .gen2 = true,
 479         .device_family = IWL_DEVICE_FAMILY_AX210,
 480         .base_params = &iwl_ax210_base_params,
 481         .umac_prph_offset = 0x300000,
 482         .integrated = true,
 483         /* TODO: the following values need to be checked */
 484         .xtal_latency = 500,
 485         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
 486 };
 487
 488 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = {
 489         .mq_rx_supported = true,
 490         .use_tfh = true,
 491         .rf_id = true,
 492         .gen2 = true,
 493         .device_family = IWL_DEVICE_FAMILY_AX210,
 494         .base_params = &iwl_ax210_base_params,
 495         .umac_prph_offset = 0x300000,
 496         .integrated = true,
 497         .low_latency_xtal = true,
 498         .xtal_latency = 12000,
 499         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
 500 };
 501
 502 const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = {
 503         .mq_rx_supported = true,
 504         .use_tfh = true,
 505         .rf_id = true,
 506         .gen2 = true,
 507         .device_family = IWL_DEVICE_FAMILY_AX210,
 508         .base_params = &iwl_ax210_base_params,
 509         .umac_prph_offset = 0x300000,
 510         .integrated = true,
 511         .low_latency_xtal = true,
 512         .xtal_latency = 12000,
 513         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
 514         .imr_enabled = true,
 515 };
 516
 517 /*
 518  * If the device doesn't support HE, no need to have that many buffers.
 519  * 22000 devices can split multiple frames into a single RB, so fewer are
 520  * needed; AX210 cannot (but use smaller RBs by default) - these sizes
 521  * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with
 522  * additional overhead to account for processing time.
 523  */
 524 #define IWL_NUM_RBDS_NON_HE             512
 525 #define IWL_NUM_RBDS_22000_HE           2048
 526 #define IWL_NUM_RBDS_AX210_HE           4096
 527
 528 /*
 529  * All JF radio modules are part of the 9000 series, but the MAC part
 530  * looks more like 22000.  That's why this device is here, but called
 531  * 9560 nevertheless.
 532  */
 533 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = {
 534         .fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
 535         IWL_DEVICE_22500,
 536         .num_rbds = IWL_NUM_RBDS_NON_HE,
 537 };
 538
 539 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = {
 540         .fw_name_pre = IWL_QU_C_JF_B_FW_PRE,
 541         IWL_DEVICE_22500,
 542         .num_rbds = IWL_NUM_RBDS_NON_HE,
 543 };
 544
 545 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = {
 546         .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE,
 547         IWL_DEVICE_22500,
 548         /*
 549          * This device doesn't support receiving BlockAck with a large bitmap
 550          * so we need to restrict the size of transmitted aggregation to the
 551          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 552          */
 553         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 554         .num_rbds = IWL_NUM_RBDS_NON_HE,
 555 };
 556
 557 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = {
 558         .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE,
 559         IWL_DEVICE_22500,
 560         /*
 561          * This device doesn't support receiving BlockAck with a large bitmap
 562          * so we need to restrict the size of transmitted aggregation to the
 563          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 564          */
 565         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 566         .num_rbds = IWL_NUM_RBDS_NON_HE,
 567 };
 568
 569 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = {
 570         .device_family = IWL_DEVICE_FAMILY_22000,
 571         .base_params = &iwl_22000_base_params,
 572         .mq_rx_supported = true,
 573         .use_tfh = true,
 574         .rf_id = true,
 575         .gen2 = true,
 576         .bisr_workaround = 1,
 577 };
 578
 579 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = {
 580         .device_family = IWL_DEVICE_FAMILY_AX210,
 581         .base_params = &iwl_ax210_base_params,
 582         .mq_rx_supported = true,
 583         .use_tfh = true,
 584         .rf_id = true,
 585         .gen2 = true,
 586         .integrated = true,
 587         .umac_prph_offset = 0x300000
 588 };
 589
 590 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = {
 591         .device_family = IWL_DEVICE_FAMILY_BZ,
 592         .base_params = &iwl_ax210_base_params,
 593         .mq_rx_supported = true,
 594         .use_tfh = true,
 595         .rf_id = true,
 596         .gen2 = true,
 597         .integrated = true,
 598         .umac_prph_offset = 0x300000,
 599         .xtal_latency = 12000,
 600         .low_latency_xtal = true,
 601         .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
 602 };
 603
 604 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101";
 605 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz";
 606 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz";
 607 const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203";
 608 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz";
 609 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz";
 610 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz";
 611 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz";
 612 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz";
 613 const char iwl_bz_name[] = "Intel(R) TBD Bz device";
 614 const char iwl_sc_name[] = "Intel(R) TBD Sc device";
 615
 616 const char iwl_ax200_killer_1650w_name[] =
 617         "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)";
 618 const char iwl_ax200_killer_1650x_name[] =
 619         "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)";
 620 const char iwl_ax201_killer_1650s_name[] =
 621         "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)";
 622 const char iwl_ax201_killer_1650i_name[] =
 623         "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)";
 624 const char iwl_ax210_killer_1675w_name[] =
 625         "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)";
 626 const char iwl_ax210_killer_1675x_name[] =
 627         "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)";
 628 const char iwl_ax211_killer_1675s_name[] =
 629         "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)";
 630 const char iwl_ax211_killer_1675i_name[] =
 631         "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)";
 632 const char iwl_ax411_killer_1690s_name[] =
 633         "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)";
 634 const char iwl_ax411_killer_1690i_name[] =
 635         "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)";
 636
 637 const struct iwl_cfg iwl_qu_b0_hr1_b0 = {
 638         .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
 639         IWL_DEVICE_22500,
 640         /*
 641          * This device doesn't support receiving BlockAck with a large bitmap
 642          * so we need to restrict the size of transmitted aggregation to the
 643          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 644          */
 645         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 646         .tx_with_siso_diversity = true,
 647         .num_rbds = IWL_NUM_RBDS_22000_HE,
 648 };
 649
 650 const struct iwl_cfg iwl_qu_b0_hr_b0 = {
 651         .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
 652         IWL_DEVICE_22500,
 653         /*
 654          * This device doesn't support receiving BlockAck with a large bitmap
 655          * so we need to restrict the size of transmitted aggregation to the
 656          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 657          */
 658         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 659         .num_rbds = IWL_NUM_RBDS_22000_HE,
 660 };
 661
 662 const struct iwl_cfg iwl_ax201_cfg_qu_hr = {
 663         .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
 664         .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
 665         IWL_DEVICE_22500,
 666         /*
 667          * This device doesn't support receiving BlockAck with a large bitmap
 668          * so we need to restrict the size of transmitted aggregation to the
 669          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 670          */
 671         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 672         .num_rbds = IWL_NUM_RBDS_22000_HE,
 673 };
 674
 675 const struct iwl_cfg iwl_qu_c0_hr1_b0 = {
 676         .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
 677         IWL_DEVICE_22500,
 678         /*
 679          * This device doesn't support receiving BlockAck with a large bitmap
 680          * so we need to restrict the size of transmitted aggregation to the
 681          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 682          */
 683         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 684         .tx_with_siso_diversity = true,
 685         .num_rbds = IWL_NUM_RBDS_22000_HE,
 686 };
 687
 688 const struct iwl_cfg iwl_qu_c0_hr_b0 = {
 689         .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
 690         IWL_DEVICE_22500,
 691         /*
 692          * This device doesn't support receiving BlockAck with a large bitmap
 693          * so we need to restrict the size of transmitted aggregation to the
 694          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 695          */
 696         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 697         .num_rbds = IWL_NUM_RBDS_22000_HE,
 698 };
 699
 700 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = {
 701         .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
 702         .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
 703         IWL_DEVICE_22500,
 704         /*
 705          * This device doesn't support receiving BlockAck with a large bitmap
 706          * so we need to restrict the size of transmitted aggregation to the
 707          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 708          */
 709         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 710         .num_rbds = IWL_NUM_RBDS_22000_HE,
 711 };
 712
 713 const struct iwl_cfg iwl_quz_a0_hr1_b0 = {
 714         .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
 715         IWL_DEVICE_22500,
 716         /*
 717          * This device doesn't support receiving BlockAck with a large bitmap
 718          * so we need to restrict the size of transmitted aggregation to the
 719          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 720          */
 721         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 722         .tx_with_siso_diversity = true,
 723         .num_rbds = IWL_NUM_RBDS_22000_HE,
 724 };
 725
 726 const struct iwl_cfg iwl_ax201_cfg_quz_hr = {
 727         .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
 728         .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
 729         IWL_DEVICE_22500,
 730         /*
 731          * This device doesn't support receiving BlockAck with a large bitmap
 732          * so we need to restrict the size of transmitted aggregation to the
 733          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 734          */
 735         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 736         .num_rbds = IWL_NUM_RBDS_22000_HE,
 737 };
 738
 739 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = {
 740         .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)",
 741         .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
 742         IWL_DEVICE_22500,
 743         /*
 744          * This device doesn't support receiving BlockAck with a large bitmap
 745          * so we need to restrict the size of transmitted aggregation to the
 746          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 747          */
 748         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 749         .num_rbds = IWL_NUM_RBDS_22000_HE,
 750 };
 751
 752 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = {
 753         .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)",
 754         .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
 755         IWL_DEVICE_22500,
 756         /*
 757          * This device doesn't support receiving BlockAck with a large bitmap
 758          * so we need to restrict the size of transmitted aggregation to the
 759          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 760          */
 761         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 762         .num_rbds = IWL_NUM_RBDS_22000_HE,
 763 };
 764
 765 const struct iwl_cfg iwl_ax200_cfg_cc = {
 766         .fw_name_pre = IWL_CC_A_FW_PRE,
 767         IWL_DEVICE_22500,
 768         /*
 769          * This device doesn't support receiving BlockAck with a large bitmap
 770          * so we need to restrict the size of transmitted aggregation to the
 771          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 772          */
 773         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 774         .num_rbds = IWL_NUM_RBDS_22000_HE,
 775 };
 776
 777 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = {
 778         .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)",
 779         .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
 780         IWL_DEVICE_22500,
 781         /*
 782          * This device doesn't support receiving BlockAck with a large bitmap
 783          * so we need to restrict the size of transmitted aggregation to the
 784          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 785          */
 786         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 787         .num_rbds = IWL_NUM_RBDS_22000_HE,
 788 };
 789
 790 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = {
 791         .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)",
 792         .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
 793         IWL_DEVICE_22500,
 794         /*
 795          * This device doesn't support receiving BlockAck with a large bitmap
 796          * so we need to restrict the size of transmitted aggregation to the
 797          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 798          */
 799         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 800         .num_rbds = IWL_NUM_RBDS_22000_HE,
 801 };
 802
 803 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = {
 804         .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)",
 805         .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
 806         IWL_DEVICE_22500,
 807         /*
 808          * This device doesn't support receiving BlockAck with a large bitmap
 809          * so we need to restrict the size of transmitted aggregation to the
 810          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 811          */
 812         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 813         .num_rbds = IWL_NUM_RBDS_22000_HE,
 814 };
 815
 816 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = {
 817         .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)",
 818         .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
 819         IWL_DEVICE_22500,
 820         /*
 821          * This device doesn't support receiving BlockAck with a large bitmap
 822          * so we need to restrict the size of transmitted aggregation to the
 823          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 824          */
 825         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 826         .num_rbds = IWL_NUM_RBDS_22000_HE,
 827 };
 828
 829 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = {
 830         .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE,
 831         IWL_DEVICE_22500,
 832         /*
 833          * This device doesn't support receiving BlockAck with a large bitmap
 834          * so we need to restrict the size of transmitted aggregation to the
 835          * HT size; mac80211 would otherwise pick the HE max (256) by default.
 836          */
 837         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
 838         .num_rbds = IWL_NUM_RBDS_22000_HE,
 839 };
 840
 841 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = {
 842         .name = "Intel(R) Wireless-AC 9560 160MHz",
 843         .fw_name_pre = IWL_SO_A_JF_B_FW_PRE,
 844         IWL_DEVICE_AX210,
 845         .num_rbds = IWL_NUM_RBDS_NON_HE,
 846 };
 847
 848 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = {
 849         .name = iwl_ax211_name,
 850         .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
 851         .uhb_supported = true,
 852         IWL_DEVICE_AX210,
 853         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 854 };
 855
 856 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = {
 857         .name = iwl_ax211_name,
 858         .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
 859         .uhb_supported = true,
 860         IWL_DEVICE_AX210,
 861         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 862         .trans.xtal_latency = 12000,
 863         .trans.low_latency_xtal = true,
 864 };
 865
 866 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = {
 867         .name = "Intel(R) Wi-Fi 6 AX210 160MHz",
 868         .fw_name_pre = IWL_TY_A_GF_A_FW_PRE,
 869         .uhb_supported = true,
 870         IWL_DEVICE_AX210,
 871         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 872 };
 873
 874 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = {
 875         .name = iwl_ax411_name,
 876         .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
 877         .uhb_supported = true,
 878         IWL_DEVICE_AX210,
 879         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 880 };
 881
 882 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = {
 883         .name = iwl_ax411_name,
 884         .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
 885         .uhb_supported = true,
 886         IWL_DEVICE_AX210,
 887         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 888         .trans.xtal_latency = 12000,
 889         .trans.low_latency_xtal = true,
 890 };
 891
 892 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = {
 893         .name = iwl_ax411_name,
 894         .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE,
 895         .uhb_supported = true,
 896         IWL_DEVICE_AX210,
 897         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 898 };
 899
 900 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = {
 901         .name = iwl_ax211_name,
 902         .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE,
 903         .uhb_supported = true,
 904         IWL_DEVICE_AX210,
 905         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 906 };
 907
 908 const struct iwl_cfg iwl_cfg_snj_hr_b0 = {
 909         .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE,
 910         .uhb_supported = true,
 911         IWL_DEVICE_AX210,
 912         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 913 };
 914
 915 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = {
 916         .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE,
 917         .uhb_supported = true,
 918         IWL_DEVICE_AX210,
 919         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 920 };
 921
 922 const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = {
 923         .fw_name_pre = IWL_MA_A_HR_B_FW_PRE,
 924         .uhb_supported = true,
 925         IWL_DEVICE_AX210,
 926         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 927 };
 928
 929 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = {
 930         .fw_name_pre = IWL_MA_A_GF_A_FW_PRE,
 931         .uhb_supported = true,
 932         IWL_DEVICE_AX210,
 933         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 934 };
 935
 936 const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = {
 937         .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE,
 938         .uhb_supported = true,
 939         IWL_DEVICE_AX210,
 940         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 941 };
 942
 943 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = {
 944         .fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
 945         .uhb_supported = true,
 946         IWL_DEVICE_AX210,
 947         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 948 };
 949
 950 const struct iwl_cfg iwl_cfg_ma_a0_ms_a0 = {
 951         .fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
 952         .uhb_supported = false,
 953         IWL_DEVICE_AX210,
 954         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 955 };
 956
 957 const struct iwl_cfg iwl_cfg_ma_b0_fm_a0 = {
 958         .fw_name_pre = IWL_MA_B_FM_A_FW_PRE,
 959         .uhb_supported = true,
 960         IWL_DEVICE_AX210,
 961         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 962 };
 963
 964 const struct iwl_cfg iwl_cfg_ma_b0_hr_b0 = {
 965         .fw_name_pre = IWL_MA_B_HR_B_FW_PRE,
 966         .uhb_supported = true,
 967         IWL_DEVICE_AX210,
 968         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 969 };
 970
 971 const struct iwl_cfg iwl_cfg_ma_b0_gf_a0 = {
 972         .fw_name_pre = IWL_MA_B_GF_A_FW_PRE,
 973         .uhb_supported = true,
 974         IWL_DEVICE_AX210,
 975         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 976 };
 977
 978 const struct iwl_cfg iwl_cfg_ma_b0_gf4_a0 = {
 979         .fw_name_pre = IWL_MA_B_GF4_A_FW_PRE,
 980         .uhb_supported = true,
 981         IWL_DEVICE_AX210,
 982         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 983 };
 984
 985 const struct iwl_cfg iwl_cfg_ma_b0_mr_a0 = {
 986         .fw_name_pre = IWL_MA_B_MR_A_FW_PRE,
 987         .uhb_supported = true,
 988         IWL_DEVICE_AX210,
 989         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 990 };
 991
 992 const struct iwl_cfg iwl_cfg_so_a0_ms_a0 = {
 993         .fw_name_pre = IWL_SO_A_MR_A_FW_PRE,
 994         .uhb_supported = false,
 995         IWL_DEVICE_AX210,
 996         .num_rbds = IWL_NUM_RBDS_AX210_HE,
 997 };
 998
 999 const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = {
1000         .fw_name_pre = IWL_MA_A_FM_A_FW_PRE,
1001         .uhb_supported = true,
1002         IWL_DEVICE_AX210,
1003         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1004 };
1005
1006 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = {
1007         .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
1008         .uhb_supported = true,
1009         IWL_DEVICE_AX210,
1010         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1011 };
1012
1013 const struct iwl_cfg iwl_cfg_snj_a0_ms_a0 = {
1014         .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
1015         .uhb_supported = false,
1016         IWL_DEVICE_AX210,
1017         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1018 };
1019
1020 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = {
1021         .fw_name_pre = IWL_SO_A_HR_B_FW_PRE,
1022         IWL_DEVICE_AX210,
1023         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1024 };
1025
1026 const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = {
1027         .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
1028         IWL_DEVICE_22500,
1029         /*
1030          * This device doesn't support receiving BlockAck with a large bitmap
1031          * so we need to restrict the size of transmitted aggregation to the
1032          * HT size; mac80211 would otherwise pick the HE max (256) by default.
1033          */
1034         .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
1035         .num_rbds = IWL_NUM_RBDS_22000_HE,
1036 };
1037
1038 const struct iwl_cfg iwl_cfg_bz_a0_hr_a0 = {
1039         .fw_name_pre = IWL_BZ_A_HR_A_FW_PRE,
1040         .uhb_supported = true,
1041         IWL_DEVICE_BZ,
1042         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1043         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1044 };
1045
1046 const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = {
1047         .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE,
1048         .uhb_supported = true,
1049         IWL_DEVICE_BZ,
1050         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1051         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1052 };
1053
1054 const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = {
1055         .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE,
1056         .uhb_supported = true,
1057         IWL_DEVICE_BZ,
1058         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1059         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1060 };
1061
1062 const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = {
1063         .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE,
1064         .uhb_supported = true,
1065         IWL_DEVICE_BZ,
1066         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1067         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1068 };
1069
1070 const struct iwl_cfg iwl_cfg_bz_b0_gf_a0 = {
1071         .fw_name_pre = IWL_BZ_B_GF_A_FW_PRE,
1072         .uhb_supported = true,
1073         IWL_DEVICE_BZ,
1074         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1075         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1076 };
1077
1078 const struct iwl_cfg iwl_cfg_bz_b0_gf4_a0 = {
1079         .fw_name_pre = IWL_BZ_B_GF4_A_FW_PRE,
1080         .uhb_supported = true,
1081         IWL_DEVICE_BZ,
1082         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1083         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1084 };
1085
1086 const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = {
1087         .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE,
1088         .uhb_supported = true,
1089         IWL_DEVICE_BZ,
1090         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1091         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1092 };
1093
1094 const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = {
1095         .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE,
1096         .uhb_supported = true,
1097         IWL_DEVICE_BZ,
1098         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1099         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1100 };
1101
1102 const struct iwl_cfg iwl_cfg_bz_a0_fm4_a0 = {
1103         .fw_name_pre = IWL_BZ_A_FM4_A_FW_PRE,
1104         .uhb_supported = true,
1105         IWL_DEVICE_BZ,
1106         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1107         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1108 };
1109
1110 const struct iwl_cfg iwl_cfg_bz_a0_fm_b0 = {
1111         .fw_name_pre = IWL_BZ_A_FM_B_FW_PRE,
1112         .uhb_supported = true,
1113         IWL_DEVICE_BZ,
1114         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1115         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1116 };
1117
1118 const struct iwl_cfg iwl_cfg_bz_a0_fm_c0 = {
1119         .fw_name_pre = IWL_BZ_A_FM_C_FW_PRE,
1120         .uhb_supported = true,
1121         IWL_DEVICE_BZ,
1122         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1123         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1124 };
1125
1126 const struct iwl_cfg iwl_cfg_bz_a0_fm4_b0 = {
1127         .fw_name_pre = IWL_BZ_A_FM4_B_FW_PRE,
1128         .uhb_supported = true,
1129         IWL_DEVICE_BZ,
1130         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1131         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1132 };
1133
1134 const struct iwl_cfg iwl_cfg_bz_b0_fm_b0 = {
1135         .fw_name_pre = IWL_BZ_B_FM_B_FW_PRE,
1136         .uhb_supported = true,
1137         IWL_DEVICE_BZ,
1138         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1139         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1140 };
1141
1142 const struct iwl_cfg iwl_cfg_bz_b0_fm4_b0 = {
1143         .fw_name_pre = IWL_BZ_B_FM4_B_FW_PRE,
1144         .uhb_supported = true,
1145         IWL_DEVICE_BZ,
1146         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1147         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1148 };
1149
1150 const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = {
1151         .fw_name_pre = IWL_GL_A_FM_A_FW_PRE,
1152         .uhb_supported = true,
1153         IWL_DEVICE_GL_A,
1154         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1155         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1156 };
1157
1158 const struct iwl_cfg iwl_cfg_gl_b0_fm_b0 = {
1159         .fw_name_pre = IWL_GL_B_FM_B_FW_PRE,
1160         .uhb_supported = true,
1161         IWL_DEVICE_BZ,
1162         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1163         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1164 };
1165
1166 const struct iwl_cfg iwl_cfg_gl_c0_fm_c0 = {
1167         .fw_name_pre = IWL_GL_C_FM_C_FW_PRE,
1168         .uhb_supported = true,
1169         IWL_DEVICE_BZ,
1170         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1171         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1172 };
1173
1174 const struct iwl_cfg iwl_cfg_bz_z0_gf_a0 = {
1175         .fw_name_pre = IWL_BZ_Z_GF_A_FW_PRE,
1176         .uhb_supported = true,
1177         IWL_DEVICE_BZ,
1178         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1179         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1180 };
1181
1182 const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0 = {
1183         .fw_name_pre = IWL_BNJ_A_FM_A_FW_PRE,
1184         .uhb_supported = true,
1185         IWL_DEVICE_BZ,
1186         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1187         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1188 };
1189
1190 const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0 = {
1191         .fw_name_pre = IWL_BNJ_A_FM4_A_FW_PRE,
1192         .uhb_supported = true,
1193         IWL_DEVICE_BZ,
1194         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1195         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1196 };
1197
1198 const struct iwl_cfg iwl_cfg_bnj_b0_fm4_b0 = {
1199         .fw_name_pre = IWL_BNJ_B_FM4_B_FW_PRE,
1200         .uhb_supported = true,
1201         IWL_DEVICE_BZ,
1202         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1203         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1204 };
1205
1206 const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0 = {
1207         .fw_name_pre = IWL_BNJ_A_GF_A_FW_PRE,
1208         .uhb_supported = true,
1209         IWL_DEVICE_BZ,
1210         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1211         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1212 };
1213
1214 const struct iwl_cfg iwl_cfg_bnj_b0_gf_a0 = {
1215         .fw_name_pre = IWL_BNJ_B_GF_A_FW_PRE,
1216         .uhb_supported = true,
1217         IWL_DEVICE_BZ,
1218         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1219         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1220 };
1221
1222 const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0 = {
1223         .fw_name_pre = IWL_BNJ_A_GF4_A_FW_PRE,
1224         .uhb_supported = true,
1225         IWL_DEVICE_BZ,
1226         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1227         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1228 };
1229
1230 const struct iwl_cfg iwl_cfg_bnj_b0_gf4_a0 = {
1231         .fw_name_pre = IWL_BNJ_B_GF4_A_FW_PRE,
1232         .uhb_supported = true,
1233         IWL_DEVICE_BZ,
1234         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1235         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1236 };
1237
1238 const struct iwl_cfg iwl_cfg_bnj_a0_hr_a0 = {
1239         .fw_name_pre = IWL_BNJ_A_HR_A_FW_PRE,
1240         .uhb_supported = true,
1241         IWL_DEVICE_BZ,
1242         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1243         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1244 };
1245
1246 const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0 = {
1247         .fw_name_pre = IWL_BNJ_A_HR_B_FW_PRE,
1248         .uhb_supported = true,
1249         IWL_DEVICE_BZ,
1250         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1251         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1252 };
1253
1254 const struct iwl_cfg iwl_cfg_bnj_b0_hr_a0 = {
1255         .fw_name_pre = IWL_BNJ_B_HR_A_FW_PRE,
1256         .uhb_supported = true,
1257         IWL_DEVICE_BZ,
1258         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1259         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1260 };
1261
1262 const struct iwl_cfg iwl_cfg_bnj_b0_hr_b0 = {
1263         .fw_name_pre = IWL_BNJ_B_HR_B_FW_PRE,
1264         .uhb_supported = true,
1265         IWL_DEVICE_BZ,
1266         .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1267         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1268 };
1269
1270 const struct iwl_cfg iwl_cfg_bnj_b0_fm_b0 = {
1271         .fw_name_pre = IWL_BNJ_B_FM_B_FW_PRE,
1272         .uhb_supported = true,
1273         IWL_DEVICE_BZ,
1274         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1275         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1276 };
1277
1278 const struct iwl_cfg iwl_cfg_sc_a0_fm_b0 = {
1279         .fw_name_pre = IWL_SC_A_FM_B_FW_PRE,
1280         .uhb_supported = true,
1281         IWL_DEVICE_SC,
1282         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1283         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1284 };
1285
1286 const struct iwl_cfg iwl_cfg_sc_a0_fm_c0 = {
1287         .fw_name_pre = IWL_SC_A_FM_C_FW_PRE,
1288         .uhb_supported = true,
1289         IWL_DEVICE_SC,
1290         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1291         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1292 };
1293
1294 const struct iwl_cfg iwl_cfg_sc_a0_hr_a0 = {
1295         .fw_name_pre = IWL_SC_A_HR_A_FW_PRE,
1296         .uhb_supported = true,
1297         IWL_DEVICE_SC,
1298         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1299         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1300 };
1301
1302 const struct iwl_cfg iwl_cfg_sc_a0_hr_b0 = {
1303         .fw_name_pre = IWL_SC_A_HR_B_FW_PRE,
1304         .uhb_supported = true,
1305         IWL_DEVICE_SC,
1306         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1307         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1308 };
1309
1310 const struct iwl_cfg iwl_cfg_sc_a0_gf_a0 = {
1311         .fw_name_pre = IWL_SC_A_GF_A_FW_PRE,
1312         .uhb_supported = true,
1313         IWL_DEVICE_SC,
1314         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1315         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1316 };
1317
1318 const struct iwl_cfg iwl_cfg_sc_a0_gf4_a0 = {
1319         .fw_name_pre = IWL_SC_A_GF4_A_FW_PRE,
1320         .uhb_supported = true,
1321         IWL_DEVICE_SC,
1322         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1323         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1324 };
1325
1326 const struct iwl_cfg iwl_cfg_sc_a0_wh_a0 = {
1327         .fw_name_pre = IWL_SC_A_WH_A_FW_PRE,
1328         .uhb_supported = true,
1329         IWL_DEVICE_SC,
1330         .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1331         .num_rbds = IWL_NUM_RBDS_AX210_HE,
1332 };
1333
1334 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1335 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1336 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1337 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1338 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1339 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1340 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1341 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22500_UCODE_API_MAX));
1342 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1343 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1344 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1345 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1346 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1347 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1348 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1349 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1350 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1351 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1352 MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1353 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1354 MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1355 MODULE_FIRMWARE(IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1356 MODULE_FIRMWARE(IWL_MA_B_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1357 MODULE_FIRMWARE(IWL_MA_B_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1358 MODULE_FIRMWARE(IWL_MA_B_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1359 MODULE_FIRMWARE(IWL_MA_B_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1360 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1361 MODULE_FIRMWARE(IWL_BZ_A_HR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1362 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1363 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1364 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1365 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1366 MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1367 MODULE_FIRMWARE(IWL_BZ_A_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1368 MODULE_FIRMWARE(IWL_BZ_A_FM_C_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1369 MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1370 MODULE_FIRMWARE(IWL_BNJ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1371 MODULE_FIRMWARE(IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1372 MODULE_FIRMWARE(IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1373 MODULE_FIRMWARE(IWL_BNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1374 MODULE_FIRMWARE(IWL_BNJ_B_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1375 MODULE_FIRMWARE(IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1376 MODULE_FIRMWARE(IWL_BNJ_B_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1377 MODULE_FIRMWARE(IWL_BNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1378 MODULE_FIRMWARE(IWL_BNJ_B_HR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1379 MODULE_FIRMWARE(IWL_BNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1380 MODULE_FIRMWARE(IWL_BZ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1381 MODULE_FIRMWARE(IWL_BZ_A_FM4_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1382 MODULE_FIRMWARE(IWL_GL_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1383 MODULE_FIRMWARE(IWL_GL_C_FM_C_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1384 MODULE_FIRMWARE(IWL_BNJ_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1385 MODULE_FIRMWARE(IWL_SC_A_FM_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1386 MODULE_FIRMWARE(IWL_SC_A_FM_C_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1387 MODULE_FIRMWARE(IWL_SC_A_HR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1388 MODULE_FIRMWARE(IWL_SC_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1389 MODULE_FIRMWARE(IWL_SC_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1390 MODULE_FIRMWARE(IWL_SC_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1391 MODULE_FIRMWARE(IWL_SC_A_WH_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));