2 ****************************************************************************************
4 * @file ecrnx_ipc_app.h
6 * @brief IPC module register definitions
8 * Copyright (C) ESWIN 2015-2020
10 ****************************************************************************************
13 #ifndef _REG_IPC_APP_H_
14 #define _REG_IPC_APP_H_
20 #include "ipc_compat.h"
22 #include "reg_access.h"
24 #define REG_IPC_APP_DECODING_MASK 0x0000007F
27 * @brief APP2EMB_TRIGGER register definition
29 * Bits Field Name Reset Value
30 * ----- ------------------ -----------
31 * 31:00 APP2EMB_TRIGGER 0x0
34 #define IPC_APP2EMB_TRIGGER_ADDR 0x12000000
35 #define IPC_APP2EMB_TRIGGER_OFFSET 0x00000000
36 #define IPC_APP2EMB_TRIGGER_INDEX 0x00000000
37 #define IPC_APP2EMB_TRIGGER_RESET 0x00000000
39 __INLINE u32 ipc_app2emb_trigger_get(void *env)
41 return REG_IPC_APP_RD(env, IPC_APP2EMB_TRIGGER_INDEX);
44 __INLINE void ipc_app2emb_trigger_set(void *env, u32 value)
46 REG_IPC_APP_WR(env, IPC_APP2EMB_TRIGGER_INDEX, value);
50 #define IPC_APP2EMB_TRIGGER_MASK ((u32)0xFFFFFFFF)
51 #define IPC_APP2EMB_TRIGGER_LSB 0
52 #define IPC_APP2EMB_TRIGGER_WIDTH ((u32)0x00000020)
54 #define IPC_APP2EMB_TRIGGER_RST 0x0
56 __INLINE u32 ipc_app2emb_trigger_getf(void *env)
58 u32 localVal = REG_IPC_APP_RD(env, IPC_APP2EMB_TRIGGER_INDEX);
59 ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
60 return (localVal >> 0);
63 __INLINE void ipc_app2emb_trigger_setf(void *env, u32 app2embtrigger)
65 ASSERT_ERR((((u32)app2embtrigger << 0) & ~((u32)0xFFFFFFFF)) == 0);
66 REG_IPC_APP_WR(env, IPC_APP2EMB_TRIGGER_INDEX, (u32)app2embtrigger << 0);
70 * @brief EMB2APP_RAWSTATUS register definition
72 * Bits Field Name Reset Value
73 * ----- ------------------ -----------
74 * 31:00 EMB2APP_RAWSTATUS 0x0
77 #define IPC_EMB2APP_RAWSTATUS_ADDR 0x12000004
78 #define IPC_EMB2APP_RAWSTATUS_OFFSET 0x00000004
79 #define IPC_EMB2APP_RAWSTATUS_INDEX 0x00000001
80 #define IPC_EMB2APP_RAWSTATUS_RESET 0x00000000
82 __INLINE u32 ipc_emb2app_rawstatus_get(void *env)
84 return REG_IPC_APP_RD(env, IPC_EMB2APP_RAWSTATUS_INDEX);
87 __INLINE void ipc_emb2app_rawstatus_set(void *env, u32 value)
89 REG_IPC_APP_WR(env, IPC_EMB2APP_RAWSTATUS_INDEX, value);
93 #define IPC_EMB2APP_RAWSTATUS_MASK ((u32)0xFFFFFFFF)
94 #define IPC_EMB2APP_RAWSTATUS_LSB 0
95 #define IPC_EMB2APP_RAWSTATUS_WIDTH ((u32)0x00000020)
97 #define IPC_EMB2APP_RAWSTATUS_RST 0x0
99 __INLINE u32 ipc_emb2app_rawstatus_getf(void *env)
101 u32 localVal = REG_IPC_APP_RD(env, IPC_EMB2APP_RAWSTATUS_INDEX);
102 ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
103 return (localVal >> 0);
107 * @brief EMB2APP_ACK register definition
109 * Bits Field Name Reset Value
110 * ----- ------------------ -----------
111 * 31:00 EMB2APP_ACK 0x0
114 #define IPC_EMB2APP_ACK_ADDR 0x12000008
115 #define IPC_EMB2APP_ACK_OFFSET 0x00000008
116 #define IPC_EMB2APP_ACK_INDEX 0x00000002
117 #define IPC_EMB2APP_ACK_RESET 0x00000000
119 __INLINE u32 ipc_emb2app_ack_get(void *env)
121 return REG_IPC_APP_RD(env, IPC_EMB2APP_ACK_INDEX);
124 __INLINE void ipc_emb2app_ack_clear(void *env, u32 value)
126 REG_IPC_APP_WR(env, IPC_EMB2APP_ACK_INDEX, value);
130 #define IPC_EMB2APP_ACK_MASK ((u32)0xFFFFFFFF)
131 #define IPC_EMB2APP_ACK_LSB 0
132 #define IPC_EMB2APP_ACK_WIDTH ((u32)0x00000020)
134 #define IPC_EMB2APP_ACK_RST 0x0
136 __INLINE u32 ipc_emb2app_ack_getf(void *env)
138 u32 localVal = REG_IPC_APP_RD(env, IPC_EMB2APP_ACK_INDEX);
139 ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
140 return (localVal >> 0);
143 __INLINE void ipc_emb2app_ack_clearf(void *env, u32 emb2appack)
145 ASSERT_ERR((((u32)emb2appack << 0) & ~((u32)0xFFFFFFFF)) == 0);
146 REG_IPC_APP_WR(env, IPC_EMB2APP_ACK_INDEX, (u32)emb2appack << 0);
150 * @brief EMB2APP_UNMASK_SET register definition
152 * Bits Field Name Reset Value
153 * ----- ------------------ -----------
154 * 31:00 EMB2APP_UNMASK 0x0
157 #define IPC_EMB2APP_UNMASK_SET_ADDR 0x1200000C
158 #define IPC_EMB2APP_UNMASK_SET_OFFSET 0x0000000C
159 #define IPC_EMB2APP_UNMASK_SET_INDEX 0x00000003
160 #define IPC_EMB2APP_UNMASK_SET_RESET 0x00000000
162 __INLINE u32 ipc_emb2app_unmask_get(void *env)
164 return REG_IPC_APP_RD(env, IPC_EMB2APP_UNMASK_SET_INDEX);
167 __INLINE void ipc_emb2app_unmask_set(void *env, u32 value)
169 REG_IPC_APP_WR(env, IPC_EMB2APP_UNMASK_SET_INDEX, value);
173 #define IPC_EMB2APP_UNMASK_MASK ((u32)0xFFFFFFFF)
174 #define IPC_EMB2APP_UNMASK_LSB 0
175 #define IPC_EMB2APP_UNMASK_WIDTH ((u32)0x00000020)
177 #define IPC_EMB2APP_UNMASK_RST 0x0
179 __INLINE u32 ipc_emb2app_unmask_getf(void *env)
181 u32 localVal = REG_IPC_APP_RD(env, IPC_EMB2APP_UNMASK_SET_INDEX);
182 ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
183 return (localVal >> 0);
186 __INLINE void ipc_emb2app_unmask_setf(void *env, u32 emb2appunmask)
188 ASSERT_ERR((((u32)emb2appunmask << 0) & ~((u32)0xFFFFFFFF)) == 0);
189 REG_IPC_APP_WR(env, IPC_EMB2APP_UNMASK_SET_INDEX, (u32)emb2appunmask << 0);
193 * @brief EMB2APP_UNMASK_CLEAR register definition
195 * Bits Field Name Reset Value
196 * ----- ------------------ -----------
197 * 31:00 EMB2APP_UNMASK 0x0
200 #define IPC_EMB2APP_UNMASK_CLEAR_ADDR 0x12000010
201 #define IPC_EMB2APP_UNMASK_CLEAR_OFFSET 0x00000010
202 #define IPC_EMB2APP_UNMASK_CLEAR_INDEX 0x00000004
203 #define IPC_EMB2APP_UNMASK_CLEAR_RESET 0x00000000
205 __INLINE void ipc_emb2app_unmask_clear(void *env, u32 value)
207 REG_IPC_APP_WR(env, IPC_EMB2APP_UNMASK_CLEAR_INDEX, value);
210 // fields defined in symmetrical set/clear register
211 __INLINE void ipc_emb2app_unmask_clearf(void *env, u32 emb2appunmask)
213 ASSERT_ERR((((u32)emb2appunmask << 0) & ~((u32)0xFFFFFFFF)) == 0);
214 REG_IPC_APP_WR(env, IPC_EMB2APP_UNMASK_CLEAR_INDEX, (u32)emb2appunmask << 0);
218 * @brief EMB2APP_STATUS register definition
220 * Bits Field Name Reset Value
221 * ----- ------------------ -----------
222 * 31:00 EMB2APP_STATUS 0x0
225 #ifdef CONFIG_ECRNX_OLD_IPC
226 #define IPC_EMB2APP_STATUS_ADDR 0x12000014
227 #define IPC_EMB2APP_STATUS_OFFSET 0x00000014
228 #define IPC_EMB2APP_STATUS_INDEX 0x00000005
230 #define IPC_EMB2APP_STATUS_ADDR 0x1200001C
231 #define IPC_EMB2APP_STATUS_OFFSET 0x0000001C
232 #define IPC_EMB2APP_STATUS_INDEX 0x00000007
234 #define IPC_EMB2APP_STATUS_RESET 0x00000000
236 __INLINE u32 ipc_emb2app_status_get(void *env)
238 return REG_IPC_APP_RD(env, IPC_EMB2APP_STATUS_INDEX);
241 __INLINE void ipc_emb2app_status_set(void *env, u32 value)
243 REG_IPC_APP_WR(env, IPC_EMB2APP_STATUS_INDEX, value);
247 #define IPC_EMB2APP_STATUS_MASK ((u32)0xFFFFFFFF)
248 #define IPC_EMB2APP_STATUS_LSB 0
249 #define IPC_EMB2APP_STATUS_WIDTH ((u32)0x00000020)
251 #define IPC_EMB2APP_STATUS_RST 0x0
253 __INLINE u32 ipc_emb2app_status_getf(void *env)
255 u32 localVal = REG_IPC_APP_RD(env, IPC_EMB2APP_STATUS_INDEX);
256 ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
257 return (localVal >> 0);
261 * @brief APP_SIGNATURE register definition
263 * Bits Field Name Reset Value
264 * ----- ------------------ ----------
265 * 31:00 APP_SIGNATURE 0x0
268 #define IPC_APP_SIGNATURE_ADDR 0x12000040
269 #define IPC_APP_SIGNATURE_OFFSET 0x00000040
270 #define IPC_APP_SIGNATURE_INDEX 0x00000010
271 #define IPC_APP_SIGNATURE_RESET 0x00000000
273 __INLINE u32 ipc_app_signature_get(void *env)
275 return REG_IPC_APP_RD(env, IPC_APP_SIGNATURE_INDEX);
278 __INLINE void ipc_app_signature_set(void *env, u32 value)
280 REG_IPC_APP_WR(env, IPC_APP_SIGNATURE_INDEX, value);
284 #define IPC_APP_SIGNATURE_MASK ((u32)0xFFFFFFFF)
285 #define IPC_APP_SIGNATURE_LSB 0
286 #define IPC_APP_SIGNATURE_WIDTH ((u32)0x00000020)
288 #define IPC_APP_SIGNATURE_RST 0x0
290 __INLINE u32 ipc_app_signature_getf(void *env)
292 u32 localVal = REG_IPC_APP_RD(env, IPC_APP_SIGNATURE_INDEX);
293 ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
294 return (localVal >> 0);
298 #endif // _REG_IPC_APP_H_