2 ******************************************************************************
6 * @brief Definitions and macros for MAC HW and platform register accesses
8 * Copyright (C) ESWIN 2015-2020
10 ******************************************************************************
16 /*****************************************************************************
17 * Addresses within ECRNX_ADDR_CPU
18 *****************************************************************************/
19 #define RAM_LMAC_FW_ADDR 0x00000000
21 /*****************************************************************************
22 * Addresses within ECRNX_ADDR_SYSTEM
23 *****************************************************************************/
25 #define SHARED_RAM_START_ADDR 0x00000000
28 #define IPC_REG_BASE_ADDR 0x00800000
30 /* System Controller Registers */
31 #define SYSCTRL_SIGNATURE_ADDR 0x00900000
32 // old diag register name
33 #define SYSCTRL_DIAG_CONF_ADDR 0x00900068
34 #define SYSCTRL_PHYDIAG_CONF_ADDR 0x00900074
35 #define SYSCTRL_RIUDIAG_CONF_ADDR 0x00900078
36 // new diag register name
37 #define SYSCTRL_DIAG_CONF0 0x00900064
38 #define SYSCTRL_DIAG_CONF1 0x00900068
39 #define SYSCTRL_DIAG_CONF2 0x00900074
40 #define SYSCTRL_DIAG_CONF3 0x00900078
41 #define SYSCTRL_MISC_CNTL_ADDR 0x009000E0
42 #define BOOTROM_ENABLE BIT(4)
43 #define FPGA_B_RESET BIT(1)
44 #define SOFT_RESET BIT(0)
47 #define NXMAC_VERSION_1_ADDR 0x00B00004
48 #define NXMAC_MU_MIMO_TX_BIT BIT(19)
49 #define NXMAC_BFMER_BIT BIT(18)
50 #define NXMAC_BFMEE_BIT BIT(17)
51 #define NXMAC_MAC_80211MH_FORMAT_BIT BIT(16)
52 #define NXMAC_COEX_BIT BIT(14)
53 #define NXMAC_WAPI_BIT BIT(13)
54 #define NXMAC_TPC_BIT BIT(12)
55 #define NXMAC_VHT_BIT BIT(11)
56 #define NXMAC_HT_BIT BIT(10)
57 #define NXMAC_GCMP_BIT BIT(9)
58 #define NXMAC_RCE_BIT BIT(8)
59 #define NXMAC_CCMP_BIT BIT(7)
60 #define NXMAC_TKIP_BIT BIT(6)
61 #define NXMAC_WEP_BIT BIT(5)
62 #define NXMAC_SECURITY_BIT BIT(4)
63 #define NXMAC_SME_BIT BIT(3)
64 #define NXMAC_HCCA_BIT BIT(2)
65 #define NXMAC_EDCA_BIT BIT(1)
66 #define NXMAC_QOS_BIT BIT(0)
68 #define NXMAC_RX_CNTRL_ADDR 0x00B00060
69 #define NXMAC_EN_DUPLICATE_DETECTION_BIT BIT(31)
70 #define NXMAC_ACCEPT_UNKNOWN_BIT BIT(30)
71 #define NXMAC_ACCEPT_OTHER_DATA_FRAMES_BIT BIT(29)
72 #define NXMAC_ACCEPT_QO_S_NULL_BIT BIT(28)
73 #define NXMAC_ACCEPT_QCFWO_DATA_BIT BIT(27)
74 #define NXMAC_ACCEPT_Q_DATA_BIT BIT(26)
75 #define NXMAC_ACCEPT_CFWO_DATA_BIT BIT(25)
76 #define NXMAC_ACCEPT_DATA_BIT BIT(24)
77 #define NXMAC_ACCEPT_OTHER_CNTRL_FRAMES_BIT BIT(23)
78 #define NXMAC_ACCEPT_CF_END_BIT BIT(22)
79 #define NXMAC_ACCEPT_ACK_BIT BIT(21)
80 #define NXMAC_ACCEPT_CTS_BIT BIT(20)
81 #define NXMAC_ACCEPT_RTS_BIT BIT(19)
82 #define NXMAC_ACCEPT_PS_POLL_BIT BIT(18)
83 #define NXMAC_ACCEPT_BA_BIT BIT(17)
84 #define NXMAC_ACCEPT_BAR_BIT BIT(16)
85 #define NXMAC_ACCEPT_OTHER_MGMT_FRAMES_BIT BIT(15)
86 #define NXMAC_ACCEPT_BFMEE_FRAMES_BIT BIT(14)
87 #define NXMAC_ACCEPT_ALL_BEACON_BIT BIT(13)
88 #define NXMAC_ACCEPT_NOT_EXPECTED_BA_BIT BIT(12)
89 #define NXMAC_ACCEPT_DECRYPT_ERROR_FRAMES_BIT BIT(11)
90 #define NXMAC_ACCEPT_BEACON_BIT BIT(10)
91 #define NXMAC_ACCEPT_PROBE_RESP_BIT BIT(9)
92 #define NXMAC_ACCEPT_PROBE_REQ_BIT BIT(8)
93 #define NXMAC_ACCEPT_MY_UNICAST_BIT BIT(7)
94 #define NXMAC_ACCEPT_UNICAST_BIT BIT(6)
95 #define NXMAC_ACCEPT_ERROR_FRAMES_BIT BIT(5)
96 #define NXMAC_ACCEPT_OTHER_BSSID_BIT BIT(4)
97 #define NXMAC_ACCEPT_BROADCAST_BIT BIT(3)
98 #define NXMAC_ACCEPT_MULTICAST_BIT BIT(2)
99 #define NXMAC_DONT_DECRYPT_BIT BIT(1)
100 #define NXMAC_EXC_UNENCRYPTED_BIT BIT(0)
102 #define NXMAC_DEBUG_PORT_SEL_ADDR 0x00B00510
103 #define NXMAC_SW_SET_PROFILING_ADDR 0x00B08564
104 #define NXMAC_SW_CLEAR_PROFILING_ADDR 0x00B08568
107 #define MDM_HDMCONFIG_ADDR 0x00C00000
108 #define MDM_HDMVERSION_ADDR 0x00C0003C
110 /* Clock gating configuration */
111 #define MDM_MEMCLKCTRL0_ADDR 0x00C00848
112 #define MDM_CLKGATEFCTRL0_ADDR 0x00C00874
113 #define CRM_CLKGATEFCTRL0_ADDR 0x00940010
116 #define AGC_ECRNXAGCCNTL_ADDR 0x00C02060
119 #define PHY_LDPC_RAM_ADDR 0x00C09000
122 #define FCU_ECRNXFCAGCCNTL_ADDR 0x00C09034
125 #define PHY_AGC_UCODE_ADDR 0x00C0A000
128 #define RIU_ECRNXVERSION_ADDR 0x00C0B000
129 #define RIU_ECRNXDYNAMICCONFIG_ADDR 0x00C0B008
130 #define RIU_AGCMEMBISTSTAT_ADDR 0x00C0B238
131 #define RIU_AGCMEMSIGNATURESTAT_ADDR 0x00C0B23C
132 #define RIU_ECRNXAGCCNTL_ADDR 0x00C0B390
135 #define RC_SYSTEM_CONFIGURATION_ADDR 0x00C0C000
136 #define RC_ACCES_TO_CATAXIA_REG_ADDR 0x00C0C004
139 #define FPGAB_MPIF_SEL_ADDR 0x00C10030
140 #define RF_V6_DIAGPORT_CONF1_ADDR 0x00C10010
141 #define RF_v6_PHYDIAG_CONF1_ADDR 0x00C10018
143 #define RF_V7_DIAGPORT_CONF1_ADDR 0x00F10010
144 #define RF_v7_PHYDIAG_CONF1_ADDR 0x00F10018
146 /*****************************************************************************
147 * Macros for generated register files
148 *****************************************************************************/
149 /* Macros for IPC registers access (used in reg_ipc_app.h) */
150 #define REG_IPC_APP_RD(env, INDEX) \
151 (*(volatile u32*)((u8*)env + IPC_REG_BASE_ADDR + 4*(INDEX)))
153 #define REG_IPC_APP_WR(env, INDEX, value) \
154 (*(volatile u32*)((u8*)env + IPC_REG_BASE_ADDR + 4*(INDEX)) = value)
156 #endif /* REG_ACCESS_H_ */