2 ****************************************************************************************
6 * Copyright (C) ESWIN 2015-2020
8 ****************************************************************************************
11 #ifndef _ECRNX_PROF_H_
12 #define _ECRNX_PROF_H_
14 #include "reg_access.h"
15 #include "ecrnx_platform.h"
17 static inline void ecrnx_prof_set(struct ecrnx_hw *ecrnx_hw, int val)
19 struct ecrnx_plat *ecrnx_plat = ecrnx_hw->plat;
20 ECRNX_REG_WRITE(val, ecrnx_plat, ECRNX_ADDR_SYSTEM, NXMAC_SW_SET_PROFILING_ADDR);
23 static inline void ecrnx_prof_clear(struct ecrnx_hw *ecrnx_hw, int val)
25 struct ecrnx_plat *ecrnx_plat = ecrnx_hw->plat;
26 ECRNX_REG_WRITE(val, ecrnx_plat, ECRNX_ADDR_SYSTEM, NXMAC_SW_CLEAR_PROFILING_ADDR);
30 /* Defines for SW Profiling registers values */
51 SW_PROF_HOSTBUF_IDX = 12,
52 /****** IPC IRQs related signals ******/
54 SW_PROF_IRQ_E2A_RXDESC = 16, // to make sure we let 16 bits available for LMAC FW
55 SW_PROF_IRQ_E2A_TXCFM,
64 SW_PROF_IRQ_A2E_TXCFM_BACK,
66 /****** Driver functions related signals ******/
67 SW_PROF_WAIT_QUEUE_STOP,
68 SW_PROF_WAIT_QUEUE_WAKEUP,
70 SW_PROF_ECRNX_IPC_IRQ_HDLR,
71 SW_PROF_ECRNX_IPC_THR_IRQ_HDLR,
73 SW_PROF_ECRNX_PATTERN,
77 // [LT]For debug purpose only
79 #define SW_PROF_CHAN_CTXT_CFM_HDL_BIT (21)
80 #define SW_PROF_CHAN_CTXT_CFM_BIT (22)
81 #define SW_PROF_CHAN_CTXT_CFM_SWDONE_BIT (23)
82 #define SW_PROF_CHAN_CTXT_PUSH_BIT (24)
83 #define SW_PROF_CHAN_CTXT_QUEUE_BIT (25)
84 #define SW_PROF_CHAN_CTXT_TX_BIT (26)
85 #define SW_PROF_CHAN_CTXT_TX_PAUSE_BIT (27)
86 #define SW_PROF_CHAN_CTXT_PSWTCH_BIT (28)
87 #define SW_PROF_CHAN_CTXT_SWTCH_BIT (29)
91 #define REG_SW_SET_PROFILING_CHAN(env, bit) \
92 ecrnx_prof_set((struct ecrnx_hw*)env, BIT(bit))
94 #define REG_SW_CLEAR_PROFILING_CHAN(env, bit) \
95 ecrnx_prof_clear((struct ecrnx_hw*)env, BIT(bit))
98 #define SW_PROF_CHAN_CTXT_CFM_HDL_BIT (0)
99 #define SW_PROF_CHAN_CTXT_CFM_BIT (0)
100 #define SW_PROF_CHAN_CTXT_CFM_SWDONE_BIT (0)
101 #define SW_PROF_CHAN_CTXT_PUSH_BIT (0)
102 #define SW_PROF_CHAN_CTXT_QUEUE_BIT (0)
103 #define SW_PROF_CHAN_CTXT_TX_BIT (0)
104 #define SW_PROF_CHAN_CTXT_TX_PAUSE_BIT (0)
105 #define SW_PROF_CHAN_CTXT_PSWTCH_BIT (0)
106 #define SW_PROF_CHAN_CTXT_SWTCH_BIT (0)
108 #define REG_SW_SET_PROFILING_CHAN(env, bit) do {} while (0)
109 #define REG_SW_CLEAR_PROFILING_CHAN(env, bit) do {} while (0)
112 #ifdef CONFIG_ECRNX_ESWIN
113 #undef CONFIG_ECRNX_SW_PROFILING
115 #ifdef CONFIG_ECRNX_SW_PROFILING
116 /* Macros for SW PRofiling registers access */
117 #define REG_SW_SET_PROFILING(env, bit) \
118 ecrnx_prof_set((struct ecrnx_hw*)env, BIT(bit))
120 #define REG_SW_SET_HOSTBUF_IDX_PROFILING(env, val) \
121 ecrnx_prof_set((struct ecrnx_hw*)env, val<<(SW_PROF_HOSTBUF_IDX))
123 #define REG_SW_CLEAR_PROFILING(env, bit) \
124 ecrnx_prof_clear((struct ecrnx_hw*)env, BIT(bit))
126 #define REG_SW_CLEAR_HOSTBUF_IDX_PROFILING(env) \
127 ecrnx_prof_clear((struct ecrnx_hw*)env,0x0F<<(SW_PROF_HOSTBUF_IDX))
130 #define REG_SW_SET_PROFILING(env, value) do {} while (0)
131 #define REG_SW_CLEAR_PROFILING(env, value) do {} while (0)
132 #define REG_SW_SET_HOSTBUF_IDX_PROFILING(env, val) do {} while (0)
133 #define REG_SW_CLEAR_HOSTBUF_IDX_PROFILING(env) do {} while (0)
136 #endif /* _ECRNX_PROF_H_ */