1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2010 Broadcom Corporation
6 #include <linux/types.h>
7 #include <linux/atomic.h>
8 #include <linux/kernel.h>
9 #include <linux/kthread.h>
10 #include <linux/printk.h>
11 #include <linux/pci_ids.h>
12 #include <linux/netdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/sched/signal.h>
15 #include <linux/mmc/sdio.h>
16 #include <linux/mmc/sdio_ids.h>
17 #include <linux/mmc/sdio_func.h>
18 #include <linux/mmc/card.h>
19 #include <linux/mmc/core.h>
20 #include <linux/semaphore.h>
21 #include <linux/firmware.h>
22 #include <linux/module.h>
23 #include <linux/bcma/bcma.h>
24 #include <linux/debugfs.h>
25 #include <linux/vmalloc.h>
26 #include <asm/unaligned.h>
28 #include <brcmu_wifi.h>
29 #include <brcmu_utils.h>
30 #include <brcm_hw_ids.h>
39 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500)
40 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500)
42 /* watermark expressed in number of words */
43 #define DEFAULT_F2_WATERMARK 0x8
44 #define CY_4373_F2_WATERMARK 0x40
45 #define CY_4373_F1_MESBUSYCTRL (CY_4373_F2_WATERMARK | SBSDIO_MESBUSYCTRL_ENAB)
46 #define CY_43012_F2_WATERMARK 0x60
47 #define CY_43012_MES_WATERMARK 0x50
48 #define CY_43012_MESBUSYCTRL (CY_43012_MES_WATERMARK | \
49 SBSDIO_MESBUSYCTRL_ENAB)
50 #define CY_4339_F2_WATERMARK 48
51 #define CY_4339_MES_WATERMARK 80
52 #define CY_4339_MESBUSYCTRL (CY_4339_MES_WATERMARK | \
53 SBSDIO_MESBUSYCTRL_ENAB)
54 #define CY_43455_F2_WATERMARK 0x60
55 #define CY_43455_MES_WATERMARK 0x50
56 #define CY_43455_MESBUSYCTRL (CY_43455_MES_WATERMARK | \
57 SBSDIO_MESBUSYCTRL_ENAB)
58 #define CY_435X_F2_WATERMARK 0x40
59 #define CY_435X_F1_MESBUSYCTRL (CY_435X_F2_WATERMARK | \
60 SBSDIO_MESBUSYCTRL_ENAB)
64 #define BRCMF_TRAP_INFO_SIZE 80
66 #define CBUF_LEN (128)
68 /* Device console log buffer state */
69 #define CONSOLE_BUFFER_MAX 2024
72 __le32 buf; /* Can't be pointer on (64-bit) hosts */
75 char *_buf_compat; /* Redundant pointer for backward compat. */
80 * When there is no UART (e.g. Quickturn),
81 * the host should write a complete
82 * input line directly into cbuf and then write
83 * the length into vcons_in.
84 * This may also be used when there is a real UART
85 * (at risk of conflicting with
86 * the real UART). vcons_out is currently unused.
91 /* Output (logging) buffer
92 * Console output is written to a ring buffer log_buf at index log_idx.
93 * The host may read the output when it sees log_idx advance.
94 * Output will be lost if the output wraps around faster than the host
97 struct rte_log_le log_le;
99 /* Console input line buffer
100 * Characters are read one at a time into cbuf
101 * until <CR> is received, then
102 * the buffer is processed as a command line.
103 * Also used for virtual UART.
110 #include <chipcommon.h>
114 #include "tracepoint.h"
116 #define TXQLEN 2048 /* bulk tx queue length */
117 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
118 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
121 #define TXRETRIES 2 /* # of retries for tx frames */
123 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
126 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
129 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
131 #define MEMBLOCK 2048 /* Block size used for downloading
133 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
134 biggest possible glom */
136 #define BRCMF_FIRSTREAD (1 << 6)
138 #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */
140 /* SBSDIO_DEVICE_CTL */
142 /* 1: device will assert busy signal when receiving CMD53 */
143 #define SBSDIO_DEVCTL_SETBUSY 0x01
144 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
145 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
146 /* 1: mask all interrupts to host except the chipActive (rev 8) */
147 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
148 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
149 * sdio bus power cycle to clear (rev 9) */
150 #define SBSDIO_DEVCTL_PADS_ISO 0x08
151 /* 1: enable F2 Watermark */
152 #define SBSDIO_DEVCTL_F2WM_ENAB 0x10
153 /* Force SD->SB reset mapping (rev 11) */
154 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
155 /* Determined by CoreControl bit */
156 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
157 /* Force backplane reset */
158 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
159 /* Force no backplane reset */
160 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
162 /* direct(mapped) cis space */
164 /* MAPPED common CIS address */
165 #define SBSDIO_CIS_BASE_COMMON 0x1000
166 /* maximum bytes in one CIS */
167 #define SBSDIO_CIS_SIZE_LIMIT 0x200
168 /* cis offset addr is < 17 bits */
169 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
171 /* manfid tuple length, include tuple, link bytes */
172 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
174 #define SD_REG(field) \
175 (offsetof(struct sdpcmd_regs, field))
177 /* SDIO function 1 register CHIPCLKCSR */
178 /* Force ALP request to backplane */
179 #define SBSDIO_FORCE_ALP 0x01
180 /* Force HT request to backplane */
181 #define SBSDIO_FORCE_HT 0x02
182 /* Force ILP request to backplane */
183 #define SBSDIO_FORCE_ILP 0x04
184 /* Make ALP ready (power up xtal) */
185 #define SBSDIO_ALP_AVAIL_REQ 0x08
186 /* Make HT ready (power up PLL) */
187 #define SBSDIO_HT_AVAIL_REQ 0x10
188 /* Squelch clock requests from HW */
189 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
190 /* Status: ALP is ready */
191 #define SBSDIO_ALP_AVAIL 0x40
192 /* Status: HT is ready */
193 #define SBSDIO_HT_AVAIL 0x80
194 #define SBSDIO_CSR_MASK 0x1F
195 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
196 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
197 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
198 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
199 #define SBSDIO_CLKAV(regval, alponly) \
200 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
203 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
204 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
205 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
206 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
207 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
208 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
209 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
210 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
211 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
212 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
213 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
214 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
215 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
216 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
217 #define I_PC (1 << 10) /* descriptor error */
218 #define I_PD (1 << 11) /* data error */
219 #define I_DE (1 << 12) /* Descriptor protocol Error */
220 #define I_RU (1 << 13) /* Receive descriptor Underflow */
221 #define I_RO (1 << 14) /* Receive fifo Overflow */
222 #define I_XU (1 << 15) /* Transmit fifo Underflow */
223 #define I_RI (1 << 16) /* Receive Interrupt */
224 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
225 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
226 #define I_XI (1 << 24) /* Transmit Interrupt */
227 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
228 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
229 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
230 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
231 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
232 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
233 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
234 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
235 #define I_DMA (I_RI | I_XI | I_ERRORS)
238 #define CC_CISRDY (1 << 0) /* CIS Ready */
239 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
240 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
241 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
242 #define CC_XMTDATAAVAIL_MODE (1 << 4)
243 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
246 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
247 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
248 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
249 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
252 * Software allocation of To SB Mailbox resources
255 /* tosbmailbox bits corresponding to intstatus bits */
256 #define SMB_NAK (1 << 0) /* Frame NAK */
257 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
258 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
259 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
261 /* tosbmailboxdata */
262 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
265 * Software allocation of To Host Mailbox resources
269 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
270 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
271 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
272 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
274 /* tohostmailboxdata */
275 #define HMB_DATA_NAKHANDLED 0x0001 /* retransmit NAK'd frame */
276 #define HMB_DATA_DEVREADY 0x0002 /* talk to host after enable */
277 #define HMB_DATA_FC 0x0004 /* per prio flowcontrol update flag */
278 #define HMB_DATA_FWREADY 0x0008 /* fw ready for protocol activity */
279 #define HMB_DATA_FWHALT 0x0010 /* firmware halted */
281 #define HMB_DATA_FCDATA_MASK 0xff000000
282 #define HMB_DATA_FCDATA_SHIFT 24
284 #define HMB_DATA_VERSION_MASK 0x00ff0000
285 #define HMB_DATA_VERSION_SHIFT 16
288 * Software-defined protocol header
291 /* Current protocol version */
292 #define SDPCM_PROT_VERSION 4
295 * Shared structure between dongle and the host.
296 * The structure contains pointers to trap or assert information.
298 #define SDPCM_SHARED_VERSION 0x0003
299 #define SDPCM_SHARED_VERSION_MASK 0x00FF
300 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
301 #define SDPCM_SHARED_ASSERT 0x0200
302 #define SDPCM_SHARED_TRAP 0x0400
304 /* Space for header read, limit for data packets */
305 #define MAX_HDR_READ (1 << 6)
306 #define MAX_RX_DATASZ 2048
308 /* Bump up limit on waiting for HT to account for first startup;
309 * if the image is doing a CRC calculation before programming the PMU
310 * for HT availability, it could take a couple hundred ms more, so
311 * max out at a 1 second (1000000us).
313 #undef PMU_MAX_TRANSITION_DLY
314 #define PMU_MAX_TRANSITION_DLY 1000000
316 /* Value for ChipClockCSR during initial setup */
317 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
318 SBSDIO_ALP_AVAIL_REQ)
320 /* Flags for SDH calls */
321 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
323 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
326 #define BRCMF_IDLE_INTERVAL 1
328 #define KSO_WAIT_US 50
329 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
330 #define BRCMF_SDIO_MAX_ACCESS_ERRORS 5
333 /* Device console log buffer state */
334 struct brcmf_console {
335 uint count; /* Poll interval msec counter */
336 uint log_addr; /* Log struct address (fixed) */
337 struct rte_log_le log_le; /* Log struct (host copy) */
338 uint bufsize; /* Size of log buffer */
339 u8 *buf; /* Log buffer (host copy) */
340 uint last; /* Last buffer read index */
343 struct brcmf_trap_info {
357 __le32 r9; /* sb/v6 */
358 __le32 r10; /* sl/v7 */
359 __le32 r11; /* fp/v8 */
367 struct sdpcm_shared {
371 u32 assert_file_addr;
373 u32 console_addr; /* Address of struct rte_console */
379 struct sdpcm_shared_le {
382 __le32 assert_exp_addr;
383 __le32 assert_file_addr;
385 __le32 console_addr; /* Address of struct rte_console */
386 __le32 msgtrace_addr;
391 /* dongle SDIO bus specific header info */
392 struct brcmf_sdio_hdrinfo {
404 * hold counter variables
406 struct brcmf_sdio_count {
407 uint intrcount; /* Count of device interrupt callbacks */
408 uint lastintrs; /* Count as of last watchdog timer */
409 uint pollcnt; /* Count of active polls */
410 uint regfails; /* Count of R_REG failures */
411 uint tx_sderrs; /* Count of tx attempts with sd errors */
412 uint fcqueued; /* Tx packets that got queued */
413 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
414 uint rx_toolong; /* Receive frames too long to receive */
415 uint rxc_errors; /* SDIO errors when reading control frames */
416 uint rx_hdrfail; /* SDIO errors on header reads */
417 uint rx_badhdr; /* Bad received headers (roosync?) */
418 uint rx_badseq; /* Mismatched rx sequence number */
419 uint fc_rcvd; /* Number of flow-control events received */
420 uint fc_xoff; /* Number which turned on flow-control */
421 uint fc_xon; /* Number which turned off flow-control */
422 uint rxglomfail; /* Failed deglom attempts */
423 uint rxglomframes; /* Number of glom frames (superframes) */
424 uint rxglompkts; /* Number of packets from glom frames */
425 uint f2rxhdrs; /* Number of header reads */
426 uint f2rxdata; /* Number of frame data reads */
427 uint f2txdata; /* Number of f2 frame writes */
428 uint f1regdata; /* Number of f1 register accesses */
429 uint tickcnt; /* Number of watchdog been schedule */
430 ulong tx_ctlerrs; /* Err of sending ctrl frames */
431 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
432 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
433 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
434 ulong rx_readahead_cnt; /* packets where header read-ahead was used */
437 /* misc chip info needed by some of the routines */
438 /* Private data for SDIO bus interaction */
440 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
441 struct brcmf_chip *ci; /* Chip info struct */
442 struct brcmf_core *sdio_core; /* sdio core info struct */
444 u32 hostintmask; /* Copy of Host Interrupt Mask */
445 atomic_t intstatus; /* Intstatus bits (events) pending */
446 atomic_t fcstate; /* State of dongle flow-control */
448 uint blocksize; /* Block size of SDIO transfers */
449 uint roundup; /* Max roundup limit */
451 struct pktq txq; /* Queue length used for flow-control */
452 u8 flowcontrol; /* per prio flow control bitmask */
453 u8 tx_seq; /* Transmit sequence number (next) */
454 u8 tx_max; /* Maximum transmit sequence allowed */
456 u8 *hdrbuf; /* buffer for handling rx frame */
457 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
458 u8 rx_seq; /* Receive sequence number (expected) */
459 struct brcmf_sdio_hdrinfo cur_read;
460 /* info of current read frame */
461 bool rxskip; /* Skip receive (awaiting NAK ACK) */
462 bool rxpending; /* Data frame pending in dongle */
464 uint rxbound; /* Rx frames to read before resched */
465 uint txbound; /* Tx frames to send before resched */
468 struct sk_buff *glomd; /* Packet containing glomming descriptor */
469 struct sk_buff_head glom; /* Packet list for glommed superframe */
471 u8 *rxbuf; /* Buffer for receiving control packets */
472 uint rxblen; /* Allocated length of rxbuf */
473 u8 *rxctl; /* Aligned pointer into rxbuf */
474 u8 *rxctl_orig; /* pointer for freeing rxctl */
475 uint rxlen; /* Length of valid data in buffer */
476 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
478 u8 sdpcm_ver; /* Bus protocol reported by dongle */
480 bool intr; /* Use interrupts */
481 bool poll; /* Use polling */
482 atomic_t ipend; /* Device interrupt is pending */
483 uint spurious; /* Count of spurious interrupts */
484 uint pollrate; /* Ticks between device polls */
485 uint polltick; /* Tick counter */
488 uint console_interval;
489 struct brcmf_console console; /* Console output polling support */
490 uint console_addr; /* Console address from shared struct */
493 uint clkstate; /* State of sd and backplane clock(s) */
494 s32 idletime; /* Control for activity timeout */
495 s32 idlecount; /* Activity timeout counter */
496 s32 idleclock; /* How to set bus driver when idle */
497 bool rxflow_mode; /* Rx flow control mode */
498 bool rxflow; /* Is rx flow control on */
499 bool alp_only; /* Don't use HT clock (ALP only) */
503 bool ctrl_frame_stat;
506 spinlock_t txq_lock; /* protect bus->txq */
507 wait_queue_head_t ctrl_wait;
508 wait_queue_head_t dcmd_resp_wait;
510 struct timer_list timer;
511 struct completion watchdog_wait;
512 struct task_struct *watchdog_tsk;
515 struct workqueue_struct *brcmf_wq;
516 struct work_struct datawork;
520 bool txoff; /* Transmit flow-controlled */
521 struct brcmf_sdio_count sdcnt;
522 bool sr_enabled; /* SaveRestore enabled */
525 u8 tx_hdrlen; /* sdio bus header length for tx packet */
526 bool txglom; /* host tx glomming enable flag */
527 u16 head_align; /* buffer pointer alignment */
528 u16 sgentry_align; /* scatter-gather buffer alignment */
534 #define CLK_PENDING 2
538 static int qcount[NUMPRIO];
541 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
543 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
545 /* Limit on rounding up frames */
546 static const uint max_roundup = 512;
548 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
554 enum brcmf_sdio_frmtype {
555 BRCMF_SDIO_FT_NORMAL,
560 #define SDIOD_DRVSTR_KEY(chip, pmu) (((unsigned int)(chip) << 16) | (pmu))
562 /* SDIO Pad drive strength to select value mappings */
563 struct sdiod_drive_str {
564 u8 strength; /* Pad Drive Strength in mA */
565 u8 sel; /* Chip-specific select value */
568 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
569 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
580 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
581 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
591 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
592 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
598 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
599 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
606 BRCMF_FW_DEF(43143, "brcmfmac43143-sdio");
607 BRCMF_FW_DEF(43241B0, "brcmfmac43241b0-sdio");
608 BRCMF_FW_DEF(43241B4, "brcmfmac43241b4-sdio");
609 BRCMF_FW_DEF(43241B5, "brcmfmac43241b5-sdio");
610 BRCMF_FW_DEF(4329, "brcmfmac4329-sdio");
611 BRCMF_FW_DEF(4330, "brcmfmac4330-sdio");
612 BRCMF_FW_DEF(4334, "brcmfmac4334-sdio");
613 BRCMF_FW_DEF(43340, "brcmfmac43340-sdio");
614 BRCMF_FW_DEF(4335, "brcmfmac4335-sdio");
615 BRCMF_FW_DEF(43362, "brcmfmac43362-sdio");
616 BRCMF_FW_DEF(4339, "brcmfmac4339-sdio");
617 BRCMF_FW_DEF(43430A0, "brcmfmac43430a0-sdio");
618 /* Note the names are not postfixed with a1 for backward compatibility */
619 BRCMF_FW_CLM_DEF(43430A1, "brcmfmac43430-sdio");
620 BRCMF_FW_DEF(43430B0, "brcmfmac43430b0-sdio");
621 BRCMF_FW_CLM_DEF(43455, "brcmfmac43455-sdio");
622 BRCMF_FW_DEF(43456, "brcmfmac43456-sdio");
623 BRCMF_FW_CLM_DEF(4354, "brcmfmac4354-sdio");
624 BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-sdio");
625 BRCMF_FW_DEF(4359, "brcmfmac4359-sdio");
626 BRCMF_FW_CLM_DEF(4373, "brcmfmac4373-sdio");
627 BRCMF_FW_CLM_DEF(43012, "brcmfmac43012-sdio");
628 BRCMF_FW_CLM_DEF(43752, "brcmfmac43752-sdio");
630 /* firmware config files */
631 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-sdio.*.txt");
633 /* per-board firmware binaries */
634 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-sdio.*.bin");
636 static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
637 BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
638 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
639 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
640 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5),
641 BRCMF_FW_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329),
642 BRCMF_FW_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330),
643 BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
644 BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
645 BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340),
646 BRCMF_FW_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
647 BRCMF_FW_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
648 BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
649 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0),
650 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000002, 43430A1),
651 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFC, 43430B0),
652 BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0x00000200, 43456),
653 BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFDC0, 43455),
654 BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
655 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
656 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359),
657 BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373),
658 BRCMF_FW_ENTRY(CY_CC_43012_CHIP_ID, 0xFFFFFFFF, 43012),
659 BRCMF_FW_ENTRY(CY_CC_43752_CHIP_ID, 0xFFFFFFFF, 43752)
662 #define TXCTL_CREDITS 2
664 static void pkt_align(struct sk_buff *p, int len, int align)
667 datalign = (unsigned long)(p->data);
668 datalign = roundup(datalign, (align)) - datalign;
670 skb_pull(p, datalign);
674 /* To check if there's window offered */
675 static bool data_ok(struct brcmf_sdio *bus)
679 /* Reserve TXCTL_CREDITS credits for txctl when it is ready to send */
680 if (bus->ctrl_frame_stat)
681 tx_rsv = TXCTL_CREDITS;
683 return (bus->tx_max - bus->tx_seq - tx_rsv) != 0 &&
684 ((bus->tx_max - bus->tx_seq - tx_rsv) & 0x80) == 0;
688 /* To check if there's window offered */
689 static bool txctl_ok(struct brcmf_sdio *bus)
691 return (bus->tx_max - bus->tx_seq) != 0 &&
692 ((bus->tx_max - bus->tx_seq) & 0x80) == 0;
696 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
698 u8 wr_val = 0, rd_val, cmp_val, bmask;
703 brcmf_dbg(TRACE, "Enter: on=%d\n", on);
705 sdio_retune_crc_disable(bus->sdiodev->func1);
707 /* Cannot re-tune if device is asleep; defer till we're awake */
709 sdio_retune_hold_now(bus->sdiodev->func1);
711 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
712 /* 1st KSO write goes to AOS wake up core if device is asleep */
713 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err);
715 /* In case of 43012 chip, the chip could go down immediately after
716 * KSO bit is cleared. So the further reads of KSO register could
717 * fail. Thereby just bailing out immediately after clearing KSO
718 * bit, to avoid polling of KSO bit.
720 if (!on && bus->ci->chip == CY_CC_43012_CHIP_ID)
724 /* device WAKEUP through KSO:
725 * write bit 0 & read back until
726 * both bits 0 (kso bit) & 1 (dev on status) are set
728 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
729 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
731 usleep_range(2000, 3000);
733 /* Put device to sleep, turn off KSO */
735 /* only check for bit0, bit1(dev on status) may not
736 * get cleared right away
738 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
742 /* reliable KSO bit set/clr:
743 * the sdiod sleep write access is synced to PMU 32khz clk
744 * just one write attempt may fail,
745 * read it back until it matches written value
747 rd_val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
750 if ((rd_val & bmask) == cmp_val)
754 /* bail out upon subsequent access errors */
755 if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS))
759 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val,
762 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
765 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
768 if (try_cnt > MAX_KSO_ATTEMPTS)
769 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
772 sdio_retune_release(bus->sdiodev->func1);
774 sdio_retune_crc_enable(bus->sdiodev->func1);
779 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
781 /* Turn backplane clock on or off */
782 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
785 u8 clkctl, clkreq, devctl;
786 unsigned long timeout;
788 brcmf_dbg(SDIO, "Enter\n");
792 if (bus->sr_enabled) {
793 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
798 /* Request HT Avail */
800 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
802 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
805 brcmf_err("HT Avail request error: %d\n", err);
809 /* Check current status */
810 clkctl = brcmf_sdiod_readb(bus->sdiodev,
811 SBSDIO_FUNC1_CHIPCLKCSR, &err);
813 brcmf_err("HT Avail read error: %d\n", err);
817 /* Go to pending and await interrupt if appropriate */
818 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
819 /* Allow only clock-available interrupt */
820 devctl = brcmf_sdiod_readb(bus->sdiodev,
821 SBSDIO_DEVICE_CTL, &err);
823 brcmf_err("Devctl error setting CA: %d\n", err);
827 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
828 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL,
830 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
831 bus->clkstate = CLK_PENDING;
834 } else if (bus->clkstate == CLK_PENDING) {
835 /* Cancel CA-only interrupt filter */
836 devctl = brcmf_sdiod_readb(bus->sdiodev,
837 SBSDIO_DEVICE_CTL, &err);
838 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
839 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL,
843 /* Otherwise, wait here (polling) for HT Avail */
845 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
846 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
847 clkctl = brcmf_sdiod_readb(bus->sdiodev,
848 SBSDIO_FUNC1_CHIPCLKCSR,
850 if (time_after(jiffies, timeout))
853 usleep_range(5000, 10000);
856 brcmf_err("HT Avail request error: %d\n", err);
859 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
860 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
861 PMU_MAX_TRANSITION_DLY, clkctl);
865 /* Mark clock available */
866 bus->clkstate = CLK_AVAIL;
867 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
870 if (!bus->alp_only) {
871 if (SBSDIO_ALPONLY(clkctl))
872 brcmf_err("HT Clock should be on\n");
874 #endif /* defined (DEBUG) */
879 if (bus->clkstate == CLK_PENDING) {
880 /* Cancel CA-only interrupt filter */
881 devctl = brcmf_sdiod_readb(bus->sdiodev,
882 SBSDIO_DEVICE_CTL, &err);
883 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
884 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL,
888 bus->clkstate = CLK_SDONLY;
889 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
891 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
893 brcmf_err("Failed access turning clock off: %d\n",
901 /* Change idle/active SD state */
902 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
904 brcmf_dbg(SDIO, "Enter\n");
907 bus->clkstate = CLK_SDONLY;
909 bus->clkstate = CLK_NONE;
914 /* Transition SD and backplane clock readiness */
915 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
918 uint oldstate = bus->clkstate;
921 brcmf_dbg(SDIO, "Enter\n");
923 /* Early exit if we're already there */
924 if (bus->clkstate == target)
929 /* Make sure SD clock is available */
930 if (bus->clkstate == CLK_NONE)
931 brcmf_sdio_sdclk(bus, true);
932 /* Now request HT Avail on the backplane */
933 brcmf_sdio_htclk(bus, true, pendok);
937 /* Remove HT request, or bring up SD clock */
938 if (bus->clkstate == CLK_NONE)
939 brcmf_sdio_sdclk(bus, true);
940 else if (bus->clkstate == CLK_AVAIL)
941 brcmf_sdio_htclk(bus, false, false);
943 brcmf_err("request for %d -> %d\n",
944 bus->clkstate, target);
948 /* Make sure to remove HT request */
949 if (bus->clkstate == CLK_AVAIL)
950 brcmf_sdio_htclk(bus, false, false);
951 /* Now remove the SD clock */
952 brcmf_sdio_sdclk(bus, false);
956 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
963 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
968 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
969 (sleep ? "SLEEP" : "WAKE"),
970 (bus->sleeping ? "SLEEP" : "WAKE"));
972 /* If SR is enabled control bus state with KSO */
973 if (bus->sr_enabled) {
974 /* Done if we're already in the requested state */
975 if (sleep == bus->sleeping)
980 clkcsr = brcmf_sdiod_readb(bus->sdiodev,
981 SBSDIO_FUNC1_CHIPCLKCSR,
983 if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
984 brcmf_dbg(SDIO, "no clock, set ALP\n");
985 brcmf_sdiod_writeb(bus->sdiodev,
986 SBSDIO_FUNC1_CHIPCLKCSR,
987 SBSDIO_ALP_AVAIL_REQ, &err);
989 err = brcmf_sdio_kso_control(bus, false);
991 err = brcmf_sdio_kso_control(bus, true);
994 brcmf_err("error while changing bus sleep state %d\n",
1001 /* control clocks */
1003 if (!bus->sr_enabled)
1004 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
1006 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
1007 brcmf_sdio_wd_timer(bus, true);
1009 bus->sleeping = sleep;
1010 brcmf_dbg(SDIO, "new state %s\n",
1011 (sleep ? "SLEEP" : "WAKE"));
1013 brcmf_dbg(SDIO, "Exit: err=%d\n", err);
1019 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
1021 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
1024 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
1025 struct sdpcm_shared *sh)
1030 struct sdpcm_shared_le sh_le;
1033 sdio_claim_host(bus->sdiodev->func1);
1034 brcmf_sdio_bus_sleep(bus, false, false);
1037 * Read last word in socram to determine
1038 * address of sdpcm_shared structure
1040 shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
1041 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
1042 shaddr -= bus->ci->srsize;
1043 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
1049 * Check if addr is valid.
1050 * NVRAM length at the end of memory should have been overwritten.
1052 addr = le32_to_cpu(addr_le);
1053 if (!brcmf_sdio_valid_shared_address(addr)) {
1054 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
1059 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
1061 /* Read hndrte_shared structure */
1062 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1063 sizeof(struct sdpcm_shared_le));
1067 sdio_release_host(bus->sdiodev->func1);
1070 sh->flags = le32_to_cpu(sh_le.flags);
1071 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1072 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1073 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1074 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1075 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1076 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1078 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1079 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1080 SDPCM_SHARED_VERSION,
1081 sh->flags & SDPCM_SHARED_VERSION_MASK);
1087 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
1089 sdio_release_host(bus->sdiodev->func1);
1093 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1095 struct sdpcm_shared sh;
1097 if (brcmf_sdio_readshared(bus, &sh) == 0)
1098 bus->console_addr = sh.console_addr;
1101 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1106 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1108 struct brcmf_sdio_dev *sdiod = bus->sdiodev;
1109 struct brcmf_core *core = bus->sdio_core;
1115 brcmf_dbg(SDIO, "Enter\n");
1117 /* Read mailbox data and ack that we did so */
1118 hmb_data = brcmf_sdiod_readl(sdiod,
1119 core->base + SD_REG(tohostmailboxdata),
1123 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox),
1126 bus->sdcnt.f1regdata += 2;
1128 /* dongle indicates the firmware has halted/crashed */
1129 if (hmb_data & HMB_DATA_FWHALT) {
1130 brcmf_dbg(SDIO, "mailbox indicates firmware halted\n");
1131 brcmf_fw_crashed(&sdiod->func1->dev);
1134 /* Dongle recomposed rx frames, accept them again */
1135 if (hmb_data & HMB_DATA_NAKHANDLED) {
1136 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1139 brcmf_err("unexpected NAKHANDLED!\n");
1141 bus->rxskip = false;
1142 intstatus |= I_HMB_FRAME_IND;
1146 * DEVREADY does not occur with gSPI.
1148 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1150 (hmb_data & HMB_DATA_VERSION_MASK) >>
1151 HMB_DATA_VERSION_SHIFT;
1152 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1153 brcmf_err("Version mismatch, dongle reports %d, "
1155 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1157 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1161 * Retrieve console state address now that firmware should have
1164 brcmf_sdio_get_console_addr(bus);
1168 * Flow Control has been moved into the RX headers and this out of band
1169 * method isn't used any more.
1170 * remaining backward compatible with older dongles.
1172 if (hmb_data & HMB_DATA_FC) {
1173 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1174 HMB_DATA_FCDATA_SHIFT;
1176 if (fcbits & ~bus->flowcontrol)
1177 bus->sdcnt.fc_xoff++;
1179 if (bus->flowcontrol & ~fcbits)
1180 bus->sdcnt.fc_xon++;
1182 bus->sdcnt.fc_rcvd++;
1183 bus->flowcontrol = fcbits;
1186 /* Shouldn't be any others */
1187 if (hmb_data & ~(HMB_DATA_DEVREADY |
1188 HMB_DATA_NAKHANDLED |
1192 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1193 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1199 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1201 struct brcmf_sdio_dev *sdiod = bus->sdiodev;
1202 struct brcmf_core *core = bus->sdio_core;
1208 brcmf_err("%sterminate frame%s\n",
1209 abort ? "abort command, " : "",
1210 rtx ? ", send NAK" : "");
1213 brcmf_sdiod_abort(bus->sdiodev, bus->sdiodev->func2);
1215 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
1217 bus->sdcnt.f1regdata++;
1219 /* Wait until the packet has been flushed (device/FIFO stable) */
1220 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1221 hi = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCHI,
1223 lo = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCLO,
1225 bus->sdcnt.f1regdata += 2;
1227 if ((hi == 0) && (lo == 0))
1230 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1231 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1232 lastrbc, (hi << 8) + lo);
1234 lastrbc = (hi << 8) + lo;
1238 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1240 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1244 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox),
1247 bus->sdcnt.f1regdata++;
1252 /* Clear partial in any case */
1253 bus->cur_read.len = 0;
1256 static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
1258 struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
1261 /* On failure, abort the command and terminate the frame */
1262 brcmf_err("sdio error, abort command and terminate frame\n");
1263 bus->sdcnt.tx_sderrs++;
1265 brcmf_sdiod_abort(sdiodev, sdiodev->func2);
1266 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
1267 bus->sdcnt.f1regdata++;
1269 for (i = 0; i < 3; i++) {
1270 hi = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1271 lo = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1272 bus->sdcnt.f1regdata += 2;
1273 if ((hi == 0) && (lo == 0))
1278 /* return total length of buffer chain */
1279 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1285 skb_queue_walk(&bus->glom, p)
1290 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1292 struct sk_buff *cur, *next;
1294 skb_queue_walk_safe(&bus->glom, cur, next) {
1295 skb_unlink(cur, &bus->glom);
1296 brcmu_pkt_buf_free_skb(cur);
1301 * brcmfmac sdio bus specific header
1302 * This is the lowest layer header wrapped on the packets transmitted between
1303 * host and WiFi dongle which contains information needed for SDIO core and
1306 * It consists of 3 parts: hardware header, hardware extension header and
1308 * hardware header (frame tag) - 4 bytes
1309 * Byte 0~1: Frame length
1310 * Byte 2~3: Checksum, bit-wise inverse of frame length
1311 * hardware extension header - 8 bytes
1312 * Tx glom mode only, N/A for Rx or normal Tx
1313 * Byte 0~1: Packet length excluding hw frame tag
1315 * Byte 3: Frame flags, bit 0: last frame indication
1316 * Byte 4~5: Reserved
1317 * Byte 6~7: Tail padding length
1318 * software header - 8 bytes
1319 * Byte 0: Rx/Tx sequence number
1320 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1321 * Byte 2: Length of next data frame, reserved for Tx
1322 * Byte 3: Data offset
1323 * Byte 4: Flow control bits, reserved for Tx
1324 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1325 * Byte 6~7: Reserved
1327 #define SDPCM_HWHDR_LEN 4
1328 #define SDPCM_HWEXT_LEN 8
1329 #define SDPCM_SWHDR_LEN 8
1330 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1331 /* software header */
1332 #define SDPCM_SEQ_MASK 0x000000ff
1333 #define SDPCM_SEQ_WRAP 256
1334 #define SDPCM_CHANNEL_MASK 0x00000f00
1335 #define SDPCM_CHANNEL_SHIFT 8
1336 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1337 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1338 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1339 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1340 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1341 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1342 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1343 #define SDPCM_NEXTLEN_SHIFT 16
1344 #define SDPCM_DOFFSET_MASK 0xff000000
1345 #define SDPCM_DOFFSET_SHIFT 24
1346 #define SDPCM_FCMASK_MASK 0x000000ff
1347 #define SDPCM_WINDOW_MASK 0x0000ff00
1348 #define SDPCM_WINDOW_SHIFT 8
1350 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1353 hdrvalue = le32_to_cpu(*(__le32 *)swheader);
1354 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1357 static inline bool brcmf_sdio_fromevntchan(u8 *swheader)
1362 hdrvalue = le32_to_cpu(*(__le32 *)swheader);
1363 ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT);
1365 return (ret == SDPCM_EVENT_CHANNEL);
1368 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1369 struct brcmf_sdio_hdrinfo *rd,
1370 enum brcmf_sdio_frmtype type)
1373 u8 rx_seq, fc, tx_seq_max;
1376 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1379 len = get_unaligned_le16(header);
1380 checksum = get_unaligned_le16(header + sizeof(u16));
1381 /* All zero means no more to read */
1382 if (!(len | checksum)) {
1383 bus->rxpending = false;
1386 if ((u16)(~(len ^ checksum))) {
1387 brcmf_err("HW header checksum error\n");
1388 bus->sdcnt.rx_badhdr++;
1389 brcmf_sdio_rxfail(bus, false, false);
1392 if (len < SDPCM_HDRLEN) {
1393 brcmf_err("HW header length error\n");
1396 if (type == BRCMF_SDIO_FT_SUPER &&
1397 (roundup(len, bus->blocksize) != rd->len)) {
1398 brcmf_err("HW superframe header length error\n");
1401 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1402 brcmf_err("HW subframe header length error\n");
1407 /* software header */
1408 header += SDPCM_HWHDR_LEN;
1409 swheader = le32_to_cpu(*(__le32 *)header);
1410 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1411 brcmf_err("Glom descriptor found in superframe head\n");
1415 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1416 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1417 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1418 type != BRCMF_SDIO_FT_SUPER) {
1419 brcmf_err("HW header length too long\n");
1420 bus->sdcnt.rx_toolong++;
1421 brcmf_sdio_rxfail(bus, false, false);
1425 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1426 brcmf_err("Wrong channel for superframe\n");
1430 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1431 rd->channel != SDPCM_EVENT_CHANNEL) {
1432 brcmf_err("Wrong channel for subframe\n");
1436 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1437 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1438 brcmf_err("seq %d: bad data offset\n", rx_seq);
1439 bus->sdcnt.rx_badhdr++;
1440 brcmf_sdio_rxfail(bus, false, false);
1444 if (rd->seq_num != rx_seq) {
1445 brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num);
1446 bus->sdcnt.rx_badseq++;
1447 rd->seq_num = rx_seq;
1449 /* no need to check the reset for subframe */
1450 if (type == BRCMF_SDIO_FT_SUB)
1452 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1453 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1454 /* only warm for NON glom packet */
1455 if (rd->channel != SDPCM_GLOM_CHANNEL)
1456 brcmf_err("seq %d: next length error\n", rx_seq);
1459 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1460 fc = swheader & SDPCM_FCMASK_MASK;
1461 if (bus->flowcontrol != fc) {
1462 if (~bus->flowcontrol & fc)
1463 bus->sdcnt.fc_xoff++;
1464 if (bus->flowcontrol & ~fc)
1465 bus->sdcnt.fc_xon++;
1466 bus->sdcnt.fc_rcvd++;
1467 bus->flowcontrol = fc;
1469 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1470 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1471 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1472 tx_seq_max = bus->tx_seq + 2;
1474 bus->tx_max = tx_seq_max;
1479 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1481 *(__le16 *)header = cpu_to_le16(frm_length);
1482 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1485 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1486 struct brcmf_sdio_hdrinfo *hd_info)
1491 brcmf_sdio_update_hwhdr(header, hd_info->len);
1492 hdr_offset = SDPCM_HWHDR_LEN;
1495 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1496 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1497 hdrval = (u16)hd_info->tail_pad << 16;
1498 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1499 hdr_offset += SDPCM_HWEXT_LEN;
1502 hdrval = hd_info->seq_num;
1503 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1505 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1507 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1508 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1509 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1512 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1517 struct sk_buff *pfirst, *pnext;
1522 struct brcmf_sdio_hdrinfo rd_new;
1524 /* If packets, issue read(s) and send up packet chain */
1525 /* Return sequence numbers consumed? */
1527 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1528 bus->glomd, skb_peek(&bus->glom));
1530 /* If there's a descriptor, generate the packet chain */
1532 pfirst = pnext = NULL;
1533 dlen = (u16) (bus->glomd->len);
1534 dptr = bus->glomd->data;
1535 if (!dlen || (dlen & 1)) {
1536 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1541 for (totlen = num = 0; dlen; num++) {
1542 /* Get (and move past) next length */
1543 sublen = get_unaligned_le16(dptr);
1544 dlen -= sizeof(u16);
1545 dptr += sizeof(u16);
1546 if ((sublen < SDPCM_HDRLEN) ||
1547 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1548 brcmf_err("descriptor len %d bad: %d\n",
1553 if (sublen % bus->sgentry_align) {
1554 brcmf_err("sublen %d not multiple of %d\n",
1555 sublen, bus->sgentry_align);
1559 /* For last frame, adjust read len so total
1560 is a block multiple */
1563 (roundup(totlen, bus->blocksize) - totlen);
1564 totlen = roundup(totlen, bus->blocksize);
1567 /* Allocate/chain packet for next subframe */
1568 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1569 if (pnext == NULL) {
1570 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1574 skb_queue_tail(&bus->glom, pnext);
1576 /* Adhere to start alignment requirements */
1577 pkt_align(pnext, sublen, bus->sgentry_align);
1580 /* If all allocations succeeded, save packet chain
1583 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1585 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1586 totlen != bus->cur_read.len) {
1587 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1588 bus->cur_read.len, totlen, rxseq);
1590 pfirst = pnext = NULL;
1592 brcmf_sdio_free_glom(bus);
1596 /* Done with descriptor packet */
1597 brcmu_pkt_buf_free_skb(bus->glomd);
1599 bus->cur_read.len = 0;
1602 /* Ok -- either we just generated a packet chain,
1603 or had one from before */
1604 if (!skb_queue_empty(&bus->glom)) {
1605 if (BRCMF_GLOM_ON()) {
1606 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1607 skb_queue_walk(&bus->glom, pnext) {
1608 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1609 pnext, (u8 *) (pnext->data),
1610 pnext->len, pnext->len);
1614 pfirst = skb_peek(&bus->glom);
1615 dlen = (u16) brcmf_sdio_glom_len(bus);
1617 /* Do an SDIO read for the superframe. Configurable iovar to
1618 * read directly into the chained packet, or allocate a large
1619 * packet and and copy into the chain.
1621 sdio_claim_host(bus->sdiodev->func1);
1622 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1624 sdio_release_host(bus->sdiodev->func1);
1625 bus->sdcnt.f2rxdata++;
1627 /* On failure, kill the superframe */
1629 brcmf_err("glom read of %d bytes failed: %d\n",
1632 sdio_claim_host(bus->sdiodev->func1);
1633 brcmf_sdio_rxfail(bus, true, false);
1634 bus->sdcnt.rxglomfail++;
1635 brcmf_sdio_free_glom(bus);
1636 sdio_release_host(bus->sdiodev->func1);
1640 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1641 pfirst->data, min_t(int, pfirst->len, 48),
1644 rd_new.seq_num = rxseq;
1646 sdio_claim_host(bus->sdiodev->func1);
1647 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1648 BRCMF_SDIO_FT_SUPER);
1649 sdio_release_host(bus->sdiodev->func1);
1650 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1652 /* Remove superframe header, remember offset */
1653 skb_pull(pfirst, rd_new.dat_offset);
1656 /* Validate all the subframe headers */
1657 skb_queue_walk(&bus->glom, pnext) {
1658 /* leave when invalid subframe is found */
1662 rd_new.len = pnext->len;
1663 rd_new.seq_num = rxseq++;
1664 sdio_claim_host(bus->sdiodev->func1);
1665 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1667 sdio_release_host(bus->sdiodev->func1);
1668 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1669 pnext->data, 32, "subframe:\n");
1675 /* Terminate frame on error */
1676 sdio_claim_host(bus->sdiodev->func1);
1677 brcmf_sdio_rxfail(bus, true, false);
1678 bus->sdcnt.rxglomfail++;
1679 brcmf_sdio_free_glom(bus);
1680 sdio_release_host(bus->sdiodev->func1);
1681 bus->cur_read.len = 0;
1685 /* Basic SD framing looks ok - process each packet (header) */
1687 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1688 dptr = (u8 *) (pfirst->data);
1689 sublen = get_unaligned_le16(dptr);
1690 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1692 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1694 "Rx Subframe Data:\n");
1696 __skb_trim(pfirst, sublen);
1697 skb_pull(pfirst, doff);
1699 if (pfirst->len == 0) {
1700 skb_unlink(pfirst, &bus->glom);
1701 brcmu_pkt_buf_free_skb(pfirst);
1705 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1707 min_t(int, pfirst->len, 32),
1708 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1709 bus->glom.qlen, pfirst, pfirst->data,
1710 pfirst->len, pfirst->next,
1712 skb_unlink(pfirst, &bus->glom);
1713 if (brcmf_sdio_fromevntchan(&dptr[SDPCM_HWHDR_LEN]))
1714 brcmf_rx_event(bus->sdiodev->dev, pfirst);
1716 brcmf_rx_frame(bus->sdiodev->dev, pfirst,
1718 bus->sdcnt.rxglompkts++;
1721 bus->sdcnt.rxglomframes++;
1726 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1729 DECLARE_WAITQUEUE(wait, current);
1730 int timeout = DCMD_RESP_TIMEOUT;
1732 /* Wait until control frame is available */
1733 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1734 set_current_state(TASK_INTERRUPTIBLE);
1736 while (!(*condition) && (!signal_pending(current) && timeout))
1737 timeout = schedule_timeout(timeout);
1739 if (signal_pending(current))
1742 set_current_state(TASK_RUNNING);
1743 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1748 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1750 wake_up_interruptible(&bus->dcmd_resp_wait);
1755 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1758 u8 *buf = NULL, *rbuf;
1761 brcmf_dbg(SDIO, "Enter\n");
1763 buf = vzalloc(bus->rxblen);
1768 pad = ((unsigned long)rbuf % bus->head_align);
1770 rbuf += (bus->head_align - pad);
1772 /* Copy the already-read portion over */
1773 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1774 if (len <= BRCMF_FIRSTREAD)
1777 /* Raise rdlen to next SDIO block to avoid tail command */
1778 rdlen = len - BRCMF_FIRSTREAD;
1779 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1780 pad = bus->blocksize - (rdlen % bus->blocksize);
1781 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1782 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1784 } else if (rdlen % bus->head_align) {
1785 rdlen += bus->head_align - (rdlen % bus->head_align);
1788 /* Drop if the read is too big or it exceeds our maximum */
1789 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1790 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1791 rdlen, bus->sdiodev->bus_if->maxctl);
1792 brcmf_sdio_rxfail(bus, false, false);
1796 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1797 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1798 len, len - doff, bus->sdiodev->bus_if->maxctl);
1799 bus->sdcnt.rx_toolong++;
1800 brcmf_sdio_rxfail(bus, false, false);
1804 /* Read remain of frame body */
1805 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1806 bus->sdcnt.f2rxdata++;
1808 /* Control frame failures need retransmission */
1810 brcmf_err("read %d control bytes failed: %d\n",
1812 bus->sdcnt.rxc_errors++;
1813 brcmf_sdio_rxfail(bus, true, true);
1816 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1820 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1821 buf, len, "RxCtrl:\n");
1823 /* Point to valid data and indicate its length */
1824 spin_lock_bh(&bus->rxctl_lock);
1826 brcmf_err("last control frame is being processed.\n");
1827 spin_unlock_bh(&bus->rxctl_lock);
1831 bus->rxctl = buf + doff;
1832 bus->rxctl_orig = buf;
1833 bus->rxlen = len - doff;
1834 spin_unlock_bh(&bus->rxctl_lock);
1837 /* Awake any waiters */
1838 brcmf_sdio_dcmd_resp_wake(bus);
1841 /* Pad read to blocksize for efficiency */
1842 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1844 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1845 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1846 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1847 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1849 } else if (*rdlen % bus->head_align) {
1850 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1854 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1856 struct sk_buff *pkt; /* Packet for event or data frames */
1857 u16 pad; /* Number of pad bytes to read */
1858 uint rxleft = 0; /* Remaining number of frames allowed */
1859 int ret; /* Return code from calls */
1860 uint rxcount = 0; /* Total frames read */
1861 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1864 brcmf_dbg(SDIO, "Enter\n");
1866 /* Not finished unless we encounter no more frames indication */
1867 bus->rxpending = true;
1869 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1870 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
1871 rd->seq_num++, rxleft--) {
1873 /* Handle glomming separately */
1874 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1876 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1877 bus->glomd, skb_peek(&bus->glom));
1878 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1879 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1880 rd->seq_num += cnt - 1;
1881 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1885 rd->len_left = rd->len;
1886 /* read header first for unknow frame length */
1887 sdio_claim_host(bus->sdiodev->func1);
1889 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1890 bus->rxhdr, BRCMF_FIRSTREAD);
1891 bus->sdcnt.f2rxhdrs++;
1893 brcmf_err("RXHEADER FAILED: %d\n",
1895 bus->sdcnt.rx_hdrfail++;
1896 brcmf_sdio_rxfail(bus, true, true);
1897 sdio_release_host(bus->sdiodev->func1);
1901 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1902 bus->rxhdr, SDPCM_HDRLEN,
1905 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1906 BRCMF_SDIO_FT_NORMAL)) {
1907 sdio_release_host(bus->sdiodev->func1);
1908 if (!bus->rxpending)
1914 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1915 brcmf_sdio_read_control(bus, bus->rxhdr,
1918 /* prepare the descriptor for the next read */
1919 rd->len = rd->len_nxtfrm << 4;
1921 /* treat all packet as event if we don't know */
1922 rd->channel = SDPCM_EVENT_CHANNEL;
1923 sdio_release_host(bus->sdiodev->func1);
1926 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1927 rd->len - BRCMF_FIRSTREAD : 0;
1928 head_read = BRCMF_FIRSTREAD;
1931 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1933 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1936 /* Give up on data, request rtx of events */
1937 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1938 brcmf_sdio_rxfail(bus, false,
1939 RETRYCHAN(rd->channel));
1940 sdio_release_host(bus->sdiodev->func1);
1943 skb_pull(pkt, head_read);
1944 pkt_align(pkt, rd->len_left, bus->head_align);
1946 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1947 bus->sdcnt.f2rxdata++;
1948 sdio_release_host(bus->sdiodev->func1);
1951 brcmf_err("read %d bytes from channel %d failed: %d\n",
1952 rd->len, rd->channel, ret);
1953 brcmu_pkt_buf_free_skb(pkt);
1954 sdio_claim_host(bus->sdiodev->func1);
1955 brcmf_sdio_rxfail(bus, true,
1956 RETRYCHAN(rd->channel));
1957 sdio_release_host(bus->sdiodev->func1);
1962 skb_push(pkt, head_read);
1963 memcpy(pkt->data, bus->rxhdr, head_read);
1966 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
1967 rd_new.seq_num = rd->seq_num;
1968 sdio_claim_host(bus->sdiodev->func1);
1969 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
1970 BRCMF_SDIO_FT_NORMAL)) {
1972 brcmf_sdio_rxfail(bus, true, true);
1973 sdio_release_host(bus->sdiodev->func1);
1974 brcmu_pkt_buf_free_skb(pkt);
1977 bus->sdcnt.rx_readahead_cnt++;
1978 if (rd->len != roundup(rd_new.len, 16)) {
1979 brcmf_err("frame length mismatch:read %d, should be %d\n",
1981 roundup(rd_new.len, 16) >> 4);
1983 brcmf_sdio_rxfail(bus, true, true);
1984 sdio_release_host(bus->sdiodev->func1);
1985 brcmu_pkt_buf_free_skb(pkt);
1988 sdio_release_host(bus->sdiodev->func1);
1989 rd->len_nxtfrm = rd_new.len_nxtfrm;
1990 rd->channel = rd_new.channel;
1991 rd->dat_offset = rd_new.dat_offset;
1993 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
1996 bus->rxhdr, SDPCM_HDRLEN,
1999 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
2000 brcmf_err("readahead on control packet %d?\n",
2002 /* Force retry w/normal header read */
2004 sdio_claim_host(bus->sdiodev->func1);
2005 brcmf_sdio_rxfail(bus, false, true);
2006 sdio_release_host(bus->sdiodev->func1);
2007 brcmu_pkt_buf_free_skb(pkt);
2012 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
2013 pkt->data, rd->len, "Rx Data:\n");
2015 /* Save superframe descriptor and allocate packet frame */
2016 if (rd->channel == SDPCM_GLOM_CHANNEL) {
2017 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
2018 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2020 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
2023 __skb_trim(pkt, rd->len);
2024 skb_pull(pkt, SDPCM_HDRLEN);
2027 brcmf_err("%s: glom superframe w/o "
2028 "descriptor!\n", __func__);
2029 sdio_claim_host(bus->sdiodev->func1);
2030 brcmf_sdio_rxfail(bus, false, false);
2031 sdio_release_host(bus->sdiodev->func1);
2033 /* prepare the descriptor for the next read */
2034 rd->len = rd->len_nxtfrm << 4;
2036 /* treat all packet as event if we don't know */
2037 rd->channel = SDPCM_EVENT_CHANNEL;
2041 /* Fill in packet len and prio, deliver upward */
2042 __skb_trim(pkt, rd->len);
2043 skb_pull(pkt, rd->dat_offset);
2046 brcmu_pkt_buf_free_skb(pkt);
2047 else if (rd->channel == SDPCM_EVENT_CHANNEL)
2048 brcmf_rx_event(bus->sdiodev->dev, pkt);
2050 brcmf_rx_frame(bus->sdiodev->dev, pkt,
2053 /* prepare the descriptor for the next read */
2054 rd->len = rd->len_nxtfrm << 4;
2056 /* treat all packet as event if we don't know */
2057 rd->channel = SDPCM_EVENT_CHANNEL;
2060 rxcount = maxframes - rxleft;
2061 /* Message if we hit the limit */
2063 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
2065 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2066 /* Back off rxseq if awaiting rtx, update rx_seq */
2069 bus->rx_seq = rd->seq_num;
2075 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2077 wake_up_interruptible(&bus->ctrl_wait);
2081 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2083 struct brcmf_bus_stats *stats;
2087 dat_buf = (u8 *)(pkt->data);
2089 /* Check head padding */
2090 head_pad = ((unsigned long)dat_buf % bus->head_align);
2092 if (skb_headroom(pkt) < head_pad) {
2093 stats = &bus->sdiodev->bus_if->stats;
2094 atomic_inc(&stats->pktcowed);
2095 if (skb_cow_head(pkt, head_pad)) {
2096 atomic_inc(&stats->pktcow_failed);
2101 skb_push(pkt, head_pad);
2102 dat_buf = (u8 *)(pkt->data);
2104 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2109 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2112 /* flag marking a dummy skb added for DMA alignment requirement */
2113 #define ALIGN_SKB_FLAG 0x8000
2114 /* bit mask of data length chopped from the previous packet */
2115 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2117 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2118 struct sk_buff_head *pktq,
2119 struct sk_buff *pkt, u16 total_len)
2121 struct brcmf_sdio_dev *sdiodev;
2122 struct sk_buff *pkt_pad;
2123 u16 tail_pad, tail_chop, chain_pad;
2124 unsigned int blksize;
2128 sdiodev = bus->sdiodev;
2129 blksize = sdiodev->func2->cur_blksize;
2130 /* sg entry alignment should be a divisor of block size */
2131 WARN_ON(blksize % bus->sgentry_align);
2133 /* Check tail padding */
2134 lastfrm = skb_queue_is_last(pktq, pkt);
2136 tail_chop = pkt->len % bus->sgentry_align;
2138 tail_pad = bus->sgentry_align - tail_chop;
2139 chain_pad = (total_len + tail_pad) % blksize;
2140 if (lastfrm && chain_pad)
2141 tail_pad += blksize - chain_pad;
2142 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2143 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
2145 if (pkt_pad == NULL)
2147 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2148 if (unlikely(ret < 0)) {
2152 memcpy(pkt_pad->data,
2153 pkt->data + pkt->len - tail_chop,
2155 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2156 skb_trim(pkt, pkt->len - tail_chop);
2157 skb_trim(pkt_pad, tail_pad + tail_chop);
2158 __skb_queue_after(pktq, pkt, pkt_pad);
2160 ntail = pkt->data_len + tail_pad -
2161 (pkt->end - pkt->tail);
2162 if (skb_cloned(pkt) || ntail > 0)
2163 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2165 if (skb_linearize(pkt))
2167 __skb_put(pkt, tail_pad);
2174 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2175 * @bus: brcmf_sdio structure pointer
2176 * @pktq: packet list pointer
2177 * @chan: virtual channel to transmit the packet
2179 * Processes to be applied to the packet
2180 * - Align data buffer pointer
2181 * - Align data buffer length
2183 * Return: negative value if there is error
2186 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2189 u16 head_pad, total_len;
2190 struct sk_buff *pkt_next;
2193 struct brcmf_sdio_hdrinfo hd_info = {0};
2195 txseq = bus->tx_seq;
2197 skb_queue_walk(pktq, pkt_next) {
2198 /* alignment packet inserted in previous
2199 * loop cycle can be skipped as it is
2200 * already properly aligned and does not
2201 * need an sdpcm header.
2203 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2206 /* align packet data pointer */
2207 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2210 head_pad = (u16)ret;
2212 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
2214 total_len += pkt_next->len;
2216 hd_info.len = pkt_next->len;
2217 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2218 if (bus->txglom && pktq->qlen > 1) {
2219 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2220 pkt_next, total_len);
2223 hd_info.tail_pad = (u16)ret;
2224 total_len += (u16)ret;
2227 hd_info.channel = chan;
2228 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2229 hd_info.seq_num = txseq++;
2231 /* Now fill the header */
2232 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2234 if (BRCMF_BYTES_ON() &&
2235 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2236 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2237 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
2239 else if (BRCMF_HDRS_ON())
2240 brcmf_dbg_hex_dump(true, pkt_next->data,
2241 head_pad + bus->tx_hdrlen,
2244 /* Hardware length tag of the first packet should be total
2245 * length of the chain (including padding)
2248 brcmf_sdio_update_hwhdr(__skb_peek(pktq)->data, total_len);
2253 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2254 * @bus: brcmf_sdio structure pointer
2255 * @pktq: packet list pointer
2257 * Processes to be applied to the packet
2258 * - Remove head padding
2259 * - Remove tail padding
2262 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2267 u16 dummy_flags, chop_len;
2268 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2270 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2271 dummy_flags = *(u16 *)(pkt_next->cb);
2272 if (dummy_flags & ALIGN_SKB_FLAG) {
2273 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2275 pkt_prev = pkt_next->prev;
2276 skb_put(pkt_prev, chop_len);
2278 __skb_unlink(pkt_next, pktq);
2279 brcmu_pkt_buf_free_skb(pkt_next);
2281 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2282 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2283 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2284 SDPCM_DOFFSET_SHIFT;
2285 skb_pull(pkt_next, dat_offset);
2287 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2288 skb_trim(pkt_next, pkt_next->len - tail_pad);
2294 /* Writes a HW/SW header into the packet and sends it. */
2295 /* Assumes: (a) header space already there, (b) caller holds lock */
2296 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2300 struct sk_buff *pkt_next, *tmp;
2302 brcmf_dbg(TRACE, "Enter\n");
2304 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2308 sdio_claim_host(bus->sdiodev->func1);
2309 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2310 bus->sdcnt.f2txdata++;
2313 brcmf_sdio_txfail(bus);
2315 sdio_release_host(bus->sdiodev->func1);
2318 brcmf_sdio_txpkt_postp(bus, pktq);
2320 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2321 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2322 __skb_unlink(pkt_next, pktq);
2323 brcmf_proto_bcdc_txcomplete(bus->sdiodev->dev, pkt_next,
2329 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2331 struct sk_buff *pkt;
2332 struct sk_buff_head pktq;
2333 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus);
2335 int ret = 0, prec_out, i;
2337 u8 tx_prec_map, pkt_num;
2339 brcmf_dbg(TRACE, "Enter\n");
2341 tx_prec_map = ~bus->flowcontrol;
2343 /* Send frames until the limit or some other event */
2344 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2347 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2348 bus->sdiodev->txglomsz);
2349 pkt_num = min_t(u32, pkt_num,
2350 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2351 __skb_queue_head_init(&pktq);
2352 spin_lock_bh(&bus->txq_lock);
2353 for (i = 0; i < pkt_num; i++) {
2354 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2358 __skb_queue_tail(&pktq, pkt);
2360 spin_unlock_bh(&bus->txq_lock);
2364 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2368 /* In poll mode, need to check for other events */
2370 /* Check device status, signal pending interrupt */
2371 sdio_claim_host(bus->sdiodev->func1);
2372 intstatus = brcmf_sdiod_readl(bus->sdiodev,
2373 intstat_addr, &ret);
2374 sdio_release_host(bus->sdiodev->func1);
2376 bus->sdcnt.f2txdata++;
2379 if (intstatus & bus->hostintmask)
2380 atomic_set(&bus->ipend, 1);
2384 /* Deflow-control stack if needed */
2385 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
2386 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2388 brcmf_proto_bcdc_txflowblock(bus->sdiodev->dev, false);
2394 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
2399 struct brcmf_sdio_hdrinfo hd_info = {0};
2402 brcmf_dbg(SDIO, "Enter\n");
2404 /* Back the pointer to make room for bus header */
2405 frame -= bus->tx_hdrlen;
2406 len += bus->tx_hdrlen;
2408 /* Add alignment padding (optional for ctl frames) */
2409 doff = ((unsigned long)frame % bus->head_align);
2413 memset(frame + bus->tx_hdrlen, 0, doff);
2416 /* Round send length to next SDIO block */
2418 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2419 pad = bus->blocksize - (len % bus->blocksize);
2420 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2422 } else if (len % bus->head_align) {
2423 pad = bus->head_align - (len % bus->head_align);
2427 hd_info.len = len - pad;
2428 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2429 hd_info.dat_offset = doff + bus->tx_hdrlen;
2430 hd_info.seq_num = bus->tx_seq;
2431 hd_info.lastfrm = true;
2432 hd_info.tail_pad = pad;
2433 brcmf_sdio_hdpack(bus, frame, &hd_info);
2436 brcmf_sdio_update_hwhdr(frame, len);
2438 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2439 frame, len, "Tx Frame:\n");
2440 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2442 frame, min_t(u16, len, 16), "TxHdr:\n");
2445 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2448 brcmf_sdio_txfail(bus);
2450 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2451 } while (ret < 0 && retries++ < TXRETRIES);
2456 static bool brcmf_chip_is_ulp(struct brcmf_chip *ci)
2458 if (ci->chip == CY_CC_43012_CHIP_ID)
2464 static void brcmf_sdio_bus_stop(struct device *dev)
2466 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2467 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2468 struct brcmf_sdio *bus = sdiodev->bus;
2469 struct brcmf_core *core = bus->sdio_core;
2470 u32 local_hostintmask;
2474 brcmf_dbg(TRACE, "Enter\n");
2476 if (bus->watchdog_tsk) {
2477 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2478 kthread_stop(bus->watchdog_tsk);
2479 bus->watchdog_tsk = NULL;
2482 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
2483 sdio_claim_host(sdiodev->func1);
2485 /* Enable clock for device interrupts */
2486 brcmf_sdio_bus_sleep(bus, false, false);
2488 /* Disable and clear interrupts at the chip level also */
2489 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(hostintmask),
2492 local_hostintmask = bus->hostintmask;
2493 bus->hostintmask = 0;
2495 /* Force backplane clocks to assure F2 interrupt propagates */
2496 saveclk = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2500 bpreq |= brcmf_chip_is_ulp(bus->ci) ?
2501 SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT;
2502 brcmf_sdiod_writeb(sdiodev,
2503 SBSDIO_FUNC1_CHIPCLKCSR,
2507 brcmf_err("Failed to force clock for F2: err %d\n",
2510 /* Turn off the bus (F2), free any pending packets */
2511 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2512 sdio_disable_func(sdiodev->func2);
2514 /* Clear any pending interrupts now that F2 is disabled */
2515 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(intstatus),
2516 local_hostintmask, NULL);
2518 sdio_release_host(sdiodev->func1);
2520 /* Clear the data packet queues */
2521 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2523 /* Clear any held glomming stuff */
2524 brcmu_pkt_buf_free_skb(bus->glomd);
2525 brcmf_sdio_free_glom(bus);
2527 /* Clear rx control and wake any waiters */
2528 spin_lock_bh(&bus->rxctl_lock);
2530 spin_unlock_bh(&bus->rxctl_lock);
2531 brcmf_sdio_dcmd_resp_wake(bus);
2533 /* Reset some F2 state stuff */
2534 bus->rxskip = false;
2535 bus->tx_seq = bus->rx_seq = 0;
2538 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2540 struct brcmf_sdio_dev *sdiodev;
2541 unsigned long flags;
2543 sdiodev = bus->sdiodev;
2544 if (sdiodev->oob_irq_requested) {
2545 spin_lock_irqsave(&sdiodev->irq_en_lock, flags);
2546 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2547 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr);
2548 sdiodev->irq_en = true;
2550 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags);
2554 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2556 struct brcmf_core *core = bus->sdio_core;
2561 addr = core->base + SD_REG(intstatus);
2563 val = brcmf_sdiod_readl(bus->sdiodev, addr, &ret);
2564 bus->sdcnt.f1regdata++;
2568 val &= bus->hostintmask;
2569 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2571 /* Clear interrupts */
2573 brcmf_sdiod_writel(bus->sdiodev, addr, val, &ret);
2574 bus->sdcnt.f1regdata++;
2575 atomic_or(val, &bus->intstatus);
2581 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2583 struct brcmf_sdio_dev *sdiod = bus->sdiodev;
2585 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus);
2586 unsigned long intstatus;
2587 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2588 uint framecnt; /* Temporary counter of tx/rx frames */
2591 brcmf_dbg(SDIO, "Enter\n");
2593 sdio_claim_host(bus->sdiodev->func1);
2595 /* If waiting for HTAVAIL, check status */
2596 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2597 u8 clkctl, devctl = 0;
2600 /* Check for inconsistent device control */
2601 devctl = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2605 /* Read CSR, if clock on switch to AVAIL, else ignore */
2606 clkctl = brcmf_sdiod_readb(bus->sdiodev,
2607 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2609 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2612 if (SBSDIO_HTAV(clkctl)) {
2613 devctl = brcmf_sdiod_readb(bus->sdiodev,
2614 SBSDIO_DEVICE_CTL, &err);
2615 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2616 brcmf_sdiod_writeb(bus->sdiodev,
2617 SBSDIO_DEVICE_CTL, devctl, &err);
2618 bus->clkstate = CLK_AVAIL;
2622 /* Make sure backplane clock is on */
2623 brcmf_sdio_bus_sleep(bus, false, true);
2625 /* Pending interrupt indicates new device status */
2626 if (atomic_read(&bus->ipend) > 0) {
2627 atomic_set(&bus->ipend, 0);
2628 err = brcmf_sdio_intr_rstatus(bus);
2631 /* Start with leftover status bits */
2632 intstatus = atomic_xchg(&bus->intstatus, 0);
2634 /* Handle flow-control change: read new state in case our ack
2635 * crossed another change interrupt. If change still set, assume
2636 * FC ON for safety, let next loop through do the debounce.
2638 if (intstatus & I_HMB_FC_CHANGE) {
2639 intstatus &= ~I_HMB_FC_CHANGE;
2640 brcmf_sdiod_writel(sdiod, intstat_addr, I_HMB_FC_CHANGE, &err);
2642 newstatus = brcmf_sdiod_readl(sdiod, intstat_addr, &err);
2644 bus->sdcnt.f1regdata += 2;
2645 atomic_set(&bus->fcstate,
2646 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2647 intstatus |= (newstatus & bus->hostintmask);
2650 /* Handle host mailbox indication */
2651 if (intstatus & I_HMB_HOST_INT) {
2652 intstatus &= ~I_HMB_HOST_INT;
2653 intstatus |= brcmf_sdio_hostmail(bus);
2656 sdio_release_host(bus->sdiodev->func1);
2658 /* Generally don't ask for these, can get CRC errors... */
2659 if (intstatus & I_WR_OOSYNC) {
2660 brcmf_err("Dongle reports WR_OOSYNC\n");
2661 intstatus &= ~I_WR_OOSYNC;
2664 if (intstatus & I_RD_OOSYNC) {
2665 brcmf_err("Dongle reports RD_OOSYNC\n");
2666 intstatus &= ~I_RD_OOSYNC;
2669 if (intstatus & I_SBINT) {
2670 brcmf_err("Dongle reports SBINT\n");
2671 intstatus &= ~I_SBINT;
2674 /* Would be active due to wake-wlan in gSPI */
2675 if (intstatus & I_CHIPACTIVE) {
2676 brcmf_dbg(SDIO, "Dongle reports CHIPACTIVE\n");
2677 intstatus &= ~I_CHIPACTIVE;
2680 /* Ignore frame indications if rxskip is set */
2682 intstatus &= ~I_HMB_FRAME_IND;
2684 /* On frame indication, read available frames */
2685 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
2686 brcmf_sdio_readframes(bus, bus->rxbound);
2687 if (!bus->rxpending)
2688 intstatus &= ~I_HMB_FRAME_IND;
2691 /* Keep still-pending events for next scheduling */
2693 atomic_or(intstatus, &bus->intstatus);
2695 brcmf_sdio_clrintr(bus);
2697 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
2699 sdio_claim_host(bus->sdiodev->func1);
2700 if (bus->ctrl_frame_stat) {
2701 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
2702 bus->ctrl_frame_len);
2703 bus->ctrl_frame_err = err;
2705 bus->ctrl_frame_stat = false;
2707 brcmf_err("sdio ctrlframe tx failed err=%d\n",
2710 sdio_release_host(bus->sdiodev->func1);
2711 brcmf_sdio_wait_event_wakeup(bus);
2713 /* Send queued frames (limit 1 if rx may still be pending) */
2714 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2715 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
2717 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2719 brcmf_sdio_sendfromq(bus, framecnt);
2722 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
2723 brcmf_err("failed backplane access over SDIO, halting operation\n");
2724 atomic_set(&bus->intstatus, 0);
2725 if (bus->ctrl_frame_stat) {
2726 sdio_claim_host(bus->sdiodev->func1);
2727 if (bus->ctrl_frame_stat) {
2728 bus->ctrl_frame_err = -ENODEV;
2730 bus->ctrl_frame_stat = false;
2731 brcmf_sdio_wait_event_wakeup(bus);
2733 sdio_release_host(bus->sdiodev->func1);
2735 } else if (atomic_read(&bus->intstatus) ||
2736 atomic_read(&bus->ipend) > 0 ||
2737 (!atomic_read(&bus->fcstate) &&
2738 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2740 bus->dpc_triggered = true;
2744 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2746 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2747 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2748 struct brcmf_sdio *bus = sdiodev->bus;
2753 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
2756 int eprec = -1; /* precedence to evict from */
2758 /* Fast case, precedence queue is not full and we are also not
2759 * exceeding total queue length
2761 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
2762 brcmu_pktq_penq(q, prec, pkt);
2766 /* Determine precedence from which to evict packet, if any */
2767 if (pktq_pfull(q, prec)) {
2769 } else if (pktq_full(q)) {
2770 p = brcmu_pktq_peek_tail(q, &eprec);
2775 /* Evict if needed */
2777 /* Detect queueing to unconfigured precedence */
2779 return false; /* refuse newer (incoming) packet */
2780 /* Evict packet according to discard policy */
2781 p = brcmu_pktq_pdeq_tail(q, eprec);
2783 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2784 brcmu_pkt_buf_free_skb(p);
2788 p = brcmu_pktq_penq(q, prec, pkt);
2790 brcmf_err("brcmu_pktq_penq() failed\n");
2795 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2799 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2800 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2801 struct brcmf_sdio *bus = sdiodev->bus;
2803 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
2804 if (sdiodev->state != BRCMF_SDIOD_DATA)
2807 /* Add space for the header */
2808 skb_push(pkt, bus->tx_hdrlen);
2809 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2811 /* In WLAN, priority is always set by the AP using WMM parameters
2812 * and this need not always follow the standard 802.1d priority.
2813 * Based on AP WMM config, map from 802.1d priority to corresponding
2816 prec = brcmf_map_prio_to_prec(bus_if->drvr->config,
2817 (pkt->priority & PRIOMASK));
2819 /* Check for existing queue, current flow-control,
2820 pending event, or pending clock */
2821 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2822 bus->sdcnt.fcqueued++;
2824 /* Priority based enq */
2825 spin_lock_bh(&bus->txq_lock);
2826 /* reset bus_flags in packet cb */
2827 *(u16 *)(pkt->cb) = 0;
2828 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
2829 skb_pull(pkt, bus->tx_hdrlen);
2830 brcmf_err("out of bus->txq !!!\n");
2836 if (pktq_len(&bus->txq) >= TXHI) {
2838 brcmf_proto_bcdc_txflowblock(dev, true);
2840 spin_unlock_bh(&bus->txq_lock);
2843 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2844 qcount[prec] = pktq_plen(&bus->txq, prec);
2847 brcmf_sdio_trigger_dpc(bus);
2852 #define CONSOLE_LINE_MAX 192
2854 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2856 struct brcmf_console *c = &bus->console;
2857 u8 line[CONSOLE_LINE_MAX], ch;
2861 /* Don't do anything until FWREADY updates console address */
2862 if (bus->console_addr == 0)
2865 /* Read console log struct */
2866 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2867 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2872 /* Allocate console buffer (one time only) */
2873 if (c->buf == NULL) {
2874 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2875 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2880 idx = le32_to_cpu(c->log_le.idx);
2882 /* Protect against corrupt value */
2883 if (idx > c->bufsize)
2886 /* Skip reading the console buffer if the index pointer
2891 /* Read the console buffer */
2892 addr = le32_to_cpu(c->log_le.buf);
2893 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2897 while (c->last != idx) {
2898 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2899 if (c->last == idx) {
2900 /* This would output a partial line.
2902 * the buffer pointer and output this
2903 * line next time around.
2908 c->last = c->bufsize - n;
2911 ch = c->buf[c->last];
2912 c->last = (c->last + 1) % c->bufsize;
2919 if (line[n - 1] == '\r')
2922 pr_debug("CONSOLE: %s\n", line);
2932 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2934 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2935 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2936 struct brcmf_sdio *bus = sdiodev->bus;
2939 brcmf_dbg(TRACE, "Enter\n");
2940 if (sdiodev->state != BRCMF_SDIOD_DATA)
2944 bus->ctrl_frame_buf = msg;
2945 bus->ctrl_frame_len = msglen;
2947 bus->ctrl_frame_stat = true;
2949 brcmf_sdio_trigger_dpc(bus);
2950 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
2953 if (bus->ctrl_frame_stat) {
2954 sdio_claim_host(bus->sdiodev->func1);
2955 if (bus->ctrl_frame_stat) {
2956 brcmf_dbg(SDIO, "ctrl_frame timeout\n");
2957 bus->ctrl_frame_stat = false;
2960 sdio_release_host(bus->sdiodev->func1);
2963 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
2964 bus->ctrl_frame_err);
2966 ret = bus->ctrl_frame_err;
2970 bus->sdcnt.tx_ctlerrs++;
2972 bus->sdcnt.tx_ctlpkts++;
2978 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
2979 struct sdpcm_shared *sh)
2981 u32 addr, console_ptr, console_size, console_index;
2982 char *conbuf = NULL;
2986 /* obtain console information from device memory */
2987 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2988 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2989 (u8 *)&sh_val, sizeof(u32));
2992 console_ptr = le32_to_cpu(sh_val);
2994 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
2995 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2996 (u8 *)&sh_val, sizeof(u32));
2999 console_size = le32_to_cpu(sh_val);
3001 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
3002 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
3003 (u8 *)&sh_val, sizeof(u32));
3006 console_index = le32_to_cpu(sh_val);
3008 /* allocate buffer for console data */
3009 if (console_size <= CONSOLE_BUFFER_MAX)
3010 conbuf = vzalloc(console_size+1);
3015 /* obtain the console data from device */
3016 conbuf[console_size] = '\0';
3017 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
3022 rv = seq_write(seq, conbuf + console_index,
3023 console_size - console_index);
3027 if (console_index > 0)
3028 rv = seq_write(seq, conbuf, console_index - 1);
3035 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
3036 struct sdpcm_shared *sh)
3039 struct brcmf_trap_info tr;
3041 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
3042 brcmf_dbg(INFO, "no trap in firmware\n");
3046 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
3047 sizeof(struct brcmf_trap_info));
3053 "dongle trap info: type 0x%x @ epc 0x%08x\n"
3054 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
3055 " lr 0x%08x pc 0x%08x offset 0x%x\n"
3056 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
3057 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
3058 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
3059 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
3060 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
3061 le32_to_cpu(tr.pc), sh->trap_addr,
3062 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
3063 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
3064 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
3065 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
3067 pr_debug("dongle trap info: type 0x%x @ epc 0x%08x\n"
3068 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
3069 " lr 0x%08x pc 0x%08x offset 0x%x\n"
3070 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
3071 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
3072 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
3073 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
3074 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
3075 le32_to_cpu(tr.pc), sh->trap_addr,
3076 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
3077 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
3078 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
3079 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
3083 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
3084 struct sdpcm_shared *sh)
3087 char file[80] = "?";
3088 char expr[80] = "<???>";
3090 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
3091 brcmf_dbg(INFO, "firmware not built with -assert\n");
3093 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
3094 brcmf_dbg(INFO, "no assert in dongle\n");
3098 sdio_claim_host(bus->sdiodev->func1);
3099 if (sh->assert_file_addr != 0) {
3100 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3101 sh->assert_file_addr, (u8 *)file, 80);
3105 if (sh->assert_exp_addr != 0) {
3106 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3107 sh->assert_exp_addr, (u8 *)expr, 80);
3111 sdio_release_host(bus->sdiodev->func1);
3113 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
3114 file, sh->assert_line, expr);
3118 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3121 struct sdpcm_shared sh;
3123 error = brcmf_sdio_readshared(bus, &sh);
3128 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3129 brcmf_dbg(INFO, "firmware not built with -assert\n");
3130 else if (sh.flags & SDPCM_SHARED_ASSERT)
3131 brcmf_err("assertion in dongle\n");
3133 if (sh.flags & SDPCM_SHARED_TRAP) {
3134 brcmf_err("firmware trap in dongle\n");
3135 brcmf_sdio_trap_info(NULL, bus, &sh);
3141 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
3144 struct sdpcm_shared sh;
3146 error = brcmf_sdio_readshared(bus, &sh);
3150 error = brcmf_sdio_assert_info(seq, bus, &sh);
3154 error = brcmf_sdio_trap_info(seq, bus, &sh);
3158 error = brcmf_sdio_dump_console(seq, bus, &sh);
3164 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
3166 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3167 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
3169 return brcmf_sdio_died_dump(seq, bus);
3172 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
3174 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3175 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3176 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
3179 "intrcount: %u\nlastintrs: %u\n"
3180 "pollcnt: %u\nregfails: %u\n"
3181 "tx_sderrs: %u\nfcqueued: %u\n"
3182 "rxrtx: %u\nrx_toolong: %u\n"
3183 "rxc_errors: %u\nrx_hdrfail: %u\n"
3184 "rx_badhdr: %u\nrx_badseq: %u\n"
3185 "fc_rcvd: %u\nfc_xoff: %u\n"
3186 "fc_xon: %u\nrxglomfail: %u\n"
3187 "rxglomframes: %u\nrxglompkts: %u\n"
3188 "f2rxhdrs: %u\nf2rxdata: %u\n"
3189 "f2txdata: %u\nf1regdata: %u\n"
3190 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3191 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3192 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3193 sdcnt->intrcount, sdcnt->lastintrs,
3194 sdcnt->pollcnt, sdcnt->regfails,
3195 sdcnt->tx_sderrs, sdcnt->fcqueued,
3196 sdcnt->rxrtx, sdcnt->rx_toolong,
3197 sdcnt->rxc_errors, sdcnt->rx_hdrfail,
3198 sdcnt->rx_badhdr, sdcnt->rx_badseq,
3199 sdcnt->fc_rcvd, sdcnt->fc_xoff,
3200 sdcnt->fc_xon, sdcnt->rxglomfail,
3201 sdcnt->rxglomframes, sdcnt->rxglompkts,
3202 sdcnt->f2rxhdrs, sdcnt->f2rxdata,
3203 sdcnt->f2txdata, sdcnt->f1regdata,
3204 sdcnt->tickcnt, sdcnt->tx_ctlerrs,
3205 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
3206 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
3211 static void brcmf_sdio_debugfs_create(struct device *dev)
3213 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3214 struct brcmf_pub *drvr = bus_if->drvr;
3215 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3216 struct brcmf_sdio *bus = sdiodev->bus;
3217 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3219 if (IS_ERR_OR_NULL(dentry))
3222 bus->console_interval = BRCMF_CONSOLE;
3224 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
3225 brcmf_debugfs_add_entry(drvr, "counters",
3226 brcmf_debugfs_sdio_count_read);
3227 debugfs_create_u32("console_interval", 0644, dentry,
3228 &bus->console_interval);
3231 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3236 static void brcmf_sdio_debugfs_create(struct device *dev)
3242 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3248 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3249 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3250 struct brcmf_sdio *bus = sdiodev->bus;
3252 brcmf_dbg(TRACE, "Enter\n");
3253 if (sdiodev->state != BRCMF_SDIOD_DATA)
3256 /* Wait until control frame is available */
3257 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3259 spin_lock_bh(&bus->rxctl_lock);
3261 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3263 buf = bus->rxctl_orig;
3264 bus->rxctl_orig = NULL;
3266 spin_unlock_bh(&bus->rxctl_lock);
3270 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3272 } else if (timeleft == 0) {
3273 brcmf_err("resumed on timeout\n");
3274 brcmf_sdio_checkdied(bus);
3275 } else if (pending) {
3276 brcmf_dbg(CTL, "cancelled\n");
3277 return -ERESTARTSYS;
3279 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3280 brcmf_sdio_checkdied(bus);
3284 bus->sdcnt.rx_ctlpkts++;
3286 bus->sdcnt.rx_ctlerrs++;
3288 return rxlen ? (int)rxlen : -ETIMEDOUT;
3293 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3294 u8 *ram_data, uint ram_sz)
3303 /* read back and verify */
3304 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3306 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3307 /* do not proceed while no memory but */
3313 while (offset < ram_sz) {
3314 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3316 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3318 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3322 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3323 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3338 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3339 u8 *ram_data, uint ram_sz)
3345 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3346 const struct firmware *fw)
3350 brcmf_dbg(TRACE, "Enter\n");
3352 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3353 (u8 *)fw->data, fw->size);
3355 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3356 err, (int)fw->size, bus->ci->rambase);
3357 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3358 (u8 *)fw->data, fw->size))
3364 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3365 void *vars, u32 varsz)
3370 brcmf_dbg(TRACE, "Enter\n");
3372 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3373 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3375 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3376 err, varsz, address);
3377 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3383 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
3384 const struct firmware *fw,
3385 void *nvram, u32 nvlen)
3390 sdio_claim_host(bus->sdiodev->func1);
3391 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3393 rstvec = get_unaligned_le32(fw->data);
3394 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3396 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3397 release_firmware(fw);
3399 brcmf_err("dongle image file download failed\n");
3400 brcmf_fw_nvram_free(nvram);
3404 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
3405 brcmf_fw_nvram_free(nvram);
3407 brcmf_err("dongle nvram file download failed\n");
3411 /* Take arm out of reset */
3412 if (!brcmf_chip_set_active(bus->ci, rstvec)) {
3413 brcmf_err("error getting out of ARM core reset\n");
3418 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3419 sdio_release_host(bus->sdiodev->func1);
3423 static bool brcmf_sdio_aos_no_decode(struct brcmf_sdio *bus)
3425 if (bus->ci->chip == CY_CC_43012_CHIP_ID ||
3426 bus->ci->chip == CY_CC_43752_CHIP_ID)
3432 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3440 brcmf_dbg(TRACE, "Enter\n");
3442 if (brcmf_chip_is_ulp(bus->ci)) {
3443 wakeupctrl = SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT;
3444 chipclkcsr = SBSDIO_HT_AVAIL_REQ;
3446 wakeupctrl = SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3447 chipclkcsr = SBSDIO_FORCE_HT;
3450 if (brcmf_sdio_aos_no_decode(bus)) {
3451 cardcap = SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC;
3453 cardcap = (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3454 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT);
3457 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3459 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3462 val |= 1 << wakeupctrl;
3463 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3465 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3469 /* Add CMD14 Support */
3470 brcmf_sdiod_func0_wb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3474 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3478 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3481 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3486 bus->sr_enabled = true;
3487 brcmf_dbg(INFO, "SR enabled\n");
3490 /* enable KSO bit */
3491 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3493 struct brcmf_core *core = bus->sdio_core;
3497 brcmf_dbg(TRACE, "Enter\n");
3499 /* KSO bit added in SDIO core rev 12 */
3503 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3505 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3509 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3510 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3511 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3512 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3515 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3524 static int brcmf_sdio_bus_preinit(struct device *dev)
3526 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3527 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3528 struct brcmf_sdio *bus = sdiodev->bus;
3529 struct brcmf_core *core = bus->sdio_core;
3534 /* maxctl provided by common layer */
3535 if (WARN_ON(!bus_if->maxctl))
3538 /* Allocate control receive buffer */
3539 bus_if->maxctl += bus->roundup;
3540 value = roundup((bus_if->maxctl + SDPCM_HDRLEN), ALIGNMENT);
3541 value += bus->head_align;
3542 bus->rxbuf = kmalloc(value, GFP_ATOMIC);
3544 bus->rxblen = value;
3546 /* the commands below use the terms tx and rx from
3547 * a device perspective, ie. bus:txglom affects the
3548 * bus transfers from device to host.
3550 if (core->rev < 12) {
3551 /* for sdio core rev < 12, disable txgloming */
3553 err = brcmf_iovar_data_set(dev, "bus:txglom", &iovar,
3556 /* otherwise, set txglomalign */
3557 value = sdiodev->settings->bus.sdio.sd_sgentry_align;
3558 /* SDIO ADMA requires at least 32 bit alignment */
3559 iovar = cpu_to_le32(max_t(u32, value, ALIGNMENT));
3560 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &iovar,
3567 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3568 if (sdiodev->sg_support) {
3569 bus->txglom = false;
3570 iovar = cpu_to_le32(1);
3571 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3572 &iovar, sizeof(iovar));
3574 /* bus:rxglom is allowed to fail */
3578 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3581 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3587 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev)
3589 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3590 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3591 struct brcmf_sdio *bus = sdiodev->bus;
3593 return bus->ci->ramsize - bus->ci->srsize;
3596 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data,
3599 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3600 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3601 struct brcmf_sdio *bus = sdiodev->bus;
3607 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase,
3610 address = bus->ci->rambase;
3612 sdio_claim_host(sdiodev->func1);
3613 while (offset < mem_size) {
3614 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK :
3616 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len);
3618 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3628 sdio_release_host(sdiodev->func1);
3632 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
3634 if (!bus->dpc_triggered) {
3635 bus->dpc_triggered = true;
3636 queue_work(bus->brcmf_wq, &bus->datawork);
3640 void brcmf_sdio_isr(struct brcmf_sdio *bus, bool in_isr)
3642 brcmf_dbg(TRACE, "Enter\n");
3645 brcmf_err("bus is null pointer, exiting\n");
3649 /* Count the interrupt call */
3650 bus->sdcnt.intrcount++;
3652 atomic_set(&bus->ipend, 1);
3654 if (brcmf_sdio_intr_rstatus(bus)) {
3655 brcmf_err("failed backplane access\n");
3658 /* Disable additional interrupts (is this needed now)? */
3660 brcmf_err("isr w/o interrupt configured!\n");
3662 bus->dpc_triggered = true;
3663 queue_work(bus->brcmf_wq, &bus->datawork);
3666 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3668 brcmf_dbg(TIMER, "Enter\n");
3670 /* Poll period: check device if appropriate. */
3671 if (!bus->sr_enabled &&
3672 bus->poll && (++bus->polltick >= bus->pollrate)) {
3675 /* Reset poll tick */
3678 /* Check device if no interrupts */
3680 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3682 if (!bus->dpc_triggered) {
3685 sdio_claim_host(bus->sdiodev->func1);
3686 devpend = brcmf_sdiod_func0_rb(bus->sdiodev,
3687 SDIO_CCCR_INTx, NULL);
3688 sdio_release_host(bus->sdiodev->func1);
3689 intstatus = devpend & (INTR_STATUS_FUNC1 |
3693 /* If there is something, make like the ISR and
3696 bus->sdcnt.pollcnt++;
3697 atomic_set(&bus->ipend, 1);
3699 bus->dpc_triggered = true;
3700 queue_work(bus->brcmf_wq, &bus->datawork);
3704 /* Update interrupt tracking */
3705 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3708 /* Poll for console output periodically */
3709 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() &&
3710 bus->console_interval != 0) {
3711 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL);
3712 if (bus->console.count >= bus->console_interval) {
3713 bus->console.count -= bus->console_interval;
3714 sdio_claim_host(bus->sdiodev->func1);
3715 /* Make sure backplane clock is on */
3716 brcmf_sdio_bus_sleep(bus, false, false);
3717 if (brcmf_sdio_readconsole(bus) < 0)
3719 bus->console_interval = 0;
3720 sdio_release_host(bus->sdiodev->func1);
3725 /* On idle timeout clear activity flag and/or turn off clock */
3726 if (!bus->dpc_triggered) {
3728 if ((!bus->dpc_running) && (bus->idletime > 0) &&
3729 (bus->clkstate == CLK_AVAIL)) {
3731 if (bus->idlecount > bus->idletime) {
3732 brcmf_dbg(SDIO, "idle\n");
3733 sdio_claim_host(bus->sdiodev->func1);
3735 if (!BRCMF_FWCON_ON() ||
3736 bus->console_interval == 0)
3738 brcmf_sdio_wd_timer(bus, false);
3740 brcmf_sdio_bus_sleep(bus, true, false);
3741 sdio_release_host(bus->sdiodev->func1);
3751 static void brcmf_sdio_dataworker(struct work_struct *work)
3753 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3756 bus->dpc_running = true;
3758 while (READ_ONCE(bus->dpc_triggered)) {
3759 bus->dpc_triggered = false;
3760 brcmf_sdio_dpc(bus);
3763 bus->dpc_running = false;
3764 if (brcmf_sdiod_freezing(bus->sdiodev)) {
3765 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
3766 brcmf_sdiod_try_freeze(bus->sdiodev);
3767 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3772 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3773 struct brcmf_chip *ci, u32 drivestrength)
3775 const struct sdiod_drive_str *str_tab = NULL;
3779 u32 drivestrength_sel = 0;
3783 if (!(ci->cc_caps & CC_CAP_PMU))
3786 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3787 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
3788 str_tab = sdiod_drvstr_tab1_1v8;
3789 str_mask = 0x00003800;
3792 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
3793 str_tab = sdiod_drvstr_tab6_1v8;
3794 str_mask = 0x00001800;
3797 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
3798 /* note: 43143 does not support tristate */
3799 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3800 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3801 str_tab = sdiod_drvstr_tab2_3v3;
3802 str_mask = 0x00000007;
3805 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3806 ci->name, drivestrength);
3808 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
3809 str_tab = sdiod_drive_strength_tab5_1v8;
3810 str_mask = 0x00003800;
3814 brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n",
3815 ci->name, ci->chiprev, ci->pmurev);
3819 if (str_tab != NULL) {
3820 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci);
3822 for (i = 0; str_tab[i].strength != 0; i++) {
3823 if (drivestrength >= str_tab[i].strength) {
3824 drivestrength_sel = str_tab[i].sel;
3828 addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
3829 brcmf_sdiod_writel(sdiodev, addr, 1, NULL);
3830 cc_data_temp = brcmf_sdiod_readl(sdiodev, addr, NULL);
3831 cc_data_temp &= ~str_mask;
3832 drivestrength_sel <<= str_shift;
3833 cc_data_temp |= drivestrength_sel;
3834 brcmf_sdiod_writel(sdiodev, addr, cc_data_temp, NULL);
3836 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3837 str_tab[i].strength, drivestrength, cc_data_temp);
3841 static int brcmf_sdio_buscoreprep(void *ctx)
3843 struct brcmf_sdio_dev *sdiodev = ctx;
3847 /* Try forcing SDIO core to do ALPAvail request only */
3848 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3849 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3851 brcmf_err("error writing for HT off\n");
3855 /* If register supported, wait for ALPAvail and then force ALP */
3856 /* This may take up to 15 milliseconds */
3857 clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3859 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3860 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3865 SPINWAIT(((clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3867 !SBSDIO_ALPAV(clkval)),
3868 PMU_MAX_TRANSITION_DLY);
3870 if (!SBSDIO_ALPAV(clkval)) {
3871 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3876 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3877 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3880 /* Also, disable the extra SDIO pull-ups */
3881 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3886 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
3889 struct brcmf_sdio_dev *sdiodev = ctx;
3890 struct brcmf_core *core = sdiodev->bus->sdio_core;
3893 /* clear all interrupts */
3894 reg_addr = core->base + SD_REG(intstatus);
3895 brcmf_sdiod_writel(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3898 /* Write reset vector to address 0 */
3899 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3903 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3905 struct brcmf_sdio_dev *sdiodev = ctx;
3908 val = brcmf_sdiod_readl(sdiodev, addr, NULL);
3911 * this is a bit of special handling if reading the chipcommon chipid
3912 * register. The 4339 is a next-gen of the 4335. It uses the same
3913 * SDIO device id as 4335 and the chipid register returns 4335 as well.
3914 * It can be identified as 4339 by looking at the chip revision. It
3915 * is corrected here so the chip.c module has the right info.
3917 if (addr == CORE_CC_REG(SI_ENUM_BASE_DEFAULT, chipid) &&
3918 (sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4339 ||
3919 sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4335_4339)) {
3920 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3922 val &= ~CID_ID_MASK;
3923 val |= BRCM_CC_4339_CHIP_ID;
3930 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3932 struct brcmf_sdio_dev *sdiodev = ctx;
3934 brcmf_sdiod_writel(sdiodev, addr, val, NULL);
3937 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3938 .prepare = brcmf_sdio_buscoreprep,
3939 .activate = brcmf_sdio_buscore_activate,
3940 .read32 = brcmf_sdio_buscore_read32,
3941 .write32 = brcmf_sdio_buscore_write32,
3945 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3947 struct brcmf_sdio_dev *sdiodev;
3955 sdiodev = bus->sdiodev;
3956 sdio_claim_host(sdiodev->func1);
3958 enum_base = brcmf_chip_enum_base(sdiodev->func1->device);
3960 pr_debug("F1 signature read @0x%08x=0x%4x\n", enum_base,
3961 brcmf_sdiod_readl(sdiodev, enum_base, NULL));
3964 * Force PLL off until brcmf_chip_attach()
3965 * programs PLL control regs
3968 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, BRCMF_INIT_CLKCTL1,
3971 clkctl = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3974 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3975 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3976 err, BRCMF_INIT_CLKCTL1, clkctl);
3980 bus->ci = brcmf_chip_attach(sdiodev, sdiodev->func1->device,
3981 &brcmf_sdio_buscore_ops);
3982 if (IS_ERR(bus->ci)) {
3983 brcmf_err("brcmf_chip_attach failed!\n");
3988 /* Pick up the SDIO core info struct from chip.c */
3989 bus->sdio_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
3990 if (!bus->sdio_core)
3993 /* Pick up the CHIPCOMMON core info struct, for bulk IO in bcmsdh.c */
3994 sdiodev->cc_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_CHIPCOMMON);
3995 if (!sdiodev->cc_core)
3998 sdiodev->settings = brcmf_get_module_param(sdiodev->dev,
4002 if (!sdiodev->settings) {
4003 brcmf_err("Failed to get device parameters\n");
4006 /* platform specific configuration:
4007 * alignments must be at least 4 bytes for ADMA
4009 bus->head_align = ALIGNMENT;
4010 bus->sgentry_align = ALIGNMENT;
4011 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT)
4012 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align;
4013 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT)
4014 bus->sgentry_align =
4015 sdiodev->settings->bus.sdio.sd_sgentry_align;
4017 /* allocate scatter-gather table. sg support
4018 * will be disabled upon allocation failure.
4020 brcmf_sdiod_sgtable_alloc(sdiodev);
4022 #ifdef CONFIG_PM_SLEEP
4023 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ
4024 * is true or when platform data OOB irq is true).
4026 if ((sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_KEEP_POWER) &&
4027 ((sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_WAKE_SDIO_IRQ) ||
4028 (sdiodev->settings->bus.sdio.oob_irq_supported)))
4029 sdiodev->bus_if->wowl_supported = true;
4032 if (brcmf_sdio_kso_init(bus)) {
4033 brcmf_err("error enabling KSO\n");
4037 if (sdiodev->settings->bus.sdio.drive_strength)
4038 drivestrength = sdiodev->settings->bus.sdio.drive_strength;
4040 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
4041 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength);
4043 /* Set card control so an SDIO card reset does a WLAN backplane reset */
4044 reg_val = brcmf_sdiod_func0_rb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err);
4048 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
4050 brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
4054 /* set PMUControl so a backplane reset does PMU state reload */
4055 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol);
4056 reg_val = brcmf_sdiod_readl(sdiodev, reg_addr, &err);
4060 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
4062 brcmf_sdiod_writel(sdiodev, reg_addr, reg_val, &err);
4066 sdio_release_host(sdiodev->func1);
4068 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
4070 /* allocate header buffer */
4071 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
4074 /* Locate an appropriately-aligned portion of hdrbuf */
4075 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
4078 /* Set the poll and/or interrupt flags */
4087 sdio_release_host(sdiodev->func1);
4092 brcmf_sdio_watchdog_thread(void *data)
4094 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
4097 allow_signal(SIGTERM);
4098 /* Run until signal received */
4099 brcmf_sdiod_freezer_count(bus->sdiodev);
4101 if (kthread_should_stop())
4103 brcmf_sdiod_freezer_uncount(bus->sdiodev);
4104 wait = wait_for_completion_interruptible(&bus->watchdog_wait);
4105 brcmf_sdiod_freezer_count(bus->sdiodev);
4106 brcmf_sdiod_try_freeze(bus->sdiodev);
4108 brcmf_sdio_bus_watchdog(bus);
4109 /* Count the tick for reference */
4110 bus->sdcnt.tickcnt++;
4111 reinit_completion(&bus->watchdog_wait);
4119 brcmf_sdio_watchdog(struct timer_list *t)
4121 struct brcmf_sdio *bus = from_timer(bus, t, timer);
4123 if (bus->watchdog_tsk) {
4124 complete(&bus->watchdog_wait);
4125 /* Reschedule the watchdog */
4127 mod_timer(&bus->timer,
4128 jiffies + BRCMF_WD_POLL);
4133 int brcmf_sdio_get_fwname(struct device *dev, const char *ext, u8 *fw_name)
4135 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
4136 struct brcmf_fw_request *fwreq;
4137 struct brcmf_fw_name fwnames[] = {
4141 fwreq = brcmf_fw_alloc_request(bus_if->chip, bus_if->chiprev,
4143 ARRAY_SIZE(brcmf_sdio_fwnames),
4144 fwnames, ARRAY_SIZE(fwnames));
4152 static int brcmf_sdio_bus_reset(struct device *dev)
4155 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
4156 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
4158 brcmf_dbg(SDIO, "Enter\n");
4160 /* start by unregistering irqs */
4161 brcmf_sdiod_intr_unregister(sdiodev);
4163 brcmf_sdiod_remove(sdiodev);
4165 /* reset the adapter */
4166 sdio_claim_host(sdiodev->func1);
4167 mmc_hw_reset(sdiodev->func1->card->host);
4168 sdio_release_host(sdiodev->func1);
4170 brcmf_bus_change_state(sdiodev->bus_if, BRCMF_BUS_DOWN);
4172 ret = brcmf_sdiod_probe(sdiodev);
4174 brcmf_err("Failed to probe after sdio device reset: ret %d\n",
4181 static const struct brcmf_bus_ops brcmf_sdio_bus_ops = {
4182 .stop = brcmf_sdio_bus_stop,
4183 .preinit = brcmf_sdio_bus_preinit,
4184 .txdata = brcmf_sdio_bus_txdata,
4185 .txctl = brcmf_sdio_bus_txctl,
4186 .rxctl = brcmf_sdio_bus_rxctl,
4187 .gettxq = brcmf_sdio_bus_gettxq,
4188 .wowl_config = brcmf_sdio_wowl_config,
4189 .get_ramsize = brcmf_sdio_bus_get_ramsize,
4190 .get_memdump = brcmf_sdio_bus_get_memdump,
4191 .get_fwname = brcmf_sdio_get_fwname,
4192 .debugfs_create = brcmf_sdio_debugfs_create,
4193 .reset = brcmf_sdio_bus_reset
4196 #define BRCMF_SDIO_FW_CODE 0
4197 #define BRCMF_SDIO_FW_NVRAM 1
4199 static void brcmf_sdio_firmware_callback(struct device *dev, int err,
4200 struct brcmf_fw_request *fwreq)
4202 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
4203 struct brcmf_sdio_dev *sdiod = bus_if->bus_priv.sdio;
4204 struct brcmf_sdio *bus = sdiod->bus;
4205 struct brcmf_core *core = bus->sdio_core;
4206 const struct firmware *code;
4212 brcmf_dbg(TRACE, "Enter: dev=%s, err=%d\n", dev_name(dev), err);
4217 code = fwreq->items[BRCMF_SDIO_FW_CODE].binary;
4218 nvram = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.data;
4219 nvram_len = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.len;
4222 /* try to download image and nvram to the dongle */
4223 bus->alp_only = true;
4224 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
4227 bus->alp_only = false;
4229 /* Start the watchdog timer */
4230 bus->sdcnt.tickcnt = 0;
4231 brcmf_sdio_wd_timer(bus, true);
4233 sdio_claim_host(sdiod->func1);
4235 /* Make sure backplane clock is on, needed to generate F2 interrupt */
4236 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4237 if (bus->clkstate != CLK_AVAIL)
4240 /* Force clocks on backplane to be sure F2 interrupt propagates */
4241 saveclk = brcmf_sdiod_readb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, &err);
4244 bpreq |= brcmf_chip_is_ulp(bus->ci) ?
4245 SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT;
4246 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR,
4250 brcmf_err("Failed to force clock for F2: err %d\n", err);
4254 /* Enable function 2 (frame transfers) */
4255 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailboxdata),
4256 SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, NULL);
4258 err = sdio_enable_func(sdiod->func2);
4260 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
4262 /* If F2 successfully enabled, set core and enable interrupts */
4264 /* Set up the interrupt mask and enable interrupts */
4265 bus->hostintmask = HOSTINTMASK;
4266 brcmf_sdiod_writel(sdiod, core->base + SD_REG(hostintmask),
4267 bus->hostintmask, NULL);
4269 switch (sdiod->func1->device) {
4270 case SDIO_DEVICE_ID_BROADCOM_CYPRESS_4373:
4271 case SDIO_DEVICE_ID_BROADCOM_CYPRESS_43752:
4272 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n",
4273 CY_4373_F2_WATERMARK);
4274 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
4275 CY_4373_F2_WATERMARK, &err);
4276 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL,
4278 devctl |= SBSDIO_DEVCTL_F2WM_ENAB;
4279 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl,
4281 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL,
4282 CY_4373_F1_MESBUSYCTRL, &err);
4284 case SDIO_DEVICE_ID_BROADCOM_CYPRESS_43012:
4285 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n",
4286 CY_43012_F2_WATERMARK);
4287 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
4288 CY_43012_F2_WATERMARK, &err);
4289 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL,
4291 devctl |= SBSDIO_DEVCTL_F2WM_ENAB;
4292 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl,
4294 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL,
4295 CY_43012_MESBUSYCTRL, &err);
4297 case SDIO_DEVICE_ID_BROADCOM_4329:
4298 case SDIO_DEVICE_ID_BROADCOM_4339:
4299 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n",
4300 CY_4339_F2_WATERMARK);
4301 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
4302 CY_4339_F2_WATERMARK, &err);
4303 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL,
4305 devctl |= SBSDIO_DEVCTL_F2WM_ENAB;
4306 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl,
4308 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL,
4309 CY_4339_MESBUSYCTRL, &err);
4311 case SDIO_DEVICE_ID_BROADCOM_43455:
4312 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n",
4313 CY_43455_F2_WATERMARK);
4314 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
4315 CY_43455_F2_WATERMARK, &err);
4316 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL,
4318 devctl |= SBSDIO_DEVCTL_F2WM_ENAB;
4319 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl,
4321 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL,
4322 CY_43455_MESBUSYCTRL, &err);
4324 case SDIO_DEVICE_ID_BROADCOM_4359:
4325 case SDIO_DEVICE_ID_BROADCOM_4354:
4326 case SDIO_DEVICE_ID_BROADCOM_4356:
4327 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n",
4328 CY_435X_F2_WATERMARK);
4329 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
4330 CY_435X_F2_WATERMARK, &err);
4331 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL,
4333 devctl |= SBSDIO_DEVCTL_F2WM_ENAB;
4334 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl,
4336 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL,
4337 CY_435X_F1_MESBUSYCTRL, &err);
4340 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
4341 DEFAULT_F2_WATERMARK, &err);
4345 /* Disable F2 again */
4346 sdio_disable_func(sdiod->func2);
4350 if (brcmf_chip_sr_capable(bus->ci)) {
4351 brcmf_sdio_sr_init(bus);
4353 /* Restore previous clock setting */
4354 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR,
4359 /* Assign bus interface call back */
4360 sdiod->bus_if->dev = sdiod->dev;
4361 sdiod->bus_if->ops = &brcmf_sdio_bus_ops;
4362 sdiod->bus_if->chip = bus->ci->chip;
4363 sdiod->bus_if->chiprev = bus->ci->chiprev;
4365 /* Allow full data communication using DPC from now on. */
4366 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
4368 err = brcmf_sdiod_intr_register(sdiod);
4370 brcmf_err("intr register failed:%d\n", err);
4373 /* If we didn't come up, turn off backplane clock */
4375 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4379 sdio_release_host(sdiod->func1);
4381 err = brcmf_alloc(sdiod->dev, sdiod->settings);
4383 brcmf_err("brcmf_alloc failed\n");
4387 /* Attach to the common layer, reserve hdr space */
4388 err = brcmf_attach(sdiod->dev);
4390 brcmf_err("brcmf_attach failed\n");
4398 brcmf_free(sdiod->dev);
4400 sdio_claim_host(sdiod->func1);
4402 brcmf_sdio_checkdied(bus);
4404 sdio_release_host(sdiod->func1);
4406 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
4407 device_release_driver(&sdiod->func2->dev);
4408 device_release_driver(dev);
4411 static struct brcmf_fw_request *
4412 brcmf_sdio_prepare_fw_request(struct brcmf_sdio *bus)
4414 struct brcmf_fw_request *fwreq;
4415 struct brcmf_fw_name fwnames[] = {
4416 { ".bin", bus->sdiodev->fw_name },
4417 { ".txt", bus->sdiodev->nvram_name },
4420 fwreq = brcmf_fw_alloc_request(bus->ci->chip, bus->ci->chiprev,
4422 ARRAY_SIZE(brcmf_sdio_fwnames),
4423 fwnames, ARRAY_SIZE(fwnames));
4427 fwreq->items[BRCMF_SDIO_FW_CODE].type = BRCMF_FW_TYPE_BINARY;
4428 fwreq->items[BRCMF_SDIO_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM;
4429 fwreq->board_type = bus->sdiodev->settings->board_type;
4434 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4437 struct brcmf_sdio *bus;
4438 struct workqueue_struct *wq;
4439 struct brcmf_fw_request *fwreq;
4441 brcmf_dbg(TRACE, "Enter\n");
4443 /* Allocate private bus interface state */
4444 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4448 bus->sdiodev = sdiodev;
4450 skb_queue_head_init(&bus->glom);
4451 bus->txbound = BRCMF_TXBOUND;
4452 bus->rxbound = BRCMF_RXBOUND;
4453 bus->txminmax = BRCMF_TXMINMAX;
4454 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4456 /* single-threaded workqueue */
4457 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM | WQ_HIGHPRI,
4458 dev_name(&sdiodev->func1->dev));
4460 brcmf_err("insufficient memory to create txworkqueue\n");
4463 brcmf_sdiod_freezer_count(sdiodev);
4464 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4467 /* attempt to attach to the dongle */
4468 if (!(brcmf_sdio_probe_attach(bus))) {
4469 brcmf_err("brcmf_sdio_probe_attach failed\n");
4473 spin_lock_init(&bus->rxctl_lock);
4474 spin_lock_init(&bus->txq_lock);
4475 init_waitqueue_head(&bus->ctrl_wait);
4476 init_waitqueue_head(&bus->dcmd_resp_wait);
4478 /* Set up the watchdog timer */
4479 timer_setup(&bus->timer, brcmf_sdio_watchdog, 0);
4480 /* Initialize watchdog thread */
4481 init_completion(&bus->watchdog_wait);
4482 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4483 bus, "brcmf_wdog/%s",
4484 dev_name(&sdiodev->func1->dev));
4485 if (IS_ERR(bus->watchdog_tsk)) {
4486 pr_warn("brcmf_watchdog thread failed to start\n");
4487 bus->watchdog_tsk = NULL;
4489 /* Initialize DPC thread */
4490 bus->dpc_triggered = false;
4491 bus->dpc_running = false;
4493 /* default sdio bus header length for tx packet */
4494 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4496 /* Query the F2 block size, set roundup accordingly */
4497 bus->blocksize = bus->sdiodev->func2->cur_blksize;
4498 bus->roundup = min(max_roundup, bus->blocksize);
4500 sdio_claim_host(bus->sdiodev->func1);
4502 /* Disable F2 to clear any intermediate frame state on the dongle */
4503 sdio_disable_func(bus->sdiodev->func2);
4505 bus->rxflow = false;
4507 /* Done with backplane-dependent accesses, can drop clock... */
4508 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4510 sdio_release_host(bus->sdiodev->func1);
4512 /* ...and initialize clock/power states */
4513 bus->clkstate = CLK_SDONLY;
4514 bus->idletime = BRCMF_IDLE_INTERVAL;
4515 bus->idleclock = BRCMF_IDLE_ACTIVE;
4518 bus->sr_enabled = false;
4520 brcmf_dbg(INFO, "completed!!\n");
4522 fwreq = brcmf_sdio_prepare_fw_request(bus);
4528 ret = brcmf_fw_get_firmwares(sdiodev->dev, fwreq,
4529 brcmf_sdio_firmware_callback);
4531 brcmf_err("async firmware request failed: %d\n", ret);
4539 brcmf_sdio_remove(bus);
4543 /* Detach and free everything */
4544 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4546 brcmf_dbg(TRACE, "Enter\n");
4549 /* Stop watchdog task */
4550 if (bus->watchdog_tsk) {
4551 send_sig(SIGTERM, bus->watchdog_tsk, 1);
4552 kthread_stop(bus->watchdog_tsk);
4553 bus->watchdog_tsk = NULL;
4556 /* De-register interrupt handler */
4557 brcmf_sdiod_intr_unregister(bus->sdiodev);
4559 brcmf_detach(bus->sdiodev->dev);
4560 brcmf_free(bus->sdiodev->dev);
4562 cancel_work_sync(&bus->datawork);
4564 destroy_workqueue(bus->brcmf_wq);
4567 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
4568 sdio_claim_host(bus->sdiodev->func1);
4569 brcmf_sdio_wd_timer(bus, false);
4570 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4571 /* Leave the device in state where it is
4572 * 'passive'. This is done by resetting all
4576 brcmf_chip_set_passive(bus->ci);
4577 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4578 sdio_release_host(bus->sdiodev->func1);
4580 brcmf_chip_detach(bus->ci);
4582 if (bus->sdiodev->settings)
4583 brcmf_release_module_param(bus->sdiodev->settings);
4590 brcmf_dbg(TRACE, "Disconnected\n");
4593 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active)
4595 /* Totally stop the timer */
4596 if (!active && bus->wd_active) {
4597 del_timer_sync(&bus->timer);
4598 bus->wd_active = false;
4602 /* don't start the wd until fw is loaded */
4603 if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
4607 if (!bus->wd_active) {
4608 /* Create timer again when watchdog period is
4609 dynamically changed or in the first instance
4611 bus->timer.expires = jiffies + BRCMF_WD_POLL;
4612 add_timer(&bus->timer);
4613 bus->wd_active = true;
4615 /* Re arm the timer, at last watchdog period */
4616 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL);
4621 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
4625 sdio_claim_host(bus->sdiodev->func1);
4626 ret = brcmf_sdio_bus_sleep(bus, sleep, false);
4627 sdio_release_host(bus->sdiodev->func1);
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