2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/atomic.h>
19 #include <linux/kernel.h>
20 #include <linux/kthread.h>
21 #include <linux/printk.h>
22 #include <linux/pci_ids.h>
23 #include <linux/netdevice.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched/signal.h>
26 #include <linux/mmc/sdio.h>
27 #include <linux/mmc/sdio_ids.h>
28 #include <linux/mmc/sdio_func.h>
29 #include <linux/mmc/card.h>
30 #include <linux/semaphore.h>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <linux/bcma/bcma.h>
34 #include <linux/debugfs.h>
35 #include <linux/vmalloc.h>
36 #include <asm/unaligned.h>
38 #include <brcmu_wifi.h>
39 #include <brcmu_utils.h>
40 #include <brcm_hw_ids.h>
49 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500)
50 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500)
52 /* watermark expressed in number of words */
53 #define DEFAULT_F2_WATERMARK 0x8
54 #define CY_4373_F2_WATERMARK 0x40
55 #define CY_43012_F2_WATERMARK 0x60
59 #define BRCMF_TRAP_INFO_SIZE 80
61 #define CBUF_LEN (128)
63 /* Device console log buffer state */
64 #define CONSOLE_BUFFER_MAX 2024
67 __le32 buf; /* Can't be pointer on (64-bit) hosts */
70 char *_buf_compat; /* Redundant pointer for backward compat. */
75 * When there is no UART (e.g. Quickturn),
76 * the host should write a complete
77 * input line directly into cbuf and then write
78 * the length into vcons_in.
79 * This may also be used when there is a real UART
80 * (at risk of conflicting with
81 * the real UART). vcons_out is currently unused.
86 /* Output (logging) buffer
87 * Console output is written to a ring buffer log_buf at index log_idx.
88 * The host may read the output when it sees log_idx advance.
89 * Output will be lost if the output wraps around faster than the host
92 struct rte_log_le log_le;
94 /* Console input line buffer
95 * Characters are read one at a time into cbuf
96 * until <CR> is received, then
97 * the buffer is processed as a command line.
98 * Also used for virtual UART.
105 #include <chipcommon.h>
109 #include "tracepoint.h"
111 #define TXQLEN 2048 /* bulk tx queue length */
112 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
113 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
116 #define TXRETRIES 2 /* # of retries for tx frames */
118 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
121 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
124 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
126 #define MEMBLOCK 2048 /* Block size used for downloading
128 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
129 biggest possible glom */
131 #define BRCMF_FIRSTREAD (1 << 6)
133 #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */
135 /* SBSDIO_DEVICE_CTL */
137 /* 1: device will assert busy signal when receiving CMD53 */
138 #define SBSDIO_DEVCTL_SETBUSY 0x01
139 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
140 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
141 /* 1: mask all interrupts to host except the chipActive (rev 8) */
142 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
143 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
144 * sdio bus power cycle to clear (rev 9) */
145 #define SBSDIO_DEVCTL_PADS_ISO 0x08
146 /* 1: enable F2 Watermark */
147 #define SBSDIO_DEVCTL_F2WM_ENAB 0x10
148 /* Force SD->SB reset mapping (rev 11) */
149 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
150 /* Determined by CoreControl bit */
151 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
152 /* Force backplane reset */
153 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
154 /* Force no backplane reset */
155 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
157 /* direct(mapped) cis space */
159 /* MAPPED common CIS address */
160 #define SBSDIO_CIS_BASE_COMMON 0x1000
161 /* maximum bytes in one CIS */
162 #define SBSDIO_CIS_SIZE_LIMIT 0x200
163 /* cis offset addr is < 17 bits */
164 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
166 /* manfid tuple length, include tuple, link bytes */
167 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
169 #define SD_REG(field) \
170 (offsetof(struct sdpcmd_regs, field))
172 /* SDIO function 1 register CHIPCLKCSR */
173 /* Force ALP request to backplane */
174 #define SBSDIO_FORCE_ALP 0x01
175 /* Force HT request to backplane */
176 #define SBSDIO_FORCE_HT 0x02
177 /* Force ILP request to backplane */
178 #define SBSDIO_FORCE_ILP 0x04
179 /* Make ALP ready (power up xtal) */
180 #define SBSDIO_ALP_AVAIL_REQ 0x08
181 /* Make HT ready (power up PLL) */
182 #define SBSDIO_HT_AVAIL_REQ 0x10
183 /* Squelch clock requests from HW */
184 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
185 /* Status: ALP is ready */
186 #define SBSDIO_ALP_AVAIL 0x40
187 /* Status: HT is ready */
188 #define SBSDIO_HT_AVAIL 0x80
189 #define SBSDIO_CSR_MASK 0x1F
190 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
191 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
192 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
193 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
194 #define SBSDIO_CLKAV(regval, alponly) \
195 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
198 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
199 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
200 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
201 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
202 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
203 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
204 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
205 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
206 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
207 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
208 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
209 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
210 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
211 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
212 #define I_PC (1 << 10) /* descriptor error */
213 #define I_PD (1 << 11) /* data error */
214 #define I_DE (1 << 12) /* Descriptor protocol Error */
215 #define I_RU (1 << 13) /* Receive descriptor Underflow */
216 #define I_RO (1 << 14) /* Receive fifo Overflow */
217 #define I_XU (1 << 15) /* Transmit fifo Underflow */
218 #define I_RI (1 << 16) /* Receive Interrupt */
219 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
220 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
221 #define I_XI (1 << 24) /* Transmit Interrupt */
222 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
223 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
224 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
225 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
226 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
227 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
228 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
229 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
230 #define I_DMA (I_RI | I_XI | I_ERRORS)
233 #define CC_CISRDY (1 << 0) /* CIS Ready */
234 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
235 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
236 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
237 #define CC_XMTDATAAVAIL_MODE (1 << 4)
238 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
241 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
242 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
243 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
244 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
247 * Software allocation of To SB Mailbox resources
250 /* tosbmailbox bits corresponding to intstatus bits */
251 #define SMB_NAK (1 << 0) /* Frame NAK */
252 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
253 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
254 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
256 /* tosbmailboxdata */
257 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
260 * Software allocation of To Host Mailbox resources
264 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
265 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
266 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
267 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
269 /* tohostmailboxdata */
270 #define HMB_DATA_NAKHANDLED 0x0001 /* retransmit NAK'd frame */
271 #define HMB_DATA_DEVREADY 0x0002 /* talk to host after enable */
272 #define HMB_DATA_FC 0x0004 /* per prio flowcontrol update flag */
273 #define HMB_DATA_FWREADY 0x0008 /* fw ready for protocol activity */
274 #define HMB_DATA_FWHALT 0x0010 /* firmware halted */
276 #define HMB_DATA_FCDATA_MASK 0xff000000
277 #define HMB_DATA_FCDATA_SHIFT 24
279 #define HMB_DATA_VERSION_MASK 0x00ff0000
280 #define HMB_DATA_VERSION_SHIFT 16
283 * Software-defined protocol header
286 /* Current protocol version */
287 #define SDPCM_PROT_VERSION 4
290 * Shared structure between dongle and the host.
291 * The structure contains pointers to trap or assert information.
293 #define SDPCM_SHARED_VERSION 0x0003
294 #define SDPCM_SHARED_VERSION_MASK 0x00FF
295 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
296 #define SDPCM_SHARED_ASSERT 0x0200
297 #define SDPCM_SHARED_TRAP 0x0400
299 /* Space for header read, limit for data packets */
300 #define MAX_HDR_READ (1 << 6)
301 #define MAX_RX_DATASZ 2048
303 /* Bump up limit on waiting for HT to account for first startup;
304 * if the image is doing a CRC calculation before programming the PMU
305 * for HT availability, it could take a couple hundred ms more, so
306 * max out at a 1 second (1000000us).
308 #undef PMU_MAX_TRANSITION_DLY
309 #define PMU_MAX_TRANSITION_DLY 1000000
311 /* Value for ChipClockCSR during initial setup */
312 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
313 SBSDIO_ALP_AVAIL_REQ)
315 /* Flags for SDH calls */
316 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
318 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
321 #define BRCMF_IDLE_INTERVAL 1
323 #define KSO_WAIT_US 50
324 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
325 #define BRCMF_SDIO_MAX_ACCESS_ERRORS 5
328 * Conversion of 802.1D priority to precedence level
330 static uint prio2prec(u32 prio)
332 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
337 /* Device console log buffer state */
338 struct brcmf_console {
339 uint count; /* Poll interval msec counter */
340 uint log_addr; /* Log struct address (fixed) */
341 struct rte_log_le log_le; /* Log struct (host copy) */
342 uint bufsize; /* Size of log buffer */
343 u8 *buf; /* Log buffer (host copy) */
344 uint last; /* Last buffer read index */
347 struct brcmf_trap_info {
361 __le32 r9; /* sb/v6 */
362 __le32 r10; /* sl/v7 */
363 __le32 r11; /* fp/v8 */
371 struct sdpcm_shared {
375 u32 assert_file_addr;
377 u32 console_addr; /* Address of struct rte_console */
383 struct sdpcm_shared_le {
386 __le32 assert_exp_addr;
387 __le32 assert_file_addr;
389 __le32 console_addr; /* Address of struct rte_console */
390 __le32 msgtrace_addr;
395 /* dongle SDIO bus specific header info */
396 struct brcmf_sdio_hdrinfo {
408 * hold counter variables
410 struct brcmf_sdio_count {
411 uint intrcount; /* Count of device interrupt callbacks */
412 uint lastintrs; /* Count as of last watchdog timer */
413 uint pollcnt; /* Count of active polls */
414 uint regfails; /* Count of R_REG failures */
415 uint tx_sderrs; /* Count of tx attempts with sd errors */
416 uint fcqueued; /* Tx packets that got queued */
417 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
418 uint rx_toolong; /* Receive frames too long to receive */
419 uint rxc_errors; /* SDIO errors when reading control frames */
420 uint rx_hdrfail; /* SDIO errors on header reads */
421 uint rx_badhdr; /* Bad received headers (roosync?) */
422 uint rx_badseq; /* Mismatched rx sequence number */
423 uint fc_rcvd; /* Number of flow-control events received */
424 uint fc_xoff; /* Number which turned on flow-control */
425 uint fc_xon; /* Number which turned off flow-control */
426 uint rxglomfail; /* Failed deglom attempts */
427 uint rxglomframes; /* Number of glom frames (superframes) */
428 uint rxglompkts; /* Number of packets from glom frames */
429 uint f2rxhdrs; /* Number of header reads */
430 uint f2rxdata; /* Number of frame data reads */
431 uint f2txdata; /* Number of f2 frame writes */
432 uint f1regdata; /* Number of f1 register accesses */
433 uint tickcnt; /* Number of watchdog been schedule */
434 ulong tx_ctlerrs; /* Err of sending ctrl frames */
435 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
436 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
437 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
438 ulong rx_readahead_cnt; /* packets where header read-ahead was used */
441 /* misc chip info needed by some of the routines */
442 /* Private data for SDIO bus interaction */
444 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
445 struct brcmf_chip *ci; /* Chip info struct */
446 struct brcmf_core *sdio_core; /* sdio core info struct */
448 u32 hostintmask; /* Copy of Host Interrupt Mask */
449 atomic_t intstatus; /* Intstatus bits (events) pending */
450 atomic_t fcstate; /* State of dongle flow-control */
452 uint blocksize; /* Block size of SDIO transfers */
453 uint roundup; /* Max roundup limit */
455 struct pktq txq; /* Queue length used for flow-control */
456 u8 flowcontrol; /* per prio flow control bitmask */
457 u8 tx_seq; /* Transmit sequence number (next) */
458 u8 tx_max; /* Maximum transmit sequence allowed */
460 u8 *hdrbuf; /* buffer for handling rx frame */
461 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
462 u8 rx_seq; /* Receive sequence number (expected) */
463 struct brcmf_sdio_hdrinfo cur_read;
464 /* info of current read frame */
465 bool rxskip; /* Skip receive (awaiting NAK ACK) */
466 bool rxpending; /* Data frame pending in dongle */
468 uint rxbound; /* Rx frames to read before resched */
469 uint txbound; /* Tx frames to send before resched */
472 struct sk_buff *glomd; /* Packet containing glomming descriptor */
473 struct sk_buff_head glom; /* Packet list for glommed superframe */
475 u8 *rxbuf; /* Buffer for receiving control packets */
476 uint rxblen; /* Allocated length of rxbuf */
477 u8 *rxctl; /* Aligned pointer into rxbuf */
478 u8 *rxctl_orig; /* pointer for freeing rxctl */
479 uint rxlen; /* Length of valid data in buffer */
480 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
482 u8 sdpcm_ver; /* Bus protocol reported by dongle */
484 bool intr; /* Use interrupts */
485 bool poll; /* Use polling */
486 atomic_t ipend; /* Device interrupt is pending */
487 uint spurious; /* Count of spurious interrupts */
488 uint pollrate; /* Ticks between device polls */
489 uint polltick; /* Tick counter */
492 uint console_interval;
493 struct brcmf_console console; /* Console output polling support */
494 uint console_addr; /* Console address from shared struct */
497 uint clkstate; /* State of sd and backplane clock(s) */
498 s32 idletime; /* Control for activity timeout */
499 s32 idlecount; /* Activity timeout counter */
500 s32 idleclock; /* How to set bus driver when idle */
501 bool rxflow_mode; /* Rx flow control mode */
502 bool rxflow; /* Is rx flow control on */
503 bool alp_only; /* Don't use HT clock (ALP only) */
507 bool ctrl_frame_stat;
510 spinlock_t txq_lock; /* protect bus->txq */
511 wait_queue_head_t ctrl_wait;
512 wait_queue_head_t dcmd_resp_wait;
514 struct timer_list timer;
515 struct completion watchdog_wait;
516 struct task_struct *watchdog_tsk;
519 struct workqueue_struct *brcmf_wq;
520 struct work_struct datawork;
524 bool txoff; /* Transmit flow-controlled */
525 struct brcmf_sdio_count sdcnt;
526 bool sr_enabled; /* SaveRestore enabled */
529 u8 tx_hdrlen; /* sdio bus header length for tx packet */
530 bool txglom; /* host tx glomming enable flag */
531 u16 head_align; /* buffer pointer alignment */
532 u16 sgentry_align; /* scatter-gather buffer alignment */
538 #define CLK_PENDING 2
542 static int qcount[NUMPRIO];
545 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
547 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
549 /* Limit on rounding up frames */
550 static const uint max_roundup = 512;
552 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
558 enum brcmf_sdio_frmtype {
559 BRCMF_SDIO_FT_NORMAL,
564 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
566 /* SDIO Pad drive strength to select value mappings */
567 struct sdiod_drive_str {
568 u8 strength; /* Pad Drive Strength in mA */
569 u8 sel; /* Chip-specific select value */
572 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
573 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
584 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
585 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
595 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
596 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
602 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
603 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
610 BRCMF_FW_DEF(43143, "brcmfmac43143-sdio");
611 BRCMF_FW_DEF(43241B0, "brcmfmac43241b0-sdio");
612 BRCMF_FW_DEF(43241B4, "brcmfmac43241b4-sdio");
613 BRCMF_FW_DEF(43241B5, "brcmfmac43241b5-sdio");
614 BRCMF_FW_DEF(4329, "brcmfmac4329-sdio");
615 BRCMF_FW_DEF(4330, "brcmfmac4330-sdio");
616 BRCMF_FW_DEF(4334, "brcmfmac4334-sdio");
617 BRCMF_FW_DEF(43340, "brcmfmac43340-sdio");
618 BRCMF_FW_DEF(4335, "brcmfmac4335-sdio");
619 BRCMF_FW_DEF(43362, "brcmfmac43362-sdio");
620 BRCMF_FW_DEF(4339, "brcmfmac4339-sdio");
621 BRCMF_FW_DEF(43430A0, "brcmfmac43430a0-sdio");
622 /* Note the names are not postfixed with a1 for backward compatibility */
623 BRCMF_FW_DEF(43430A1, "brcmfmac43430-sdio");
624 BRCMF_FW_DEF(43455, "brcmfmac43455-sdio");
625 BRCMF_FW_DEF(43456, "brcmfmac43456-sdio");
626 BRCMF_FW_DEF(4354, "brcmfmac4354-sdio");
627 BRCMF_FW_DEF(4356, "brcmfmac4356-sdio");
628 BRCMF_FW_DEF(4373, "brcmfmac4373-sdio");
629 BRCMF_FW_DEF(43012, "brcmfmac43012-sdio");
631 static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
632 BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
633 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
634 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
635 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5),
636 BRCMF_FW_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329),
637 BRCMF_FW_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330),
638 BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
639 BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
640 BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340),
641 BRCMF_FW_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
642 BRCMF_FW_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
643 BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
644 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0),
645 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFE, 43430A1),
646 BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0x00000200, 43456),
647 BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFDC0, 43455),
648 BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
649 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
650 BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373),
651 BRCMF_FW_ENTRY(CY_CC_43012_CHIP_ID, 0xFFFFFFFF, 43012)
654 static void pkt_align(struct sk_buff *p, int len, int align)
657 datalign = (unsigned long)(p->data);
658 datalign = roundup(datalign, (align)) - datalign;
660 skb_pull(p, datalign);
664 /* To check if there's window offered */
665 static bool data_ok(struct brcmf_sdio *bus)
667 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
668 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
672 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
674 u8 wr_val = 0, rd_val, cmp_val, bmask;
679 brcmf_dbg(TRACE, "Enter: on=%d\n", on);
681 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
682 /* 1st KSO write goes to AOS wake up core if device is asleep */
683 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err);
685 /* In case of 43012 chip, the chip could go down immediately after
686 * KSO bit is cleared. So the further reads of KSO register could
687 * fail. Thereby just bailing out immediately after clearing KSO
688 * bit, to avoid polling of KSO bit.
690 if (!on && bus->ci->chip == CY_CC_43012_CHIP_ID)
694 /* device WAKEUP through KSO:
695 * write bit 0 & read back until
696 * both bits 0 (kso bit) & 1 (dev on status) are set
698 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
699 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
701 usleep_range(2000, 3000);
703 /* Put device to sleep, turn off KSO */
705 /* only check for bit0, bit1(dev on status) may not
706 * get cleared right away
708 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
712 /* reliable KSO bit set/clr:
713 * the sdiod sleep write access is synced to PMU 32khz clk
714 * just one write attempt may fail,
715 * read it back until it matches written value
717 rd_val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
720 if ((rd_val & bmask) == cmp_val)
724 /* bail out upon subsequent access errors */
725 if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS))
729 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val,
732 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
735 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
738 if (try_cnt > MAX_KSO_ATTEMPTS)
739 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
744 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
746 /* Turn backplane clock on or off */
747 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
750 u8 clkctl, clkreq, devctl;
751 unsigned long timeout;
753 brcmf_dbg(SDIO, "Enter\n");
757 if (bus->sr_enabled) {
758 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
763 /* Request HT Avail */
765 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
767 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
770 brcmf_err("HT Avail request error: %d\n", err);
774 /* Check current status */
775 clkctl = brcmf_sdiod_readb(bus->sdiodev,
776 SBSDIO_FUNC1_CHIPCLKCSR, &err);
778 brcmf_err("HT Avail read error: %d\n", err);
782 /* Go to pending and await interrupt if appropriate */
783 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
784 /* Allow only clock-available interrupt */
785 devctl = brcmf_sdiod_readb(bus->sdiodev,
786 SBSDIO_DEVICE_CTL, &err);
788 brcmf_err("Devctl error setting CA: %d\n", err);
792 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
793 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL,
795 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
796 bus->clkstate = CLK_PENDING;
799 } else if (bus->clkstate == CLK_PENDING) {
800 /* Cancel CA-only interrupt filter */
801 devctl = brcmf_sdiod_readb(bus->sdiodev,
802 SBSDIO_DEVICE_CTL, &err);
803 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
804 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL,
808 /* Otherwise, wait here (polling) for HT Avail */
810 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
811 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
812 clkctl = brcmf_sdiod_readb(bus->sdiodev,
813 SBSDIO_FUNC1_CHIPCLKCSR,
815 if (time_after(jiffies, timeout))
818 usleep_range(5000, 10000);
821 brcmf_err("HT Avail request error: %d\n", err);
824 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
825 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
826 PMU_MAX_TRANSITION_DLY, clkctl);
830 /* Mark clock available */
831 bus->clkstate = CLK_AVAIL;
832 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
835 if (!bus->alp_only) {
836 if (SBSDIO_ALPONLY(clkctl))
837 brcmf_err("HT Clock should be on\n");
839 #endif /* defined (DEBUG) */
844 if (bus->clkstate == CLK_PENDING) {
845 /* Cancel CA-only interrupt filter */
846 devctl = brcmf_sdiod_readb(bus->sdiodev,
847 SBSDIO_DEVICE_CTL, &err);
848 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
849 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL,
853 bus->clkstate = CLK_SDONLY;
854 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
856 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
858 brcmf_err("Failed access turning clock off: %d\n",
866 /* Change idle/active SD state */
867 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
869 brcmf_dbg(SDIO, "Enter\n");
872 bus->clkstate = CLK_SDONLY;
874 bus->clkstate = CLK_NONE;
879 /* Transition SD and backplane clock readiness */
880 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
883 uint oldstate = bus->clkstate;
886 brcmf_dbg(SDIO, "Enter\n");
888 /* Early exit if we're already there */
889 if (bus->clkstate == target)
894 /* Make sure SD clock is available */
895 if (bus->clkstate == CLK_NONE)
896 brcmf_sdio_sdclk(bus, true);
897 /* Now request HT Avail on the backplane */
898 brcmf_sdio_htclk(bus, true, pendok);
902 /* Remove HT request, or bring up SD clock */
903 if (bus->clkstate == CLK_NONE)
904 brcmf_sdio_sdclk(bus, true);
905 else if (bus->clkstate == CLK_AVAIL)
906 brcmf_sdio_htclk(bus, false, false);
908 brcmf_err("request for %d -> %d\n",
909 bus->clkstate, target);
913 /* Make sure to remove HT request */
914 if (bus->clkstate == CLK_AVAIL)
915 brcmf_sdio_htclk(bus, false, false);
916 /* Now remove the SD clock */
917 brcmf_sdio_sdclk(bus, false);
921 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
928 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
933 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
934 (sleep ? "SLEEP" : "WAKE"),
935 (bus->sleeping ? "SLEEP" : "WAKE"));
937 /* If SR is enabled control bus state with KSO */
938 if (bus->sr_enabled) {
939 /* Done if we're already in the requested state */
940 if (sleep == bus->sleeping)
945 clkcsr = brcmf_sdiod_readb(bus->sdiodev,
946 SBSDIO_FUNC1_CHIPCLKCSR,
948 if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
949 brcmf_dbg(SDIO, "no clock, set ALP\n");
950 brcmf_sdiod_writeb(bus->sdiodev,
951 SBSDIO_FUNC1_CHIPCLKCSR,
952 SBSDIO_ALP_AVAIL_REQ, &err);
954 err = brcmf_sdio_kso_control(bus, false);
956 err = brcmf_sdio_kso_control(bus, true);
959 brcmf_err("error while changing bus sleep state %d\n",
968 if (!bus->sr_enabled)
969 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
971 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
972 brcmf_sdio_wd_timer(bus, true);
974 bus->sleeping = sleep;
975 brcmf_dbg(SDIO, "new state %s\n",
976 (sleep ? "SLEEP" : "WAKE"));
978 brcmf_dbg(SDIO, "Exit: err=%d\n", err);
984 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
986 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
989 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
990 struct sdpcm_shared *sh)
995 struct sdpcm_shared_le sh_le;
998 sdio_claim_host(bus->sdiodev->func1);
999 brcmf_sdio_bus_sleep(bus, false, false);
1002 * Read last word in socram to determine
1003 * address of sdpcm_shared structure
1005 shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
1006 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
1007 shaddr -= bus->ci->srsize;
1008 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
1014 * Check if addr is valid.
1015 * NVRAM length at the end of memory should have been overwritten.
1017 addr = le32_to_cpu(addr_le);
1018 if (!brcmf_sdio_valid_shared_address(addr)) {
1019 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
1024 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
1026 /* Read hndrte_shared structure */
1027 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1028 sizeof(struct sdpcm_shared_le));
1032 sdio_release_host(bus->sdiodev->func1);
1035 sh->flags = le32_to_cpu(sh_le.flags);
1036 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1037 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1038 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1039 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1040 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1041 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1043 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1044 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1045 SDPCM_SHARED_VERSION,
1046 sh->flags & SDPCM_SHARED_VERSION_MASK);
1052 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
1054 sdio_release_host(bus->sdiodev->func1);
1058 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1060 struct sdpcm_shared sh;
1062 if (brcmf_sdio_readshared(bus, &sh) == 0)
1063 bus->console_addr = sh.console_addr;
1066 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1071 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1073 struct brcmf_sdio_dev *sdiod = bus->sdiodev;
1074 struct brcmf_core *core = bus->sdio_core;
1080 brcmf_dbg(SDIO, "Enter\n");
1082 /* Read mailbox data and ack that we did so */
1083 hmb_data = brcmf_sdiod_readl(sdiod,
1084 core->base + SD_REG(tohostmailboxdata),
1088 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox),
1091 bus->sdcnt.f1regdata += 2;
1093 /* dongle indicates the firmware has halted/crashed */
1094 if (hmb_data & HMB_DATA_FWHALT) {
1095 brcmf_dbg(SDIO, "mailbox indicates firmware halted\n");
1096 brcmf_fw_crashed(&sdiod->func1->dev);
1099 /* Dongle recomposed rx frames, accept them again */
1100 if (hmb_data & HMB_DATA_NAKHANDLED) {
1101 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1104 brcmf_err("unexpected NAKHANDLED!\n");
1106 bus->rxskip = false;
1107 intstatus |= I_HMB_FRAME_IND;
1111 * DEVREADY does not occur with gSPI.
1113 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1115 (hmb_data & HMB_DATA_VERSION_MASK) >>
1116 HMB_DATA_VERSION_SHIFT;
1117 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1118 brcmf_err("Version mismatch, dongle reports %d, "
1120 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1122 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1126 * Retrieve console state address now that firmware should have
1129 brcmf_sdio_get_console_addr(bus);
1133 * Flow Control has been moved into the RX headers and this out of band
1134 * method isn't used any more.
1135 * remaining backward compatible with older dongles.
1137 if (hmb_data & HMB_DATA_FC) {
1138 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1139 HMB_DATA_FCDATA_SHIFT;
1141 if (fcbits & ~bus->flowcontrol)
1142 bus->sdcnt.fc_xoff++;
1144 if (bus->flowcontrol & ~fcbits)
1145 bus->sdcnt.fc_xon++;
1147 bus->sdcnt.fc_rcvd++;
1148 bus->flowcontrol = fcbits;
1151 /* Shouldn't be any others */
1152 if (hmb_data & ~(HMB_DATA_DEVREADY |
1153 HMB_DATA_NAKHANDLED |
1157 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1158 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1164 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1166 struct brcmf_sdio_dev *sdiod = bus->sdiodev;
1167 struct brcmf_core *core = bus->sdio_core;
1173 brcmf_err("%sterminate frame%s\n",
1174 abort ? "abort command, " : "",
1175 rtx ? ", send NAK" : "");
1178 brcmf_sdiod_abort(bus->sdiodev, bus->sdiodev->func2);
1180 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
1182 bus->sdcnt.f1regdata++;
1184 /* Wait until the packet has been flushed (device/FIFO stable) */
1185 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1186 hi = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCHI,
1188 lo = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCLO,
1190 bus->sdcnt.f1regdata += 2;
1192 if ((hi == 0) && (lo == 0))
1195 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1196 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1197 lastrbc, (hi << 8) + lo);
1199 lastrbc = (hi << 8) + lo;
1203 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1205 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1209 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox),
1212 bus->sdcnt.f1regdata++;
1217 /* Clear partial in any case */
1218 bus->cur_read.len = 0;
1221 static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
1223 struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
1226 /* On failure, abort the command and terminate the frame */
1227 brcmf_err("sdio error, abort command and terminate frame\n");
1228 bus->sdcnt.tx_sderrs++;
1230 brcmf_sdiod_abort(sdiodev, sdiodev->func2);
1231 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
1232 bus->sdcnt.f1regdata++;
1234 for (i = 0; i < 3; i++) {
1235 hi = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1236 lo = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1237 bus->sdcnt.f1regdata += 2;
1238 if ((hi == 0) && (lo == 0))
1243 /* return total length of buffer chain */
1244 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1250 skb_queue_walk(&bus->glom, p)
1255 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1257 struct sk_buff *cur, *next;
1259 skb_queue_walk_safe(&bus->glom, cur, next) {
1260 skb_unlink(cur, &bus->glom);
1261 brcmu_pkt_buf_free_skb(cur);
1266 * brcmfmac sdio bus specific header
1267 * This is the lowest layer header wrapped on the packets transmitted between
1268 * host and WiFi dongle which contains information needed for SDIO core and
1271 * It consists of 3 parts: hardware header, hardware extension header and
1273 * hardware header (frame tag) - 4 bytes
1274 * Byte 0~1: Frame length
1275 * Byte 2~3: Checksum, bit-wise inverse of frame length
1276 * hardware extension header - 8 bytes
1277 * Tx glom mode only, N/A for Rx or normal Tx
1278 * Byte 0~1: Packet length excluding hw frame tag
1280 * Byte 3: Frame flags, bit 0: last frame indication
1281 * Byte 4~5: Reserved
1282 * Byte 6~7: Tail padding length
1283 * software header - 8 bytes
1284 * Byte 0: Rx/Tx sequence number
1285 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1286 * Byte 2: Length of next data frame, reserved for Tx
1287 * Byte 3: Data offset
1288 * Byte 4: Flow control bits, reserved for Tx
1289 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1290 * Byte 6~7: Reserved
1292 #define SDPCM_HWHDR_LEN 4
1293 #define SDPCM_HWEXT_LEN 8
1294 #define SDPCM_SWHDR_LEN 8
1295 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1296 /* software header */
1297 #define SDPCM_SEQ_MASK 0x000000ff
1298 #define SDPCM_SEQ_WRAP 256
1299 #define SDPCM_CHANNEL_MASK 0x00000f00
1300 #define SDPCM_CHANNEL_SHIFT 8
1301 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1302 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1303 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1304 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1305 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1306 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1307 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1308 #define SDPCM_NEXTLEN_SHIFT 16
1309 #define SDPCM_DOFFSET_MASK 0xff000000
1310 #define SDPCM_DOFFSET_SHIFT 24
1311 #define SDPCM_FCMASK_MASK 0x000000ff
1312 #define SDPCM_WINDOW_MASK 0x0000ff00
1313 #define SDPCM_WINDOW_SHIFT 8
1315 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1318 hdrvalue = *(u32 *)swheader;
1319 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1322 static inline bool brcmf_sdio_fromevntchan(u8 *swheader)
1327 hdrvalue = *(u32 *)swheader;
1328 ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT);
1330 return (ret == SDPCM_EVENT_CHANNEL);
1333 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1334 struct brcmf_sdio_hdrinfo *rd,
1335 enum brcmf_sdio_frmtype type)
1338 u8 rx_seq, fc, tx_seq_max;
1341 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1344 len = get_unaligned_le16(header);
1345 checksum = get_unaligned_le16(header + sizeof(u16));
1346 /* All zero means no more to read */
1347 if (!(len | checksum)) {
1348 bus->rxpending = false;
1351 if ((u16)(~(len ^ checksum))) {
1352 brcmf_err("HW header checksum error\n");
1353 bus->sdcnt.rx_badhdr++;
1354 brcmf_sdio_rxfail(bus, false, false);
1357 if (len < SDPCM_HDRLEN) {
1358 brcmf_err("HW header length error\n");
1361 if (type == BRCMF_SDIO_FT_SUPER &&
1362 (roundup(len, bus->blocksize) != rd->len)) {
1363 brcmf_err("HW superframe header length error\n");
1366 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1367 brcmf_err("HW subframe header length error\n");
1372 /* software header */
1373 header += SDPCM_HWHDR_LEN;
1374 swheader = le32_to_cpu(*(__le32 *)header);
1375 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1376 brcmf_err("Glom descriptor found in superframe head\n");
1380 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1381 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1382 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1383 type != BRCMF_SDIO_FT_SUPER) {
1384 brcmf_err("HW header length too long\n");
1385 bus->sdcnt.rx_toolong++;
1386 brcmf_sdio_rxfail(bus, false, false);
1390 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1391 brcmf_err("Wrong channel for superframe\n");
1395 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1396 rd->channel != SDPCM_EVENT_CHANNEL) {
1397 brcmf_err("Wrong channel for subframe\n");
1401 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1402 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1403 brcmf_err("seq %d: bad data offset\n", rx_seq);
1404 bus->sdcnt.rx_badhdr++;
1405 brcmf_sdio_rxfail(bus, false, false);
1409 if (rd->seq_num != rx_seq) {
1410 brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num);
1411 bus->sdcnt.rx_badseq++;
1412 rd->seq_num = rx_seq;
1414 /* no need to check the reset for subframe */
1415 if (type == BRCMF_SDIO_FT_SUB)
1417 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1418 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1419 /* only warm for NON glom packet */
1420 if (rd->channel != SDPCM_GLOM_CHANNEL)
1421 brcmf_err("seq %d: next length error\n", rx_seq);
1424 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1425 fc = swheader & SDPCM_FCMASK_MASK;
1426 if (bus->flowcontrol != fc) {
1427 if (~bus->flowcontrol & fc)
1428 bus->sdcnt.fc_xoff++;
1429 if (bus->flowcontrol & ~fc)
1430 bus->sdcnt.fc_xon++;
1431 bus->sdcnt.fc_rcvd++;
1432 bus->flowcontrol = fc;
1434 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1435 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1436 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1437 tx_seq_max = bus->tx_seq + 2;
1439 bus->tx_max = tx_seq_max;
1444 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1446 *(__le16 *)header = cpu_to_le16(frm_length);
1447 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1450 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1451 struct brcmf_sdio_hdrinfo *hd_info)
1456 brcmf_sdio_update_hwhdr(header, hd_info->len);
1457 hdr_offset = SDPCM_HWHDR_LEN;
1460 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1461 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1462 hdrval = (u16)hd_info->tail_pad << 16;
1463 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1464 hdr_offset += SDPCM_HWEXT_LEN;
1467 hdrval = hd_info->seq_num;
1468 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1470 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1472 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1473 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1474 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1477 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1482 struct sk_buff *pfirst, *pnext;
1487 struct brcmf_sdio_hdrinfo rd_new;
1489 /* If packets, issue read(s) and send up packet chain */
1490 /* Return sequence numbers consumed? */
1492 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1493 bus->glomd, skb_peek(&bus->glom));
1495 /* If there's a descriptor, generate the packet chain */
1497 pfirst = pnext = NULL;
1498 dlen = (u16) (bus->glomd->len);
1499 dptr = bus->glomd->data;
1500 if (!dlen || (dlen & 1)) {
1501 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1506 for (totlen = num = 0; dlen; num++) {
1507 /* Get (and move past) next length */
1508 sublen = get_unaligned_le16(dptr);
1509 dlen -= sizeof(u16);
1510 dptr += sizeof(u16);
1511 if ((sublen < SDPCM_HDRLEN) ||
1512 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1513 brcmf_err("descriptor len %d bad: %d\n",
1518 if (sublen % bus->sgentry_align) {
1519 brcmf_err("sublen %d not multiple of %d\n",
1520 sublen, bus->sgentry_align);
1524 /* For last frame, adjust read len so total
1525 is a block multiple */
1528 (roundup(totlen, bus->blocksize) - totlen);
1529 totlen = roundup(totlen, bus->blocksize);
1532 /* Allocate/chain packet for next subframe */
1533 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1534 if (pnext == NULL) {
1535 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1539 skb_queue_tail(&bus->glom, pnext);
1541 /* Adhere to start alignment requirements */
1542 pkt_align(pnext, sublen, bus->sgentry_align);
1545 /* If all allocations succeeded, save packet chain
1548 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1550 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1551 totlen != bus->cur_read.len) {
1552 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1553 bus->cur_read.len, totlen, rxseq);
1555 pfirst = pnext = NULL;
1557 brcmf_sdio_free_glom(bus);
1561 /* Done with descriptor packet */
1562 brcmu_pkt_buf_free_skb(bus->glomd);
1564 bus->cur_read.len = 0;
1567 /* Ok -- either we just generated a packet chain,
1568 or had one from before */
1569 if (!skb_queue_empty(&bus->glom)) {
1570 if (BRCMF_GLOM_ON()) {
1571 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1572 skb_queue_walk(&bus->glom, pnext) {
1573 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1574 pnext, (u8 *) (pnext->data),
1575 pnext->len, pnext->len);
1579 pfirst = skb_peek(&bus->glom);
1580 dlen = (u16) brcmf_sdio_glom_len(bus);
1582 /* Do an SDIO read for the superframe. Configurable iovar to
1583 * read directly into the chained packet, or allocate a large
1584 * packet and and copy into the chain.
1586 sdio_claim_host(bus->sdiodev->func1);
1587 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1589 sdio_release_host(bus->sdiodev->func1);
1590 bus->sdcnt.f2rxdata++;
1592 /* On failure, kill the superframe */
1594 brcmf_err("glom read of %d bytes failed: %d\n",
1597 sdio_claim_host(bus->sdiodev->func1);
1598 brcmf_sdio_rxfail(bus, true, false);
1599 bus->sdcnt.rxglomfail++;
1600 brcmf_sdio_free_glom(bus);
1601 sdio_release_host(bus->sdiodev->func1);
1605 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1606 pfirst->data, min_t(int, pfirst->len, 48),
1609 rd_new.seq_num = rxseq;
1611 sdio_claim_host(bus->sdiodev->func1);
1612 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1613 BRCMF_SDIO_FT_SUPER);
1614 sdio_release_host(bus->sdiodev->func1);
1615 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1617 /* Remove superframe header, remember offset */
1618 skb_pull(pfirst, rd_new.dat_offset);
1621 /* Validate all the subframe headers */
1622 skb_queue_walk(&bus->glom, pnext) {
1623 /* leave when invalid subframe is found */
1627 rd_new.len = pnext->len;
1628 rd_new.seq_num = rxseq++;
1629 sdio_claim_host(bus->sdiodev->func1);
1630 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1632 sdio_release_host(bus->sdiodev->func1);
1633 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1634 pnext->data, 32, "subframe:\n");
1640 /* Terminate frame on error */
1641 sdio_claim_host(bus->sdiodev->func1);
1642 brcmf_sdio_rxfail(bus, true, false);
1643 bus->sdcnt.rxglomfail++;
1644 brcmf_sdio_free_glom(bus);
1645 sdio_release_host(bus->sdiodev->func1);
1646 bus->cur_read.len = 0;
1650 /* Basic SD framing looks ok - process each packet (header) */
1652 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1653 dptr = (u8 *) (pfirst->data);
1654 sublen = get_unaligned_le16(dptr);
1655 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1657 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1659 "Rx Subframe Data:\n");
1661 __skb_trim(pfirst, sublen);
1662 skb_pull(pfirst, doff);
1664 if (pfirst->len == 0) {
1665 skb_unlink(pfirst, &bus->glom);
1666 brcmu_pkt_buf_free_skb(pfirst);
1670 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1672 min_t(int, pfirst->len, 32),
1673 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1674 bus->glom.qlen, pfirst, pfirst->data,
1675 pfirst->len, pfirst->next,
1677 skb_unlink(pfirst, &bus->glom);
1678 if (brcmf_sdio_fromevntchan(&dptr[SDPCM_HWHDR_LEN]))
1679 brcmf_rx_event(bus->sdiodev->dev, pfirst);
1681 brcmf_rx_frame(bus->sdiodev->dev, pfirst,
1683 bus->sdcnt.rxglompkts++;
1686 bus->sdcnt.rxglomframes++;
1691 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1694 DECLARE_WAITQUEUE(wait, current);
1695 int timeout = DCMD_RESP_TIMEOUT;
1697 /* Wait until control frame is available */
1698 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1699 set_current_state(TASK_INTERRUPTIBLE);
1701 while (!(*condition) && (!signal_pending(current) && timeout))
1702 timeout = schedule_timeout(timeout);
1704 if (signal_pending(current))
1707 set_current_state(TASK_RUNNING);
1708 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1713 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1715 wake_up_interruptible(&bus->dcmd_resp_wait);
1720 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1723 u8 *buf = NULL, *rbuf;
1726 brcmf_dbg(SDIO, "Enter\n");
1728 buf = vzalloc(bus->rxblen);
1733 pad = ((unsigned long)rbuf % bus->head_align);
1735 rbuf += (bus->head_align - pad);
1737 /* Copy the already-read portion over */
1738 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1739 if (len <= BRCMF_FIRSTREAD)
1742 /* Raise rdlen to next SDIO block to avoid tail command */
1743 rdlen = len - BRCMF_FIRSTREAD;
1744 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1745 pad = bus->blocksize - (rdlen % bus->blocksize);
1746 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1747 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1749 } else if (rdlen % bus->head_align) {
1750 rdlen += bus->head_align - (rdlen % bus->head_align);
1753 /* Drop if the read is too big or it exceeds our maximum */
1754 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1755 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1756 rdlen, bus->sdiodev->bus_if->maxctl);
1757 brcmf_sdio_rxfail(bus, false, false);
1761 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1762 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1763 len, len - doff, bus->sdiodev->bus_if->maxctl);
1764 bus->sdcnt.rx_toolong++;
1765 brcmf_sdio_rxfail(bus, false, false);
1769 /* Read remain of frame body */
1770 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1771 bus->sdcnt.f2rxdata++;
1773 /* Control frame failures need retransmission */
1775 brcmf_err("read %d control bytes failed: %d\n",
1777 bus->sdcnt.rxc_errors++;
1778 brcmf_sdio_rxfail(bus, true, true);
1781 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1785 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1786 buf, len, "RxCtrl:\n");
1788 /* Point to valid data and indicate its length */
1789 spin_lock_bh(&bus->rxctl_lock);
1791 brcmf_err("last control frame is being processed.\n");
1792 spin_unlock_bh(&bus->rxctl_lock);
1796 bus->rxctl = buf + doff;
1797 bus->rxctl_orig = buf;
1798 bus->rxlen = len - doff;
1799 spin_unlock_bh(&bus->rxctl_lock);
1802 /* Awake any waiters */
1803 brcmf_sdio_dcmd_resp_wake(bus);
1806 /* Pad read to blocksize for efficiency */
1807 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1809 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1810 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1811 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1812 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1814 } else if (*rdlen % bus->head_align) {
1815 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1819 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1821 struct sk_buff *pkt; /* Packet for event or data frames */
1822 u16 pad; /* Number of pad bytes to read */
1823 uint rxleft = 0; /* Remaining number of frames allowed */
1824 int ret; /* Return code from calls */
1825 uint rxcount = 0; /* Total frames read */
1826 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1829 brcmf_dbg(SDIO, "Enter\n");
1831 /* Not finished unless we encounter no more frames indication */
1832 bus->rxpending = true;
1834 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1835 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
1836 rd->seq_num++, rxleft--) {
1838 /* Handle glomming separately */
1839 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1841 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1842 bus->glomd, skb_peek(&bus->glom));
1843 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1844 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1845 rd->seq_num += cnt - 1;
1846 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1850 rd->len_left = rd->len;
1851 /* read header first for unknow frame length */
1852 sdio_claim_host(bus->sdiodev->func1);
1854 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1855 bus->rxhdr, BRCMF_FIRSTREAD);
1856 bus->sdcnt.f2rxhdrs++;
1858 brcmf_err("RXHEADER FAILED: %d\n",
1860 bus->sdcnt.rx_hdrfail++;
1861 brcmf_sdio_rxfail(bus, true, true);
1862 sdio_release_host(bus->sdiodev->func1);
1866 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1867 bus->rxhdr, SDPCM_HDRLEN,
1870 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1871 BRCMF_SDIO_FT_NORMAL)) {
1872 sdio_release_host(bus->sdiodev->func1);
1873 if (!bus->rxpending)
1879 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1880 brcmf_sdio_read_control(bus, bus->rxhdr,
1883 /* prepare the descriptor for the next read */
1884 rd->len = rd->len_nxtfrm << 4;
1886 /* treat all packet as event if we don't know */
1887 rd->channel = SDPCM_EVENT_CHANNEL;
1888 sdio_release_host(bus->sdiodev->func1);
1891 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1892 rd->len - BRCMF_FIRSTREAD : 0;
1893 head_read = BRCMF_FIRSTREAD;
1896 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1898 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1901 /* Give up on data, request rtx of events */
1902 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1903 brcmf_sdio_rxfail(bus, false,
1904 RETRYCHAN(rd->channel));
1905 sdio_release_host(bus->sdiodev->func1);
1908 skb_pull(pkt, head_read);
1909 pkt_align(pkt, rd->len_left, bus->head_align);
1911 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1912 bus->sdcnt.f2rxdata++;
1913 sdio_release_host(bus->sdiodev->func1);
1916 brcmf_err("read %d bytes from channel %d failed: %d\n",
1917 rd->len, rd->channel, ret);
1918 brcmu_pkt_buf_free_skb(pkt);
1919 sdio_claim_host(bus->sdiodev->func1);
1920 brcmf_sdio_rxfail(bus, true,
1921 RETRYCHAN(rd->channel));
1922 sdio_release_host(bus->sdiodev->func1);
1927 skb_push(pkt, head_read);
1928 memcpy(pkt->data, bus->rxhdr, head_read);
1931 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
1932 rd_new.seq_num = rd->seq_num;
1933 sdio_claim_host(bus->sdiodev->func1);
1934 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
1935 BRCMF_SDIO_FT_NORMAL)) {
1937 brcmu_pkt_buf_free_skb(pkt);
1939 bus->sdcnt.rx_readahead_cnt++;
1940 if (rd->len != roundup(rd_new.len, 16)) {
1941 brcmf_err("frame length mismatch:read %d, should be %d\n",
1943 roundup(rd_new.len, 16) >> 4);
1945 brcmf_sdio_rxfail(bus, true, true);
1946 sdio_release_host(bus->sdiodev->func1);
1947 brcmu_pkt_buf_free_skb(pkt);
1950 sdio_release_host(bus->sdiodev->func1);
1951 rd->len_nxtfrm = rd_new.len_nxtfrm;
1952 rd->channel = rd_new.channel;
1953 rd->dat_offset = rd_new.dat_offset;
1955 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
1958 bus->rxhdr, SDPCM_HDRLEN,
1961 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
1962 brcmf_err("readahead on control packet %d?\n",
1964 /* Force retry w/normal header read */
1966 sdio_claim_host(bus->sdiodev->func1);
1967 brcmf_sdio_rxfail(bus, false, true);
1968 sdio_release_host(bus->sdiodev->func1);
1969 brcmu_pkt_buf_free_skb(pkt);
1974 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1975 pkt->data, rd->len, "Rx Data:\n");
1977 /* Save superframe descriptor and allocate packet frame */
1978 if (rd->channel == SDPCM_GLOM_CHANNEL) {
1979 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
1980 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
1982 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1985 __skb_trim(pkt, rd->len);
1986 skb_pull(pkt, SDPCM_HDRLEN);
1989 brcmf_err("%s: glom superframe w/o "
1990 "descriptor!\n", __func__);
1991 sdio_claim_host(bus->sdiodev->func1);
1992 brcmf_sdio_rxfail(bus, false, false);
1993 sdio_release_host(bus->sdiodev->func1);
1995 /* prepare the descriptor for the next read */
1996 rd->len = rd->len_nxtfrm << 4;
1998 /* treat all packet as event if we don't know */
1999 rd->channel = SDPCM_EVENT_CHANNEL;
2003 /* Fill in packet len and prio, deliver upward */
2004 __skb_trim(pkt, rd->len);
2005 skb_pull(pkt, rd->dat_offset);
2008 brcmu_pkt_buf_free_skb(pkt);
2009 else if (rd->channel == SDPCM_EVENT_CHANNEL)
2010 brcmf_rx_event(bus->sdiodev->dev, pkt);
2012 brcmf_rx_frame(bus->sdiodev->dev, pkt,
2015 /* prepare the descriptor for the next read */
2016 rd->len = rd->len_nxtfrm << 4;
2018 /* treat all packet as event if we don't know */
2019 rd->channel = SDPCM_EVENT_CHANNEL;
2022 rxcount = maxframes - rxleft;
2023 /* Message if we hit the limit */
2025 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
2027 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2028 /* Back off rxseq if awaiting rtx, update rx_seq */
2031 bus->rx_seq = rd->seq_num;
2037 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2039 wake_up_interruptible(&bus->ctrl_wait);
2043 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2045 struct brcmf_bus_stats *stats;
2049 dat_buf = (u8 *)(pkt->data);
2051 /* Check head padding */
2052 head_pad = ((unsigned long)dat_buf % bus->head_align);
2054 if (skb_headroom(pkt) < head_pad) {
2055 stats = &bus->sdiodev->bus_if->stats;
2056 atomic_inc(&stats->pktcowed);
2057 if (skb_cow_head(pkt, head_pad)) {
2058 atomic_inc(&stats->pktcow_failed);
2063 skb_push(pkt, head_pad);
2064 dat_buf = (u8 *)(pkt->data);
2066 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2071 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2074 /* flag marking a dummy skb added for DMA alignment requirement */
2075 #define ALIGN_SKB_FLAG 0x8000
2076 /* bit mask of data length chopped from the previous packet */
2077 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2079 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2080 struct sk_buff_head *pktq,
2081 struct sk_buff *pkt, u16 total_len)
2083 struct brcmf_sdio_dev *sdiodev;
2084 struct sk_buff *pkt_pad;
2085 u16 tail_pad, tail_chop, chain_pad;
2086 unsigned int blksize;
2090 sdiodev = bus->sdiodev;
2091 blksize = sdiodev->func2->cur_blksize;
2092 /* sg entry alignment should be a divisor of block size */
2093 WARN_ON(blksize % bus->sgentry_align);
2095 /* Check tail padding */
2096 lastfrm = skb_queue_is_last(pktq, pkt);
2098 tail_chop = pkt->len % bus->sgentry_align;
2100 tail_pad = bus->sgentry_align - tail_chop;
2101 chain_pad = (total_len + tail_pad) % blksize;
2102 if (lastfrm && chain_pad)
2103 tail_pad += blksize - chain_pad;
2104 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2105 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
2107 if (pkt_pad == NULL)
2109 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2110 if (unlikely(ret < 0)) {
2114 memcpy(pkt_pad->data,
2115 pkt->data + pkt->len - tail_chop,
2117 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2118 skb_trim(pkt, pkt->len - tail_chop);
2119 skb_trim(pkt_pad, tail_pad + tail_chop);
2120 __skb_queue_after(pktq, pkt, pkt_pad);
2122 ntail = pkt->data_len + tail_pad -
2123 (pkt->end - pkt->tail);
2124 if (skb_cloned(pkt) || ntail > 0)
2125 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2127 if (skb_linearize(pkt))
2129 __skb_put(pkt, tail_pad);
2136 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2137 * @bus: brcmf_sdio structure pointer
2138 * @pktq: packet list pointer
2139 * @chan: virtual channel to transmit the packet
2141 * Processes to be applied to the packet
2142 * - Align data buffer pointer
2143 * - Align data buffer length
2145 * Return: negative value if there is error
2148 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2151 u16 head_pad, total_len;
2152 struct sk_buff *pkt_next;
2155 struct brcmf_sdio_hdrinfo hd_info = {0};
2157 txseq = bus->tx_seq;
2159 skb_queue_walk(pktq, pkt_next) {
2160 /* alignment packet inserted in previous
2161 * loop cycle can be skipped as it is
2162 * already properly aligned and does not
2163 * need an sdpcm header.
2165 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2168 /* align packet data pointer */
2169 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2172 head_pad = (u16)ret;
2174 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
2176 total_len += pkt_next->len;
2178 hd_info.len = pkt_next->len;
2179 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2180 if (bus->txglom && pktq->qlen > 1) {
2181 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2182 pkt_next, total_len);
2185 hd_info.tail_pad = (u16)ret;
2186 total_len += (u16)ret;
2189 hd_info.channel = chan;
2190 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2191 hd_info.seq_num = txseq++;
2193 /* Now fill the header */
2194 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2196 if (BRCMF_BYTES_ON() &&
2197 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2198 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2199 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
2201 else if (BRCMF_HDRS_ON())
2202 brcmf_dbg_hex_dump(true, pkt_next->data,
2203 head_pad + bus->tx_hdrlen,
2206 /* Hardware length tag of the first packet should be total
2207 * length of the chain (including padding)
2210 brcmf_sdio_update_hwhdr(__skb_peek(pktq)->data, total_len);
2215 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2216 * @bus: brcmf_sdio structure pointer
2217 * @pktq: packet list pointer
2219 * Processes to be applied to the packet
2220 * - Remove head padding
2221 * - Remove tail padding
2224 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2229 u16 dummy_flags, chop_len;
2230 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2232 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2233 dummy_flags = *(u16 *)(pkt_next->cb);
2234 if (dummy_flags & ALIGN_SKB_FLAG) {
2235 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2237 pkt_prev = pkt_next->prev;
2238 skb_put(pkt_prev, chop_len);
2240 __skb_unlink(pkt_next, pktq);
2241 brcmu_pkt_buf_free_skb(pkt_next);
2243 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2244 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2245 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2246 SDPCM_DOFFSET_SHIFT;
2247 skb_pull(pkt_next, dat_offset);
2249 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2250 skb_trim(pkt_next, pkt_next->len - tail_pad);
2256 /* Writes a HW/SW header into the packet and sends it. */
2257 /* Assumes: (a) header space already there, (b) caller holds lock */
2258 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2262 struct sk_buff *pkt_next, *tmp;
2264 brcmf_dbg(TRACE, "Enter\n");
2266 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2270 sdio_claim_host(bus->sdiodev->func1);
2271 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2272 bus->sdcnt.f2txdata++;
2275 brcmf_sdio_txfail(bus);
2277 sdio_release_host(bus->sdiodev->func1);
2280 brcmf_sdio_txpkt_postp(bus, pktq);
2282 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2283 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2284 __skb_unlink(pkt_next, pktq);
2285 brcmf_proto_bcdc_txcomplete(bus->sdiodev->dev, pkt_next,
2291 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2293 struct sk_buff *pkt;
2294 struct sk_buff_head pktq;
2295 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus);
2297 int ret = 0, prec_out, i;
2299 u8 tx_prec_map, pkt_num;
2301 brcmf_dbg(TRACE, "Enter\n");
2303 tx_prec_map = ~bus->flowcontrol;
2305 /* Send frames until the limit or some other event */
2306 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2309 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2310 bus->sdiodev->txglomsz);
2311 pkt_num = min_t(u32, pkt_num,
2312 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2313 __skb_queue_head_init(&pktq);
2314 spin_lock_bh(&bus->txq_lock);
2315 for (i = 0; i < pkt_num; i++) {
2316 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2320 __skb_queue_tail(&pktq, pkt);
2322 spin_unlock_bh(&bus->txq_lock);
2326 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2330 /* In poll mode, need to check for other events */
2332 /* Check device status, signal pending interrupt */
2333 sdio_claim_host(bus->sdiodev->func1);
2334 intstatus = brcmf_sdiod_readl(bus->sdiodev,
2335 intstat_addr, &ret);
2336 sdio_release_host(bus->sdiodev->func1);
2338 bus->sdcnt.f2txdata++;
2341 if (intstatus & bus->hostintmask)
2342 atomic_set(&bus->ipend, 1);
2346 /* Deflow-control stack if needed */
2347 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
2348 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2350 brcmf_proto_bcdc_txflowblock(bus->sdiodev->dev, false);
2356 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
2361 struct brcmf_sdio_hdrinfo hd_info = {0};
2364 brcmf_dbg(SDIO, "Enter\n");
2366 /* Back the pointer to make room for bus header */
2367 frame -= bus->tx_hdrlen;
2368 len += bus->tx_hdrlen;
2370 /* Add alignment padding (optional for ctl frames) */
2371 doff = ((unsigned long)frame % bus->head_align);
2375 memset(frame + bus->tx_hdrlen, 0, doff);
2378 /* Round send length to next SDIO block */
2380 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2381 pad = bus->blocksize - (len % bus->blocksize);
2382 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2384 } else if (len % bus->head_align) {
2385 pad = bus->head_align - (len % bus->head_align);
2389 hd_info.len = len - pad;
2390 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2391 hd_info.dat_offset = doff + bus->tx_hdrlen;
2392 hd_info.seq_num = bus->tx_seq;
2393 hd_info.lastfrm = true;
2394 hd_info.tail_pad = pad;
2395 brcmf_sdio_hdpack(bus, frame, &hd_info);
2398 brcmf_sdio_update_hwhdr(frame, len);
2400 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2401 frame, len, "Tx Frame:\n");
2402 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2404 frame, min_t(u16, len, 16), "TxHdr:\n");
2407 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2410 brcmf_sdio_txfail(bus);
2412 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2413 } while (ret < 0 && retries++ < TXRETRIES);
2418 static bool brcmf_chip_is_ulp(struct brcmf_chip *ci)
2420 if (ci->chip == CY_CC_43012_CHIP_ID)
2426 static void brcmf_sdio_bus_stop(struct device *dev)
2428 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2429 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2430 struct brcmf_sdio *bus = sdiodev->bus;
2431 struct brcmf_core *core = bus->sdio_core;
2432 u32 local_hostintmask;
2436 brcmf_dbg(TRACE, "Enter\n");
2438 if (bus->watchdog_tsk) {
2439 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2440 kthread_stop(bus->watchdog_tsk);
2441 bus->watchdog_tsk = NULL;
2444 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
2445 sdio_claim_host(sdiodev->func1);
2447 /* Enable clock for device interrupts */
2448 brcmf_sdio_bus_sleep(bus, false, false);
2450 /* Disable and clear interrupts at the chip level also */
2451 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(hostintmask),
2454 local_hostintmask = bus->hostintmask;
2455 bus->hostintmask = 0;
2457 /* Force backplane clocks to assure F2 interrupt propagates */
2458 saveclk = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2462 bpreq |= brcmf_chip_is_ulp(bus->ci) ?
2463 SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT;
2464 brcmf_sdiod_writeb(sdiodev,
2465 SBSDIO_FUNC1_CHIPCLKCSR,
2469 brcmf_err("Failed to force clock for F2: err %d\n",
2472 /* Turn off the bus (F2), free any pending packets */
2473 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2474 sdio_disable_func(sdiodev->func2);
2476 /* Clear any pending interrupts now that F2 is disabled */
2477 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(intstatus),
2478 local_hostintmask, NULL);
2480 sdio_release_host(sdiodev->func1);
2482 /* Clear the data packet queues */
2483 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2485 /* Clear any held glomming stuff */
2486 brcmu_pkt_buf_free_skb(bus->glomd);
2487 brcmf_sdio_free_glom(bus);
2489 /* Clear rx control and wake any waiters */
2490 spin_lock_bh(&bus->rxctl_lock);
2492 spin_unlock_bh(&bus->rxctl_lock);
2493 brcmf_sdio_dcmd_resp_wake(bus);
2495 /* Reset some F2 state stuff */
2496 bus->rxskip = false;
2497 bus->tx_seq = bus->rx_seq = 0;
2500 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2502 struct brcmf_sdio_dev *sdiodev;
2503 unsigned long flags;
2505 sdiodev = bus->sdiodev;
2506 if (sdiodev->oob_irq_requested) {
2507 spin_lock_irqsave(&sdiodev->irq_en_lock, flags);
2508 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2509 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr);
2510 sdiodev->irq_en = true;
2512 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags);
2516 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2518 struct brcmf_core *core = bus->sdio_core;
2523 addr = core->base + SD_REG(intstatus);
2525 val = brcmf_sdiod_readl(bus->sdiodev, addr, &ret);
2526 bus->sdcnt.f1regdata++;
2530 val &= bus->hostintmask;
2531 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2533 /* Clear interrupts */
2535 brcmf_sdiod_writel(bus->sdiodev, addr, val, &ret);
2536 bus->sdcnt.f1regdata++;
2537 atomic_or(val, &bus->intstatus);
2543 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2545 struct brcmf_sdio_dev *sdiod = bus->sdiodev;
2547 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus);
2548 unsigned long intstatus;
2549 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2550 uint framecnt; /* Temporary counter of tx/rx frames */
2553 brcmf_dbg(SDIO, "Enter\n");
2555 sdio_claim_host(bus->sdiodev->func1);
2557 /* If waiting for HTAVAIL, check status */
2558 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2559 u8 clkctl, devctl = 0;
2562 /* Check for inconsistent device control */
2563 devctl = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2567 /* Read CSR, if clock on switch to AVAIL, else ignore */
2568 clkctl = brcmf_sdiod_readb(bus->sdiodev,
2569 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2571 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2574 if (SBSDIO_HTAV(clkctl)) {
2575 devctl = brcmf_sdiod_readb(bus->sdiodev,
2576 SBSDIO_DEVICE_CTL, &err);
2577 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2578 brcmf_sdiod_writeb(bus->sdiodev,
2579 SBSDIO_DEVICE_CTL, devctl, &err);
2580 bus->clkstate = CLK_AVAIL;
2584 /* Make sure backplane clock is on */
2585 brcmf_sdio_bus_sleep(bus, false, true);
2587 /* Pending interrupt indicates new device status */
2588 if (atomic_read(&bus->ipend) > 0) {
2589 atomic_set(&bus->ipend, 0);
2590 err = brcmf_sdio_intr_rstatus(bus);
2593 /* Start with leftover status bits */
2594 intstatus = atomic_xchg(&bus->intstatus, 0);
2596 /* Handle flow-control change: read new state in case our ack
2597 * crossed another change interrupt. If change still set, assume
2598 * FC ON for safety, let next loop through do the debounce.
2600 if (intstatus & I_HMB_FC_CHANGE) {
2601 intstatus &= ~I_HMB_FC_CHANGE;
2602 brcmf_sdiod_writel(sdiod, intstat_addr, I_HMB_FC_CHANGE, &err);
2604 newstatus = brcmf_sdiod_readl(sdiod, intstat_addr, &err);
2606 bus->sdcnt.f1regdata += 2;
2607 atomic_set(&bus->fcstate,
2608 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2609 intstatus |= (newstatus & bus->hostintmask);
2612 /* Handle host mailbox indication */
2613 if (intstatus & I_HMB_HOST_INT) {
2614 intstatus &= ~I_HMB_HOST_INT;
2615 intstatus |= brcmf_sdio_hostmail(bus);
2618 sdio_release_host(bus->sdiodev->func1);
2620 /* Generally don't ask for these, can get CRC errors... */
2621 if (intstatus & I_WR_OOSYNC) {
2622 brcmf_err("Dongle reports WR_OOSYNC\n");
2623 intstatus &= ~I_WR_OOSYNC;
2626 if (intstatus & I_RD_OOSYNC) {
2627 brcmf_err("Dongle reports RD_OOSYNC\n");
2628 intstatus &= ~I_RD_OOSYNC;
2631 if (intstatus & I_SBINT) {
2632 brcmf_err("Dongle reports SBINT\n");
2633 intstatus &= ~I_SBINT;
2636 /* Would be active due to wake-wlan in gSPI */
2637 if (intstatus & I_CHIPACTIVE) {
2638 brcmf_dbg(SDIO, "Dongle reports CHIPACTIVE\n");
2639 intstatus &= ~I_CHIPACTIVE;
2642 /* Ignore frame indications if rxskip is set */
2644 intstatus &= ~I_HMB_FRAME_IND;
2646 /* On frame indication, read available frames */
2647 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
2648 brcmf_sdio_readframes(bus, bus->rxbound);
2649 if (!bus->rxpending)
2650 intstatus &= ~I_HMB_FRAME_IND;
2653 /* Keep still-pending events for next scheduling */
2655 atomic_or(intstatus, &bus->intstatus);
2657 brcmf_sdio_clrintr(bus);
2659 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
2661 sdio_claim_host(bus->sdiodev->func1);
2662 if (bus->ctrl_frame_stat) {
2663 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
2664 bus->ctrl_frame_len);
2665 bus->ctrl_frame_err = err;
2667 bus->ctrl_frame_stat = false;
2669 sdio_release_host(bus->sdiodev->func1);
2670 brcmf_sdio_wait_event_wakeup(bus);
2672 /* Send queued frames (limit 1 if rx may still be pending) */
2673 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2674 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
2676 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2678 brcmf_sdio_sendfromq(bus, framecnt);
2681 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
2682 brcmf_err("failed backplane access over SDIO, halting operation\n");
2683 atomic_set(&bus->intstatus, 0);
2684 if (bus->ctrl_frame_stat) {
2685 sdio_claim_host(bus->sdiodev->func1);
2686 if (bus->ctrl_frame_stat) {
2687 bus->ctrl_frame_err = -ENODEV;
2689 bus->ctrl_frame_stat = false;
2690 brcmf_sdio_wait_event_wakeup(bus);
2692 sdio_release_host(bus->sdiodev->func1);
2694 } else if (atomic_read(&bus->intstatus) ||
2695 atomic_read(&bus->ipend) > 0 ||
2696 (!atomic_read(&bus->fcstate) &&
2697 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2699 bus->dpc_triggered = true;
2703 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2705 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2706 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2707 struct brcmf_sdio *bus = sdiodev->bus;
2712 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
2715 int eprec = -1; /* precedence to evict from */
2717 /* Fast case, precedence queue is not full and we are also not
2718 * exceeding total queue length
2720 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
2721 brcmu_pktq_penq(q, prec, pkt);
2725 /* Determine precedence from which to evict packet, if any */
2726 if (pktq_pfull(q, prec)) {
2728 } else if (pktq_full(q)) {
2729 p = brcmu_pktq_peek_tail(q, &eprec);
2734 /* Evict if needed */
2736 /* Detect queueing to unconfigured precedence */
2738 return false; /* refuse newer (incoming) packet */
2739 /* Evict packet according to discard policy */
2740 p = brcmu_pktq_pdeq_tail(q, eprec);
2742 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2743 brcmu_pkt_buf_free_skb(p);
2747 p = brcmu_pktq_penq(q, prec, pkt);
2749 brcmf_err("brcmu_pktq_penq() failed\n");
2754 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2758 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2759 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2760 struct brcmf_sdio *bus = sdiodev->bus;
2762 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
2763 if (sdiodev->state != BRCMF_SDIOD_DATA)
2766 /* Add space for the header */
2767 skb_push(pkt, bus->tx_hdrlen);
2768 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2770 prec = prio2prec((pkt->priority & PRIOMASK));
2772 /* Check for existing queue, current flow-control,
2773 pending event, or pending clock */
2774 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2775 bus->sdcnt.fcqueued++;
2777 /* Priority based enq */
2778 spin_lock_bh(&bus->txq_lock);
2779 /* reset bus_flags in packet cb */
2780 *(u16 *)(pkt->cb) = 0;
2781 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
2782 skb_pull(pkt, bus->tx_hdrlen);
2783 brcmf_err("out of bus->txq !!!\n");
2789 if (pktq_len(&bus->txq) >= TXHI) {
2791 brcmf_proto_bcdc_txflowblock(dev, true);
2793 spin_unlock_bh(&bus->txq_lock);
2796 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2797 qcount[prec] = pktq_plen(&bus->txq, prec);
2800 brcmf_sdio_trigger_dpc(bus);
2805 #define CONSOLE_LINE_MAX 192
2807 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2809 struct brcmf_console *c = &bus->console;
2810 u8 line[CONSOLE_LINE_MAX], ch;
2814 /* Don't do anything until FWREADY updates console address */
2815 if (bus->console_addr == 0)
2818 /* Read console log struct */
2819 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2820 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2825 /* Allocate console buffer (one time only) */
2826 if (c->buf == NULL) {
2827 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2828 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2833 idx = le32_to_cpu(c->log_le.idx);
2835 /* Protect against corrupt value */
2836 if (idx > c->bufsize)
2839 /* Skip reading the console buffer if the index pointer
2844 /* Read the console buffer */
2845 addr = le32_to_cpu(c->log_le.buf);
2846 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2850 while (c->last != idx) {
2851 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2852 if (c->last == idx) {
2853 /* This would output a partial line.
2855 * the buffer pointer and output this
2856 * line next time around.
2861 c->last = c->bufsize - n;
2864 ch = c->buf[c->last];
2865 c->last = (c->last + 1) % c->bufsize;
2872 if (line[n - 1] == '\r')
2875 pr_debug("CONSOLE: %s\n", line);
2885 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2887 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2888 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2889 struct brcmf_sdio *bus = sdiodev->bus;
2892 brcmf_dbg(TRACE, "Enter\n");
2893 if (sdiodev->state != BRCMF_SDIOD_DATA)
2897 bus->ctrl_frame_buf = msg;
2898 bus->ctrl_frame_len = msglen;
2900 bus->ctrl_frame_stat = true;
2902 brcmf_sdio_trigger_dpc(bus);
2903 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
2906 if (bus->ctrl_frame_stat) {
2907 sdio_claim_host(bus->sdiodev->func1);
2908 if (bus->ctrl_frame_stat) {
2909 brcmf_dbg(SDIO, "ctrl_frame timeout\n");
2910 bus->ctrl_frame_stat = false;
2913 sdio_release_host(bus->sdiodev->func1);
2916 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
2917 bus->ctrl_frame_err);
2919 ret = bus->ctrl_frame_err;
2923 bus->sdcnt.tx_ctlerrs++;
2925 bus->sdcnt.tx_ctlpkts++;
2931 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
2932 struct sdpcm_shared *sh)
2934 u32 addr, console_ptr, console_size, console_index;
2935 char *conbuf = NULL;
2939 /* obtain console information from device memory */
2940 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2941 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2942 (u8 *)&sh_val, sizeof(u32));
2945 console_ptr = le32_to_cpu(sh_val);
2947 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
2948 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2949 (u8 *)&sh_val, sizeof(u32));
2952 console_size = le32_to_cpu(sh_val);
2954 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
2955 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2956 (u8 *)&sh_val, sizeof(u32));
2959 console_index = le32_to_cpu(sh_val);
2961 /* allocate buffer for console data */
2962 if (console_size <= CONSOLE_BUFFER_MAX)
2963 conbuf = vzalloc(console_size+1);
2968 /* obtain the console data from device */
2969 conbuf[console_size] = '\0';
2970 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
2975 rv = seq_write(seq, conbuf + console_index,
2976 console_size - console_index);
2980 if (console_index > 0)
2981 rv = seq_write(seq, conbuf, console_index - 1);
2988 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
2989 struct sdpcm_shared *sh)
2992 struct brcmf_trap_info tr;
2994 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
2995 brcmf_dbg(INFO, "no trap in firmware\n");
2999 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
3000 sizeof(struct brcmf_trap_info));
3006 "dongle trap info: type 0x%x @ epc 0x%08x\n"
3007 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
3008 " lr 0x%08x pc 0x%08x offset 0x%x\n"
3009 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
3010 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
3011 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
3012 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
3013 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
3014 le32_to_cpu(tr.pc), sh->trap_addr,
3015 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
3016 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
3017 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
3018 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
3020 pr_debug("dongle trap info: type 0x%x @ epc 0x%08x\n"
3021 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
3022 " lr 0x%08x pc 0x%08x offset 0x%x\n"
3023 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
3024 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
3025 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
3026 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
3027 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
3028 le32_to_cpu(tr.pc), sh->trap_addr,
3029 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
3030 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
3031 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
3032 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
3036 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
3037 struct sdpcm_shared *sh)
3040 char file[80] = "?";
3041 char expr[80] = "<???>";
3043 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
3044 brcmf_dbg(INFO, "firmware not built with -assert\n");
3046 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
3047 brcmf_dbg(INFO, "no assert in dongle\n");
3051 sdio_claim_host(bus->sdiodev->func1);
3052 if (sh->assert_file_addr != 0) {
3053 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3054 sh->assert_file_addr, (u8 *)file, 80);
3058 if (sh->assert_exp_addr != 0) {
3059 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3060 sh->assert_exp_addr, (u8 *)expr, 80);
3064 sdio_release_host(bus->sdiodev->func1);
3066 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
3067 file, sh->assert_line, expr);
3071 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3074 struct sdpcm_shared sh;
3076 error = brcmf_sdio_readshared(bus, &sh);
3081 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3082 brcmf_dbg(INFO, "firmware not built with -assert\n");
3083 else if (sh.flags & SDPCM_SHARED_ASSERT)
3084 brcmf_err("assertion in dongle\n");
3086 if (sh.flags & SDPCM_SHARED_TRAP) {
3087 brcmf_err("firmware trap in dongle\n");
3088 brcmf_sdio_trap_info(NULL, bus, &sh);
3094 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
3097 struct sdpcm_shared sh;
3099 error = brcmf_sdio_readshared(bus, &sh);
3103 error = brcmf_sdio_assert_info(seq, bus, &sh);
3107 error = brcmf_sdio_trap_info(seq, bus, &sh);
3111 error = brcmf_sdio_dump_console(seq, bus, &sh);
3117 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
3119 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3120 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
3122 return brcmf_sdio_died_dump(seq, bus);
3125 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
3127 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3128 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3129 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
3132 "intrcount: %u\nlastintrs: %u\n"
3133 "pollcnt: %u\nregfails: %u\n"
3134 "tx_sderrs: %u\nfcqueued: %u\n"
3135 "rxrtx: %u\nrx_toolong: %u\n"
3136 "rxc_errors: %u\nrx_hdrfail: %u\n"
3137 "rx_badhdr: %u\nrx_badseq: %u\n"
3138 "fc_rcvd: %u\nfc_xoff: %u\n"
3139 "fc_xon: %u\nrxglomfail: %u\n"
3140 "rxglomframes: %u\nrxglompkts: %u\n"
3141 "f2rxhdrs: %u\nf2rxdata: %u\n"
3142 "f2txdata: %u\nf1regdata: %u\n"
3143 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3144 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3145 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3146 sdcnt->intrcount, sdcnt->lastintrs,
3147 sdcnt->pollcnt, sdcnt->regfails,
3148 sdcnt->tx_sderrs, sdcnt->fcqueued,
3149 sdcnt->rxrtx, sdcnt->rx_toolong,
3150 sdcnt->rxc_errors, sdcnt->rx_hdrfail,
3151 sdcnt->rx_badhdr, sdcnt->rx_badseq,
3152 sdcnt->fc_rcvd, sdcnt->fc_xoff,
3153 sdcnt->fc_xon, sdcnt->rxglomfail,
3154 sdcnt->rxglomframes, sdcnt->rxglompkts,
3155 sdcnt->f2rxhdrs, sdcnt->f2rxdata,
3156 sdcnt->f2txdata, sdcnt->f1regdata,
3157 sdcnt->tickcnt, sdcnt->tx_ctlerrs,
3158 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
3159 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
3164 static void brcmf_sdio_debugfs_create(struct device *dev)
3166 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3167 struct brcmf_pub *drvr = bus_if->drvr;
3168 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3169 struct brcmf_sdio *bus = sdiodev->bus;
3170 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3172 if (IS_ERR_OR_NULL(dentry))
3175 bus->console_interval = BRCMF_CONSOLE;
3177 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
3178 brcmf_debugfs_add_entry(drvr, "counters",
3179 brcmf_debugfs_sdio_count_read);
3180 debugfs_create_u32("console_interval", 0644, dentry,
3181 &bus->console_interval);
3184 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3189 static void brcmf_sdio_debugfs_create(struct device *dev)
3195 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3201 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3202 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3203 struct brcmf_sdio *bus = sdiodev->bus;
3205 brcmf_dbg(TRACE, "Enter\n");
3206 if (sdiodev->state != BRCMF_SDIOD_DATA)
3209 /* Wait until control frame is available */
3210 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3212 spin_lock_bh(&bus->rxctl_lock);
3214 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3216 buf = bus->rxctl_orig;
3217 bus->rxctl_orig = NULL;
3219 spin_unlock_bh(&bus->rxctl_lock);
3223 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3225 } else if (timeleft == 0) {
3226 brcmf_err("resumed on timeout\n");
3227 brcmf_sdio_checkdied(bus);
3228 } else if (pending) {
3229 brcmf_dbg(CTL, "cancelled\n");
3230 return -ERESTARTSYS;
3232 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3233 brcmf_sdio_checkdied(bus);
3237 bus->sdcnt.rx_ctlpkts++;
3239 bus->sdcnt.rx_ctlerrs++;
3241 return rxlen ? (int)rxlen : -ETIMEDOUT;
3246 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3247 u8 *ram_data, uint ram_sz)
3256 /* read back and verify */
3257 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3259 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3260 /* do not proceed while no memory but */
3266 while (offset < ram_sz) {
3267 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3269 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3271 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3275 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3276 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3291 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3292 u8 *ram_data, uint ram_sz)
3298 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3299 const struct firmware *fw)
3303 brcmf_dbg(TRACE, "Enter\n");
3305 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3306 (u8 *)fw->data, fw->size);
3308 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3309 err, (int)fw->size, bus->ci->rambase);
3310 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3311 (u8 *)fw->data, fw->size))
3317 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3318 void *vars, u32 varsz)
3323 brcmf_dbg(TRACE, "Enter\n");
3325 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3326 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3328 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3329 err, varsz, address);
3330 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3336 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
3337 const struct firmware *fw,
3338 void *nvram, u32 nvlen)
3343 sdio_claim_host(bus->sdiodev->func1);
3344 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3346 rstvec = get_unaligned_le32(fw->data);
3347 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3349 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3350 release_firmware(fw);
3352 brcmf_err("dongle image file download failed\n");
3353 brcmf_fw_nvram_free(nvram);
3357 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
3358 brcmf_fw_nvram_free(nvram);
3360 brcmf_err("dongle nvram file download failed\n");
3364 /* Take arm out of reset */
3365 if (!brcmf_chip_set_active(bus->ci, rstvec)) {
3366 brcmf_err("error getting out of ARM core reset\n");
3371 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3372 sdio_release_host(bus->sdiodev->func1);
3376 static bool brcmf_sdio_aos_no_decode(struct brcmf_sdio *bus)
3378 if (bus->ci->chip == CY_CC_43012_CHIP_ID)
3384 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3392 brcmf_dbg(TRACE, "Enter\n");
3394 if (brcmf_chip_is_ulp(bus->ci)) {
3395 wakeupctrl = SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT;
3396 chipclkcsr = SBSDIO_HT_AVAIL_REQ;
3398 wakeupctrl = SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3399 chipclkcsr = SBSDIO_FORCE_HT;
3402 if (brcmf_sdio_aos_no_decode(bus)) {
3403 cardcap = SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC;
3405 cardcap = (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3406 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT);
3409 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3411 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3414 val |= 1 << wakeupctrl;
3415 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3417 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3421 /* Add CMD14 Support */
3422 brcmf_sdiod_func0_wb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3426 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3430 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3433 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3438 bus->sr_enabled = true;
3439 brcmf_dbg(INFO, "SR enabled\n");
3442 /* enable KSO bit */
3443 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3445 struct brcmf_core *core = bus->sdio_core;
3449 brcmf_dbg(TRACE, "Enter\n");
3451 /* KSO bit added in SDIO core rev 12 */
3455 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3457 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3461 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3462 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3463 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3464 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3467 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3476 static int brcmf_sdio_bus_preinit(struct device *dev)
3478 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3479 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3480 struct brcmf_sdio *bus = sdiodev->bus;
3481 struct brcmf_core *core = bus->sdio_core;
3485 /* maxctl provided by common layer */
3486 if (WARN_ON(!bus_if->maxctl))
3489 /* Allocate control receive buffer */
3490 bus_if->maxctl += bus->roundup;
3491 value = roundup((bus_if->maxctl + SDPCM_HDRLEN), ALIGNMENT);
3492 value += bus->head_align;
3493 bus->rxbuf = kmalloc(value, GFP_ATOMIC);
3495 bus->rxblen = value;
3497 /* the commands below use the terms tx and rx from
3498 * a device perspective, ie. bus:txglom affects the
3499 * bus transfers from device to host.
3501 if (core->rev < 12) {
3502 /* for sdio core rev < 12, disable txgloming */
3504 err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
3507 /* otherwise, set txglomalign */
3508 value = sdiodev->settings->bus.sdio.sd_sgentry_align;
3509 /* SDIO ADMA requires at least 32 bit alignment */
3510 value = max_t(u32, value, ALIGNMENT);
3511 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3518 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3519 if (sdiodev->sg_support) {
3520 bus->txglom = false;
3522 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3523 &value, sizeof(u32));
3525 /* bus:rxglom is allowed to fail */
3529 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3532 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3538 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev)
3540 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3541 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3542 struct brcmf_sdio *bus = sdiodev->bus;
3544 return bus->ci->ramsize - bus->ci->srsize;
3547 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data,
3550 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3551 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3552 struct brcmf_sdio *bus = sdiodev->bus;
3558 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase,
3561 address = bus->ci->rambase;
3563 sdio_claim_host(sdiodev->func1);
3564 while (offset < mem_size) {
3565 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK :
3567 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len);
3569 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3579 sdio_release_host(sdiodev->func1);
3583 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
3585 if (!bus->dpc_triggered) {
3586 bus->dpc_triggered = true;
3587 queue_work(bus->brcmf_wq, &bus->datawork);
3591 void brcmf_sdio_isr(struct brcmf_sdio *bus)
3593 brcmf_dbg(TRACE, "Enter\n");
3596 brcmf_err("bus is null pointer, exiting\n");
3600 /* Count the interrupt call */
3601 bus->sdcnt.intrcount++;
3603 atomic_set(&bus->ipend, 1);
3605 if (brcmf_sdio_intr_rstatus(bus)) {
3606 brcmf_err("failed backplane access\n");
3609 /* Disable additional interrupts (is this needed now)? */
3611 brcmf_err("isr w/o interrupt configured!\n");
3613 bus->dpc_triggered = true;
3614 queue_work(bus->brcmf_wq, &bus->datawork);
3617 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3619 brcmf_dbg(TIMER, "Enter\n");
3621 /* Poll period: check device if appropriate. */
3622 if (!bus->sr_enabled &&
3623 bus->poll && (++bus->polltick >= bus->pollrate)) {
3626 /* Reset poll tick */
3629 /* Check device if no interrupts */
3631 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3633 if (!bus->dpc_triggered) {
3636 sdio_claim_host(bus->sdiodev->func1);
3637 devpend = brcmf_sdiod_func0_rb(bus->sdiodev,
3638 SDIO_CCCR_INTx, NULL);
3639 sdio_release_host(bus->sdiodev->func1);
3640 intstatus = devpend & (INTR_STATUS_FUNC1 |
3644 /* If there is something, make like the ISR and
3647 bus->sdcnt.pollcnt++;
3648 atomic_set(&bus->ipend, 1);
3650 bus->dpc_triggered = true;
3651 queue_work(bus->brcmf_wq, &bus->datawork);
3655 /* Update interrupt tracking */
3656 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3659 /* Poll for console output periodically */
3660 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() &&
3661 bus->console_interval != 0) {
3662 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL);
3663 if (bus->console.count >= bus->console_interval) {
3664 bus->console.count -= bus->console_interval;
3665 sdio_claim_host(bus->sdiodev->func1);
3666 /* Make sure backplane clock is on */
3667 brcmf_sdio_bus_sleep(bus, false, false);
3668 if (brcmf_sdio_readconsole(bus) < 0)
3670 bus->console_interval = 0;
3671 sdio_release_host(bus->sdiodev->func1);
3676 /* On idle timeout clear activity flag and/or turn off clock */
3677 if (!bus->dpc_triggered) {
3679 if ((!bus->dpc_running) && (bus->idletime > 0) &&
3680 (bus->clkstate == CLK_AVAIL)) {
3682 if (bus->idlecount > bus->idletime) {
3683 brcmf_dbg(SDIO, "idle\n");
3684 sdio_claim_host(bus->sdiodev->func1);
3685 brcmf_sdio_wd_timer(bus, false);
3687 brcmf_sdio_bus_sleep(bus, true, false);
3688 sdio_release_host(bus->sdiodev->func1);
3698 static void brcmf_sdio_dataworker(struct work_struct *work)
3700 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3703 bus->dpc_running = true;
3705 while (READ_ONCE(bus->dpc_triggered)) {
3706 bus->dpc_triggered = false;
3707 brcmf_sdio_dpc(bus);
3710 bus->dpc_running = false;
3711 if (brcmf_sdiod_freezing(bus->sdiodev)) {
3712 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
3713 brcmf_sdiod_try_freeze(bus->sdiodev);
3714 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3719 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3720 struct brcmf_chip *ci, u32 drivestrength)
3722 const struct sdiod_drive_str *str_tab = NULL;
3726 u32 drivestrength_sel = 0;
3730 if (!(ci->cc_caps & CC_CAP_PMU))
3733 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3734 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
3735 str_tab = sdiod_drvstr_tab1_1v8;
3736 str_mask = 0x00003800;
3739 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
3740 str_tab = sdiod_drvstr_tab6_1v8;
3741 str_mask = 0x00001800;
3744 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
3745 /* note: 43143 does not support tristate */
3746 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3747 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3748 str_tab = sdiod_drvstr_tab2_3v3;
3749 str_mask = 0x00000007;
3752 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3753 ci->name, drivestrength);
3755 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
3756 str_tab = sdiod_drive_strength_tab5_1v8;
3757 str_mask = 0x00003800;
3761 brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n",
3762 ci->name, ci->chiprev, ci->pmurev);
3766 if (str_tab != NULL) {
3767 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci);
3769 for (i = 0; str_tab[i].strength != 0; i++) {
3770 if (drivestrength >= str_tab[i].strength) {
3771 drivestrength_sel = str_tab[i].sel;
3775 addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
3776 brcmf_sdiod_writel(sdiodev, addr, 1, NULL);
3777 cc_data_temp = brcmf_sdiod_readl(sdiodev, addr, NULL);
3778 cc_data_temp &= ~str_mask;
3779 drivestrength_sel <<= str_shift;
3780 cc_data_temp |= drivestrength_sel;
3781 brcmf_sdiod_writel(sdiodev, addr, cc_data_temp, NULL);
3783 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3784 str_tab[i].strength, drivestrength, cc_data_temp);
3788 static int brcmf_sdio_buscoreprep(void *ctx)
3790 struct brcmf_sdio_dev *sdiodev = ctx;
3794 /* Try forcing SDIO core to do ALPAvail request only */
3795 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3796 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3798 brcmf_err("error writing for HT off\n");
3802 /* If register supported, wait for ALPAvail and then force ALP */
3803 /* This may take up to 15 milliseconds */
3804 clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3806 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3807 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3812 SPINWAIT(((clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3814 !SBSDIO_ALPAV(clkval)),
3815 PMU_MAX_TRANSITION_DLY);
3817 if (!SBSDIO_ALPAV(clkval)) {
3818 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3823 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3824 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3827 /* Also, disable the extra SDIO pull-ups */
3828 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3833 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
3836 struct brcmf_sdio_dev *sdiodev = ctx;
3837 struct brcmf_core *core = sdiodev->bus->sdio_core;
3840 /* clear all interrupts */
3841 reg_addr = core->base + SD_REG(intstatus);
3842 brcmf_sdiod_writel(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3845 /* Write reset vector to address 0 */
3846 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3850 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3852 struct brcmf_sdio_dev *sdiodev = ctx;
3855 val = brcmf_sdiod_readl(sdiodev, addr, NULL);
3858 * this is a bit of special handling if reading the chipcommon chipid
3859 * register. The 4339 is a next-gen of the 4335. It uses the same
3860 * SDIO device id as 4335 and the chipid register returns 4335 as well.
3861 * It can be identified as 4339 by looking at the chip revision. It
3862 * is corrected here so the chip.c module has the right info.
3864 if (addr == CORE_CC_REG(SI_ENUM_BASE, chipid) &&
3865 (sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4339 ||
3866 sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4335_4339)) {
3867 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3869 val &= ~CID_ID_MASK;
3870 val |= BRCM_CC_4339_CHIP_ID;
3877 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3879 struct brcmf_sdio_dev *sdiodev = ctx;
3881 brcmf_sdiod_writel(sdiodev, addr, val, NULL);
3884 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3885 .prepare = brcmf_sdio_buscoreprep,
3886 .activate = brcmf_sdio_buscore_activate,
3887 .read32 = brcmf_sdio_buscore_read32,
3888 .write32 = brcmf_sdio_buscore_write32,
3892 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3894 struct brcmf_sdio_dev *sdiodev;
3901 sdiodev = bus->sdiodev;
3902 sdio_claim_host(sdiodev->func1);
3904 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3905 brcmf_sdiod_readl(sdiodev, SI_ENUM_BASE, NULL));
3908 * Force PLL off until brcmf_chip_attach()
3909 * programs PLL control regs
3912 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, BRCMF_INIT_CLKCTL1,
3915 clkctl = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3918 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3919 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3920 err, BRCMF_INIT_CLKCTL1, clkctl);
3924 bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops);
3925 if (IS_ERR(bus->ci)) {
3926 brcmf_err("brcmf_chip_attach failed!\n");
3931 /* Pick up the SDIO core info struct from chip.c */
3932 bus->sdio_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
3933 if (!bus->sdio_core)
3936 /* Pick up the CHIPCOMMON core info struct, for bulk IO in bcmsdh.c */
3937 sdiodev->cc_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_CHIPCOMMON);
3938 if (!sdiodev->cc_core)
3941 sdiodev->settings = brcmf_get_module_param(sdiodev->dev,
3945 if (!sdiodev->settings) {
3946 brcmf_err("Failed to get device parameters\n");
3949 /* platform specific configuration:
3950 * alignments must be at least 4 bytes for ADMA
3952 bus->head_align = ALIGNMENT;
3953 bus->sgentry_align = ALIGNMENT;
3954 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT)
3955 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align;
3956 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT)
3957 bus->sgentry_align =
3958 sdiodev->settings->bus.sdio.sd_sgentry_align;
3960 /* allocate scatter-gather table. sg support
3961 * will be disabled upon allocation failure.
3963 brcmf_sdiod_sgtable_alloc(sdiodev);
3965 #ifdef CONFIG_PM_SLEEP
3966 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ
3967 * is true or when platform data OOB irq is true).
3969 if ((sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_KEEP_POWER) &&
3970 ((sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_WAKE_SDIO_IRQ) ||
3971 (sdiodev->settings->bus.sdio.oob_irq_supported)))
3972 sdiodev->bus_if->wowl_supported = true;
3975 if (brcmf_sdio_kso_init(bus)) {
3976 brcmf_err("error enabling KSO\n");
3980 if (sdiodev->settings->bus.sdio.drive_strength)
3981 drivestrength = sdiodev->settings->bus.sdio.drive_strength;
3983 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
3984 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength);
3986 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3987 reg_val = brcmf_sdiod_func0_rb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err);
3991 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
3993 brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
3997 /* set PMUControl so a backplane reset does PMU state reload */
3998 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol);
3999 reg_val = brcmf_sdiod_readl(sdiodev, reg_addr, &err);
4003 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
4005 brcmf_sdiod_writel(sdiodev, reg_addr, reg_val, &err);
4009 sdio_release_host(sdiodev->func1);
4011 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
4013 /* allocate header buffer */
4014 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
4017 /* Locate an appropriately-aligned portion of hdrbuf */
4018 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
4021 /* Set the poll and/or interrupt flags */
4030 sdio_release_host(sdiodev->func1);
4035 brcmf_sdio_watchdog_thread(void *data)
4037 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
4040 allow_signal(SIGTERM);
4041 /* Run until signal received */
4042 brcmf_sdiod_freezer_count(bus->sdiodev);
4044 if (kthread_should_stop())
4046 brcmf_sdiod_freezer_uncount(bus->sdiodev);
4047 wait = wait_for_completion_interruptible(&bus->watchdog_wait);
4048 brcmf_sdiod_freezer_count(bus->sdiodev);
4049 brcmf_sdiod_try_freeze(bus->sdiodev);
4051 brcmf_sdio_bus_watchdog(bus);
4052 /* Count the tick for reference */
4053 bus->sdcnt.tickcnt++;
4054 reinit_completion(&bus->watchdog_wait);
4062 brcmf_sdio_watchdog(struct timer_list *t)
4064 struct brcmf_sdio *bus = from_timer(bus, t, timer);
4066 if (bus->watchdog_tsk) {
4067 complete(&bus->watchdog_wait);
4068 /* Reschedule the watchdog */
4070 mod_timer(&bus->timer,
4071 jiffies + BRCMF_WD_POLL);
4076 int brcmf_sdio_get_fwname(struct device *dev, const char *ext, u8 *fw_name)
4078 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
4079 struct brcmf_fw_request *fwreq;
4080 struct brcmf_fw_name fwnames[] = {
4084 fwreq = brcmf_fw_alloc_request(bus_if->chip, bus_if->chiprev,
4086 ARRAY_SIZE(brcmf_sdio_fwnames),
4087 fwnames, ARRAY_SIZE(fwnames));
4095 static const struct brcmf_bus_ops brcmf_sdio_bus_ops = {
4096 .stop = brcmf_sdio_bus_stop,
4097 .preinit = brcmf_sdio_bus_preinit,
4098 .txdata = brcmf_sdio_bus_txdata,
4099 .txctl = brcmf_sdio_bus_txctl,
4100 .rxctl = brcmf_sdio_bus_rxctl,
4101 .gettxq = brcmf_sdio_bus_gettxq,
4102 .wowl_config = brcmf_sdio_wowl_config,
4103 .get_ramsize = brcmf_sdio_bus_get_ramsize,
4104 .get_memdump = brcmf_sdio_bus_get_memdump,
4105 .get_fwname = brcmf_sdio_get_fwname,
4106 .debugfs_create = brcmf_sdio_debugfs_create
4109 #define BRCMF_SDIO_FW_CODE 0
4110 #define BRCMF_SDIO_FW_NVRAM 1
4112 static void brcmf_sdio_firmware_callback(struct device *dev, int err,
4113 struct brcmf_fw_request *fwreq)
4115 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
4116 struct brcmf_sdio_dev *sdiod = bus_if->bus_priv.sdio;
4117 struct brcmf_sdio *bus = sdiod->bus;
4118 struct brcmf_core *core = bus->sdio_core;
4119 const struct firmware *code;
4125 brcmf_dbg(TRACE, "Enter: dev=%s, err=%d\n", dev_name(dev), err);
4130 code = fwreq->items[BRCMF_SDIO_FW_CODE].binary;
4131 nvram = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.data;
4132 nvram_len = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.len;
4135 /* try to download image and nvram to the dongle */
4136 bus->alp_only = true;
4137 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
4140 bus->alp_only = false;
4142 /* Start the watchdog timer */
4143 bus->sdcnt.tickcnt = 0;
4144 brcmf_sdio_wd_timer(bus, true);
4146 sdio_claim_host(sdiod->func1);
4148 /* Make sure backplane clock is on, needed to generate F2 interrupt */
4149 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4150 if (bus->clkstate != CLK_AVAIL)
4153 /* Force clocks on backplane to be sure F2 interrupt propagates */
4154 saveclk = brcmf_sdiod_readb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, &err);
4157 bpreq |= brcmf_chip_is_ulp(bus->ci) ?
4158 SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT;
4159 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR,
4163 brcmf_err("Failed to force clock for F2: err %d\n", err);
4167 /* Enable function 2 (frame transfers) */
4168 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailboxdata),
4169 SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, NULL);
4171 err = sdio_enable_func(sdiod->func2);
4173 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
4175 /* If F2 successfully enabled, set core and enable interrupts */
4177 /* Set up the interrupt mask and enable interrupts */
4178 bus->hostintmask = HOSTINTMASK;
4179 brcmf_sdiod_writel(sdiod, core->base + SD_REG(hostintmask),
4180 bus->hostintmask, NULL);
4182 switch (sdiod->func1->device) {
4183 case SDIO_DEVICE_ID_CYPRESS_4373:
4184 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n",
4185 CY_4373_F2_WATERMARK);
4186 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
4187 CY_4373_F2_WATERMARK, &err);
4188 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL,
4190 devctl |= SBSDIO_DEVCTL_F2WM_ENAB;
4191 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl,
4193 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL,
4194 CY_4373_F2_WATERMARK |
4195 SBSDIO_MESBUSYCTRL_ENAB, &err);
4197 case SDIO_DEVICE_ID_CYPRESS_43012:
4198 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n",
4199 CY_43012_F2_WATERMARK);
4200 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
4201 CY_43012_F2_WATERMARK, &err);
4202 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL,
4204 devctl |= SBSDIO_DEVCTL_F2WM_ENAB;
4205 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl,
4209 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
4210 DEFAULT_F2_WATERMARK, &err);
4214 /* Disable F2 again */
4215 sdio_disable_func(sdiod->func2);
4219 if (brcmf_chip_sr_capable(bus->ci)) {
4220 brcmf_sdio_sr_init(bus);
4222 /* Restore previous clock setting */
4223 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR,
4228 /* Allow full data communication using DPC from now on. */
4229 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
4231 err = brcmf_sdiod_intr_register(sdiod);
4233 brcmf_err("intr register failed:%d\n", err);
4236 /* If we didn't come up, turn off backplane clock */
4238 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4242 sdio_release_host(sdiod->func1);
4244 /* Assign bus interface call back */
4245 sdiod->bus_if->dev = sdiod->dev;
4246 sdiod->bus_if->ops = &brcmf_sdio_bus_ops;
4247 sdiod->bus_if->chip = bus->ci->chip;
4248 sdiod->bus_if->chiprev = bus->ci->chiprev;
4250 /* Attach to the common layer, reserve hdr space */
4251 err = brcmf_attach(sdiod->dev, sdiod->settings);
4253 brcmf_err("brcmf_attach failed\n");
4254 sdio_claim_host(sdiod->func1);
4262 brcmf_sdio_checkdied(bus);
4264 sdio_release_host(sdiod->func1);
4266 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
4267 device_release_driver(&sdiod->func2->dev);
4268 device_release_driver(dev);
4271 static struct brcmf_fw_request *
4272 brcmf_sdio_prepare_fw_request(struct brcmf_sdio *bus)
4274 struct brcmf_fw_request *fwreq;
4275 struct brcmf_fw_name fwnames[] = {
4276 { ".bin", bus->sdiodev->fw_name },
4277 { ".txt", bus->sdiodev->nvram_name },
4280 fwreq = brcmf_fw_alloc_request(bus->ci->chip, bus->ci->chiprev,
4282 ARRAY_SIZE(brcmf_sdio_fwnames),
4283 fwnames, ARRAY_SIZE(fwnames));
4287 fwreq->items[BRCMF_SDIO_FW_CODE].type = BRCMF_FW_TYPE_BINARY;
4288 fwreq->items[BRCMF_SDIO_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM;
4289 fwreq->board_type = bus->sdiodev->settings->board_type;
4294 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4297 struct brcmf_sdio *bus;
4298 struct workqueue_struct *wq;
4299 struct brcmf_fw_request *fwreq;
4301 brcmf_dbg(TRACE, "Enter\n");
4303 /* Allocate private bus interface state */
4304 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4308 bus->sdiodev = sdiodev;
4310 skb_queue_head_init(&bus->glom);
4311 bus->txbound = BRCMF_TXBOUND;
4312 bus->rxbound = BRCMF_RXBOUND;
4313 bus->txminmax = BRCMF_TXMINMAX;
4314 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4316 /* single-threaded workqueue */
4317 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
4318 dev_name(&sdiodev->func1->dev));
4320 brcmf_err("insufficient memory to create txworkqueue\n");
4323 brcmf_sdiod_freezer_count(sdiodev);
4324 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4327 /* attempt to attach to the dongle */
4328 if (!(brcmf_sdio_probe_attach(bus))) {
4329 brcmf_err("brcmf_sdio_probe_attach failed\n");
4333 spin_lock_init(&bus->rxctl_lock);
4334 spin_lock_init(&bus->txq_lock);
4335 init_waitqueue_head(&bus->ctrl_wait);
4336 init_waitqueue_head(&bus->dcmd_resp_wait);
4338 /* Set up the watchdog timer */
4339 timer_setup(&bus->timer, brcmf_sdio_watchdog, 0);
4340 /* Initialize watchdog thread */
4341 init_completion(&bus->watchdog_wait);
4342 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4343 bus, "brcmf_wdog/%s",
4344 dev_name(&sdiodev->func1->dev));
4345 if (IS_ERR(bus->watchdog_tsk)) {
4346 pr_warn("brcmf_watchdog thread failed to start\n");
4347 bus->watchdog_tsk = NULL;
4349 /* Initialize DPC thread */
4350 bus->dpc_triggered = false;
4351 bus->dpc_running = false;
4353 /* default sdio bus header length for tx packet */
4354 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4356 /* Query the F2 block size, set roundup accordingly */
4357 bus->blocksize = bus->sdiodev->func2->cur_blksize;
4358 bus->roundup = min(max_roundup, bus->blocksize);
4360 sdio_claim_host(bus->sdiodev->func1);
4362 /* Disable F2 to clear any intermediate frame state on the dongle */
4363 sdio_disable_func(bus->sdiodev->func2);
4365 bus->rxflow = false;
4367 /* Done with backplane-dependent accesses, can drop clock... */
4368 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4370 sdio_release_host(bus->sdiodev->func1);
4372 /* ...and initialize clock/power states */
4373 bus->clkstate = CLK_SDONLY;
4374 bus->idletime = BRCMF_IDLE_INTERVAL;
4375 bus->idleclock = BRCMF_IDLE_ACTIVE;
4378 bus->sr_enabled = false;
4380 brcmf_dbg(INFO, "completed!!\n");
4382 fwreq = brcmf_sdio_prepare_fw_request(bus);
4388 ret = brcmf_fw_get_firmwares(sdiodev->dev, fwreq,
4389 brcmf_sdio_firmware_callback);
4391 brcmf_err("async firmware request failed: %d\n", ret);
4399 brcmf_sdio_remove(bus);
4403 /* Detach and free everything */
4404 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4406 brcmf_dbg(TRACE, "Enter\n");
4409 /* Stop watchdog task */
4410 if (bus->watchdog_tsk) {
4411 send_sig(SIGTERM, bus->watchdog_tsk, 1);
4412 kthread_stop(bus->watchdog_tsk);
4413 bus->watchdog_tsk = NULL;
4416 /* De-register interrupt handler */
4417 brcmf_sdiod_intr_unregister(bus->sdiodev);
4419 brcmf_detach(bus->sdiodev->dev);
4421 cancel_work_sync(&bus->datawork);
4423 destroy_workqueue(bus->brcmf_wq);
4426 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
4427 sdio_claim_host(bus->sdiodev->func1);
4428 brcmf_sdio_wd_timer(bus, false);
4429 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4430 /* Leave the device in state where it is
4431 * 'passive'. This is done by resetting all
4435 brcmf_chip_set_passive(bus->ci);
4436 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4437 sdio_release_host(bus->sdiodev->func1);
4439 brcmf_chip_detach(bus->ci);
4441 if (bus->sdiodev->settings)
4442 brcmf_release_module_param(bus->sdiodev->settings);
4449 brcmf_dbg(TRACE, "Disconnected\n");
4452 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active)
4454 /* Totally stop the timer */
4455 if (!active && bus->wd_active) {
4456 del_timer_sync(&bus->timer);
4457 bus->wd_active = false;
4461 /* don't start the wd until fw is loaded */
4462 if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
4466 if (!bus->wd_active) {
4467 /* Create timer again when watchdog period is
4468 dynamically changed or in the first instance
4470 bus->timer.expires = jiffies + BRCMF_WD_POLL;
4471 add_timer(&bus->timer);
4472 bus->wd_active = true;
4474 /* Re arm the timer, at last watchdog period */
4475 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL);
4480 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
4484 sdio_claim_host(bus->sdiodev->func1);
4485 ret = brcmf_sdio_bus_sleep(bus, sleep, false);
4486 sdio_release_host(bus->sdiodev->func1);