1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2010 Broadcom Corporation
6 #include <linux/types.h>
7 #include <linux/atomic.h>
8 #include <linux/kernel.h>
9 #include <linux/kthread.h>
10 #include <linux/printk.h>
11 #include <linux/pci_ids.h>
12 #include <linux/netdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/sched/signal.h>
15 #include <linux/mmc/sdio.h>
16 #include <linux/mmc/sdio_ids.h>
17 #include <linux/mmc/sdio_func.h>
18 #include <linux/mmc/card.h>
19 #include <linux/mmc/core.h>
20 #include <linux/semaphore.h>
21 #include <linux/firmware.h>
22 #include <linux/module.h>
23 #include <linux/bcma/bcma.h>
24 #include <linux/debugfs.h>
25 #include <linux/vmalloc.h>
26 #include <asm/unaligned.h>
28 #include <brcmu_wifi.h>
29 #include <brcmu_utils.h>
30 #include <brcm_hw_ids.h>
40 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500)
41 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500)
43 /* watermark expressed in number of words */
44 #define DEFAULT_F2_WATERMARK 0x8
45 #define CY_4373_F2_WATERMARK 0x40
46 #define CY_4373_F1_MESBUSYCTRL (CY_4373_F2_WATERMARK | SBSDIO_MESBUSYCTRL_ENAB)
47 #define CY_43012_F2_WATERMARK 0x60
48 #define CY_43012_MES_WATERMARK 0x50
49 #define CY_43012_MESBUSYCTRL (CY_43012_MES_WATERMARK | \
50 SBSDIO_MESBUSYCTRL_ENAB)
51 #define CY_4339_F2_WATERMARK 48
52 #define CY_4339_MES_WATERMARK 80
53 #define CY_4339_MESBUSYCTRL (CY_4339_MES_WATERMARK | \
54 SBSDIO_MESBUSYCTRL_ENAB)
55 #define CY_43455_F2_WATERMARK 0x60
56 #define CY_43455_MES_WATERMARK 0x50
57 #define CY_43455_MESBUSYCTRL (CY_43455_MES_WATERMARK | \
58 SBSDIO_MESBUSYCTRL_ENAB)
59 #define CY_435X_F2_WATERMARK 0x40
60 #define CY_435X_F1_MESBUSYCTRL (CY_435X_F2_WATERMARK | \
61 SBSDIO_MESBUSYCTRL_ENAB)
65 #define BRCMF_TRAP_INFO_SIZE 80
67 #define CBUF_LEN (128)
69 /* Device console log buffer state */
70 #define CONSOLE_BUFFER_MAX 2024
73 __le32 buf; /* Can't be pointer on (64-bit) hosts */
76 char *_buf_compat; /* Redundant pointer for backward compat. */
81 * When there is no UART (e.g. Quickturn),
82 * the host should write a complete
83 * input line directly into cbuf and then write
84 * the length into vcons_in.
85 * This may also be used when there is a real UART
86 * (at risk of conflicting with
87 * the real UART). vcons_out is currently unused.
92 /* Output (logging) buffer
93 * Console output is written to a ring buffer log_buf at index log_idx.
94 * The host may read the output when it sees log_idx advance.
95 * Output will be lost if the output wraps around faster than the host
98 struct rte_log_le log_le;
100 /* Console input line buffer
101 * Characters are read one at a time into cbuf
102 * until <CR> is received, then
103 * the buffer is processed as a command line.
104 * Also used for virtual UART.
111 #include <chipcommon.h>
115 #include "tracepoint.h"
117 #define TXQLEN 2048 /* bulk tx queue length */
118 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
119 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
122 #define TXRETRIES 2 /* # of retries for tx frames */
124 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
127 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
130 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
132 #define MEMBLOCK 2048 /* Block size used for downloading
134 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
135 biggest possible glom */
137 #define BRCMF_FIRSTREAD (1 << 6)
139 #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */
141 /* SBSDIO_DEVICE_CTL */
143 /* 1: device will assert busy signal when receiving CMD53 */
144 #define SBSDIO_DEVCTL_SETBUSY 0x01
145 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
146 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
147 /* 1: mask all interrupts to host except the chipActive (rev 8) */
148 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
149 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
150 * sdio bus power cycle to clear (rev 9) */
151 #define SBSDIO_DEVCTL_PADS_ISO 0x08
152 /* 1: enable F2 Watermark */
153 #define SBSDIO_DEVCTL_F2WM_ENAB 0x10
154 /* Force SD->SB reset mapping (rev 11) */
155 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
156 /* Determined by CoreControl bit */
157 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
158 /* Force backplane reset */
159 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
160 /* Force no backplane reset */
161 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
163 /* direct(mapped) cis space */
165 /* MAPPED common CIS address */
166 #define SBSDIO_CIS_BASE_COMMON 0x1000
167 /* maximum bytes in one CIS */
168 #define SBSDIO_CIS_SIZE_LIMIT 0x200
169 /* cis offset addr is < 17 bits */
170 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
172 /* manfid tuple length, include tuple, link bytes */
173 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
175 #define SD_REG(field) \
176 (offsetof(struct sdpcmd_regs, field))
178 /* SDIO function 1 register CHIPCLKCSR */
179 /* Force ALP request to backplane */
180 #define SBSDIO_FORCE_ALP 0x01
181 /* Force HT request to backplane */
182 #define SBSDIO_FORCE_HT 0x02
183 /* Force ILP request to backplane */
184 #define SBSDIO_FORCE_ILP 0x04
185 /* Make ALP ready (power up xtal) */
186 #define SBSDIO_ALP_AVAIL_REQ 0x08
187 /* Make HT ready (power up PLL) */
188 #define SBSDIO_HT_AVAIL_REQ 0x10
189 /* Squelch clock requests from HW */
190 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
191 /* Status: ALP is ready */
192 #define SBSDIO_ALP_AVAIL 0x40
193 /* Status: HT is ready */
194 #define SBSDIO_HT_AVAIL 0x80
195 #define SBSDIO_CSR_MASK 0x1F
196 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
197 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
198 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
199 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
200 #define SBSDIO_CLKAV(regval, alponly) \
201 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
204 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
205 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
206 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
207 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
208 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
209 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
210 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
211 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
212 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
213 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
214 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
215 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
216 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
217 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
218 #define I_PC (1 << 10) /* descriptor error */
219 #define I_PD (1 << 11) /* data error */
220 #define I_DE (1 << 12) /* Descriptor protocol Error */
221 #define I_RU (1 << 13) /* Receive descriptor Underflow */
222 #define I_RO (1 << 14) /* Receive fifo Overflow */
223 #define I_XU (1 << 15) /* Transmit fifo Underflow */
224 #define I_RI (1 << 16) /* Receive Interrupt */
225 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
226 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
227 #define I_XI (1 << 24) /* Transmit Interrupt */
228 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
229 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
230 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
231 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
232 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
233 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
234 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
235 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
236 #define I_DMA (I_RI | I_XI | I_ERRORS)
239 #define CC_CISRDY (1 << 0) /* CIS Ready */
240 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
241 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
242 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
243 #define CC_XMTDATAAVAIL_MODE (1 << 4)
244 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
247 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
248 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
249 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
250 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
253 * Software allocation of To SB Mailbox resources
256 /* tosbmailbox bits corresponding to intstatus bits */
257 #define SMB_NAK (1 << 0) /* Frame NAK */
258 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
259 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
260 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
262 /* tosbmailboxdata */
263 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
266 * Software allocation of To Host Mailbox resources
270 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
271 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
272 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
273 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
275 /* tohostmailboxdata */
276 #define HMB_DATA_NAKHANDLED 0x0001 /* retransmit NAK'd frame */
277 #define HMB_DATA_DEVREADY 0x0002 /* talk to host after enable */
278 #define HMB_DATA_FC 0x0004 /* per prio flowcontrol update flag */
279 #define HMB_DATA_FWREADY 0x0008 /* fw ready for protocol activity */
280 #define HMB_DATA_FWHALT 0x0010 /* firmware halted */
282 #define HMB_DATA_FCDATA_MASK 0xff000000
283 #define HMB_DATA_FCDATA_SHIFT 24
285 #define HMB_DATA_VERSION_MASK 0x00ff0000
286 #define HMB_DATA_VERSION_SHIFT 16
289 * Software-defined protocol header
292 /* Current protocol version */
293 #define SDPCM_PROT_VERSION 4
296 * Shared structure between dongle and the host.
297 * The structure contains pointers to trap or assert information.
299 #define SDPCM_SHARED_VERSION 0x0003
300 #define SDPCM_SHARED_VERSION_MASK 0x00FF
301 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
302 #define SDPCM_SHARED_ASSERT 0x0200
303 #define SDPCM_SHARED_TRAP 0x0400
305 /* Space for header read, limit for data packets */
306 #define MAX_HDR_READ (1 << 6)
307 #define MAX_RX_DATASZ 2048
309 /* Bump up limit on waiting for HT to account for first startup;
310 * if the image is doing a CRC calculation before programming the PMU
311 * for HT availability, it could take a couple hundred ms more, so
312 * max out at a 1 second (1000000us).
314 #undef PMU_MAX_TRANSITION_DLY
315 #define PMU_MAX_TRANSITION_DLY 1000000
317 /* Value for ChipClockCSR during initial setup */
318 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
319 SBSDIO_ALP_AVAIL_REQ)
321 /* Flags for SDH calls */
322 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
324 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
327 #define BRCMF_IDLE_INTERVAL 1
329 #define KSO_WAIT_US 50
330 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
331 #define BRCMF_SDIO_MAX_ACCESS_ERRORS 5
334 /* Device console log buffer state */
335 struct brcmf_console {
336 uint count; /* Poll interval msec counter */
337 uint log_addr; /* Log struct address (fixed) */
338 struct rte_log_le log_le; /* Log struct (host copy) */
339 uint bufsize; /* Size of log buffer */
340 u8 *buf; /* Log buffer (host copy) */
341 uint last; /* Last buffer read index */
344 struct brcmf_trap_info {
358 __le32 r9; /* sb/v6 */
359 __le32 r10; /* sl/v7 */
360 __le32 r11; /* fp/v8 */
368 struct sdpcm_shared {
372 u32 assert_file_addr;
374 u32 console_addr; /* Address of struct rte_console */
380 struct sdpcm_shared_le {
383 __le32 assert_exp_addr;
384 __le32 assert_file_addr;
386 __le32 console_addr; /* Address of struct rte_console */
387 __le32 msgtrace_addr;
392 /* dongle SDIO bus specific header info */
393 struct brcmf_sdio_hdrinfo {
405 * hold counter variables
407 struct brcmf_sdio_count {
408 uint intrcount; /* Count of device interrupt callbacks */
409 uint lastintrs; /* Count as of last watchdog timer */
410 uint pollcnt; /* Count of active polls */
411 uint regfails; /* Count of R_REG failures */
412 uint tx_sderrs; /* Count of tx attempts with sd errors */
413 uint fcqueued; /* Tx packets that got queued */
414 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
415 uint rx_toolong; /* Receive frames too long to receive */
416 uint rxc_errors; /* SDIO errors when reading control frames */
417 uint rx_hdrfail; /* SDIO errors on header reads */
418 uint rx_badhdr; /* Bad received headers (roosync?) */
419 uint rx_badseq; /* Mismatched rx sequence number */
420 uint fc_rcvd; /* Number of flow-control events received */
421 uint fc_xoff; /* Number which turned on flow-control */
422 uint fc_xon; /* Number which turned off flow-control */
423 uint rxglomfail; /* Failed deglom attempts */
424 uint rxglomframes; /* Number of glom frames (superframes) */
425 uint rxglompkts; /* Number of packets from glom frames */
426 uint f2rxhdrs; /* Number of header reads */
427 uint f2rxdata; /* Number of frame data reads */
428 uint f2txdata; /* Number of f2 frame writes */
429 uint f1regdata; /* Number of f1 register accesses */
430 uint tickcnt; /* Number of watchdog been schedule */
431 ulong tx_ctlerrs; /* Err of sending ctrl frames */
432 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
433 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
434 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
435 ulong rx_readahead_cnt; /* packets where header read-ahead was used */
438 /* misc chip info needed by some of the routines */
439 /* Private data for SDIO bus interaction */
441 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
442 struct brcmf_chip *ci; /* Chip info struct */
443 struct brcmf_core *sdio_core; /* sdio core info struct */
445 u32 hostintmask; /* Copy of Host Interrupt Mask */
446 atomic_t intstatus; /* Intstatus bits (events) pending */
447 atomic_t fcstate; /* State of dongle flow-control */
449 uint blocksize; /* Block size of SDIO transfers */
450 uint roundup; /* Max roundup limit */
452 struct pktq txq; /* Queue length used for flow-control */
453 u8 flowcontrol; /* per prio flow control bitmask */
454 u8 tx_seq; /* Transmit sequence number (next) */
455 u8 tx_max; /* Maximum transmit sequence allowed */
457 u8 *hdrbuf; /* buffer for handling rx frame */
458 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
459 u8 rx_seq; /* Receive sequence number (expected) */
460 struct brcmf_sdio_hdrinfo cur_read;
461 /* info of current read frame */
462 bool rxskip; /* Skip receive (awaiting NAK ACK) */
463 bool rxpending; /* Data frame pending in dongle */
465 uint rxbound; /* Rx frames to read before resched */
466 uint txbound; /* Tx frames to send before resched */
469 struct sk_buff *glomd; /* Packet containing glomming descriptor */
470 struct sk_buff_head glom; /* Packet list for glommed superframe */
472 u8 *rxbuf; /* Buffer for receiving control packets */
473 uint rxblen; /* Allocated length of rxbuf */
474 u8 *rxctl; /* Aligned pointer into rxbuf */
475 u8 *rxctl_orig; /* pointer for freeing rxctl */
476 uint rxlen; /* Length of valid data in buffer */
477 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
479 u8 sdpcm_ver; /* Bus protocol reported by dongle */
481 bool intr; /* Use interrupts */
482 bool poll; /* Use polling */
483 atomic_t ipend; /* Device interrupt is pending */
484 uint spurious; /* Count of spurious interrupts */
485 uint pollrate; /* Ticks between device polls */
486 uint polltick; /* Tick counter */
489 uint console_interval;
490 struct brcmf_console console; /* Console output polling support */
491 uint console_addr; /* Console address from shared struct */
494 uint clkstate; /* State of sd and backplane clock(s) */
495 s32 idletime; /* Control for activity timeout */
496 s32 idlecount; /* Activity timeout counter */
497 s32 idleclock; /* How to set bus driver when idle */
498 bool rxflow_mode; /* Rx flow control mode */
499 bool rxflow; /* Is rx flow control on */
500 bool alp_only; /* Don't use HT clock (ALP only) */
504 bool ctrl_frame_stat;
507 spinlock_t txq_lock; /* protect bus->txq */
508 wait_queue_head_t ctrl_wait;
509 wait_queue_head_t dcmd_resp_wait;
511 struct timer_list timer;
512 struct completion watchdog_wait;
513 struct task_struct *watchdog_tsk;
516 struct workqueue_struct *brcmf_wq;
517 struct work_struct datawork;
521 bool txoff; /* Transmit flow-controlled */
522 struct brcmf_sdio_count sdcnt;
523 bool sr_enabled; /* SaveRestore enabled */
526 u8 tx_hdrlen; /* sdio bus header length for tx packet */
527 bool txglom; /* host tx glomming enable flag */
528 u16 head_align; /* buffer pointer alignment */
529 u16 sgentry_align; /* scatter-gather buffer alignment */
535 #define CLK_PENDING 2
539 static int qcount[NUMPRIO];
542 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
544 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
546 /* Limit on rounding up frames */
547 static const uint max_roundup = 512;
549 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
555 enum brcmf_sdio_frmtype {
556 BRCMF_SDIO_FT_NORMAL,
561 #define SDIOD_DRVSTR_KEY(chip, pmu) (((unsigned int)(chip) << 16) | (pmu))
563 /* SDIO Pad drive strength to select value mappings */
564 struct sdiod_drive_str {
565 u8 strength; /* Pad Drive Strength in mA */
566 u8 sel; /* Chip-specific select value */
569 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
570 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
581 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
582 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
592 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
593 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
599 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
600 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
607 BRCMF_FW_DEF(43143, "brcmfmac43143-sdio");
608 BRCMF_FW_DEF(43241B0, "brcmfmac43241b0-sdio");
609 BRCMF_FW_DEF(43241B4, "brcmfmac43241b4-sdio");
610 BRCMF_FW_DEF(43241B5, "brcmfmac43241b5-sdio");
611 BRCMF_FW_DEF(4329, "brcmfmac4329-sdio");
612 BRCMF_FW_DEF(4330, "brcmfmac4330-sdio");
613 BRCMF_FW_DEF(4334, "brcmfmac4334-sdio");
614 BRCMF_FW_DEF(43340, "brcmfmac43340-sdio");
615 BRCMF_FW_DEF(43341, "brcmfmac43341-sdio");
616 BRCMF_FW_DEF(4335, "brcmfmac4335-sdio");
617 BRCMF_FW_DEF(43362, "brcmfmac43362-sdio");
618 BRCMF_FW_DEF(4339, "brcmfmac4339-sdio");
619 BRCMF_FW_DEF(43430A0, "brcmfmac43430a0-sdio");
620 /* Note the names are not postfixed with a1 for backward compatibility */
621 BRCMF_FW_CLM_DEF(43430A1, "brcmfmac43430-sdio");
622 BRCMF_FW_DEF(43430B0, "brcmfmac43430b0-sdio");
623 BRCMF_FW_CLM_DEF(43455, "brcmfmac43455-sdio");
624 BRCMF_FW_DEF(43456, "brcmfmac43456-sdio");
625 BRCMF_FW_CLM_DEF(4354, "brcmfmac4354-sdio");
626 BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-sdio");
627 BRCMF_FW_DEF(4359, "brcmfmac4359-sdio");
628 BRCMF_FW_CLM_DEF(4373, "brcmfmac4373-sdio");
629 BRCMF_FW_CLM_DEF(43012, "brcmfmac43012-sdio");
630 BRCMF_FW_CLM_DEF(43752, "brcmfmac43752-sdio");
632 /* firmware config files */
633 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-sdio.*.txt");
635 /* per-board firmware binaries */
636 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-sdio.*.bin");
638 static const struct brcmf_firmware_mapping sdio_fwnames[] = {
639 BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
640 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
641 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
642 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5),
643 BRCMF_FW_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329),
644 BRCMF_FW_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330),
645 BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
646 BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
647 BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43341),
648 BRCMF_FW_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
649 BRCMF_FW_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
650 BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
651 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0),
652 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000002, 43430A1),
653 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFC, 43430B0),
654 BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0x00000200, 43456),
655 BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFDC0, 43455),
656 BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
657 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
658 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359),
659 BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373),
660 BRCMF_FW_ENTRY(CY_CC_43012_CHIP_ID, 0xFFFFFFFF, 43012),
661 BRCMF_FW_ENTRY(CY_CC_43752_CHIP_ID, 0xFFFFFFFF, 43752)
664 static const struct brcmf_firmware_mapping *brcmf_sdio_fwnames;
665 static u32 brcmf_sdio_fwnames_count;
667 #define TXCTL_CREDITS 2
669 static void pkt_align(struct sk_buff *p, int len, int align)
672 datalign = (unsigned long)(p->data);
673 datalign = roundup(datalign, (align)) - datalign;
675 skb_pull(p, datalign);
679 /* To check if there's window offered */
680 static bool data_ok(struct brcmf_sdio *bus)
684 /* Reserve TXCTL_CREDITS credits for txctl when it is ready to send */
685 if (bus->ctrl_frame_stat)
686 tx_rsv = TXCTL_CREDITS;
688 return (bus->tx_max - bus->tx_seq - tx_rsv) != 0 &&
689 ((bus->tx_max - bus->tx_seq - tx_rsv) & 0x80) == 0;
693 /* To check if there's window offered */
694 static bool txctl_ok(struct brcmf_sdio *bus)
696 return (bus->tx_max - bus->tx_seq) != 0 &&
697 ((bus->tx_max - bus->tx_seq) & 0x80) == 0;
701 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
703 u8 wr_val = 0, rd_val, cmp_val, bmask;
708 brcmf_dbg(TRACE, "Enter: on=%d\n", on);
710 sdio_retune_crc_disable(bus->sdiodev->func1);
712 /* Cannot re-tune if device is asleep; defer till we're awake */
714 sdio_retune_hold_now(bus->sdiodev->func1);
716 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
717 /* 1st KSO write goes to AOS wake up core if device is asleep */
718 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err);
720 /* In case of 43012 chip, the chip could go down immediately after
721 * KSO bit is cleared. So the further reads of KSO register could
722 * fail. Thereby just bailing out immediately after clearing KSO
723 * bit, to avoid polling of KSO bit.
725 if (!on && bus->ci->chip == CY_CC_43012_CHIP_ID)
729 /* device WAKEUP through KSO:
730 * write bit 0 & read back until
731 * both bits 0 (kso bit) & 1 (dev on status) are set
733 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
734 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
736 usleep_range(2000, 3000);
738 /* Put device to sleep, turn off KSO */
740 /* only check for bit0, bit1(dev on status) may not
741 * get cleared right away
743 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
747 /* reliable KSO bit set/clr:
748 * the sdiod sleep write access is synced to PMU 32khz clk
749 * just one write attempt may fail,
750 * read it back until it matches written value
752 rd_val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
755 if ((rd_val & bmask) == cmp_val)
759 /* bail out upon subsequent access errors */
760 if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS))
764 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val,
767 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
770 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
773 if (try_cnt > MAX_KSO_ATTEMPTS)
774 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
777 sdio_retune_release(bus->sdiodev->func1);
779 sdio_retune_crc_enable(bus->sdiodev->func1);
784 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
786 /* Turn backplane clock on or off */
787 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
790 u8 clkctl, clkreq, devctl;
791 unsigned long timeout;
793 brcmf_dbg(SDIO, "Enter\n");
797 if (bus->sr_enabled) {
798 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
803 /* Request HT Avail */
805 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
807 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
810 brcmf_err("HT Avail request error: %d\n", err);
814 /* Check current status */
815 clkctl = brcmf_sdiod_readb(bus->sdiodev,
816 SBSDIO_FUNC1_CHIPCLKCSR, &err);
818 brcmf_err("HT Avail read error: %d\n", err);
822 /* Go to pending and await interrupt if appropriate */
823 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
824 /* Allow only clock-available interrupt */
825 devctl = brcmf_sdiod_readb(bus->sdiodev,
826 SBSDIO_DEVICE_CTL, &err);
828 brcmf_err("Devctl error setting CA: %d\n", err);
832 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
833 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL,
835 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
836 bus->clkstate = CLK_PENDING;
839 } else if (bus->clkstate == CLK_PENDING) {
840 /* Cancel CA-only interrupt filter */
841 devctl = brcmf_sdiod_readb(bus->sdiodev,
842 SBSDIO_DEVICE_CTL, &err);
843 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
844 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL,
848 /* Otherwise, wait here (polling) for HT Avail */
850 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
851 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
852 clkctl = brcmf_sdiod_readb(bus->sdiodev,
853 SBSDIO_FUNC1_CHIPCLKCSR,
855 if (time_after(jiffies, timeout))
858 usleep_range(5000, 10000);
861 brcmf_err("HT Avail request error: %d\n", err);
864 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
865 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
866 PMU_MAX_TRANSITION_DLY, clkctl);
870 /* Mark clock available */
871 bus->clkstate = CLK_AVAIL;
872 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
875 if (!bus->alp_only) {
876 if (SBSDIO_ALPONLY(clkctl))
877 brcmf_err("HT Clock should be on\n");
879 #endif /* defined (DEBUG) */
884 if (bus->clkstate == CLK_PENDING) {
885 /* Cancel CA-only interrupt filter */
886 devctl = brcmf_sdiod_readb(bus->sdiodev,
887 SBSDIO_DEVICE_CTL, &err);
888 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
889 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL,
893 bus->clkstate = CLK_SDONLY;
894 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
896 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
898 brcmf_err("Failed access turning clock off: %d\n",
906 /* Change idle/active SD state */
907 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
909 brcmf_dbg(SDIO, "Enter\n");
912 bus->clkstate = CLK_SDONLY;
914 bus->clkstate = CLK_NONE;
919 /* Transition SD and backplane clock readiness */
920 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
923 uint oldstate = bus->clkstate;
926 brcmf_dbg(SDIO, "Enter\n");
928 /* Early exit if we're already there */
929 if (bus->clkstate == target)
934 /* Make sure SD clock is available */
935 if (bus->clkstate == CLK_NONE)
936 brcmf_sdio_sdclk(bus, true);
937 /* Now request HT Avail on the backplane */
938 brcmf_sdio_htclk(bus, true, pendok);
942 /* Remove HT request, or bring up SD clock */
943 if (bus->clkstate == CLK_NONE)
944 brcmf_sdio_sdclk(bus, true);
945 else if (bus->clkstate == CLK_AVAIL)
946 brcmf_sdio_htclk(bus, false, false);
948 brcmf_err("request for %d -> %d\n",
949 bus->clkstate, target);
953 /* Make sure to remove HT request */
954 if (bus->clkstate == CLK_AVAIL)
955 brcmf_sdio_htclk(bus, false, false);
956 /* Now remove the SD clock */
957 brcmf_sdio_sdclk(bus, false);
961 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
968 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
973 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
974 (sleep ? "SLEEP" : "WAKE"),
975 (bus->sleeping ? "SLEEP" : "WAKE"));
977 /* If SR is enabled control bus state with KSO */
978 if (bus->sr_enabled) {
979 /* Done if we're already in the requested state */
980 if (sleep == bus->sleeping)
985 clkcsr = brcmf_sdiod_readb(bus->sdiodev,
986 SBSDIO_FUNC1_CHIPCLKCSR,
988 if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
989 brcmf_dbg(SDIO, "no clock, set ALP\n");
990 brcmf_sdiod_writeb(bus->sdiodev,
991 SBSDIO_FUNC1_CHIPCLKCSR,
992 SBSDIO_ALP_AVAIL_REQ, &err);
994 err = brcmf_sdio_kso_control(bus, false);
996 err = brcmf_sdio_kso_control(bus, true);
999 brcmf_err("error while changing bus sleep state %d\n",
1006 /* control clocks */
1008 if (!bus->sr_enabled)
1009 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
1011 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
1012 brcmf_sdio_wd_timer(bus, true);
1014 bus->sleeping = sleep;
1015 brcmf_dbg(SDIO, "new state %s\n",
1016 (sleep ? "SLEEP" : "WAKE"));
1018 brcmf_dbg(SDIO, "Exit: err=%d\n", err);
1024 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
1026 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
1029 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
1030 struct sdpcm_shared *sh)
1035 struct sdpcm_shared_le sh_le;
1038 sdio_claim_host(bus->sdiodev->func1);
1039 brcmf_sdio_bus_sleep(bus, false, false);
1042 * Read last word in socram to determine
1043 * address of sdpcm_shared structure
1045 shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
1046 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
1047 shaddr -= bus->ci->srsize;
1048 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
1054 * Check if addr is valid.
1055 * NVRAM length at the end of memory should have been overwritten.
1057 addr = le32_to_cpu(addr_le);
1058 if (!brcmf_sdio_valid_shared_address(addr)) {
1059 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
1064 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
1066 /* Read hndrte_shared structure */
1067 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1068 sizeof(struct sdpcm_shared_le));
1072 sdio_release_host(bus->sdiodev->func1);
1075 sh->flags = le32_to_cpu(sh_le.flags);
1076 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1077 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1078 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1079 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1080 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1081 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1083 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1084 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1085 SDPCM_SHARED_VERSION,
1086 sh->flags & SDPCM_SHARED_VERSION_MASK);
1092 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
1094 sdio_release_host(bus->sdiodev->func1);
1098 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1100 struct sdpcm_shared sh;
1102 if (brcmf_sdio_readshared(bus, &sh) == 0)
1103 bus->console_addr = sh.console_addr;
1106 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1111 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1113 struct brcmf_sdio_dev *sdiod = bus->sdiodev;
1114 struct brcmf_core *core = bus->sdio_core;
1120 brcmf_dbg(SDIO, "Enter\n");
1122 /* Read mailbox data and ack that we did so */
1123 hmb_data = brcmf_sdiod_readl(sdiod,
1124 core->base + SD_REG(tohostmailboxdata),
1128 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox),
1131 bus->sdcnt.f1regdata += 2;
1133 /* dongle indicates the firmware has halted/crashed */
1134 if (hmb_data & HMB_DATA_FWHALT) {
1135 brcmf_dbg(SDIO, "mailbox indicates firmware halted\n");
1136 brcmf_fw_crashed(&sdiod->func1->dev);
1139 /* Dongle recomposed rx frames, accept them again */
1140 if (hmb_data & HMB_DATA_NAKHANDLED) {
1141 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1144 brcmf_err("unexpected NAKHANDLED!\n");
1146 bus->rxskip = false;
1147 intstatus |= I_HMB_FRAME_IND;
1151 * DEVREADY does not occur with gSPI.
1153 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1155 (hmb_data & HMB_DATA_VERSION_MASK) >>
1156 HMB_DATA_VERSION_SHIFT;
1157 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1158 brcmf_err("Version mismatch, dongle reports %d, "
1160 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1162 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1166 * Retrieve console state address now that firmware should have
1169 brcmf_sdio_get_console_addr(bus);
1173 * Flow Control has been moved into the RX headers and this out of band
1174 * method isn't used any more.
1175 * remaining backward compatible with older dongles.
1177 if (hmb_data & HMB_DATA_FC) {
1178 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1179 HMB_DATA_FCDATA_SHIFT;
1181 if (fcbits & ~bus->flowcontrol)
1182 bus->sdcnt.fc_xoff++;
1184 if (bus->flowcontrol & ~fcbits)
1185 bus->sdcnt.fc_xon++;
1187 bus->sdcnt.fc_rcvd++;
1188 bus->flowcontrol = fcbits;
1191 /* Shouldn't be any others */
1192 if (hmb_data & ~(HMB_DATA_DEVREADY |
1193 HMB_DATA_NAKHANDLED |
1197 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1198 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1204 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1206 struct brcmf_sdio_dev *sdiod = bus->sdiodev;
1207 struct brcmf_core *core = bus->sdio_core;
1213 brcmf_err("%sterminate frame%s\n",
1214 abort ? "abort command, " : "",
1215 rtx ? ", send NAK" : "");
1218 brcmf_sdiod_abort(bus->sdiodev, bus->sdiodev->func2);
1220 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
1222 bus->sdcnt.f1regdata++;
1224 /* Wait until the packet has been flushed (device/FIFO stable) */
1225 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1226 hi = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCHI,
1228 lo = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCLO,
1230 bus->sdcnt.f1regdata += 2;
1232 if ((hi == 0) && (lo == 0))
1235 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1236 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1237 lastrbc, (hi << 8) + lo);
1239 lastrbc = (hi << 8) + lo;
1243 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1245 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1249 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox),
1252 bus->sdcnt.f1regdata++;
1257 /* Clear partial in any case */
1258 bus->cur_read.len = 0;
1261 static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
1263 struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
1266 /* On failure, abort the command and terminate the frame */
1267 brcmf_err("sdio error, abort command and terminate frame\n");
1268 bus->sdcnt.tx_sderrs++;
1270 brcmf_sdiod_abort(sdiodev, sdiodev->func2);
1271 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
1272 bus->sdcnt.f1regdata++;
1274 for (i = 0; i < 3; i++) {
1275 hi = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1276 lo = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1277 bus->sdcnt.f1regdata += 2;
1278 if ((hi == 0) && (lo == 0))
1283 /* return total length of buffer chain */
1284 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1290 skb_queue_walk(&bus->glom, p)
1295 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1297 struct sk_buff *cur, *next;
1299 skb_queue_walk_safe(&bus->glom, cur, next) {
1300 skb_unlink(cur, &bus->glom);
1301 brcmu_pkt_buf_free_skb(cur);
1306 * brcmfmac sdio bus specific header
1307 * This is the lowest layer header wrapped on the packets transmitted between
1308 * host and WiFi dongle which contains information needed for SDIO core and
1311 * It consists of 3 parts: hardware header, hardware extension header and
1313 * hardware header (frame tag) - 4 bytes
1314 * Byte 0~1: Frame length
1315 * Byte 2~3: Checksum, bit-wise inverse of frame length
1316 * hardware extension header - 8 bytes
1317 * Tx glom mode only, N/A for Rx or normal Tx
1318 * Byte 0~1: Packet length excluding hw frame tag
1320 * Byte 3: Frame flags, bit 0: last frame indication
1321 * Byte 4~5: Reserved
1322 * Byte 6~7: Tail padding length
1323 * software header - 8 bytes
1324 * Byte 0: Rx/Tx sequence number
1325 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1326 * Byte 2: Length of next data frame, reserved for Tx
1327 * Byte 3: Data offset
1328 * Byte 4: Flow control bits, reserved for Tx
1329 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1330 * Byte 6~7: Reserved
1332 #define SDPCM_HWHDR_LEN 4
1333 #define SDPCM_HWEXT_LEN 8
1334 #define SDPCM_SWHDR_LEN 8
1335 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1336 /* software header */
1337 #define SDPCM_SEQ_MASK 0x000000ff
1338 #define SDPCM_SEQ_WRAP 256
1339 #define SDPCM_CHANNEL_MASK 0x00000f00
1340 #define SDPCM_CHANNEL_SHIFT 8
1341 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1342 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1343 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1344 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1345 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1346 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1347 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1348 #define SDPCM_NEXTLEN_SHIFT 16
1349 #define SDPCM_DOFFSET_MASK 0xff000000
1350 #define SDPCM_DOFFSET_SHIFT 24
1351 #define SDPCM_FCMASK_MASK 0x000000ff
1352 #define SDPCM_WINDOW_MASK 0x0000ff00
1353 #define SDPCM_WINDOW_SHIFT 8
1355 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1358 hdrvalue = le32_to_cpu(*(__le32 *)swheader);
1359 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1362 static inline bool brcmf_sdio_fromevntchan(u8 *swheader)
1367 hdrvalue = le32_to_cpu(*(__le32 *)swheader);
1368 ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT);
1370 return (ret == SDPCM_EVENT_CHANNEL);
1373 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1374 struct brcmf_sdio_hdrinfo *rd,
1375 enum brcmf_sdio_frmtype type)
1378 u8 rx_seq, fc, tx_seq_max;
1381 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1384 len = get_unaligned_le16(header);
1385 checksum = get_unaligned_le16(header + sizeof(u16));
1386 /* All zero means no more to read */
1387 if (!(len | checksum)) {
1388 bus->rxpending = false;
1391 if ((u16)(~(len ^ checksum))) {
1392 brcmf_err("HW header checksum error\n");
1393 bus->sdcnt.rx_badhdr++;
1394 brcmf_sdio_rxfail(bus, false, false);
1397 if (len < SDPCM_HDRLEN) {
1398 brcmf_err("HW header length error\n");
1401 if (type == BRCMF_SDIO_FT_SUPER &&
1402 (roundup(len, bus->blocksize) != rd->len)) {
1403 brcmf_err("HW superframe header length error\n");
1406 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1407 brcmf_err("HW subframe header length error\n");
1412 /* software header */
1413 header += SDPCM_HWHDR_LEN;
1414 swheader = le32_to_cpu(*(__le32 *)header);
1415 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1416 brcmf_err("Glom descriptor found in superframe head\n");
1420 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1421 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1422 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1423 type != BRCMF_SDIO_FT_SUPER) {
1424 brcmf_err("HW header length too long\n");
1425 bus->sdcnt.rx_toolong++;
1426 brcmf_sdio_rxfail(bus, false, false);
1430 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1431 brcmf_err("Wrong channel for superframe\n");
1435 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1436 rd->channel != SDPCM_EVENT_CHANNEL) {
1437 brcmf_err("Wrong channel for subframe\n");
1441 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1442 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1443 brcmf_err("seq %d: bad data offset\n", rx_seq);
1444 bus->sdcnt.rx_badhdr++;
1445 brcmf_sdio_rxfail(bus, false, false);
1449 if (rd->seq_num != rx_seq) {
1450 brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num);
1451 bus->sdcnt.rx_badseq++;
1452 rd->seq_num = rx_seq;
1454 /* no need to check the reset for subframe */
1455 if (type == BRCMF_SDIO_FT_SUB)
1457 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1458 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1459 /* only warm for NON glom packet */
1460 if (rd->channel != SDPCM_GLOM_CHANNEL)
1461 brcmf_err("seq %d: next length error\n", rx_seq);
1464 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1465 fc = swheader & SDPCM_FCMASK_MASK;
1466 if (bus->flowcontrol != fc) {
1467 if (~bus->flowcontrol & fc)
1468 bus->sdcnt.fc_xoff++;
1469 if (bus->flowcontrol & ~fc)
1470 bus->sdcnt.fc_xon++;
1471 bus->sdcnt.fc_rcvd++;
1472 bus->flowcontrol = fc;
1474 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1475 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1476 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1477 tx_seq_max = bus->tx_seq + 2;
1479 bus->tx_max = tx_seq_max;
1484 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1486 *(__le16 *)header = cpu_to_le16(frm_length);
1487 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1490 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1491 struct brcmf_sdio_hdrinfo *hd_info)
1496 brcmf_sdio_update_hwhdr(header, hd_info->len);
1497 hdr_offset = SDPCM_HWHDR_LEN;
1500 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1501 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1502 hdrval = (u16)hd_info->tail_pad << 16;
1503 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1504 hdr_offset += SDPCM_HWEXT_LEN;
1507 hdrval = hd_info->seq_num;
1508 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1510 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1512 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1513 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1514 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1517 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1522 struct sk_buff *pfirst, *pnext;
1527 struct brcmf_sdio_hdrinfo rd_new;
1529 /* If packets, issue read(s) and send up packet chain */
1530 /* Return sequence numbers consumed? */
1532 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1533 bus->glomd, skb_peek(&bus->glom));
1535 /* If there's a descriptor, generate the packet chain */
1537 pfirst = pnext = NULL;
1538 dlen = (u16) (bus->glomd->len);
1539 dptr = bus->glomd->data;
1540 if (!dlen || (dlen & 1)) {
1541 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1546 for (totlen = num = 0; dlen; num++) {
1547 /* Get (and move past) next length */
1548 sublen = get_unaligned_le16(dptr);
1549 dlen -= sizeof(u16);
1550 dptr += sizeof(u16);
1551 if ((sublen < SDPCM_HDRLEN) ||
1552 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1553 brcmf_err("descriptor len %d bad: %d\n",
1558 if (sublen % bus->sgentry_align) {
1559 brcmf_err("sublen %d not multiple of %d\n",
1560 sublen, bus->sgentry_align);
1564 /* For last frame, adjust read len so total
1565 is a block multiple */
1568 (roundup(totlen, bus->blocksize) - totlen);
1569 totlen = roundup(totlen, bus->blocksize);
1572 /* Allocate/chain packet for next subframe */
1573 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1574 if (pnext == NULL) {
1575 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1579 skb_queue_tail(&bus->glom, pnext);
1581 /* Adhere to start alignment requirements */
1582 pkt_align(pnext, sublen, bus->sgentry_align);
1585 /* If all allocations succeeded, save packet chain
1588 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1590 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1591 totlen != bus->cur_read.len) {
1592 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1593 bus->cur_read.len, totlen, rxseq);
1595 pfirst = pnext = NULL;
1597 brcmf_sdio_free_glom(bus);
1601 /* Done with descriptor packet */
1602 brcmu_pkt_buf_free_skb(bus->glomd);
1604 bus->cur_read.len = 0;
1607 /* Ok -- either we just generated a packet chain,
1608 or had one from before */
1609 if (!skb_queue_empty(&bus->glom)) {
1610 if (BRCMF_GLOM_ON()) {
1611 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1612 skb_queue_walk(&bus->glom, pnext) {
1613 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1614 pnext, (u8 *) (pnext->data),
1615 pnext->len, pnext->len);
1619 pfirst = skb_peek(&bus->glom);
1620 dlen = (u16) brcmf_sdio_glom_len(bus);
1622 /* Do an SDIO read for the superframe. Configurable iovar to
1623 * read directly into the chained packet, or allocate a large
1624 * packet and and copy into the chain.
1626 sdio_claim_host(bus->sdiodev->func1);
1627 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1629 sdio_release_host(bus->sdiodev->func1);
1630 bus->sdcnt.f2rxdata++;
1632 /* On failure, kill the superframe */
1634 brcmf_err("glom read of %d bytes failed: %d\n",
1637 sdio_claim_host(bus->sdiodev->func1);
1638 brcmf_sdio_rxfail(bus, true, false);
1639 bus->sdcnt.rxglomfail++;
1640 brcmf_sdio_free_glom(bus);
1641 sdio_release_host(bus->sdiodev->func1);
1645 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1646 pfirst->data, min_t(int, pfirst->len, 48),
1649 rd_new.seq_num = rxseq;
1651 sdio_claim_host(bus->sdiodev->func1);
1652 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1653 BRCMF_SDIO_FT_SUPER);
1654 sdio_release_host(bus->sdiodev->func1);
1655 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1657 /* Remove superframe header, remember offset */
1658 skb_pull(pfirst, rd_new.dat_offset);
1661 /* Validate all the subframe headers */
1662 skb_queue_walk(&bus->glom, pnext) {
1663 /* leave when invalid subframe is found */
1667 rd_new.len = pnext->len;
1668 rd_new.seq_num = rxseq++;
1669 sdio_claim_host(bus->sdiodev->func1);
1670 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1672 sdio_release_host(bus->sdiodev->func1);
1673 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1674 pnext->data, 32, "subframe:\n");
1680 /* Terminate frame on error */
1681 sdio_claim_host(bus->sdiodev->func1);
1682 brcmf_sdio_rxfail(bus, true, false);
1683 bus->sdcnt.rxglomfail++;
1684 brcmf_sdio_free_glom(bus);
1685 sdio_release_host(bus->sdiodev->func1);
1686 bus->cur_read.len = 0;
1690 /* Basic SD framing looks ok - process each packet (header) */
1692 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1693 dptr = (u8 *) (pfirst->data);
1694 sublen = get_unaligned_le16(dptr);
1695 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1697 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1699 "Rx Subframe Data:\n");
1701 __skb_trim(pfirst, sublen);
1702 skb_pull(pfirst, doff);
1704 if (pfirst->len == 0) {
1705 skb_unlink(pfirst, &bus->glom);
1706 brcmu_pkt_buf_free_skb(pfirst);
1710 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1712 min_t(int, pfirst->len, 32),
1713 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1714 bus->glom.qlen, pfirst, pfirst->data,
1715 pfirst->len, pfirst->next,
1717 skb_unlink(pfirst, &bus->glom);
1718 if (brcmf_sdio_fromevntchan(&dptr[SDPCM_HWHDR_LEN]))
1719 brcmf_rx_event(bus->sdiodev->dev, pfirst);
1721 brcmf_rx_frame(bus->sdiodev->dev, pfirst,
1723 bus->sdcnt.rxglompkts++;
1726 bus->sdcnt.rxglomframes++;
1731 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1734 DECLARE_WAITQUEUE(wait, current);
1735 int timeout = DCMD_RESP_TIMEOUT;
1737 /* Wait until control frame is available */
1738 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1739 set_current_state(TASK_INTERRUPTIBLE);
1741 while (!(*condition) && (!signal_pending(current) && timeout))
1742 timeout = schedule_timeout(timeout);
1744 if (signal_pending(current))
1747 set_current_state(TASK_RUNNING);
1748 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1753 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1755 wake_up_interruptible(&bus->dcmd_resp_wait);
1760 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1763 u8 *buf = NULL, *rbuf;
1766 brcmf_dbg(SDIO, "Enter\n");
1768 buf = vzalloc(bus->rxblen);
1773 pad = ((unsigned long)rbuf % bus->head_align);
1775 rbuf += (bus->head_align - pad);
1777 /* Copy the already-read portion over */
1778 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1779 if (len <= BRCMF_FIRSTREAD)
1782 /* Raise rdlen to next SDIO block to avoid tail command */
1783 rdlen = len - BRCMF_FIRSTREAD;
1784 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1785 pad = bus->blocksize - (rdlen % bus->blocksize);
1786 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1787 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1789 } else if (rdlen % bus->head_align) {
1790 rdlen += bus->head_align - (rdlen % bus->head_align);
1793 /* Drop if the read is too big or it exceeds our maximum */
1794 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1795 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1796 rdlen, bus->sdiodev->bus_if->maxctl);
1797 brcmf_sdio_rxfail(bus, false, false);
1801 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1802 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1803 len, len - doff, bus->sdiodev->bus_if->maxctl);
1804 bus->sdcnt.rx_toolong++;
1805 brcmf_sdio_rxfail(bus, false, false);
1809 /* Read remain of frame body */
1810 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1811 bus->sdcnt.f2rxdata++;
1813 /* Control frame failures need retransmission */
1815 brcmf_err("read %d control bytes failed: %d\n",
1817 bus->sdcnt.rxc_errors++;
1818 brcmf_sdio_rxfail(bus, true, true);
1821 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1825 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1826 buf, len, "RxCtrl:\n");
1828 /* Point to valid data and indicate its length */
1829 spin_lock_bh(&bus->rxctl_lock);
1831 brcmf_err("last control frame is being processed.\n");
1832 spin_unlock_bh(&bus->rxctl_lock);
1836 bus->rxctl = buf + doff;
1837 bus->rxctl_orig = buf;
1838 bus->rxlen = len - doff;
1839 spin_unlock_bh(&bus->rxctl_lock);
1842 /* Awake any waiters */
1843 brcmf_sdio_dcmd_resp_wake(bus);
1846 /* Pad read to blocksize for efficiency */
1847 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1849 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1850 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1851 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1852 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1854 } else if (*rdlen % bus->head_align) {
1855 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1859 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1861 struct sk_buff *pkt; /* Packet for event or data frames */
1862 u16 pad; /* Number of pad bytes to read */
1863 uint rxleft = 0; /* Remaining number of frames allowed */
1864 int ret; /* Return code from calls */
1865 uint rxcount = 0; /* Total frames read */
1866 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1869 brcmf_dbg(SDIO, "Enter\n");
1871 /* Not finished unless we encounter no more frames indication */
1872 bus->rxpending = true;
1874 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1875 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
1876 rd->seq_num++, rxleft--) {
1878 /* Handle glomming separately */
1879 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1881 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1882 bus->glomd, skb_peek(&bus->glom));
1883 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1884 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1885 rd->seq_num += cnt - 1;
1886 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1890 rd->len_left = rd->len;
1891 /* read header first for unknow frame length */
1892 sdio_claim_host(bus->sdiodev->func1);
1894 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1895 bus->rxhdr, BRCMF_FIRSTREAD);
1896 bus->sdcnt.f2rxhdrs++;
1898 brcmf_err("RXHEADER FAILED: %d\n",
1900 bus->sdcnt.rx_hdrfail++;
1901 brcmf_sdio_rxfail(bus, true, true);
1902 sdio_release_host(bus->sdiodev->func1);
1906 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1907 bus->rxhdr, SDPCM_HDRLEN,
1910 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1911 BRCMF_SDIO_FT_NORMAL)) {
1912 sdio_release_host(bus->sdiodev->func1);
1913 if (!bus->rxpending)
1919 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1920 brcmf_sdio_read_control(bus, bus->rxhdr,
1923 /* prepare the descriptor for the next read */
1924 rd->len = rd->len_nxtfrm << 4;
1926 /* treat all packet as event if we don't know */
1927 rd->channel = SDPCM_EVENT_CHANNEL;
1928 sdio_release_host(bus->sdiodev->func1);
1931 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1932 rd->len - BRCMF_FIRSTREAD : 0;
1933 head_read = BRCMF_FIRSTREAD;
1936 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1938 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1941 /* Give up on data, request rtx of events */
1942 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1943 brcmf_sdio_rxfail(bus, false,
1944 RETRYCHAN(rd->channel));
1945 sdio_release_host(bus->sdiodev->func1);
1948 skb_pull(pkt, head_read);
1949 pkt_align(pkt, rd->len_left, bus->head_align);
1951 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1952 bus->sdcnt.f2rxdata++;
1953 sdio_release_host(bus->sdiodev->func1);
1956 brcmf_err("read %d bytes from channel %d failed: %d\n",
1957 rd->len, rd->channel, ret);
1958 brcmu_pkt_buf_free_skb(pkt);
1959 sdio_claim_host(bus->sdiodev->func1);
1960 brcmf_sdio_rxfail(bus, true,
1961 RETRYCHAN(rd->channel));
1962 sdio_release_host(bus->sdiodev->func1);
1967 skb_push(pkt, head_read);
1968 memcpy(pkt->data, bus->rxhdr, head_read);
1971 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
1972 rd_new.seq_num = rd->seq_num;
1973 sdio_claim_host(bus->sdiodev->func1);
1974 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
1975 BRCMF_SDIO_FT_NORMAL)) {
1977 brcmf_sdio_rxfail(bus, true, true);
1978 sdio_release_host(bus->sdiodev->func1);
1979 brcmu_pkt_buf_free_skb(pkt);
1982 bus->sdcnt.rx_readahead_cnt++;
1983 if (rd->len != roundup(rd_new.len, 16)) {
1984 brcmf_err("frame length mismatch:read %d, should be %d\n",
1986 roundup(rd_new.len, 16) >> 4);
1988 brcmf_sdio_rxfail(bus, true, true);
1989 sdio_release_host(bus->sdiodev->func1);
1990 brcmu_pkt_buf_free_skb(pkt);
1993 sdio_release_host(bus->sdiodev->func1);
1994 rd->len_nxtfrm = rd_new.len_nxtfrm;
1995 rd->channel = rd_new.channel;
1996 rd->dat_offset = rd_new.dat_offset;
1998 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
2001 bus->rxhdr, SDPCM_HDRLEN,
2004 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
2005 brcmf_err("readahead on control packet %d?\n",
2007 /* Force retry w/normal header read */
2009 sdio_claim_host(bus->sdiodev->func1);
2010 brcmf_sdio_rxfail(bus, false, true);
2011 sdio_release_host(bus->sdiodev->func1);
2012 brcmu_pkt_buf_free_skb(pkt);
2017 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
2018 pkt->data, rd->len, "Rx Data:\n");
2020 /* Save superframe descriptor and allocate packet frame */
2021 if (rd->channel == SDPCM_GLOM_CHANNEL) {
2022 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
2023 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2025 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
2028 __skb_trim(pkt, rd->len);
2029 skb_pull(pkt, SDPCM_HDRLEN);
2032 brcmf_err("%s: glom superframe w/o "
2033 "descriptor!\n", __func__);
2034 sdio_claim_host(bus->sdiodev->func1);
2035 brcmf_sdio_rxfail(bus, false, false);
2036 sdio_release_host(bus->sdiodev->func1);
2038 /* prepare the descriptor for the next read */
2039 rd->len = rd->len_nxtfrm << 4;
2041 /* treat all packet as event if we don't know */
2042 rd->channel = SDPCM_EVENT_CHANNEL;
2046 /* Fill in packet len and prio, deliver upward */
2047 __skb_trim(pkt, rd->len);
2048 skb_pull(pkt, rd->dat_offset);
2051 brcmu_pkt_buf_free_skb(pkt);
2052 else if (rd->channel == SDPCM_EVENT_CHANNEL)
2053 brcmf_rx_event(bus->sdiodev->dev, pkt);
2055 brcmf_rx_frame(bus->sdiodev->dev, pkt,
2058 /* prepare the descriptor for the next read */
2059 rd->len = rd->len_nxtfrm << 4;
2061 /* treat all packet as event if we don't know */
2062 rd->channel = SDPCM_EVENT_CHANNEL;
2065 rxcount = maxframes - rxleft;
2066 /* Message if we hit the limit */
2068 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
2070 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2071 /* Back off rxseq if awaiting rtx, update rx_seq */
2074 bus->rx_seq = rd->seq_num;
2080 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2082 wake_up_interruptible(&bus->ctrl_wait);
2086 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2088 struct brcmf_bus_stats *stats;
2092 dat_buf = (u8 *)(pkt->data);
2094 /* Check head padding */
2095 head_pad = ((unsigned long)dat_buf % bus->head_align);
2097 if (skb_headroom(pkt) < head_pad) {
2098 stats = &bus->sdiodev->bus_if->stats;
2099 atomic_inc(&stats->pktcowed);
2100 if (skb_cow_head(pkt, head_pad)) {
2101 atomic_inc(&stats->pktcow_failed);
2106 skb_push(pkt, head_pad);
2107 dat_buf = (u8 *)(pkt->data);
2109 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2114 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2117 /* flag marking a dummy skb added for DMA alignment requirement */
2118 #define ALIGN_SKB_FLAG 0x8000
2119 /* bit mask of data length chopped from the previous packet */
2120 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2122 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2123 struct sk_buff_head *pktq,
2124 struct sk_buff *pkt, u16 total_len)
2126 struct brcmf_sdio_dev *sdiodev;
2127 struct sk_buff *pkt_pad;
2128 u16 tail_pad, tail_chop, chain_pad;
2129 unsigned int blksize;
2133 sdiodev = bus->sdiodev;
2134 blksize = sdiodev->func2->cur_blksize;
2135 /* sg entry alignment should be a divisor of block size */
2136 WARN_ON(blksize % bus->sgentry_align);
2138 /* Check tail padding */
2139 lastfrm = skb_queue_is_last(pktq, pkt);
2141 tail_chop = pkt->len % bus->sgentry_align;
2143 tail_pad = bus->sgentry_align - tail_chop;
2144 chain_pad = (total_len + tail_pad) % blksize;
2145 if (lastfrm && chain_pad)
2146 tail_pad += blksize - chain_pad;
2147 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2148 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
2150 if (pkt_pad == NULL)
2152 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2153 if (unlikely(ret < 0)) {
2157 memcpy(pkt_pad->data,
2158 pkt->data + pkt->len - tail_chop,
2160 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2161 skb_trim(pkt, pkt->len - tail_chop);
2162 skb_trim(pkt_pad, tail_pad + tail_chop);
2163 __skb_queue_after(pktq, pkt, pkt_pad);
2165 ntail = pkt->data_len + tail_pad -
2166 (pkt->end - pkt->tail);
2167 if (skb_cloned(pkt) || ntail > 0)
2168 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2170 if (skb_linearize(pkt))
2172 __skb_put(pkt, tail_pad);
2179 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2180 * @bus: brcmf_sdio structure pointer
2181 * @pktq: packet list pointer
2182 * @chan: virtual channel to transmit the packet
2184 * Processes to be applied to the packet
2185 * - Align data buffer pointer
2186 * - Align data buffer length
2188 * Return: negative value if there is error
2191 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2194 u16 head_pad, total_len;
2195 struct sk_buff *pkt_next;
2198 struct brcmf_sdio_hdrinfo hd_info = {0};
2200 txseq = bus->tx_seq;
2202 skb_queue_walk(pktq, pkt_next) {
2203 /* alignment packet inserted in previous
2204 * loop cycle can be skipped as it is
2205 * already properly aligned and does not
2206 * need an sdpcm header.
2208 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2211 /* align packet data pointer */
2212 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2215 head_pad = (u16)ret;
2217 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
2219 total_len += pkt_next->len;
2221 hd_info.len = pkt_next->len;
2222 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2223 if (bus->txglom && pktq->qlen > 1) {
2224 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2225 pkt_next, total_len);
2228 hd_info.tail_pad = (u16)ret;
2229 total_len += (u16)ret;
2232 hd_info.channel = chan;
2233 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2234 hd_info.seq_num = txseq++;
2236 /* Now fill the header */
2237 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2239 if (BRCMF_BYTES_ON() &&
2240 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2241 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2242 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
2244 else if (BRCMF_HDRS_ON())
2245 brcmf_dbg_hex_dump(true, pkt_next->data,
2246 head_pad + bus->tx_hdrlen,
2249 /* Hardware length tag of the first packet should be total
2250 * length of the chain (including padding)
2253 brcmf_sdio_update_hwhdr(__skb_peek(pktq)->data, total_len);
2258 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2259 * @bus: brcmf_sdio structure pointer
2260 * @pktq: packet list pointer
2262 * Processes to be applied to the packet
2263 * - Remove head padding
2264 * - Remove tail padding
2267 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2272 u16 dummy_flags, chop_len;
2273 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2275 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2276 dummy_flags = *(u16 *)(pkt_next->cb);
2277 if (dummy_flags & ALIGN_SKB_FLAG) {
2278 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2280 pkt_prev = pkt_next->prev;
2281 skb_put(pkt_prev, chop_len);
2283 __skb_unlink(pkt_next, pktq);
2284 brcmu_pkt_buf_free_skb(pkt_next);
2286 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2287 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2288 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2289 SDPCM_DOFFSET_SHIFT;
2290 skb_pull(pkt_next, dat_offset);
2292 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2293 skb_trim(pkt_next, pkt_next->len - tail_pad);
2299 /* Writes a HW/SW header into the packet and sends it. */
2300 /* Assumes: (a) header space already there, (b) caller holds lock */
2301 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2305 struct sk_buff *pkt_next, *tmp;
2307 brcmf_dbg(TRACE, "Enter\n");
2309 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2313 sdio_claim_host(bus->sdiodev->func1);
2314 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2315 bus->sdcnt.f2txdata++;
2318 brcmf_sdio_txfail(bus);
2320 sdio_release_host(bus->sdiodev->func1);
2323 brcmf_sdio_txpkt_postp(bus, pktq);
2325 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2326 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2327 __skb_unlink(pkt_next, pktq);
2328 brcmf_proto_bcdc_txcomplete(bus->sdiodev->dev, pkt_next,
2334 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2336 struct sk_buff *pkt;
2337 struct sk_buff_head pktq;
2338 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus);
2340 int ret = 0, prec_out, i;
2342 u8 tx_prec_map, pkt_num;
2344 brcmf_dbg(TRACE, "Enter\n");
2346 tx_prec_map = ~bus->flowcontrol;
2348 /* Send frames until the limit or some other event */
2349 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2352 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2353 bus->sdiodev->txglomsz);
2354 pkt_num = min_t(u32, pkt_num,
2355 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2356 __skb_queue_head_init(&pktq);
2357 spin_lock_bh(&bus->txq_lock);
2358 for (i = 0; i < pkt_num; i++) {
2359 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2363 __skb_queue_tail(&pktq, pkt);
2365 spin_unlock_bh(&bus->txq_lock);
2369 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2373 /* In poll mode, need to check for other events */
2375 /* Check device status, signal pending interrupt */
2376 sdio_claim_host(bus->sdiodev->func1);
2377 intstatus = brcmf_sdiod_readl(bus->sdiodev,
2378 intstat_addr, &ret);
2379 sdio_release_host(bus->sdiodev->func1);
2381 bus->sdcnt.f2txdata++;
2384 if (intstatus & bus->hostintmask)
2385 atomic_set(&bus->ipend, 1);
2389 /* Deflow-control stack if needed */
2390 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
2391 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2393 brcmf_proto_bcdc_txflowblock(bus->sdiodev->dev, false);
2399 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
2404 struct brcmf_sdio_hdrinfo hd_info = {0};
2407 brcmf_dbg(SDIO, "Enter\n");
2409 /* Back the pointer to make room for bus header */
2410 frame -= bus->tx_hdrlen;
2411 len += bus->tx_hdrlen;
2413 /* Add alignment padding (optional for ctl frames) */
2414 doff = ((unsigned long)frame % bus->head_align);
2418 memset(frame + bus->tx_hdrlen, 0, doff);
2421 /* Round send length to next SDIO block */
2423 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2424 pad = bus->blocksize - (len % bus->blocksize);
2425 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2427 } else if (len % bus->head_align) {
2428 pad = bus->head_align - (len % bus->head_align);
2432 hd_info.len = len - pad;
2433 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2434 hd_info.dat_offset = doff + bus->tx_hdrlen;
2435 hd_info.seq_num = bus->tx_seq;
2436 hd_info.lastfrm = true;
2437 hd_info.tail_pad = pad;
2438 brcmf_sdio_hdpack(bus, frame, &hd_info);
2441 brcmf_sdio_update_hwhdr(frame, len);
2443 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2444 frame, len, "Tx Frame:\n");
2445 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2447 frame, min_t(u16, len, 16), "TxHdr:\n");
2450 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2453 brcmf_sdio_txfail(bus);
2455 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2456 } while (ret < 0 && retries++ < TXRETRIES);
2461 static bool brcmf_chip_is_ulp(struct brcmf_chip *ci)
2463 if (ci->chip == CY_CC_43012_CHIP_ID)
2469 static void brcmf_sdio_bus_stop(struct device *dev)
2471 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2472 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2473 struct brcmf_sdio *bus = sdiodev->bus;
2474 struct brcmf_core *core = bus->sdio_core;
2475 u32 local_hostintmask;
2479 brcmf_dbg(TRACE, "Enter\n");
2481 if (bus->watchdog_tsk) {
2482 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2483 kthread_stop(bus->watchdog_tsk);
2484 bus->watchdog_tsk = NULL;
2487 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
2488 sdio_claim_host(sdiodev->func1);
2490 /* Enable clock for device interrupts */
2491 brcmf_sdio_bus_sleep(bus, false, false);
2493 /* Disable and clear interrupts at the chip level also */
2494 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(hostintmask),
2497 local_hostintmask = bus->hostintmask;
2498 bus->hostintmask = 0;
2500 /* Force backplane clocks to assure F2 interrupt propagates */
2501 saveclk = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2505 bpreq |= brcmf_chip_is_ulp(bus->ci) ?
2506 SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT;
2507 brcmf_sdiod_writeb(sdiodev,
2508 SBSDIO_FUNC1_CHIPCLKCSR,
2512 brcmf_err("Failed to force clock for F2: err %d\n",
2515 /* Turn off the bus (F2), free any pending packets */
2516 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2517 sdio_disable_func(sdiodev->func2);
2519 /* Clear any pending interrupts now that F2 is disabled */
2520 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(intstatus),
2521 local_hostintmask, NULL);
2523 sdio_release_host(sdiodev->func1);
2525 /* Clear the data packet queues */
2526 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2528 /* Clear any held glomming stuff */
2529 brcmu_pkt_buf_free_skb(bus->glomd);
2530 brcmf_sdio_free_glom(bus);
2532 /* Clear rx control and wake any waiters */
2533 spin_lock_bh(&bus->rxctl_lock);
2535 spin_unlock_bh(&bus->rxctl_lock);
2536 brcmf_sdio_dcmd_resp_wake(bus);
2538 /* Reset some F2 state stuff */
2539 bus->rxskip = false;
2540 bus->tx_seq = bus->rx_seq = 0;
2543 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2545 struct brcmf_sdio_dev *sdiodev;
2546 unsigned long flags;
2548 sdiodev = bus->sdiodev;
2549 if (sdiodev->oob_irq_requested) {
2550 spin_lock_irqsave(&sdiodev->irq_en_lock, flags);
2551 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2552 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr);
2553 sdiodev->irq_en = true;
2555 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags);
2559 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2561 struct brcmf_core *core = bus->sdio_core;
2566 addr = core->base + SD_REG(intstatus);
2568 val = brcmf_sdiod_readl(bus->sdiodev, addr, &ret);
2569 bus->sdcnt.f1regdata++;
2573 val &= bus->hostintmask;
2574 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2576 /* Clear interrupts */
2578 brcmf_sdiod_writel(bus->sdiodev, addr, val, &ret);
2579 bus->sdcnt.f1regdata++;
2580 atomic_or(val, &bus->intstatus);
2586 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2588 struct brcmf_sdio_dev *sdiod = bus->sdiodev;
2590 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus);
2591 unsigned long intstatus;
2592 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2593 uint framecnt; /* Temporary counter of tx/rx frames */
2596 brcmf_dbg(SDIO, "Enter\n");
2598 sdio_claim_host(bus->sdiodev->func1);
2600 /* If waiting for HTAVAIL, check status */
2601 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2602 u8 clkctl, devctl = 0;
2605 /* Check for inconsistent device control */
2606 devctl = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2610 /* Read CSR, if clock on switch to AVAIL, else ignore */
2611 clkctl = brcmf_sdiod_readb(bus->sdiodev,
2612 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2614 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2617 if (SBSDIO_HTAV(clkctl)) {
2618 devctl = brcmf_sdiod_readb(bus->sdiodev,
2619 SBSDIO_DEVICE_CTL, &err);
2620 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2621 brcmf_sdiod_writeb(bus->sdiodev,
2622 SBSDIO_DEVICE_CTL, devctl, &err);
2623 bus->clkstate = CLK_AVAIL;
2627 /* Make sure backplane clock is on */
2628 brcmf_sdio_bus_sleep(bus, false, true);
2630 /* Pending interrupt indicates new device status */
2631 if (atomic_read(&bus->ipend) > 0) {
2632 atomic_set(&bus->ipend, 0);
2633 err = brcmf_sdio_intr_rstatus(bus);
2636 /* Start with leftover status bits */
2637 intstatus = atomic_xchg(&bus->intstatus, 0);
2639 /* Handle flow-control change: read new state in case our ack
2640 * crossed another change interrupt. If change still set, assume
2641 * FC ON for safety, let next loop through do the debounce.
2643 if (intstatus & I_HMB_FC_CHANGE) {
2644 intstatus &= ~I_HMB_FC_CHANGE;
2645 brcmf_sdiod_writel(sdiod, intstat_addr, I_HMB_FC_CHANGE, &err);
2647 newstatus = brcmf_sdiod_readl(sdiod, intstat_addr, &err);
2649 bus->sdcnt.f1regdata += 2;
2650 atomic_set(&bus->fcstate,
2651 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2652 intstatus |= (newstatus & bus->hostintmask);
2655 /* Handle host mailbox indication */
2656 if (intstatus & I_HMB_HOST_INT) {
2657 intstatus &= ~I_HMB_HOST_INT;
2658 intstatus |= brcmf_sdio_hostmail(bus);
2661 sdio_release_host(bus->sdiodev->func1);
2663 /* Generally don't ask for these, can get CRC errors... */
2664 if (intstatus & I_WR_OOSYNC) {
2665 brcmf_err("Dongle reports WR_OOSYNC\n");
2666 intstatus &= ~I_WR_OOSYNC;
2669 if (intstatus & I_RD_OOSYNC) {
2670 brcmf_err("Dongle reports RD_OOSYNC\n");
2671 intstatus &= ~I_RD_OOSYNC;
2674 if (intstatus & I_SBINT) {
2675 brcmf_err("Dongle reports SBINT\n");
2676 intstatus &= ~I_SBINT;
2679 /* Would be active due to wake-wlan in gSPI */
2680 if (intstatus & I_CHIPACTIVE) {
2681 brcmf_dbg(SDIO, "Dongle reports CHIPACTIVE\n");
2682 intstatus &= ~I_CHIPACTIVE;
2685 /* Ignore frame indications if rxskip is set */
2687 intstatus &= ~I_HMB_FRAME_IND;
2689 /* On frame indication, read available frames */
2690 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
2691 brcmf_sdio_readframes(bus, bus->rxbound);
2692 if (!bus->rxpending)
2693 intstatus &= ~I_HMB_FRAME_IND;
2696 /* Keep still-pending events for next scheduling */
2698 atomic_or(intstatus, &bus->intstatus);
2700 brcmf_sdio_clrintr(bus);
2702 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
2704 sdio_claim_host(bus->sdiodev->func1);
2705 if (bus->ctrl_frame_stat) {
2706 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
2707 bus->ctrl_frame_len);
2708 bus->ctrl_frame_err = err;
2710 bus->ctrl_frame_stat = false;
2712 brcmf_err("sdio ctrlframe tx failed err=%d\n",
2715 sdio_release_host(bus->sdiodev->func1);
2716 brcmf_sdio_wait_event_wakeup(bus);
2718 /* Send queued frames (limit 1 if rx may still be pending) */
2719 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2720 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
2722 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2724 brcmf_sdio_sendfromq(bus, framecnt);
2727 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
2728 brcmf_err("failed backplane access over SDIO, halting operation\n");
2729 atomic_set(&bus->intstatus, 0);
2730 if (bus->ctrl_frame_stat) {
2731 sdio_claim_host(bus->sdiodev->func1);
2732 if (bus->ctrl_frame_stat) {
2733 bus->ctrl_frame_err = -ENODEV;
2735 bus->ctrl_frame_stat = false;
2736 brcmf_sdio_wait_event_wakeup(bus);
2738 sdio_release_host(bus->sdiodev->func1);
2740 } else if (atomic_read(&bus->intstatus) ||
2741 atomic_read(&bus->ipend) > 0 ||
2742 (!atomic_read(&bus->fcstate) &&
2743 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2745 bus->dpc_triggered = true;
2749 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2751 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2752 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2753 struct brcmf_sdio *bus = sdiodev->bus;
2758 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
2761 int eprec = -1; /* precedence to evict from */
2763 /* Fast case, precedence queue is not full and we are also not
2764 * exceeding total queue length
2766 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
2767 brcmu_pktq_penq(q, prec, pkt);
2771 /* Determine precedence from which to evict packet, if any */
2772 if (pktq_pfull(q, prec)) {
2774 } else if (pktq_full(q)) {
2775 p = brcmu_pktq_peek_tail(q, &eprec);
2780 /* Evict if needed */
2782 /* Detect queueing to unconfigured precedence */
2784 return false; /* refuse newer (incoming) packet */
2785 /* Evict packet according to discard policy */
2786 p = brcmu_pktq_pdeq_tail(q, eprec);
2788 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2789 brcmu_pkt_buf_free_skb(p);
2793 p = brcmu_pktq_penq(q, prec, pkt);
2795 brcmf_err("brcmu_pktq_penq() failed\n");
2800 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2804 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2805 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2806 struct brcmf_sdio *bus = sdiodev->bus;
2808 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
2809 if (sdiodev->state != BRCMF_SDIOD_DATA)
2812 /* Add space for the header */
2813 skb_push(pkt, bus->tx_hdrlen);
2814 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2816 /* In WLAN, priority is always set by the AP using WMM parameters
2817 * and this need not always follow the standard 802.1d priority.
2818 * Based on AP WMM config, map from 802.1d priority to corresponding
2821 prec = brcmf_map_prio_to_prec(bus_if->drvr->config,
2822 (pkt->priority & PRIOMASK));
2824 /* Check for existing queue, current flow-control,
2825 pending event, or pending clock */
2826 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2827 bus->sdcnt.fcqueued++;
2829 /* Priority based enq */
2830 spin_lock_bh(&bus->txq_lock);
2831 /* reset bus_flags in packet cb */
2832 *(u16 *)(pkt->cb) = 0;
2833 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
2834 skb_pull(pkt, bus->tx_hdrlen);
2835 brcmf_err("out of bus->txq !!!\n");
2841 if (pktq_len(&bus->txq) >= TXHI) {
2843 brcmf_proto_bcdc_txflowblock(dev, true);
2845 spin_unlock_bh(&bus->txq_lock);
2848 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2849 qcount[prec] = pktq_plen(&bus->txq, prec);
2852 brcmf_sdio_trigger_dpc(bus);
2857 #define CONSOLE_LINE_MAX 192
2859 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2861 struct brcmf_console *c = &bus->console;
2862 u8 line[CONSOLE_LINE_MAX], ch;
2866 /* Don't do anything until FWREADY updates console address */
2867 if (bus->console_addr == 0)
2870 /* Read console log struct */
2871 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2872 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2877 /* Allocate console buffer (one time only) */
2878 if (c->buf == NULL) {
2879 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2880 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2885 idx = le32_to_cpu(c->log_le.idx);
2887 /* Protect against corrupt value */
2888 if (idx > c->bufsize)
2891 /* Skip reading the console buffer if the index pointer
2896 /* Read the console buffer */
2897 addr = le32_to_cpu(c->log_le.buf);
2898 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2902 while (c->last != idx) {
2903 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2904 if (c->last == idx) {
2905 /* This would output a partial line.
2907 * the buffer pointer and output this
2908 * line next time around.
2913 c->last = c->bufsize - n;
2916 ch = c->buf[c->last];
2917 c->last = (c->last + 1) % c->bufsize;
2924 if (line[n - 1] == '\r')
2927 pr_debug("CONSOLE: %s\n", line);
2937 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2939 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2940 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2941 struct brcmf_sdio *bus = sdiodev->bus;
2944 brcmf_dbg(TRACE, "Enter\n");
2945 if (sdiodev->state != BRCMF_SDIOD_DATA)
2949 bus->ctrl_frame_buf = msg;
2950 bus->ctrl_frame_len = msglen;
2952 bus->ctrl_frame_stat = true;
2954 brcmf_sdio_trigger_dpc(bus);
2955 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
2958 if (bus->ctrl_frame_stat) {
2959 sdio_claim_host(bus->sdiodev->func1);
2960 if (bus->ctrl_frame_stat) {
2961 brcmf_dbg(SDIO, "ctrl_frame timeout\n");
2962 bus->ctrl_frame_stat = false;
2965 sdio_release_host(bus->sdiodev->func1);
2968 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
2969 bus->ctrl_frame_err);
2971 ret = bus->ctrl_frame_err;
2975 bus->sdcnt.tx_ctlerrs++;
2977 bus->sdcnt.tx_ctlpkts++;
2983 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
2984 struct sdpcm_shared *sh)
2986 u32 addr, console_ptr, console_size, console_index;
2987 char *conbuf = NULL;
2991 /* obtain console information from device memory */
2992 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2993 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2994 (u8 *)&sh_val, sizeof(u32));
2997 console_ptr = le32_to_cpu(sh_val);
2999 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
3000 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
3001 (u8 *)&sh_val, sizeof(u32));
3004 console_size = le32_to_cpu(sh_val);
3006 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
3007 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
3008 (u8 *)&sh_val, sizeof(u32));
3011 console_index = le32_to_cpu(sh_val);
3013 /* allocate buffer for console data */
3014 if (console_size <= CONSOLE_BUFFER_MAX)
3015 conbuf = vzalloc(console_size+1);
3020 /* obtain the console data from device */
3021 conbuf[console_size] = '\0';
3022 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
3027 rv = seq_write(seq, conbuf + console_index,
3028 console_size - console_index);
3032 if (console_index > 0)
3033 rv = seq_write(seq, conbuf, console_index - 1);
3040 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
3041 struct sdpcm_shared *sh)
3044 struct brcmf_trap_info tr;
3046 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
3047 brcmf_dbg(INFO, "no trap in firmware\n");
3051 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
3052 sizeof(struct brcmf_trap_info));
3058 "dongle trap info: type 0x%x @ epc 0x%08x\n"
3059 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
3060 " lr 0x%08x pc 0x%08x offset 0x%x\n"
3061 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
3062 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
3063 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
3064 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
3065 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
3066 le32_to_cpu(tr.pc), sh->trap_addr,
3067 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
3068 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
3069 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
3070 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
3072 pr_debug("dongle trap info: type 0x%x @ epc 0x%08x\n"
3073 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
3074 " lr 0x%08x pc 0x%08x offset 0x%x\n"
3075 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
3076 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
3077 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
3078 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
3079 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
3080 le32_to_cpu(tr.pc), sh->trap_addr,
3081 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
3082 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
3083 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
3084 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
3088 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
3089 struct sdpcm_shared *sh)
3092 char file[80] = "?";
3093 char expr[80] = "<???>";
3095 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
3096 brcmf_dbg(INFO, "firmware not built with -assert\n");
3098 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
3099 brcmf_dbg(INFO, "no assert in dongle\n");
3103 sdio_claim_host(bus->sdiodev->func1);
3104 if (sh->assert_file_addr != 0) {
3105 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3106 sh->assert_file_addr, (u8 *)file, 80);
3110 if (sh->assert_exp_addr != 0) {
3111 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3112 sh->assert_exp_addr, (u8 *)expr, 80);
3116 sdio_release_host(bus->sdiodev->func1);
3118 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
3119 file, sh->assert_line, expr);
3123 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3126 struct sdpcm_shared sh;
3128 error = brcmf_sdio_readshared(bus, &sh);
3133 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3134 brcmf_dbg(INFO, "firmware not built with -assert\n");
3135 else if (sh.flags & SDPCM_SHARED_ASSERT)
3136 brcmf_err("assertion in dongle\n");
3138 if (sh.flags & SDPCM_SHARED_TRAP) {
3139 brcmf_err("firmware trap in dongle\n");
3140 brcmf_sdio_trap_info(NULL, bus, &sh);
3146 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
3149 struct sdpcm_shared sh;
3151 error = brcmf_sdio_readshared(bus, &sh);
3155 error = brcmf_sdio_assert_info(seq, bus, &sh);
3159 error = brcmf_sdio_trap_info(seq, bus, &sh);
3163 error = brcmf_sdio_dump_console(seq, bus, &sh);
3169 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
3171 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3172 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
3174 return brcmf_sdio_died_dump(seq, bus);
3177 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
3179 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3180 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3181 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
3184 "intrcount: %u\nlastintrs: %u\n"
3185 "pollcnt: %u\nregfails: %u\n"
3186 "tx_sderrs: %u\nfcqueued: %u\n"
3187 "rxrtx: %u\nrx_toolong: %u\n"
3188 "rxc_errors: %u\nrx_hdrfail: %u\n"
3189 "rx_badhdr: %u\nrx_badseq: %u\n"
3190 "fc_rcvd: %u\nfc_xoff: %u\n"
3191 "fc_xon: %u\nrxglomfail: %u\n"
3192 "rxglomframes: %u\nrxglompkts: %u\n"
3193 "f2rxhdrs: %u\nf2rxdata: %u\n"
3194 "f2txdata: %u\nf1regdata: %u\n"
3195 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3196 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3197 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3198 sdcnt->intrcount, sdcnt->lastintrs,
3199 sdcnt->pollcnt, sdcnt->regfails,
3200 sdcnt->tx_sderrs, sdcnt->fcqueued,
3201 sdcnt->rxrtx, sdcnt->rx_toolong,
3202 sdcnt->rxc_errors, sdcnt->rx_hdrfail,
3203 sdcnt->rx_badhdr, sdcnt->rx_badseq,
3204 sdcnt->fc_rcvd, sdcnt->fc_xoff,
3205 sdcnt->fc_xon, sdcnt->rxglomfail,
3206 sdcnt->rxglomframes, sdcnt->rxglompkts,
3207 sdcnt->f2rxhdrs, sdcnt->f2rxdata,
3208 sdcnt->f2txdata, sdcnt->f1regdata,
3209 sdcnt->tickcnt, sdcnt->tx_ctlerrs,
3210 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
3211 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
3216 static void brcmf_sdio_debugfs_create(struct device *dev)
3218 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3219 struct brcmf_pub *drvr = bus_if->drvr;
3220 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3221 struct brcmf_sdio *bus = sdiodev->bus;
3222 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3224 if (IS_ERR_OR_NULL(dentry))
3227 bus->console_interval = BRCMF_CONSOLE;
3229 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
3230 brcmf_debugfs_add_entry(drvr, "counters",
3231 brcmf_debugfs_sdio_count_read);
3232 debugfs_create_u32("console_interval", 0644, dentry,
3233 &bus->console_interval);
3236 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3241 static void brcmf_sdio_debugfs_create(struct device *dev)
3247 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3253 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3254 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3255 struct brcmf_sdio *bus = sdiodev->bus;
3257 brcmf_dbg(TRACE, "Enter\n");
3258 if (sdiodev->state != BRCMF_SDIOD_DATA)
3261 /* Wait until control frame is available */
3262 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3264 spin_lock_bh(&bus->rxctl_lock);
3266 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3268 buf = bus->rxctl_orig;
3269 bus->rxctl_orig = NULL;
3271 spin_unlock_bh(&bus->rxctl_lock);
3275 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3277 } else if (timeleft == 0) {
3278 brcmf_err("resumed on timeout\n");
3279 brcmf_sdio_checkdied(bus);
3280 } else if (pending) {
3281 brcmf_dbg(CTL, "cancelled\n");
3282 return -ERESTARTSYS;
3284 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3285 brcmf_sdio_checkdied(bus);
3289 bus->sdcnt.rx_ctlpkts++;
3291 bus->sdcnt.rx_ctlerrs++;
3293 return rxlen ? (int)rxlen : -ETIMEDOUT;
3298 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3299 u8 *ram_data, uint ram_sz)
3308 /* read back and verify */
3309 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3311 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3312 /* do not proceed while no memory but */
3318 while (offset < ram_sz) {
3319 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3321 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3323 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3327 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3328 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3343 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3344 u8 *ram_data, uint ram_sz)
3350 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3351 const struct firmware *fw)
3355 brcmf_dbg(TRACE, "Enter\n");
3357 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3358 (u8 *)fw->data, fw->size);
3360 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3361 err, (int)fw->size, bus->ci->rambase);
3362 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3363 (u8 *)fw->data, fw->size))
3369 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3370 void *vars, u32 varsz)
3375 brcmf_dbg(TRACE, "Enter\n");
3377 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3378 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3380 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3381 err, varsz, address);
3382 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3388 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
3389 const struct firmware *fw,
3390 void *nvram, u32 nvlen)
3395 sdio_claim_host(bus->sdiodev->func1);
3396 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3398 rstvec = get_unaligned_le32(fw->data);
3399 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3401 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3402 release_firmware(fw);
3404 brcmf_err("dongle image file download failed\n");
3405 brcmf_fw_nvram_free(nvram);
3409 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
3410 brcmf_fw_nvram_free(nvram);
3412 brcmf_err("dongle nvram file download failed\n");
3416 /* Take arm out of reset */
3417 if (!brcmf_chip_set_active(bus->ci, rstvec)) {
3418 brcmf_err("error getting out of ARM core reset\n");
3423 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3424 sdio_release_host(bus->sdiodev->func1);
3428 static bool brcmf_sdio_aos_no_decode(struct brcmf_sdio *bus)
3430 if (bus->ci->chip == CY_CC_43012_CHIP_ID ||
3431 bus->ci->chip == CY_CC_43752_CHIP_ID)
3437 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3445 brcmf_dbg(TRACE, "Enter\n");
3447 if (brcmf_chip_is_ulp(bus->ci)) {
3448 wakeupctrl = SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT;
3449 chipclkcsr = SBSDIO_HT_AVAIL_REQ;
3451 wakeupctrl = SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3452 chipclkcsr = SBSDIO_FORCE_HT;
3455 if (brcmf_sdio_aos_no_decode(bus)) {
3456 cardcap = SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC;
3458 cardcap = (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3459 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT);
3462 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3464 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3467 val |= 1 << wakeupctrl;
3468 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3470 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3474 /* Add CMD14 Support */
3475 brcmf_sdiod_func0_wb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3479 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3483 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3486 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3491 bus->sr_enabled = true;
3492 brcmf_dbg(INFO, "SR enabled\n");
3495 /* enable KSO bit */
3496 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3498 struct brcmf_core *core = bus->sdio_core;
3502 brcmf_dbg(TRACE, "Enter\n");
3504 /* KSO bit added in SDIO core rev 12 */
3508 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3510 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3514 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3515 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3516 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3517 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3520 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3529 static int brcmf_sdio_bus_preinit(struct device *dev)
3531 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3532 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3533 struct brcmf_sdio *bus = sdiodev->bus;
3534 struct brcmf_core *core = bus->sdio_core;
3539 /* maxctl provided by common layer */
3540 if (WARN_ON(!bus_if->maxctl))
3543 /* Allocate control receive buffer */
3544 bus_if->maxctl += bus->roundup;
3545 value = roundup((bus_if->maxctl + SDPCM_HDRLEN), ALIGNMENT);
3546 value += bus->head_align;
3547 bus->rxbuf = kmalloc(value, GFP_ATOMIC);
3549 bus->rxblen = value;
3551 /* the commands below use the terms tx and rx from
3552 * a device perspective, ie. bus:txglom affects the
3553 * bus transfers from device to host.
3555 if (core->rev < 12) {
3556 /* for sdio core rev < 12, disable txgloming */
3558 err = brcmf_iovar_data_set(dev, "bus:txglom", &iovar,
3561 /* otherwise, set txglomalign */
3562 value = sdiodev->settings->bus.sdio.sd_sgentry_align;
3563 /* SDIO ADMA requires at least 32 bit alignment */
3564 iovar = cpu_to_le32(max_t(u32, value, ALIGNMENT));
3565 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &iovar,
3572 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3573 if (sdiodev->sg_support) {
3574 bus->txglom = false;
3575 iovar = cpu_to_le32(1);
3576 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3577 &iovar, sizeof(iovar));
3579 /* bus:rxglom is allowed to fail */
3583 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3586 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3592 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev)
3594 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3595 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3596 struct brcmf_sdio *bus = sdiodev->bus;
3598 return bus->ci->ramsize - bus->ci->srsize;
3601 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data,
3604 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3605 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3606 struct brcmf_sdio *bus = sdiodev->bus;
3612 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase,
3615 address = bus->ci->rambase;
3617 sdio_claim_host(sdiodev->func1);
3618 while (offset < mem_size) {
3619 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK :
3621 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len);
3623 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3633 sdio_release_host(sdiodev->func1);
3637 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
3639 if (!bus->dpc_triggered) {
3640 bus->dpc_triggered = true;
3641 queue_work(bus->brcmf_wq, &bus->datawork);
3645 void brcmf_sdio_isr(struct brcmf_sdio *bus, bool in_isr)
3647 brcmf_dbg(TRACE, "Enter\n");
3650 brcmf_err("bus is null pointer, exiting\n");
3654 /* Count the interrupt call */
3655 bus->sdcnt.intrcount++;
3657 atomic_set(&bus->ipend, 1);
3659 if (brcmf_sdio_intr_rstatus(bus)) {
3660 brcmf_err("failed backplane access\n");
3663 /* Disable additional interrupts (is this needed now)? */
3665 brcmf_err("isr w/o interrupt configured!\n");
3667 bus->dpc_triggered = true;
3668 queue_work(bus->brcmf_wq, &bus->datawork);
3671 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3673 brcmf_dbg(TIMER, "Enter\n");
3675 /* Poll period: check device if appropriate. */
3676 if (!bus->sr_enabled &&
3677 bus->poll && (++bus->polltick >= bus->pollrate)) {
3680 /* Reset poll tick */
3683 /* Check device if no interrupts */
3685 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3687 if (!bus->dpc_triggered) {
3690 sdio_claim_host(bus->sdiodev->func1);
3691 devpend = brcmf_sdiod_func0_rb(bus->sdiodev,
3692 SDIO_CCCR_INTx, NULL);
3693 sdio_release_host(bus->sdiodev->func1);
3694 intstatus = devpend & (INTR_STATUS_FUNC1 |
3698 /* If there is something, make like the ISR and
3701 bus->sdcnt.pollcnt++;
3702 atomic_set(&bus->ipend, 1);
3704 bus->dpc_triggered = true;
3705 queue_work(bus->brcmf_wq, &bus->datawork);
3709 /* Update interrupt tracking */
3710 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3713 /* Poll for console output periodically */
3714 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() &&
3715 bus->console_interval != 0) {
3716 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL);
3717 if (bus->console.count >= bus->console_interval) {
3718 bus->console.count -= bus->console_interval;
3719 sdio_claim_host(bus->sdiodev->func1);
3720 /* Make sure backplane clock is on */
3721 brcmf_sdio_bus_sleep(bus, false, false);
3722 if (brcmf_sdio_readconsole(bus) < 0)
3724 bus->console_interval = 0;
3725 sdio_release_host(bus->sdiodev->func1);
3730 /* On idle timeout clear activity flag and/or turn off clock */
3731 if (!bus->dpc_triggered) {
3733 if ((!bus->dpc_running) && (bus->idletime > 0) &&
3734 (bus->clkstate == CLK_AVAIL)) {
3736 if (bus->idlecount > bus->idletime) {
3737 brcmf_dbg(SDIO, "idle\n");
3738 sdio_claim_host(bus->sdiodev->func1);
3740 if (!BRCMF_FWCON_ON() ||
3741 bus->console_interval == 0)
3743 brcmf_sdio_wd_timer(bus, false);
3745 brcmf_sdio_bus_sleep(bus, true, false);
3746 sdio_release_host(bus->sdiodev->func1);
3756 static void brcmf_sdio_dataworker(struct work_struct *work)
3758 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3761 bus->dpc_running = true;
3763 while (READ_ONCE(bus->dpc_triggered)) {
3764 bus->dpc_triggered = false;
3765 brcmf_sdio_dpc(bus);
3768 bus->dpc_running = false;
3769 if (brcmf_sdiod_freezing(bus->sdiodev)) {
3770 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
3771 brcmf_sdiod_try_freeze(bus->sdiodev);
3772 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3777 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3778 struct brcmf_chip *ci, u32 drivestrength)
3780 const struct sdiod_drive_str *str_tab = NULL;
3784 u32 drivestrength_sel = 0;
3788 if (!(ci->cc_caps & CC_CAP_PMU))
3791 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3792 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
3793 str_tab = sdiod_drvstr_tab1_1v8;
3794 str_mask = 0x00003800;
3797 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
3798 str_tab = sdiod_drvstr_tab6_1v8;
3799 str_mask = 0x00001800;
3802 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
3803 /* note: 43143 does not support tristate */
3804 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3805 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3806 str_tab = sdiod_drvstr_tab2_3v3;
3807 str_mask = 0x00000007;
3810 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3811 ci->name, drivestrength);
3813 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
3814 str_tab = sdiod_drive_strength_tab5_1v8;
3815 str_mask = 0x00003800;
3819 brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n",
3820 ci->name, ci->chiprev, ci->pmurev);
3824 if (str_tab != NULL) {
3825 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci);
3827 for (i = 0; str_tab[i].strength != 0; i++) {
3828 if (drivestrength >= str_tab[i].strength) {
3829 drivestrength_sel = str_tab[i].sel;
3833 addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
3834 brcmf_sdiod_writel(sdiodev, addr, 1, NULL);
3835 cc_data_temp = brcmf_sdiod_readl(sdiodev, addr, NULL);
3836 cc_data_temp &= ~str_mask;
3837 drivestrength_sel <<= str_shift;
3838 cc_data_temp |= drivestrength_sel;
3839 brcmf_sdiod_writel(sdiodev, addr, cc_data_temp, NULL);
3841 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3842 str_tab[i].strength, drivestrength, cc_data_temp);
3846 static int brcmf_sdio_buscoreprep(void *ctx)
3848 struct brcmf_sdio_dev *sdiodev = ctx;
3852 /* Try forcing SDIO core to do ALPAvail request only */
3853 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3854 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3856 brcmf_err("error writing for HT off\n");
3860 /* If register supported, wait for ALPAvail and then force ALP */
3861 /* This may take up to 15 milliseconds */
3862 clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3864 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3865 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3870 SPINWAIT(((clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3872 !SBSDIO_ALPAV(clkval)),
3873 PMU_MAX_TRANSITION_DLY);
3875 if (!SBSDIO_ALPAV(clkval)) {
3876 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3881 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3882 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3885 /* Also, disable the extra SDIO pull-ups */
3886 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3891 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
3894 struct brcmf_sdio_dev *sdiodev = ctx;
3895 struct brcmf_core *core = sdiodev->bus->sdio_core;
3898 /* clear all interrupts */
3899 reg_addr = core->base + SD_REG(intstatus);
3900 brcmf_sdiod_writel(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3903 /* Write reset vector to address 0 */
3904 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3908 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3910 struct brcmf_sdio_dev *sdiodev = ctx;
3913 val = brcmf_sdiod_readl(sdiodev, addr, NULL);
3916 * this is a bit of special handling if reading the chipcommon chipid
3917 * register. The 4339 is a next-gen of the 4335. It uses the same
3918 * SDIO device id as 4335 and the chipid register returns 4335 as well.
3919 * It can be identified as 4339 by looking at the chip revision. It
3920 * is corrected here so the chip.c module has the right info.
3922 if (addr == CORE_CC_REG(SI_ENUM_BASE_DEFAULT, chipid) &&
3923 (sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4339 ||
3924 sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4335_4339)) {
3925 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3927 val &= ~CID_ID_MASK;
3928 val |= BRCM_CC_4339_CHIP_ID;
3935 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3937 struct brcmf_sdio_dev *sdiodev = ctx;
3939 brcmf_sdiod_writel(sdiodev, addr, val, NULL);
3942 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3943 .prepare = brcmf_sdio_buscoreprep,
3944 .activate = brcmf_sdio_buscore_activate,
3945 .read32 = brcmf_sdio_buscore_read32,
3946 .write32 = brcmf_sdio_buscore_write32,
3950 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3952 struct brcmf_sdio_dev *sdiodev;
3960 sdiodev = bus->sdiodev;
3961 sdio_claim_host(sdiodev->func1);
3963 enum_base = brcmf_chip_enum_base(sdiodev->func1->device);
3965 pr_debug("F1 signature read @0x%08x=0x%4x\n", enum_base,
3966 brcmf_sdiod_readl(sdiodev, enum_base, NULL));
3969 * Force PLL off until brcmf_chip_attach()
3970 * programs PLL control regs
3973 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, BRCMF_INIT_CLKCTL1,
3976 clkctl = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3979 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3980 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3981 err, BRCMF_INIT_CLKCTL1, clkctl);
3985 bus->ci = brcmf_chip_attach(sdiodev, sdiodev->func1->device,
3986 &brcmf_sdio_buscore_ops);
3987 if (IS_ERR(bus->ci)) {
3988 brcmf_err("brcmf_chip_attach failed!\n");
3993 /* Pick up the SDIO core info struct from chip.c */
3994 bus->sdio_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
3995 if (!bus->sdio_core)
3998 /* Pick up the CHIPCOMMON core info struct, for bulk IO in bcmsdh.c */
3999 sdiodev->cc_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_CHIPCOMMON);
4000 if (!sdiodev->cc_core)
4003 sdiodev->settings = brcmf_get_module_param(sdiodev->dev,
4007 if (!sdiodev->settings) {
4008 brcmf_err("Failed to get device parameters\n");
4011 /* platform specific configuration:
4012 * alignments must be at least 4 bytes for ADMA
4014 bus->head_align = ALIGNMENT;
4015 bus->sgentry_align = ALIGNMENT;
4016 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT)
4017 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align;
4018 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT)
4019 bus->sgentry_align =
4020 sdiodev->settings->bus.sdio.sd_sgentry_align;
4022 /* allocate scatter-gather table. sg support
4023 * will be disabled upon allocation failure.
4025 brcmf_sdiod_sgtable_alloc(sdiodev);
4027 #ifdef CONFIG_PM_SLEEP
4028 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ
4029 * is true or when platform data OOB irq is true).
4031 if ((sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_KEEP_POWER) &&
4032 ((sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_WAKE_SDIO_IRQ) ||
4033 (sdiodev->settings->bus.sdio.oob_irq_supported)))
4034 sdiodev->bus_if->wowl_supported = true;
4037 if (brcmf_sdio_kso_init(bus)) {
4038 brcmf_err("error enabling KSO\n");
4042 if (sdiodev->settings->bus.sdio.drive_strength)
4043 drivestrength = sdiodev->settings->bus.sdio.drive_strength;
4045 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
4046 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength);
4048 /* Set card control so an SDIO card reset does a WLAN backplane reset */
4049 reg_val = brcmf_sdiod_func0_rb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err);
4053 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
4055 brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
4059 /* set PMUControl so a backplane reset does PMU state reload */
4060 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol);
4061 reg_val = brcmf_sdiod_readl(sdiodev, reg_addr, &err);
4065 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
4067 brcmf_sdiod_writel(sdiodev, reg_addr, reg_val, &err);
4071 sdio_release_host(sdiodev->func1);
4073 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
4075 /* allocate header buffer */
4076 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
4079 /* Locate an appropriately-aligned portion of hdrbuf */
4080 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
4083 /* Set the poll and/or interrupt flags */
4092 sdio_release_host(sdiodev->func1);
4097 brcmf_sdio_watchdog_thread(void *data)
4099 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
4102 allow_signal(SIGTERM);
4103 /* Run until signal received */
4104 brcmf_sdiod_freezer_count(bus->sdiodev);
4106 if (kthread_should_stop())
4108 brcmf_sdiod_freezer_uncount(bus->sdiodev);
4109 wait = wait_for_completion_interruptible(&bus->watchdog_wait);
4110 brcmf_sdiod_freezer_count(bus->sdiodev);
4111 brcmf_sdiod_try_freeze(bus->sdiodev);
4113 brcmf_sdio_bus_watchdog(bus);
4114 /* Count the tick for reference */
4115 bus->sdcnt.tickcnt++;
4116 reinit_completion(&bus->watchdog_wait);
4124 brcmf_sdio_watchdog(struct timer_list *t)
4126 struct brcmf_sdio *bus = from_timer(bus, t, timer);
4128 if (bus->watchdog_tsk) {
4129 complete(&bus->watchdog_wait);
4130 /* Reschedule the watchdog */
4132 mod_timer(&bus->timer,
4133 jiffies + BRCMF_WD_POLL);
4138 int brcmf_sdio_get_fwname(struct device *dev, const char *ext, u8 *fw_name,
4139 bool board_specific)
4141 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
4142 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
4143 struct brcmf_fw_request *fwreq;
4144 u8 board_ext[BRCMF_FW_NAME_LEN];
4145 struct brcmf_fw_name fwnames[] = {
4149 if (board_specific) {
4150 strlcpy(board_ext, ".", BRCMF_FW_NAME_LEN);
4151 strlcat(board_ext, sdiodev->settings->board_type,
4153 strlcat(board_ext, ext, BRCMF_FW_NAME_LEN);
4154 fwnames[0].extension = board_ext;
4156 fwreq = brcmf_fw_alloc_request(bus_if->chip, bus_if->chiprev,
4158 brcmf_sdio_fwnames_count,
4159 fwnames, ARRAY_SIZE(fwnames));
4167 static int brcmf_sdio_bus_reset(struct device *dev)
4170 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
4171 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
4173 brcmf_dbg(SDIO, "Enter\n");
4175 /* start by unregistering irqs */
4176 brcmf_sdiod_intr_unregister(sdiodev);
4178 brcmf_sdiod_remove(sdiodev);
4180 /* reset the adapter */
4181 sdio_claim_host(sdiodev->func1);
4182 mmc_hw_reset(sdiodev->func1->card->host);
4183 sdio_release_host(sdiodev->func1);
4185 brcmf_bus_change_state(sdiodev->bus_if, BRCMF_BUS_DOWN);
4187 ret = brcmf_sdiod_probe(sdiodev);
4189 brcmf_err("Failed to probe after sdio device reset: ret %d\n",
4196 static const struct brcmf_bus_ops brcmf_sdio_bus_ops = {
4197 .stop = brcmf_sdio_bus_stop,
4198 .preinit = brcmf_sdio_bus_preinit,
4199 .txdata = brcmf_sdio_bus_txdata,
4200 .txctl = brcmf_sdio_bus_txctl,
4201 .rxctl = brcmf_sdio_bus_rxctl,
4202 .gettxq = brcmf_sdio_bus_gettxq,
4203 .wowl_config = brcmf_sdio_wowl_config,
4204 .get_ramsize = brcmf_sdio_bus_get_ramsize,
4205 .get_memdump = brcmf_sdio_bus_get_memdump,
4206 .get_fwname = brcmf_sdio_get_fwname,
4207 .debugfs_create = brcmf_sdio_debugfs_create,
4208 .reset = brcmf_sdio_bus_reset
4211 #define BRCMF_SDIO_FW_CODE 0
4212 #define BRCMF_SDIO_FW_NVRAM 1
4214 static struct brcmf_fw_request *
4215 brcmf_sdio_prepare_fw_request(struct brcmf_sdio *bus);
4217 static void brcmf_sdio_firmware_callback(struct device *dev, int err,
4218 struct brcmf_fw_request *fwreq)
4220 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
4221 struct brcmf_sdio_dev *sdiod = bus_if->bus_priv.sdio;
4222 struct brcmf_sdio *bus = sdiod->bus;
4223 struct brcmf_core *core = bus->sdio_core;
4224 const struct firmware *code;
4230 brcmf_dbg(TRACE, "Enter: dev=%s, err=%d\n", dev_name(dev), err);
4232 if (err && brcmf_sdio_fwnames != sdio_fwnames) {
4233 /* Try again with the standard firmware names */
4234 brcmf_sdio_fwnames = sdio_fwnames;
4235 brcmf_sdio_fwnames_count = ARRAY_SIZE(sdio_fwnames);
4237 fwreq = brcmf_sdio_prepare_fw_request(bus);
4242 err = brcmf_fw_get_firmwares(dev, fwreq,
4243 brcmf_sdio_firmware_callback);
4251 code = fwreq->items[BRCMF_SDIO_FW_CODE].binary;
4252 nvram = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.data;
4253 nvram_len = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.len;
4256 /* try to download image and nvram to the dongle */
4257 bus->alp_only = true;
4258 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
4261 bus->alp_only = false;
4263 /* Start the watchdog timer */
4264 bus->sdcnt.tickcnt = 0;
4265 brcmf_sdio_wd_timer(bus, true);
4267 sdio_claim_host(sdiod->func1);
4269 /* Make sure backplane clock is on, needed to generate F2 interrupt */
4270 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4271 if (bus->clkstate != CLK_AVAIL)
4274 /* Force clocks on backplane to be sure F2 interrupt propagates */
4275 saveclk = brcmf_sdiod_readb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, &err);
4278 bpreq |= brcmf_chip_is_ulp(bus->ci) ?
4279 SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT;
4280 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR,
4284 brcmf_err("Failed to force clock for F2: err %d\n", err);
4288 /* Enable function 2 (frame transfers) */
4289 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailboxdata),
4290 SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, NULL);
4292 err = sdio_enable_func(sdiod->func2);
4294 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
4296 /* If F2 successfully enabled, set core and enable interrupts */
4298 /* Set up the interrupt mask and enable interrupts */
4299 bus->hostintmask = HOSTINTMASK;
4300 brcmf_sdiod_writel(sdiod, core->base + SD_REG(hostintmask),
4301 bus->hostintmask, NULL);
4303 switch (sdiod->func1->device) {
4304 case SDIO_DEVICE_ID_BROADCOM_CYPRESS_4373:
4305 case SDIO_DEVICE_ID_BROADCOM_CYPRESS_43752:
4306 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n",
4307 CY_4373_F2_WATERMARK);
4308 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
4309 CY_4373_F2_WATERMARK, &err);
4310 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL,
4312 devctl |= SBSDIO_DEVCTL_F2WM_ENAB;
4313 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl,
4315 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL,
4316 CY_4373_F1_MESBUSYCTRL, &err);
4318 case SDIO_DEVICE_ID_BROADCOM_CYPRESS_43012:
4319 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n",
4320 CY_43012_F2_WATERMARK);
4321 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
4322 CY_43012_F2_WATERMARK, &err);
4323 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL,
4325 devctl |= SBSDIO_DEVCTL_F2WM_ENAB;
4326 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl,
4328 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL,
4329 CY_43012_MESBUSYCTRL, &err);
4331 case SDIO_DEVICE_ID_BROADCOM_4329:
4332 case SDIO_DEVICE_ID_BROADCOM_4339:
4333 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n",
4334 CY_4339_F2_WATERMARK);
4335 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
4336 CY_4339_F2_WATERMARK, &err);
4337 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL,
4339 devctl |= SBSDIO_DEVCTL_F2WM_ENAB;
4340 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl,
4342 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL,
4343 CY_4339_MESBUSYCTRL, &err);
4345 case SDIO_DEVICE_ID_BROADCOM_43455:
4346 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n",
4347 CY_43455_F2_WATERMARK);
4348 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
4349 CY_43455_F2_WATERMARK, &err);
4350 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL,
4352 devctl |= SBSDIO_DEVCTL_F2WM_ENAB;
4353 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl,
4355 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL,
4356 CY_43455_MESBUSYCTRL, &err);
4358 case SDIO_DEVICE_ID_BROADCOM_4359:
4359 case SDIO_DEVICE_ID_BROADCOM_4354:
4360 case SDIO_DEVICE_ID_BROADCOM_4356:
4361 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n",
4362 CY_435X_F2_WATERMARK);
4363 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
4364 CY_435X_F2_WATERMARK, &err);
4365 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL,
4367 devctl |= SBSDIO_DEVCTL_F2WM_ENAB;
4368 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl,
4370 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL,
4371 CY_435X_F1_MESBUSYCTRL, &err);
4374 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK,
4375 DEFAULT_F2_WATERMARK, &err);
4379 /* Disable F2 again */
4380 sdio_disable_func(sdiod->func2);
4384 if (brcmf_chip_sr_capable(bus->ci)) {
4385 brcmf_sdio_sr_init(bus);
4387 /* Restore previous clock setting */
4388 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR,
4393 /* Assign bus interface call back */
4394 sdiod->bus_if->dev = sdiod->dev;
4395 sdiod->bus_if->ops = &brcmf_sdio_bus_ops;
4396 sdiod->bus_if->chip = bus->ci->chip;
4397 sdiod->bus_if->chiprev = bus->ci->chiprev;
4399 /* Allow full data communication using DPC from now on. */
4400 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
4402 err = brcmf_sdiod_intr_register(sdiod);
4404 brcmf_err("intr register failed:%d\n", err);
4407 /* If we didn't come up, turn off backplane clock */
4409 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4413 sdio_release_host(sdiod->func1);
4415 err = brcmf_alloc(sdiod->dev, sdiod->settings);
4417 brcmf_err("brcmf_alloc failed\n");
4421 /* Attach to the common layer, reserve hdr space */
4422 err = brcmf_attach(sdiod->dev);
4424 brcmf_err("brcmf_attach failed\n");
4432 brcmf_free(sdiod->dev);
4434 sdio_claim_host(sdiod->func1);
4436 brcmf_sdio_checkdied(bus);
4438 sdio_release_host(sdiod->func1);
4440 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
4441 device_release_driver(&sdiod->func2->dev);
4442 device_release_driver(dev);
4445 static struct brcmf_fw_request *
4446 brcmf_sdio_prepare_fw_request(struct brcmf_sdio *bus)
4448 struct brcmf_fw_request *fwreq;
4449 struct brcmf_fw_name fwnames[] = {
4450 { ".bin", bus->sdiodev->fw_name },
4451 { ".txt", bus->sdiodev->nvram_name },
4454 fwreq = brcmf_fw_alloc_request(bus->ci->chip, bus->ci->chiprev,
4456 brcmf_sdio_fwnames_count,
4457 fwnames, ARRAY_SIZE(fwnames));
4461 fwreq->items[BRCMF_SDIO_FW_CODE].type = BRCMF_FW_TYPE_BINARY;
4462 fwreq->items[BRCMF_SDIO_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM;
4463 fwreq->board_type = bus->sdiodev->settings->board_type;
4468 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4471 struct brcmf_sdio *bus;
4472 struct workqueue_struct *wq;
4473 struct brcmf_fw_request *fwreq;
4474 struct brcmf_firmware_mapping *of_fwnames, *fwnames = NULL;
4475 const int fwname_size = sizeof(struct brcmf_firmware_mapping);
4478 brcmf_dbg(TRACE, "Enter\n");
4480 /* Allocate private bus interface state */
4481 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4485 bus->sdiodev = sdiodev;
4487 skb_queue_head_init(&bus->glom);
4488 bus->txbound = BRCMF_TXBOUND;
4489 bus->rxbound = BRCMF_RXBOUND;
4490 bus->txminmax = BRCMF_TXMINMAX;
4491 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4493 /* single-threaded workqueue */
4494 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM | WQ_HIGHPRI,
4495 dev_name(&sdiodev->func1->dev));
4497 brcmf_err("insufficient memory to create txworkqueue\n");
4500 brcmf_sdiod_freezer_count(sdiodev);
4501 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4504 /* attempt to attach to the dongle */
4505 if (!(brcmf_sdio_probe_attach(bus))) {
4506 brcmf_err("brcmf_sdio_probe_attach failed\n");
4510 spin_lock_init(&bus->rxctl_lock);
4511 spin_lock_init(&bus->txq_lock);
4512 init_waitqueue_head(&bus->ctrl_wait);
4513 init_waitqueue_head(&bus->dcmd_resp_wait);
4515 /* Set up the watchdog timer */
4516 timer_setup(&bus->timer, brcmf_sdio_watchdog, 0);
4517 /* Initialize watchdog thread */
4518 init_completion(&bus->watchdog_wait);
4519 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4520 bus, "brcmf_wdog/%s",
4521 dev_name(&sdiodev->func1->dev));
4522 if (IS_ERR(bus->watchdog_tsk)) {
4523 pr_warn("brcmf_watchdog thread failed to start\n");
4524 bus->watchdog_tsk = NULL;
4526 /* Initialize DPC thread */
4527 bus->dpc_triggered = false;
4528 bus->dpc_running = false;
4530 /* default sdio bus header length for tx packet */
4531 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4533 /* Query the F2 block size, set roundup accordingly */
4534 bus->blocksize = bus->sdiodev->func2->cur_blksize;
4535 bus->roundup = min(max_roundup, bus->blocksize);
4537 sdio_claim_host(bus->sdiodev->func1);
4539 /* Disable F2 to clear any intermediate frame state on the dongle */
4540 sdio_disable_func(bus->sdiodev->func2);
4542 bus->rxflow = false;
4544 /* Done with backplane-dependent accesses, can drop clock... */
4545 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4547 sdio_release_host(bus->sdiodev->func1);
4549 /* ...and initialize clock/power states */
4550 bus->clkstate = CLK_SDONLY;
4551 bus->idletime = BRCMF_IDLE_INTERVAL;
4552 bus->idleclock = BRCMF_IDLE_ACTIVE;
4555 bus->sr_enabled = false;
4557 brcmf_dbg(INFO, "completed!!\n");
4559 brcmf_sdio_fwnames = sdio_fwnames;
4560 brcmf_sdio_fwnames_count = ARRAY_SIZE(sdio_fwnames);
4561 of_fwnames = brcmf_of_fwnames(sdiodev->dev, &of_fw_count);
4563 fwnames = devm_kcalloc(sdiodev->dev,
4564 of_fw_count + brcmf_sdio_fwnames_count,
4565 fwname_size, GFP_KERNEL);
4568 /* The array is scanned in order, so overrides come first */
4569 memcpy(fwnames, of_fwnames, of_fw_count * fwname_size);
4570 memcpy(fwnames + of_fw_count, sdio_fwnames,
4571 brcmf_sdio_fwnames_count * fwname_size);
4572 brcmf_sdio_fwnames = fwnames;
4573 brcmf_sdio_fwnames_count += of_fw_count;
4576 fwreq = brcmf_sdio_prepare_fw_request(bus);
4582 ret = brcmf_fw_get_firmwares(sdiodev->dev, fwreq,
4583 brcmf_sdio_firmware_callback);
4585 brcmf_err("async firmware request failed: %d\n", ret);
4593 brcmf_sdio_remove(bus);
4597 /* Detach and free everything */
4598 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4600 brcmf_dbg(TRACE, "Enter\n");
4603 /* Stop watchdog task */
4604 if (bus->watchdog_tsk) {
4605 send_sig(SIGTERM, bus->watchdog_tsk, 1);
4606 kthread_stop(bus->watchdog_tsk);
4607 bus->watchdog_tsk = NULL;
4610 /* De-register interrupt handler */
4611 brcmf_sdiod_intr_unregister(bus->sdiodev);
4613 brcmf_detach(bus->sdiodev->dev);
4614 brcmf_free(bus->sdiodev->dev);
4616 cancel_work_sync(&bus->datawork);
4618 destroy_workqueue(bus->brcmf_wq);
4621 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
4622 sdio_claim_host(bus->sdiodev->func1);
4623 brcmf_sdio_wd_timer(bus, false);
4624 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4625 /* Leave the device in state where it is
4626 * 'passive'. This is done by resetting all
4630 brcmf_chip_set_passive(bus->ci);
4631 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4632 sdio_release_host(bus->sdiodev->func1);
4634 brcmf_chip_detach(bus->ci);
4636 if (bus->sdiodev->settings)
4637 brcmf_release_module_param(bus->sdiodev->settings);
4644 brcmf_dbg(TRACE, "Disconnected\n");
4647 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active)
4649 /* Totally stop the timer */
4650 if (!active && bus->wd_active) {
4651 del_timer_sync(&bus->timer);
4652 bus->wd_active = false;
4656 /* don't start the wd until fw is loaded */
4657 if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
4661 if (!bus->wd_active) {
4662 /* Create timer again when watchdog period is
4663 dynamically changed or in the first instance
4665 bus->timer.expires = jiffies + BRCMF_WD_POLL;
4666 add_timer(&bus->timer);
4667 bus->wd_active = true;
4669 /* Re arm the timer, at last watchdog period */
4670 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL);
4675 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
4679 sdio_claim_host(bus->sdiodev->func1);
4680 ret = brcmf_sdio_bus_sleep(bus, sleep, false);
4681 sdio_release_host(bus->sdiodev->func1);
projects / platform / kernel / linux-rpi.git / blob