2 * SDIO spec header file
3 * Protocol and standard (common) device definitions
5 * Copyright (C) 1999-2015, Broadcom Corporation
7 * Unless you and Broadcom execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2 (the "GPL"),
10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
11 * following added to such license:
13 * As a special exception, the copyright holders of this software give you
14 * permission to link this software with independent modules, and to copy and
15 * distribute the resulting executable under terms of your choice, provided that
16 * you also meet, for each linked independent module, the terms and conditions of
17 * the license of that module. An independent module is a module which is not
18 * derived from this software. The special exception does not apply to any
19 * modifications of the software.
21 * Notwithstanding the above, under no circumstances may you combine this
22 * software in any way with any other Broadcom software provided under a license
23 * other than the GPL, without Broadcom's express prior written consent.
25 * $Id: sdio.h 416730 2013-08-06 09:33:19Z $
32 /* CCCR structure for function 0 */
33 typedef volatile struct {
34 uint8 cccr_sdio_rev; /* RO, cccr and sdio revision */
35 uint8 sd_rev; /* RO, sd spec revision */
36 uint8 io_en; /* I/O enable */
37 uint8 io_rdy; /* I/O ready reg */
38 uint8 intr_ctl; /* Master and per function interrupt enable control */
39 uint8 intr_status; /* RO, interrupt pending status */
40 uint8 io_abort; /* read/write abort or reset all functions */
41 uint8 bus_inter; /* bus interface control */
42 uint8 capability; /* RO, card capability */
44 uint8 cis_base_low; /* 0x9 RO, common CIS base address, LSB */
46 uint8 cis_base_high; /* 0xB RO, common CIS base address, MSB */
48 /* suspend/resume registers */
49 uint8 bus_suspend; /* 0xC */
50 uint8 func_select; /* 0xD */
51 uint8 exec_flag; /* 0xE */
52 uint8 ready_flag; /* 0xF */
54 uint8 fn0_blk_size[2]; /* 0x10(LSB), 0x11(MSB) */
56 uint8 power_control; /* 0x12 (SDIO version 1.10) */
58 uint8 speed_control; /* 0x13 */
61 /* SDIO Device CCCR offsets */
62 #define SDIOD_CCCR_REV 0x00
63 #define SDIOD_CCCR_SDREV 0x01
64 #define SDIOD_CCCR_IOEN 0x02
65 #define SDIOD_CCCR_IORDY 0x03
66 #define SDIOD_CCCR_INTEN 0x04
67 #define SDIOD_CCCR_INTPEND 0x05
68 #define SDIOD_CCCR_IOABORT 0x06
69 #define SDIOD_CCCR_BICTRL 0x07
70 #define SDIOD_CCCR_CAPABLITIES 0x08
71 #define SDIOD_CCCR_CISPTR_0 0x09
72 #define SDIOD_CCCR_CISPTR_1 0x0A
73 #define SDIOD_CCCR_CISPTR_2 0x0B
74 #define SDIOD_CCCR_BUSSUSP 0x0C
75 #define SDIOD_CCCR_FUNCSEL 0x0D
76 #define SDIOD_CCCR_EXECFLAGS 0x0E
77 #define SDIOD_CCCR_RDYFLAGS 0x0F
78 #define SDIOD_CCCR_BLKSIZE_0 0x10
79 #define SDIOD_CCCR_BLKSIZE_1 0x11
80 #define SDIOD_CCCR_POWER_CONTROL 0x12
81 #define SDIOD_CCCR_SPEED_CONTROL 0x13
82 #define SDIOD_CCCR_UHSI_SUPPORT 0x14
83 #define SDIOD_CCCR_DRIVER_STRENGTH 0x15
84 #define SDIOD_CCCR_INTR_EXTN 0x16
86 /* Broadcom extensions (corerev >= 1) */
87 #define SDIOD_CCCR_BRCM_CARDCAP 0xf0
88 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02
89 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04
90 #define SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08
91 #define SDIOD_CCCR_BRCM_CARDCTL 0xf1
92 #define SDIOD_CCCR_BRCM_SEPINT 0xf2
95 #define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */
96 #define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */
97 #define SDIO_SPEC_VERSION_3_0 0x40 /* SDIO spec version 3.0 */
100 #define SD_REV_PHY_MASK 0x0f /* SD format version number */
103 #define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */
104 #define SDIO_FUNC_ENABLE_2 0x04 /* function 2 I/O enable */
107 #define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */
108 #define SDIO_FUNC_READY_2 0x04 /* function 2 I/O ready */
111 #define INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */
112 #define INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */
113 #define INTR_CTL_FUNC2_EN 0x4 /* interrupt enable for function 2 */
116 #define INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */
117 #define INTR_STATUS_FUNC2 0x4 /* interrupt pending for function 2 */
120 #define IO_ABORT_RESET_ALL 0x08 /* I/O card reset */
121 #define IO_ABORT_FUNC_MASK 0x07 /* abort selction: function x */
124 #define BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */
125 #define BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */
126 #define BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */
127 #define BUS_SD_DATA_WIDTH_MASK 0x03 /* bus width mask */
128 #define BUS_SD_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */
129 #define BUS_SD_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */
132 #define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */
133 #define SDIO_CAP_LSC 0x40 /* low speed card */
134 #define SDIO_CAP_E4MI 0x20 /* enable interrupt between block of data in 4-bit mode */
135 #define SDIO_CAP_S4MI 0x10 /* support interrupt between block of data in 4-bit mode */
136 #define SDIO_CAP_SBS 0x08 /* support suspend/resume */
137 #define SDIO_CAP_SRW 0x04 /* support read wait */
138 #define SDIO_CAP_SMB 0x02 /* support multi-block transfer */
139 #define SDIO_CAP_SDC 0x01 /* Support Direct commands during multi-byte transfer */
142 #define SDIO_POWER_SMPC 0x01 /* supports master power control (RO) */
143 #define SDIO_POWER_EMPC 0x02 /* enable master power control (allow > 200mA) (RW) */
145 /* speed_control (control device entry into high-speed clocking mode) */
146 #define SDIO_SPEED_SHS 0x01 /* supports high-speed [clocking] mode (RO) */
147 #define SDIO_SPEED_EHS 0x02 /* enable high-speed [clocking] mode (RW) */
148 #define SDIO_SPEED_UHSI_DDR50 0x08
150 /* for setting bus speed in card: 0x13h */
151 #define SDIO_BUS_SPEED_UHSISEL_M BITFIELD_MASK(3)
152 #define SDIO_BUS_SPEED_UHSISEL_S 1
154 /* for getting bus speed cap in card: 0x14h */
155 #define SDIO_BUS_SPEED_UHSICAP_M BITFIELD_MASK(3)
156 #define SDIO_BUS_SPEED_UHSICAP_S 0
158 /* for getting driver type CAP in card: 0x15h */
159 #define SDIO_BUS_DRVR_TYPE_CAP_M BITFIELD_MASK(3)
160 #define SDIO_BUS_DRVR_TYPE_CAP_S 0
162 /* for setting driver type selection in card: 0x15h */
163 #define SDIO_BUS_DRVR_TYPE_SEL_M BITFIELD_MASK(2)
164 #define SDIO_BUS_DRVR_TYPE_SEL_S 4
166 /* for getting async int support in card: 0x16h */
167 #define SDIO_BUS_ASYNCINT_CAP_M BITFIELD_MASK(1)
168 #define SDIO_BUS_ASYNCINT_CAP_S 0
170 /* for setting async int selection in card: 0x16h */
171 #define SDIO_BUS_ASYNCINT_SEL_M BITFIELD_MASK(1)
172 #define SDIO_BUS_ASYNCINT_SEL_S 1
175 #define SDIO_SEPINT_MASK 0x01 /* route sdpcmdev intr onto separate pad (chip-specific) */
176 #define SDIO_SEPINT_OE 0x02 /* 1 asserts output enable for above pad */
177 #define SDIO_SEPINT_ACT_HI 0x04 /* use active high interrupt level instead of active low */
179 /* FBR structure for function 1-7, FBR addresses and register offsets */
180 typedef volatile struct {
181 uint8 devctr; /* device interface, CSA control */
182 uint8 ext_dev; /* extended standard I/O device type code */
183 uint8 pwr_sel; /* power selection support */
184 uint8 PAD[6]; /* reserved */
186 uint8 cis_low; /* CIS LSB */
188 uint8 cis_high; /* CIS MSB */
189 uint8 csa_low; /* code storage area, LSB */
191 uint8 csa_high; /* code storage area, MSB */
192 uint8 csa_dat_win; /* data access window to function */
194 uint8 fnx_blk_size[2]; /* block size, little endian */
197 /* Maximum number of I/O funcs */
198 #define SDIOD_MAX_FUNCS 8
199 #define SDIOD_MAX_IOFUNCS 7
201 /* SDIO Device FBR Start Address */
202 #define SDIOD_FBR_STARTADDR 0x100
204 /* SDIO Device FBR Size */
205 #define SDIOD_FBR_SIZE 0x100
207 /* Macro to calculate FBR register base */
208 #define SDIOD_FBR_BASE(n) ((n) * 0x100)
210 /* Function register offsets */
211 #define SDIOD_FBR_DEVCTR 0x00 /* basic info for function */
212 #define SDIOD_FBR_EXT_DEV 0x01 /* extended I/O device code */
213 #define SDIOD_FBR_PWR_SEL 0x02 /* power selection bits */
215 /* SDIO Function CIS ptr offset */
216 #define SDIOD_FBR_CISPTR_0 0x09
217 #define SDIOD_FBR_CISPTR_1 0x0A
218 #define SDIOD_FBR_CISPTR_2 0x0B
220 /* Code Storage Area pointer */
221 #define SDIOD_FBR_CSA_ADDR_0 0x0C
222 #define SDIOD_FBR_CSA_ADDR_1 0x0D
223 #define SDIOD_FBR_CSA_ADDR_2 0x0E
224 #define SDIOD_FBR_CSA_DATA 0x0F
226 /* SDIO Function I/O Block Size */
227 #define SDIOD_FBR_BLKSIZE_0 0x10
228 #define SDIOD_FBR_BLKSIZE_1 0x11
231 #define SDIOD_FBR_DEVCTR_DIC 0x0f /* device interface code */
232 #define SDIOD_FBR_DECVTR_CSA 0x40 /* CSA support flag */
233 #define SDIOD_FBR_DEVCTR_CSA_EN 0x80 /* CSA enabled */
234 /* interface codes */
235 #define SDIOD_DIC_NONE 0 /* SDIO standard interface is not supported */
236 #define SDIOD_DIC_UART 1
237 #define SDIOD_DIC_BLUETOOTH_A 2
238 #define SDIOD_DIC_BLUETOOTH_B 3
239 #define SDIOD_DIC_GPS 4
240 #define SDIOD_DIC_CAMERA 5
241 #define SDIOD_DIC_PHS 6
242 #define SDIOD_DIC_WLAN 7
243 #define SDIOD_DIC_EXT 0xf /* extended device interface, read ext_dev register */
246 #define SDIOD_PWR_SEL_SPS 0x01 /* supports power selection */
247 #define SDIOD_PWR_SEL_EPS 0x02 /* enable power selection (low-current mode) */
250 #define SDIO_FUNC_0 0
251 #define SDIO_FUNC_1 1
252 #define SDIO_FUNC_2 2
253 #define SDIO_FUNC_3 3
254 #define SDIO_FUNC_4 4
255 #define SDIO_FUNC_5 5
256 #define SDIO_FUNC_6 6
257 #define SDIO_FUNC_7 7
259 #define SD_CARD_TYPE_UNKNOWN 0 /* bad type or unrecognized */
260 #define SD_CARD_TYPE_IO 1 /* IO only card */
261 #define SD_CARD_TYPE_MEMORY 2 /* memory only card */
262 #define SD_CARD_TYPE_COMBO 3 /* IO and memory combo card */
264 #define SDIO_MAX_BLOCK_SIZE 2048 /* maximum block size for block mode operation */
265 #define SDIO_MIN_BLOCK_SIZE 1 /* minimum block size for block mode operation */
267 /* Card registers: status bit position */
268 #define CARDREG_STATUS_BIT_OUTOFRANGE 31
269 #define CARDREG_STATUS_BIT_COMCRCERROR 23
270 #define CARDREG_STATUS_BIT_ILLEGALCOMMAND 22
271 #define CARDREG_STATUS_BIT_ERROR 19
272 #define CARDREG_STATUS_BIT_IOCURRENTSTATE3 12
273 #define CARDREG_STATUS_BIT_IOCURRENTSTATE2 11
274 #define CARDREG_STATUS_BIT_IOCURRENTSTATE1 10
275 #define CARDREG_STATUS_BIT_IOCURRENTSTATE0 9
276 #define CARDREG_STATUS_BIT_FUN_NUM_ERROR 4
280 #define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */
281 #define SD_CMD_SEND_OPCOND 1
282 #define SD_CMD_MMC_SET_RCA 3
283 #define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */
284 #define SD_CMD_SELECT_DESELECT_CARD 7
285 #define SD_CMD_SEND_CSD 9
286 #define SD_CMD_SEND_CID 10
287 #define SD_CMD_STOP_TRANSMISSION 12
288 #define SD_CMD_SEND_STATUS 13
289 #define SD_CMD_GO_INACTIVE_STATE 15
290 #define SD_CMD_SET_BLOCKLEN 16
291 #define SD_CMD_READ_SINGLE_BLOCK 17
292 #define SD_CMD_READ_MULTIPLE_BLOCK 18
293 #define SD_CMD_WRITE_BLOCK 24
294 #define SD_CMD_WRITE_MULTIPLE_BLOCK 25
295 #define SD_CMD_PROGRAM_CSD 27
296 #define SD_CMD_SET_WRITE_PROT 28
297 #define SD_CMD_CLR_WRITE_PROT 29
298 #define SD_CMD_SEND_WRITE_PROT 30
299 #define SD_CMD_ERASE_WR_BLK_START 32
300 #define SD_CMD_ERASE_WR_BLK_END 33
301 #define SD_CMD_ERASE 38
302 #define SD_CMD_LOCK_UNLOCK 42
303 #define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */
304 #define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */
305 #define SD_CMD_APP_CMD 55
306 #define SD_CMD_GEN_CMD 56
307 #define SD_CMD_READ_OCR 58
308 #define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */
309 #define SD_ACMD_SD_STATUS 13
310 #define SD_ACMD_SEND_NUM_WR_BLOCKS 22
311 #define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23
312 #define SD_ACMD_SD_SEND_OP_COND 41
313 #define SD_ACMD_SET_CLR_CARD_DETECT 42
314 #define SD_ACMD_SEND_SCR 51
316 /* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */
317 #define SD_IO_OP_READ 0 /* Read_Write: Read */
318 #define SD_IO_OP_WRITE 1 /* Read_Write: Write */
319 #define SD_IO_RW_NORMAL 0 /* no RAW */
320 #define SD_IO_RW_RAW 1 /* RAW */
321 #define SD_IO_BYTE_MODE 0 /* Byte Mode */
322 #define SD_IO_BLOCK_MODE 1 /* BlockMode */
323 #define SD_IO_FIXED_ADDRESS 0 /* fix Address */
324 #define SD_IO_INCREMENT_ADDRESS 1 /* IncrementAddress */
326 /* build SD_CMD_IO_RW_DIRECT Argument */
327 #define SDIO_IO_RW_DIRECT_ARG(rw, raw, func, addr, data) \
328 ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((raw) & 1) << 27) | \
329 (((addr) & 0x1FFFF) << 9) | ((data) & 0xFF))
331 /* build SD_CMD_IO_RW_EXTENDED Argument */
332 #define SDIO_IO_RW_EXTENDED_ARG(rw, blk, func, addr, inc_addr, count) \
333 ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((blk) & 1) << 27) | \
334 (((inc_addr) & 1) << 26) | (((addr) & 0x1FFFF) << 9) | ((count) & 0x1FF))
336 /* SDIO response parameters */
337 #define SD_RSP_NO_NONE 0
338 #define SD_RSP_NO_1 1
339 #define SD_RSP_NO_2 2
340 #define SD_RSP_NO_3 3
341 #define SD_RSP_NO_4 4
342 #define SD_RSP_NO_5 5
343 #define SD_RSP_NO_6 6
345 /* Modified R6 response (to CMD3) */
346 #define SD_RSP_MR6_COM_CRC_ERROR 0x8000
347 #define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000
348 #define SD_RSP_MR6_ERROR 0x2000
350 /* Modified R1 in R4 Response (to CMD5) */
351 #define SD_RSP_MR1_SBIT 0x80
352 #define SD_RSP_MR1_PARAMETER_ERROR 0x40
353 #define SD_RSP_MR1_RFU5 0x20
354 #define SD_RSP_MR1_FUNC_NUM_ERROR 0x10
355 #define SD_RSP_MR1_COM_CRC_ERROR 0x08
356 #define SD_RSP_MR1_ILLEGAL_COMMAND 0x04
357 #define SD_RSP_MR1_RFU1 0x02
358 #define SD_RSP_MR1_IDLE_STATE 0x01
360 /* R5 response (to CMD52 and CMD53) */
361 #define SD_RSP_R5_COM_CRC_ERROR 0x80
362 #define SD_RSP_R5_ILLEGAL_COMMAND 0x40
363 #define SD_RSP_R5_IO_CURRENTSTATE1 0x20
364 #define SD_RSP_R5_IO_CURRENTSTATE0 0x10
365 #define SD_RSP_R5_ERROR 0x08
366 #define SD_RSP_R5_RFU 0x04
367 #define SD_RSP_R5_FUNC_NUM_ERROR 0x02
368 #define SD_RSP_R5_OUT_OF_RANGE 0x01
370 #define SD_RSP_R5_ERRBITS 0xCB
373 /* ------------------------------------------------
374 * SDIO Commands and responses
376 * I/O only commands are:
377 * CMD0, CMD3, CMD5, CMD7, CMD14, CMD15, CMD52, CMD53
378 * ------------------------------------------------
382 #define SDIOH_CMD_0 0
383 #define SDIOH_CMD_3 3
384 #define SDIOH_CMD_5 5
385 #define SDIOH_CMD_7 7
386 #define SDIOH_CMD_11 11
387 #define SDIOH_CMD_14 14
388 #define SDIOH_CMD_15 15
389 #define SDIOH_CMD_19 19
390 #define SDIOH_CMD_52 52
391 #define SDIOH_CMD_53 53
392 #define SDIOH_CMD_59 59
394 /* SDIO Command Responses */
395 #define SDIOH_RSP_NONE 0
396 #define SDIOH_RSP_R1 1
397 #define SDIOH_RSP_R2 2
398 #define SDIOH_RSP_R3 3
399 #define SDIOH_RSP_R4 4
400 #define SDIOH_RSP_R5 5
401 #define SDIOH_RSP_R6 6
404 * SDIO Response Error flags
406 #define SDIOH_RSP5_ERROR_FLAGS 0xCB
408 /* ------------------------------------------------
409 * SDIO Command structures. I/O only commands are:
411 * CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53
412 * ------------------------------------------------
415 #define CMD5_OCR_M BITFIELD_MASK(24)
418 #define CMD5_S18R_M BITFIELD_MASK(1)
419 #define CMD5_S18R_S 24
421 #define CMD7_RCA_M BITFIELD_MASK(16)
422 #define CMD7_RCA_S 16
424 #define CMD14_RCA_M BITFIELD_MASK(16)
425 #define CMD14_RCA_S 16
426 #define CMD14_SLEEP_M BITFIELD_MASK(1)
427 #define CMD14_SLEEP_S 15
429 #define CMD_15_RCA_M BITFIELD_MASK(16)
430 #define CMD_15_RCA_S 16
432 #define CMD52_DATA_M BITFIELD_MASK(8) /* Bits [7:0] - Write Data/Stuff bits of CMD52
434 #define CMD52_DATA_S 0
435 #define CMD52_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */
436 #define CMD52_REG_ADDR_S 9
437 #define CMD52_RAW_M BITFIELD_MASK(1) /* Bit 27 - Read after Write flag */
438 #define CMD52_RAW_S 27
439 #define CMD52_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */
440 #define CMD52_FUNCTION_S 28
441 #define CMD52_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */
442 #define CMD52_RW_FLAG_S 31
445 #define CMD53_BYTE_BLK_CNT_M BITFIELD_MASK(9) /* Bits [8:0] - Byte/Block Count of CMD53 */
446 #define CMD53_BYTE_BLK_CNT_S 0
447 #define CMD53_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */
448 #define CMD53_REG_ADDR_S 9
449 #define CMD53_OP_CODE_M BITFIELD_MASK(1) /* Bit 26 - R/W Operation Code */
450 #define CMD53_OP_CODE_S 26
451 #define CMD53_BLK_MODE_M BITFIELD_MASK(1) /* Bit 27 - Block Mode */
452 #define CMD53_BLK_MODE_S 27
453 #define CMD53_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */
454 #define CMD53_FUNCTION_S 28
455 #define CMD53_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */
456 #define CMD53_RW_FLAG_S 31
458 /* ------------------------------------------------------
459 * SDIO Command Response structures for SD1 and SD4 modes
460 * -----------------------------------------------------
462 #define RSP4_IO_OCR_M BITFIELD_MASK(24) /* Bits [23:0] - Card's OCR Bits [23:0] */
463 #define RSP4_IO_OCR_S 0
465 #define RSP4_S18A_M BITFIELD_MASK(1) /* Bits [23:0] - Card's OCR Bits [23:0] */
466 #define RSP4_S18A_S 24
468 #define RSP4_STUFF_M BITFIELD_MASK(3) /* Bits [26:24] - Stuff bits */
469 #define RSP4_STUFF_S 24
470 #define RSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 27 - Memory present */
471 #define RSP4_MEM_PRESENT_S 27
472 #define RSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [30:28] - Number of I/O funcs */
473 #define RSP4_NUM_FUNCS_S 28
474 #define RSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 31 - SDIO card ready */
475 #define RSP4_CARD_READY_S 31
477 #define RSP6_STATUS_M BITFIELD_MASK(16) /* Bits [15:0] - Card status bits [19,22,23,12:0]
479 #define RSP6_STATUS_S 0
480 #define RSP6_IO_RCA_M BITFIELD_MASK(16) /* Bits [31:16] - RCA bits[31-16] */
481 #define RSP6_IO_RCA_S 16
483 #define RSP1_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error */
484 #define RSP1_AKE_SEQ_ERROR_S 3
485 #define RSP1_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */
486 #define RSP1_APP_CMD_S 5
487 #define RSP1_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data (buff empty) */
488 #define RSP1_READY_FOR_DATA_S 8
489 #define RSP1_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - State of card
490 * when Cmd was received
492 #define RSP1_CURR_STATE_S 9
493 #define RSP1_EARSE_RESET_M BITFIELD_MASK(1) /* Bit 13 - Erase seq cleared */
494 #define RSP1_EARSE_RESET_S 13
495 #define RSP1_CARD_ECC_DISABLE_M BITFIELD_MASK(1) /* Bit 14 - Card ECC disabled */
496 #define RSP1_CARD_ECC_DISABLE_S 14
497 #define RSP1_WP_ERASE_SKIP_M BITFIELD_MASK(1) /* Bit 15 - Partial blocks erased due to W/P */
498 #define RSP1_WP_ERASE_SKIP_S 15
499 #define RSP1_CID_CSD_OVERW_M BITFIELD_MASK(1) /* Bit 16 - Illegal write to CID or R/O bits
502 #define RSP1_CID_CSD_OVERW_S 16
503 #define RSP1_ERROR_M BITFIELD_MASK(1) /* Bit 19 - General/Unknown error */
504 #define RSP1_ERROR_S 19
505 #define RSP1_CC_ERROR_M BITFIELD_MASK(1) /* Bit 20 - Internal Card Control error */
506 #define RSP1_CC_ERROR_S 20
507 #define RSP1_CARD_ECC_FAILED_M BITFIELD_MASK(1) /* Bit 21 - Card internal ECC failed
510 #define RSP1_CARD_ECC_FAILED_S 21
511 #define RSP1_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 22 - Cmd not legal for the card state */
512 #define RSP1_ILLEGAL_CMD_S 22
513 #define RSP1_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 23 - CRC check of previous command failed
515 #define RSP1_COM_CRC_ERROR_S 23
516 #define RSP1_LOCK_UNLOCK_FAIL_M BITFIELD_MASK(1) /* Bit 24 - Card lock-unlock Cmd Seq error */
517 #define RSP1_LOCK_UNLOCK_FAIL_S 24
518 #define RSP1_CARD_LOCKED_M BITFIELD_MASK(1) /* Bit 25 - Card locked by the host */
519 #define RSP1_CARD_LOCKED_S 25
520 #define RSP1_WP_VIOLATION_M BITFIELD_MASK(1) /* Bit 26 - Attempt to program
521 * write-protected blocks
523 #define RSP1_WP_VIOLATION_S 26
524 #define RSP1_ERASE_PARAM_M BITFIELD_MASK(1) /* Bit 27 - Invalid erase blocks */
525 #define RSP1_ERASE_PARAM_S 27
526 #define RSP1_ERASE_SEQ_ERR_M BITFIELD_MASK(1) /* Bit 28 - Erase Cmd seq error */
527 #define RSP1_ERASE_SEQ_ERR_S 28
528 #define RSP1_BLK_LEN_ERR_M BITFIELD_MASK(1) /* Bit 29 - Block length error */
529 #define RSP1_BLK_LEN_ERR_S 29
530 #define RSP1_ADDR_ERR_M BITFIELD_MASK(1) /* Bit 30 - Misaligned address */
531 #define RSP1_ADDR_ERR_S 30
532 #define RSP1_OUT_OF_RANGE_M BITFIELD_MASK(1) /* Bit 31 - Cmd arg was out of range */
533 #define RSP1_OUT_OF_RANGE_S 31
536 #define RSP5_DATA_M BITFIELD_MASK(8) /* Bits [0:7] - data */
537 #define RSP5_DATA_S 0
538 #define RSP5_FLAGS_M BITFIELD_MASK(8) /* Bit [15:8] - Rsp flags */
539 #define RSP5_FLAGS_S 8
540 #define RSP5_STUFF_M BITFIELD_MASK(16) /* Bits [31:16] - Stuff bits */
541 #define RSP5_STUFF_S 16
543 /* ----------------------------------------------
544 * SDIO Command Response structures for SPI mode
545 * ----------------------------------------------
547 #define SPIRSP4_IO_OCR_M BITFIELD_MASK(16) /* Bits [15:0] - Card's OCR Bits [23:8] */
548 #define SPIRSP4_IO_OCR_S 0
549 #define SPIRSP4_STUFF_M BITFIELD_MASK(3) /* Bits [18:16] - Stuff bits */
550 #define SPIRSP4_STUFF_S 16
551 #define SPIRSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 19 - Memory present */
552 #define SPIRSP4_MEM_PRESENT_S 19
553 #define SPIRSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [22:20] - Number of I/O funcs */
554 #define SPIRSP4_NUM_FUNCS_S 20
555 #define SPIRSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 23 - SDIO card ready */
556 #define SPIRSP4_CARD_READY_S 23
557 #define SPIRSP4_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - idle state */
558 #define SPIRSP4_IDLE_STATE_S 24
559 #define SPIRSP4_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */
560 #define SPIRSP4_ILLEGAL_CMD_S 26
561 #define SPIRSP4_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */
562 #define SPIRSP4_COM_CRC_ERROR_S 27
563 #define SPIRSP4_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error
565 #define SPIRSP4_FUNC_NUM_ERROR_S 28
566 #define SPIRSP4_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */
567 #define SPIRSP4_PARAM_ERROR_S 30
568 #define SPIRSP4_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */
569 #define SPIRSP4_START_BIT_S 31
571 #define SPIRSP5_DATA_M BITFIELD_MASK(8) /* Bits [23:16] - R/W Data */
572 #define SPIRSP5_DATA_S 16
573 #define SPIRSP5_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - Idle state */
574 #define SPIRSP5_IDLE_STATE_S 24
575 #define SPIRSP5_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */
576 #define SPIRSP5_ILLEGAL_CMD_S 26
577 #define SPIRSP5_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */
578 #define SPIRSP5_COM_CRC_ERROR_S 27
579 #define SPIRSP5_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error
581 #define SPIRSP5_FUNC_NUM_ERROR_S 28
582 #define SPIRSP5_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */
583 #define SPIRSP5_PARAM_ERROR_S 30
584 #define SPIRSP5_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */
585 #define SPIRSP5_START_BIT_S 31
587 /* RSP6 card status format; Pg 68 Physical Layer spec v 1.10 */
588 #define RSP6STAT_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error
590 #define RSP6STAT_AKE_SEQ_ERROR_S 3
591 #define RSP6STAT_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */
592 #define RSP6STAT_APP_CMD_S 5
593 #define RSP6STAT_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data
596 #define RSP6STAT_READY_FOR_DATA_S 8
597 #define RSP6STAT_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - Card state at
600 #define RSP6STAT_CURR_STATE_S 9
601 #define RSP6STAT_ERROR_M BITFIELD_MASK(1) /* Bit 13 - General/Unknown error Bit 19
603 #define RSP6STAT_ERROR_S 13
604 #define RSP6STAT_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 14 - Illegal cmd for
607 #define RSP6STAT_ILLEGAL_CMD_S 14
608 #define RSP6STAT_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 15 - CRC previous command
611 #define RSP6STAT_COM_CRC_ERROR_S 15
613 #define SDIOH_XFER_TYPE_READ SD_IO_OP_READ
614 #define SDIOH_XFER_TYPE_WRITE SD_IO_OP_WRITE
616 /* command issue options */
617 #define CMD_OPTION_DEFAULT 0
618 #define CMD_OPTION_TUNING 1