3 * Software-specific definitions shared between device and host side
5 * Copyright (C) 1999-2015, Broadcom Corporation
7 * Unless you and Broadcom execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2 (the "GPL"),
10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
11 * following added to such license:
13 * As a special exception, the copyright holders of this software give you
14 * permission to link this software with independent modules, and to copy and
15 * distribute the resulting executable under terms of your choice, provided that
16 * you also meet, for each linked independent module, the terms and conditions of
17 * the license of that module. An independent module is a module which is not
18 * derived from this software. The special exception does not apply to any
19 * modifications of the software.
21 * Notwithstanding the above, under no circumstances may you combine this
22 * software in any way with any other Broadcom software provided under a license
23 * other than the GPL, without Broadcom's express prior written consent.
25 * $Id: bcmsdpcm.h 414378 2013-07-24 15:58:50Z $
32 * Software allocation of To SB Mailbox resources
36 #define I_SMB_NAK I_SMB_SW0 /* To SB Mailbox Frame NAK */
37 #define I_SMB_INT_ACK I_SMB_SW1 /* To SB Mailbox Host Interrupt ACK */
38 #define I_SMB_USE_OOB I_SMB_SW2 /* To SB Mailbox Use OOB Wakeup */
39 #define I_SMB_DEV_INT I_SMB_SW3 /* To SB Mailbox Miscellaneous Interrupt */
41 #define I_TOSBMAIL (I_SMB_NAK | I_SMB_INT_ACK | I_SMB_USE_OOB | I_SMB_DEV_INT)
43 /* tosbmailbox bits corresponding to intstatus bits */
44 #define SMB_NAK (1 << 0) /* To SB Mailbox Frame NAK */
45 #define SMB_INT_ACK (1 << 1) /* To SB Mailbox Host Interrupt ACK */
46 #define SMB_USE_OOB (1 << 2) /* To SB Mailbox Use OOB Wakeup */
47 #define SMB_DEV_INT (1 << 3) /* To SB Mailbox Miscellaneous Interrupt */
48 #define SMB_MASK 0x0000000f /* To SB Mailbox Mask */
51 #define SMB_DATA_VERSION_MASK 0x00ff0000 /* host protocol version (sent with F2 enable) */
52 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version (sent with F2 enable) */
55 * Software allocation of To Host Mailbox resources
59 #define I_HMB_FC_STATE I_HMB_SW0 /* To Host Mailbox Flow Control State */
60 #define I_HMB_FC_CHANGE I_HMB_SW1 /* To Host Mailbox Flow Control State Changed */
61 #define I_HMB_FRAME_IND I_HMB_SW2 /* To Host Mailbox Frame Indication */
62 #define I_HMB_HOST_INT I_HMB_SW3 /* To Host Mailbox Miscellaneous Interrupt */
64 #define I_TOHOSTMAIL (I_HMB_FC_CHANGE | I_HMB_FRAME_IND | I_HMB_HOST_INT)
66 /* tohostmailbox bits corresponding to intstatus bits */
67 #define HMB_FC_ON (1 << 0) /* To Host Mailbox Flow Control State */
68 #define HMB_FC_CHANGE (1 << 1) /* To Host Mailbox Flow Control State Changed */
69 #define HMB_FRAME_IND (1 << 2) /* To Host Mailbox Frame Indication */
70 #define HMB_HOST_INT (1 << 3) /* To Host Mailbox Miscellaneous Interrupt */
71 #define HMB_MASK 0x0000000f /* To Host Mailbox Mask */
73 /* tohostmailboxdata */
74 #define HMB_DATA_NAKHANDLED 0x01 /* we're ready to retransmit NAK'd frame to host */
75 #define HMB_DATA_DEVREADY 0x02 /* we're ready to to talk to host after enable */
76 #define HMB_DATA_FC 0x04 /* per prio flowcontrol update flag to host */
77 #define HMB_DATA_FWREADY 0x08 /* firmware is ready for protocol activity */
78 #define HMB_DATA_FWHALT 0x10 /* firmware has halted operation */
80 #define HMB_DATA_FCDATA_MASK 0xff000000 /* per prio flowcontrol data */
81 #define HMB_DATA_FCDATA_SHIFT 24 /* per prio flowcontrol data */
83 #define HMB_DATA_VERSION_MASK 0x00ff0000 /* device protocol version (with devready) */
84 #define HMB_DATA_VERSION_SHIFT 16 /* device protocol version (with devready) */
87 * Software-defined protocol header
90 /* Current protocol version */
91 #define SDPCM_PROT_VERSION 4
94 #define SDPCM_SEQUENCE_MASK 0x000000ff /* Sequence Number Mask */
95 #define SDPCM_PACKET_SEQUENCE(p) (((uint8 *)p)[0] & 0xff) /* p starts w/SW Header */
97 #define SDPCM_CHANNEL_MASK 0x00000f00 /* Channel Number Mask */
98 #define SDPCM_CHANNEL_SHIFT 8 /* Channel Number Shift */
99 #define SDPCM_PACKET_CHANNEL(p) (((uint8 *)p)[1] & 0x0f) /* p starts w/SW Header */
101 #define SDPCM_FLAGS_MASK 0x0000f000 /* Mask of flag bits */
102 #define SDPCM_FLAGS_SHIFT 12 /* Flag bits shift */
103 #define SDPCM_PACKET_FLAGS(p) ((((uint8 *)p)[1] & 0xf0) >> 4) /* p starts w/SW Header */
105 /* Next Read Len: lookahead length of next frame, in 16-byte units (rounded up) */
106 #define SDPCM_NEXTLEN_MASK 0x00ff0000 /* Next Read Len Mask */
107 #define SDPCM_NEXTLEN_SHIFT 16 /* Next Read Len Shift */
108 #define SDPCM_NEXTLEN_VALUE(p) ((((uint8 *)p)[2] & 0xff) << 4) /* p starts w/SW Header */
109 #define SDPCM_NEXTLEN_OFFSET 2
111 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
112 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
113 #define SDPCM_DOFFSET_VALUE(p) (((uint8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
114 #define SDPCM_DOFFSET_MASK 0xff000000
115 #define SDPCM_DOFFSET_SHIFT 24
117 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
118 #define SDPCM_FCMASK_VALUE(p) (((uint8 *)p)[SDPCM_FCMASK_OFFSET ] & 0xff)
119 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
120 #define SDPCM_WINDOW_VALUE(p) (((uint8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
121 #define SDPCM_VERSION_OFFSET 6 /* Version # */
122 #define SDPCM_VERSION_VALUE(p) (((uint8 *)p)[SDPCM_VERSION_OFFSET] & 0xff)
123 #define SDPCM_UNUSED_OFFSET 7 /* Spare */
124 #define SDPCM_UNUSED_VALUE(p) (((uint8 *)p)[SDPCM_UNUSED_OFFSET] & 0xff)
126 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
128 /* logical channel numbers */
129 #define SDPCM_CONTROL_CHANNEL 0 /* Control Request/Response Channel Id */
130 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
131 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
132 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets (superframes) */
133 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
134 #define SDPCM_MAX_CHANNEL 15
136 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for eight-bit frame seq number */
138 #define SDPCM_FLAG_RESVD0 0x01
139 #define SDPCM_FLAG_RESVD1 0x02
140 #define SDPCM_FLAG_GSPI_TXENAB 0x04
141 #define SDPCM_FLAG_GLOMDESC 0x08 /* Superframe descriptor mask */
143 /* For GLOM_CHANNEL frames, use a flag to indicate descriptor frame */
144 #define SDPCM_GLOMDESC_FLAG (SDPCM_FLAG_GLOMDESC << SDPCM_FLAGS_SHIFT)
146 #define SDPCM_GLOMDESC(p) (((uint8 *)p)[1] & 0x80)
148 /* For TEST_CHANNEL packets, define another 4-byte header */
149 #define SDPCM_TEST_HDRLEN 4 /* Generally: Cmd(1), Ext(1), Len(2);
150 * Semantics of Ext byte depend on command.
151 * Len is current or requested frame length, not
152 * including test header; sent little-endian.
154 #define SDPCM_TEST_PKT_CNT_FLD_LEN 4 /* Packet count filed legth */
155 #define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext is a pattern id. */
156 #define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext is a pattern id. */
157 #define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext is a pattern id. */
158 #define SDPCM_TEST_BURST 0x04 /* Receiver to send a burst. Ext is a frame count
159 * (Backward compatabilty) Set frame count in a
160 * 4 byte filed adjacent to the HDR
162 #define SDPCM_TEST_SEND 0x05 /* Receiver sets send mode. Ext is boolean on/off
163 * Set frame count in a 4 byte filed adjacent to
167 /* Handy macro for filling in datagen packets with a pattern */
168 #define SDPCM_TEST_FILL(byteno, id) ((uint8)(id + byteno))
171 * Software counters (first part matches hardware counters)
174 typedef volatile struct {
175 uint32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */
176 uint32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */
177 uint32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */
178 uint32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */
179 uint32 abort; /* AbortCount, SDIO: aborts */
180 uint32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */
181 uint32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */
182 uint32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */
183 uint32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */
184 uint32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */
185 uint32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */
186 uint32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */
187 uint32 rxdescuflo; /* receive descriptor underflows */
188 uint32 rxfifooflo; /* receive fifo overflows */
189 uint32 txfifouflo; /* transmit fifo underflows */
190 uint32 runt; /* runt (too short) frames recv'd from bus */
191 uint32 badlen; /* frame's rxh len does not match its hw tag len */
192 uint32 badcksum; /* frame's hw tag chksum doesn't agree with len value */
193 uint32 seqbreak; /* break in sequence # space from one rx frame to the next */
194 uint32 rxfcrc; /* frame rx header indicates crc error */
195 uint32 rxfwoos; /* frame rx header indicates write out of sync */
196 uint32 rxfwft; /* frame rx header indicates write frame termination */
197 uint32 rxfabort; /* frame rx header indicates frame aborted */
198 uint32 woosint; /* write out of sync interrupt */
199 uint32 roosint; /* read out of sync interrupt */
200 uint32 rftermint; /* read frame terminate interrupt */
201 uint32 wftermint; /* write frame terminate interrupt */
205 * Register Access Macros
208 #define SDIODREV_IS(var, val) ((var) == (val))
209 #define SDIODREV_GE(var, val) ((var) >= (val))
210 #define SDIODREV_GT(var, val) ((var) > (val))
211 #define SDIODREV_LT(var, val) ((var) < (val))
212 #define SDIODREV_LE(var, val) ((var) <= (val))
214 #define SDIODDMAREG32(h, dir, chnl) \
216 (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].xmt) : \
217 (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].rcv))
219 #define SDIODDMAREG64(h, dir, chnl) \
221 (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].xmt) : \
222 (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].rcv))
224 #define SDIODDMAREG(h, dir, chnl) \
225 (SDIODREV_LT((h)->corerev, 1) ? \
226 SDIODDMAREG32((h), (dir), (chnl)) : \
227 SDIODDMAREG64((h), (dir), (chnl)))
229 #define PCMDDMAREG(h, dir, chnl) \
231 (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.xmt) : \
232 (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.rcv))
234 #define SDPCMDMAREG(h, dir, chnl, coreid) \
235 ((coreid) == SDIOD_CORE_ID ? \
236 SDIODDMAREG(h, dir, chnl) : \
237 PCMDDMAREG(h, dir, chnl))
239 #define SDIODFIFOREG(h, corerev) \
240 (SDIODREV_LT((corerev), 1) ? \
241 ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod32.dmafifo)) : \
242 ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod64.dmafifo)))
244 #define PCMDFIFOREG(h) \
245 ((dma32diag_t *)(uintptr)&((h)->regs->dma.pcm32.dmafifo))
247 #define SDPCMFIFOREG(h, coreid, corerev) \
248 ((coreid) == SDIOD_CORE_ID ? \
249 SDIODFIFOREG(h, corerev) : \
253 * Shared structure between dongle and the host.
254 * The structure contains pointers to trap or assert information.
256 #define SDPCM_SHARED_VERSION 0x0001
257 #define SDPCM_SHARED_VERSION_MASK 0x00FF
258 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
259 #define SDPCM_SHARED_ASSERT 0x0200
260 #define SDPCM_SHARED_TRAP 0x0400
261 #define SDPCM_SHARED_IN_BRPT 0x0800
262 #define SDPCM_SHARED_SET_BRPT 0x1000
263 #define SDPCM_SHARED_PENDING_BRPT 0x2000
268 uint32 assert_exp_addr;
269 uint32 assert_file_addr;
271 uint32 console_addr; /* Address of hndrte_cons_t */
272 uint32 msgtrace_addr;
276 extern sdpcm_shared_t sdpcm_shared;
278 /* Function can be used to notify host of FW halt */
279 extern void sdpcmd_fwhalt(void);
281 #endif /* _bcmsdpcm_h_ */