2 * Broadcom BCMSDH to gSPI Protocol Conversion Layer
4 * Copyright (C) 1999-2015, Broadcom Corporation
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
24 * $Id: bcmspibrcm.c 373331 2012-12-07 04:46:22Z $
32 #include <bcmendian.h>
38 #include <sbsdio.h> /* SDIO device core hardware definitions. */
41 #include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
42 #include <sdiovar.h> /* ioctl/iovars */
43 #include <sdio.h> /* SDIO Device and Protocol Specs */
48 #include <bcmspibrcm.h>
50 extern void spi_sendrecv(sdioh_info_t *sd, uint8 *msg_out, uint8 *msg_in, int msglen);
53 #endif /* BCMSPI_ANDROID */
55 /* these are for the older cores... for newer cores we have control for each of them */
56 #define F0_RESPONSE_DELAY 16
57 #define F1_RESPONSE_DELAY 16
58 #define F2_RESPONSE_DELAY F0_RESPONSE_DELAY
61 #define GSPI_F0_RESP_DELAY 0
62 #define GSPI_F1_RESP_DELAY F1_RESPONSE_DELAY
63 #define GSPI_F2_RESP_DELAY 0
64 #define GSPI_F3_RESP_DELAY 0
68 #define DWORDMODE_ON (sd->chip == BCM4329_CHIP_ID) && (sd->chiprev == 2) && (sd->dwordmode == TRUE)
71 #if defined(DHD_DEBUG)
72 uint sd_msglevel = SDH_ERROR_VAL;
77 uint sd_hiok = FALSE; /* Use hi-speed mode if available? */
78 uint sd_sdmode = SDIOH_MODE_SPI; /* Use SD4 mode by default */
79 uint sd_f2_blocksize = 64; /* Default blocksize */
83 uint sd_power = 1; /* Default to SD Slot powered ON */
84 uint sd_clock = 1; /* Default to SD Clock turned ON */
85 uint sd_crc = 0; /* Default to SPI CRC Check turned OFF */
86 uint sd_pci_slot = 0xFFFFffff; /* Used to force selection of a particular PCI slot */
88 uint8 spi_outbuf[SPI_MAX_PKT_LEN];
89 uint8 spi_inbuf[SPI_MAX_PKT_LEN];
91 /* 128bytes buffer is enough to clear data-not-available and program response-delay F0 bits
92 * assuming we will not exceed F0 response delay > 100 bytes at 48MHz.
94 #define BUF2_PKT_LEN 128
95 uint8 spi_outbuf2[BUF2_PKT_LEN];
96 uint8 spi_inbuf2[BUF2_PKT_LEN];
98 uint *dhd_spi_lockcount = NULL;
99 #endif /* BCMSPI_ANDROID */
101 #if !(defined(SPI_PIO_RW_BIGENDIAN) && defined(SPI_PIO_32BIT_RW))
102 #define SPISWAP_WD4(x) bcmswap32(x);
103 #define SPISWAP_WD2(x) (bcmswap16(x & 0xffff)) | \
104 (bcmswap16((x & 0xffff0000) >> 16) << 16);
106 #define SPISWAP_WD4(x) x;
107 #define SPISWAP_WD2(x) bcmswap32by16(x);
111 static bool bcmspi_test_card(sdioh_info_t *sd);
112 static bool bcmspi_host_device_init_adapt(sdioh_info_t *sd);
113 static int bcmspi_set_highspeed_mode(sdioh_info_t *sd, bool hsmode);
114 static int bcmspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd_arg,
115 uint32 *data, uint32 datalen);
116 static int bcmspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr,
117 int regsize, uint32 *data);
118 static int bcmspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr,
119 int regsize, uint32 data);
120 static int bcmspi_card_bytewrite(sdioh_info_t *sd, int func, uint32 regaddr,
122 static int bcmspi_driver_init(sdioh_info_t *sd);
123 static int bcmspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
124 uint32 addr, int nbytes, uint32 *data);
125 static int bcmspi_card_regread_fixedaddr(sdioh_info_t *sd, int func, uint32 regaddr, int regsize,
127 static void bcmspi_cmd_getdstatus(sdioh_info_t *sd, uint32 *dstatus_buffer);
128 static int bcmspi_update_stats(sdioh_info_t *sd, uint32 cmd_arg);
131 * Public entry points & extern's
133 extern sdioh_info_t *
134 sdioh_attach(osl_t *osh, void *bar0, uint irq)
138 sd_trace(("%s\n", __FUNCTION__));
139 if ((sd = (sdioh_info_t *)MALLOC(osh, sizeof(sdioh_info_t))) == NULL) {
140 sd_err(("%s: out of memory, malloced %d bytes\n", __FUNCTION__, MALLOCED(osh)));
143 bzero((char *)sd, sizeof(sdioh_info_t));
145 if (spi_osinit(sd) != 0) {
146 sd_err(("%s: spi_osinit() failed\n", __FUNCTION__));
147 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
151 #ifndef BCMSPI_ANDROID
153 #endif /* !BCMSPI_ANDROID */
155 #ifndef BCMSPI_ANDROID
156 sd->intr_handler = NULL;
157 sd->intr_handler_arg = NULL;
158 sd->intr_handler_valid = FALSE;
159 #endif /* !BCMSPI_ANDROID */
162 sd->use_client_ints = TRUE;
163 sd->sd_use_dma = FALSE; /* DMA Not supported */
165 /* Spi device default is 16bit mode, change to 4 when device is changed to 32bit
170 #ifdef BCMSPI_ANDROID
171 dhd_spi_lockcount = &sd->lockcount;
172 #endif /* BCMSPI_ANDROID */
174 #ifndef BCMSPI_ANDROID
175 if (!spi_hw_attach(sd)) {
176 sd_err(("%s: spi_hw_attach() failed\n", __FUNCTION__));
178 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
181 #endif /* !BCMSPI_ANDROID */
183 if (bcmspi_driver_init(sd) != SUCCESS) {
184 sd_err(("%s: bcmspi_driver_init() failed()\n", __FUNCTION__));
185 #ifndef BCMSPI_ANDROID
187 #endif /* !BCMSPI_ANDROID */
189 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
193 if (spi_register_irq(sd, irq) != SUCCESS) {
194 sd_err(("%s: spi_register_irq() failed for irq = %d\n", __FUNCTION__, irq));
195 #ifndef BCMSPI_ANDROID
197 #endif /* !BCMSPI_ANDROID */
199 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
203 sd_trace(("%s: Done\n", __FUNCTION__));
209 sdioh_detach(osl_t *osh, sdioh_info_t *sd)
211 sd_trace(("%s\n", __FUNCTION__));
213 sd_err(("%s: detaching from hardware\n", __FUNCTION__));
214 spi_free_irq(sd->irq, sd);
215 #ifndef BCMSPI_ANDROID
217 #endif /* !BCMSPI_ANDROID */
219 #ifdef BCMSPI_ANDROID
220 dhd_spi_lockcount = NULL;
221 #endif /* !BCMSPI_ANDROID */
222 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
224 return SDIOH_API_RC_SUCCESS;
227 /* Configure callback to client when we recieve client interrupt */
229 sdioh_interrupt_register(sdioh_info_t *sd, sdioh_cb_fn_t fn, void *argh)
231 sd_trace(("%s: Entering\n", __FUNCTION__));
232 #if !defined(OOB_INTR_ONLY)
233 sd->intr_handler = fn;
234 sd->intr_handler_arg = argh;
235 sd->intr_handler_valid = TRUE;
236 #endif /* !defined(OOB_INTR_ONLY) */
237 return SDIOH_API_RC_SUCCESS;
241 sdioh_interrupt_deregister(sdioh_info_t *sd)
243 sd_trace(("%s: Entering\n", __FUNCTION__));
244 #if !defined(OOB_INTR_ONLY)
245 sd->intr_handler_valid = FALSE;
246 sd->intr_handler = NULL;
247 sd->intr_handler_arg = NULL;
248 #endif /* !defined(OOB_INTR_ONLY) */
249 return SDIOH_API_RC_SUCCESS;
253 sdioh_interrupt_query(sdioh_info_t *sd, bool *onoff)
255 #ifndef BCMSPI_ANDROID
256 sd_trace(("%s: Entering\n", __FUNCTION__));
257 *onoff = sd->client_intr_enabled;
258 #endif /* !BCMSPI_ANDROID */
259 return SDIOH_API_RC_SUCCESS;
262 #if defined(DHD_DEBUG)
264 sdioh_interrupt_pending(sdioh_info_t *sd)
271 sdioh_query_device(sdioh_info_t *sd)
273 /* Return a BRCM ID appropriate to the dongle class */
274 return (sd->num_funcs > 1) ? BCM4329_D11N_ID : BCM4318_D11G_ID;
277 /* Provide dstatus bits of spi-transaction for dhd layers. */
279 sdioh_get_dstatus(sdioh_info_t *sd)
281 return sd->card_dstatus;
285 sdioh_chipinfo(sdioh_info_t *sd, uint32 chip, uint32 chiprev)
288 sd->chiprev = chiprev;
292 sdioh_dwordmode(sdioh_info_t *sd, bool set)
297 if ((status = sdioh_request_byte(sd, SDIOH_READ, SPI_FUNC_0, SPID_STATUS_ENABLE, ®)) !=
299 sd_err(("%s: Failed to set dwordmode in gSPI\n", __FUNCTION__));
304 reg |= DWORD_PKT_LEN_EN;
305 sd->dwordmode = TRUE;
306 sd->client_block_size[SPI_FUNC_2] = 4096; /* h2spi's limit is 4KB, we support 8KB */
308 reg &= ~DWORD_PKT_LEN_EN;
309 sd->dwordmode = FALSE;
310 sd->client_block_size[SPI_FUNC_2] = 2048;
313 if ((status = sdioh_request_byte(sd, SDIOH_WRITE, SPI_FUNC_0, SPID_STATUS_ENABLE, ®)) !=
315 sd_err(("%s: Failed to set dwordmode in gSPI\n", __FUNCTION__));
322 sdioh_query_iofnum(sdioh_info_t *sd)
324 return sd->num_funcs;
348 const bcm_iovar_t sdioh_iovars[] = {
349 {"sd_msglevel", IOV_MSGLEVEL, 0, IOVT_UINT32, 0 },
350 {"sd_blocksize", IOV_BLOCKSIZE, 0, IOVT_UINT32, 0 }, /* ((fn << 16) | size) */
351 {"sd_dma", IOV_DMA, 0, IOVT_BOOL, 0 },
352 {"sd_ints", IOV_USEINTS, 0, IOVT_BOOL, 0 },
353 {"sd_numints", IOV_NUMINTS, 0, IOVT_UINT32, 0 },
354 {"sd_numlocalints", IOV_NUMLOCALINTS, 0, IOVT_UINT32, 0 },
355 {"sd_hostreg", IOV_HOSTREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
356 {"sd_devreg", IOV_DEVREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
357 {"sd_divisor", IOV_DIVISOR, 0, IOVT_UINT32, 0 },
358 {"sd_power", IOV_POWER, 0, IOVT_UINT32, 0 },
359 {"sd_clock", IOV_CLOCK, 0, IOVT_UINT32, 0 },
360 {"sd_mode", IOV_SDMODE, 0, IOVT_UINT32, 100},
361 {"sd_highspeed", IOV_HISPEED, 0, IOVT_UINT32, 0},
362 {"spi_errstats", IOV_SPIERRSTATS, 0, IOVT_BUFFER, sizeof(struct spierrstats_t) },
363 {"spi_respdelay", IOV_RESP_DELAY_ALL, 0, IOVT_BOOL, 0 },
368 sdioh_iovar_op(sdioh_info_t *si, const char *name,
369 void *params, int plen, void *arg, int len, bool set)
371 const bcm_iovar_t *vi = NULL;
384 /* Get must have return space; Set does not take qualifiers */
385 ASSERT(set || (arg && len));
386 ASSERT(!set || (!params && !plen));
388 sd_trace(("%s: Enter (%s %s)\n", __FUNCTION__, (set ? "set" : "get"), name));
390 if ((vi = bcm_iovar_lookup(sdioh_iovars, name)) == NULL) {
391 bcmerror = BCME_UNSUPPORTED;
395 if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, set)) != 0)
398 /* Set up params so get and set can share the convenience variables */
399 if (params == NULL) {
404 if (vi->type == IOVT_VOID)
406 else if (vi->type == IOVT_BUFFER)
409 val_size = sizeof(int);
411 if (plen >= (int)sizeof(int_val))
412 bcopy(params, &int_val, sizeof(int_val));
414 bool_val = (int_val != 0) ? TRUE : FALSE;
416 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
418 case IOV_GVAL(IOV_MSGLEVEL):
419 int_val = (int32)sd_msglevel;
420 bcopy(&int_val, arg, val_size);
423 case IOV_SVAL(IOV_MSGLEVEL):
424 sd_msglevel = int_val;
427 case IOV_GVAL(IOV_BLOCKSIZE):
428 if ((uint32)int_val > si->num_funcs) {
429 bcmerror = BCME_BADARG;
432 int_val = (int32)si->client_block_size[int_val];
433 bcopy(&int_val, arg, val_size);
436 case IOV_GVAL(IOV_DMA):
437 int_val = (int32)si->sd_use_dma;
438 bcopy(&int_val, arg, val_size);
441 case IOV_SVAL(IOV_DMA):
442 si->sd_use_dma = (bool)int_val;
445 case IOV_GVAL(IOV_USEINTS):
446 int_val = (int32)si->use_client_ints;
447 bcopy(&int_val, arg, val_size);
450 case IOV_SVAL(IOV_USEINTS):
453 case IOV_GVAL(IOV_DIVISOR):
454 int_val = (uint32)sd_divisor;
455 bcopy(&int_val, arg, val_size);
458 #ifndef BCMSPI_ANDROID
459 case IOV_SVAL(IOV_DIVISOR):
460 sd_divisor = int_val;
461 if (!spi_start_clock(si, (uint16)sd_divisor)) {
462 sd_err(("%s: set clock failed\n", __FUNCTION__));
463 bcmerror = BCME_ERROR;
466 #endif /* !BCMSPI_ANDROID */
468 case IOV_GVAL(IOV_POWER):
469 int_val = (uint32)sd_power;
470 bcopy(&int_val, arg, val_size);
473 case IOV_SVAL(IOV_POWER):
477 case IOV_GVAL(IOV_CLOCK):
478 int_val = (uint32)sd_clock;
479 bcopy(&int_val, arg, val_size);
482 case IOV_SVAL(IOV_CLOCK):
486 case IOV_GVAL(IOV_SDMODE):
487 int_val = (uint32)sd_sdmode;
488 bcopy(&int_val, arg, val_size);
491 case IOV_SVAL(IOV_SDMODE):
495 case IOV_GVAL(IOV_HISPEED):
496 int_val = (uint32)sd_hiok;
497 bcopy(&int_val, arg, val_size);
500 case IOV_SVAL(IOV_HISPEED):
503 if (!bcmspi_set_highspeed_mode(si, (bool)sd_hiok)) {
504 sd_err(("%s: Failed changing highspeed mode to %d.\n",
505 __FUNCTION__, sd_hiok));
506 bcmerror = BCME_ERROR;
511 case IOV_GVAL(IOV_NUMINTS):
512 int_val = (int32)si->intrcount;
513 bcopy(&int_val, arg, val_size);
516 case IOV_GVAL(IOV_NUMLOCALINTS):
517 int_val = (int32)si->local_intrcount;
518 bcopy(&int_val, arg, val_size);
520 case IOV_GVAL(IOV_DEVREG):
522 sdreg_t *sd_ptr = (sdreg_t *)params;
525 if (sdioh_cfg_read(si, sd_ptr->func, sd_ptr->offset, &data)) {
526 bcmerror = BCME_SDIO_ERROR;
531 bcopy(&int_val, arg, sizeof(int_val));
535 case IOV_SVAL(IOV_DEVREG):
537 sdreg_t *sd_ptr = (sdreg_t *)params;
538 uint8 data = (uint8)sd_ptr->value;
540 if (sdioh_cfg_write(si, sd_ptr->func, sd_ptr->offset, &data)) {
541 bcmerror = BCME_SDIO_ERROR;
548 case IOV_GVAL(IOV_SPIERRSTATS):
550 bcopy(&si->spierrstats, arg, sizeof(struct spierrstats_t));
554 case IOV_SVAL(IOV_SPIERRSTATS):
556 bzero(&si->spierrstats, sizeof(struct spierrstats_t));
560 case IOV_GVAL(IOV_RESP_DELAY_ALL):
561 int_val = (int32)si->resp_delay_all;
562 bcopy(&int_val, arg, val_size);
565 case IOV_SVAL(IOV_RESP_DELAY_ALL):
566 si->resp_delay_all = (bool)int_val;
567 int_val = STATUS_ENABLE|INTR_WITH_STATUS;
568 if (si->resp_delay_all)
569 int_val |= RESP_DELAY_ALL;
571 if (bcmspi_card_regwrite(si, SPI_FUNC_0, SPID_RESPONSE_DELAY, 1,
572 F1_RESPONSE_DELAY) != SUCCESS) {
573 sd_err(("%s: Unable to set response delay.\n", __FUNCTION__));
574 bcmerror = BCME_SDIO_ERROR;
579 if (bcmspi_card_regwrite(si, SPI_FUNC_0, SPID_STATUS_ENABLE, 1, int_val)
581 sd_err(("%s: Unable to set response delay.\n", __FUNCTION__));
582 bcmerror = BCME_SDIO_ERROR;
588 bcmerror = BCME_UNSUPPORTED;
597 sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
600 /* No lock needed since sdioh_request_byte does locking */
601 status = sdioh_request_byte(sd, SDIOH_READ, fnc_num, addr, data);
606 sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
608 /* No lock needed since sdioh_request_byte does locking */
611 if ((fnc_num == SPI_FUNC_1) && (addr == SBSDIO_FUNC1_FRAMECTRL)) {
613 status = sdioh_cfg_read(sd, fnc_num, addr, &dummy_data);
615 sd_err(("sdioh_cfg_read() failed.\n"));
620 status = sdioh_request_byte(sd, SDIOH_WRITE, fnc_num, addr, data);
625 sdioh_cis_read(sdioh_info_t *sd, uint func, uint8 *cisd, uint32 length)
630 uint16 *cis = (uint16 *)cisd;
631 uint bar0 = SI_ENUM_BASE;
635 sd_trace(("%s: Func %d\n", __FUNCTION__, func));
639 /* Set sb window address to 0x18000000 */
640 data = (bar0 >> 8) & SBSDIO_SBADDRLOW_MASK;
641 status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW, &data);
642 if (status == SUCCESS) {
643 data = (bar0 >> 16) & SBSDIO_SBADDRMID_MASK;
644 status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID, &data);
646 sd_err(("%s: Unable to set sb-addr-windows\n", __FUNCTION__));
650 if (status == SUCCESS) {
651 data = (bar0 >> 24) & SBSDIO_SBADDRHIGH_MASK;
652 status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH, &data);
654 sd_err(("%s: Unable to set sb-addr-windows\n", __FUNCTION__));
659 offset = CC_SROM_OTP; /* OTP offset in chipcommon. */
660 for (count = 0; count < length/2; count++) {
661 if (bcmspi_card_regread (sd, SDIO_FUNC_1, offset, 2, &cis_byte) < 0) {
662 sd_err(("%s: regread failed: Can't read CIS\n", __FUNCTION__));
667 *cis = (uint16)cis_byte;
678 sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr, uint8 *byte)
683 uint32 data = (uint32)(*byte);
688 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
689 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
690 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
691 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, rw == SDIOH_READ ? 0 : 1);
692 cmd_arg = SFIELD(cmd_arg, SPI_LEN, 1);
694 if (rw == SDIOH_READ) {
695 sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x\n",
696 __FUNCTION__, cmd_arg, func, regaddr));
698 sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x data=0x%x\n",
699 __FUNCTION__, cmd_arg, func, regaddr, data));
702 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, 1)) != SUCCESS) {
707 if (rw == SDIOH_READ) {
709 sd_trace(("%s: RD result=0x%x\n", __FUNCTION__, *byte));
712 bcmspi_cmd_getdstatus(sd, &dstatus);
714 sd_trace(("dstatus=0x%x\n", dstatus));
717 return SDIOH_API_RC_SUCCESS;
721 sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func, uint addr,
722 uint32 *word, uint nbytes)
728 if (rw == SDIOH_READ)
729 status = bcmspi_card_regread(sd, func, addr, nbytes, word);
731 status = bcmspi_card_regwrite(sd, func, addr, nbytes, *word);
734 return (status == SUCCESS ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
738 sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint rw, uint func,
739 uint addr, uint reg_width, uint buflen_u, uint8 *buffer, void *pkt)
742 int buflen = (int)buflen_u;
743 bool fifo = (fix_inc == SDIOH_DATA_FIX);
747 ASSERT(reg_width == 4);
748 ASSERT(buflen_u < (1 << 30));
749 ASSERT(sd->client_block_size[func]);
751 sd_data(("%s: %c len %d r_cnt %d t_cnt %d, pkt @0x%p\n",
752 __FUNCTION__, rw == SDIOH_READ ? 'R' : 'W',
753 buflen_u, sd->r_cnt, sd->t_cnt, pkt));
755 /* Break buffer down into blocksize chunks. */
757 len = MIN(sd->client_block_size[func], buflen);
758 if (bcmspi_card_buf(sd, rw, func, fifo, addr, len, (uint32 *)buffer) != SUCCESS) {
759 sd_err(("%s: bcmspi_card_buf %s failed\n",
760 __FUNCTION__, rw == SDIOH_READ ? "Read" : "Write"));
762 return SDIOH_API_RC_FAIL;
770 return SDIOH_API_RC_SUCCESS;
773 /* This function allows write to gspi bus when another rd/wr function is deep down the call stack.
774 * Its main aim is to have simpler spi writes rather than recursive writes.
775 * e.g. When there is a need to program response delay on the fly after detecting the SPI-func
776 * this call will allow to program the response delay.
779 bcmspi_card_byterewrite(sdioh_info_t *sd, int func, uint32 regaddr, uint8 byte)
787 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
788 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
789 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
790 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
791 cmd_arg = SFIELD(cmd_arg, SPI_LEN, datalen);
793 sd_trace(("%s cmd_arg = 0x%x\n", __FUNCTION__, cmd_arg));
796 /* Set up and issue the SPI command. MSByte goes out on bus first. Increase datalen
797 * according to the wordlen mode(16/32bit) the device is in.
799 ASSERT(sd->wordlen == 4 || sd->wordlen == 2);
800 datalen = ROUNDUP(datalen, sd->wordlen);
802 /* Start by copying command in the spi-outbuffer */
803 if (sd->wordlen == 4) { /* 32bit spid */
804 *(uint32 *)spi_outbuf2 = SPISWAP_WD4(cmd_arg);
806 datalen += (4 - (datalen & 0x3));
807 } else if (sd->wordlen == 2) { /* 16bit spid */
808 *(uint32 *)spi_outbuf2 = SPISWAP_WD2(cmd_arg);
812 sd_err(("%s: Host is %d bit spid, could not create SPI command.\n",
813 __FUNCTION__, 8 * sd->wordlen));
817 /* for Write, put the data into the output buffer */
819 if (sd->wordlen == 4) { /* 32bit spid */
820 *(uint32 *)&spi_outbuf2[CMDLEN] = SPISWAP_WD4(byte);
821 } else if (sd->wordlen == 2) { /* 16bit spid */
822 *(uint32 *)&spi_outbuf2[CMDLEN] = SPISWAP_WD2(byte);
826 /* +4 for cmd, +4 for dstatus */
827 hostlen = datalen + 8;
828 hostlen += (4 - (hostlen & 0x3));
829 spi_sendrecv(sd, spi_outbuf2, spi_inbuf2, hostlen);
831 /* Last 4bytes are dstatus. Device is configured to return status bits. */
832 if (sd->wordlen == 4) { /* 32bit spid */
833 sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
834 } else if (sd->wordlen == 2) { /* 16bit spid */
835 sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
837 sd_err(("%s: Host is %d bit machine, could not read SPI dstatus.\n",
838 __FUNCTION__, 8 * sd->wordlen));
842 if (sd->card_dstatus)
843 sd_trace(("dstatus after byte rewrite = 0x%x\n", sd->card_dstatus));
848 /* Program the response delay corresponding to the spi function */
850 bcmspi_prog_resp_delay(sdioh_info_t *sd, int func, uint8 resp_delay)
852 if (sd->resp_delay_all == FALSE)
855 if (sd->prev_fun == func)
858 if (F0_RESPONSE_DELAY == F1_RESPONSE_DELAY)
861 bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_RESPONSE_DELAY, resp_delay);
863 /* Remember function for which to avoid reprogramming resp-delay in next iteration */
870 #define GSPI_RESYNC_PATTERN 0x0
872 /* A resync pattern is a 32bit MOSI line with all zeros. Its a special command in gSPI.
873 * It resets the spi-bkplane logic so that all F1 related ping-pong buffer logic is
874 * synchronised and all queued resuests are cancelled.
877 bcmspi_resync_f1(sdioh_info_t *sd)
879 uint32 cmd_arg = GSPI_RESYNC_PATTERN, data = 0, datalen = 0;
882 /* Set up and issue the SPI command. MSByte goes out on bus first. Increase datalen
883 * according to the wordlen mode(16/32bit) the device is in.
885 ASSERT(sd->wordlen == 4 || sd->wordlen == 2);
886 datalen = ROUNDUP(datalen, sd->wordlen);
888 /* Start by copying command in the spi-outbuffer */
889 *(uint32 *)spi_outbuf2 = cmd_arg;
891 /* for Write, put the data into the output buffer */
892 *(uint32 *)&spi_outbuf2[CMDLEN] = data;
894 /* +4 for cmd, +4 for dstatus */
895 spi_sendrecv(sd, spi_outbuf2, spi_inbuf2, datalen + 8);
897 /* Last 4bytes are dstatus. Device is configured to return status bits. */
898 if (sd->wordlen == 4) { /* 32bit spid */
899 sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
900 } else if (sd->wordlen == 2) { /* 16bit spid */
901 sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
903 sd_err(("%s: Host is %d bit machine, could not read SPI dstatus.\n",
904 __FUNCTION__, 8 * sd->wordlen));
908 if (sd->card_dstatus)
909 sd_trace(("dstatus after resync pattern write = 0x%x\n", sd->card_dstatus));
914 uint32 dstatus_count = 0;
917 bcmspi_update_stats(sdioh_info_t *sd, uint32 cmd_arg)
919 uint32 dstatus = sd->card_dstatus;
920 struct spierrstats_t *spierrstats = &sd->spierrstats;
923 sd_trace(("cmd = 0x%x, dstatus = 0x%x\n", cmd_arg, dstatus));
925 /* Store dstatus of last few gSPI transactions */
926 spierrstats->dstatus[dstatus_count % NUM_PREV_TRANSACTIONS] = dstatus;
927 spierrstats->spicmd[dstatus_count % NUM_PREV_TRANSACTIONS] = cmd_arg;
930 if (sd->card_init_done == FALSE)
933 if (dstatus & STATUS_DATA_NOT_AVAILABLE) {
935 sd_trace(("Read data not available on F1 addr = 0x%x\n",
936 GFIELD(cmd_arg, SPI_REG_ADDR)));
938 bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_INTR_REG, DATA_UNAVAILABLE);
941 if (dstatus & STATUS_UNDERFLOW) {
942 spierrstats->rdunderflow++;
943 sd_err(("FIFO underflow happened due to current F2 read command.\n"));
946 if (dstatus & STATUS_OVERFLOW) {
947 spierrstats->wroverflow++;
948 sd_err(("FIFO overflow happened due to current (F1/F2) write command.\n"));
949 bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_INTR_REG, F1_OVERFLOW);
950 bcmspi_resync_f1(sd);
951 sd_err(("Recovering from F1 FIFO overflow.\n"));
954 if (dstatus & STATUS_F2_INTR) {
955 spierrstats->f2interrupt++;
956 sd_trace(("Interrupt from F2. SW should clear corresponding IntStatus bits\n"));
959 if (dstatus & STATUS_F3_INTR) {
960 spierrstats->f3interrupt++;
961 sd_err(("Interrupt from F3. SW should clear corresponding IntStatus bits\n"));
964 if (dstatus & STATUS_HOST_CMD_DATA_ERR) {
965 spierrstats->hostcmddataerr++;
966 sd_err(("Error in CMD or Host data, detected by CRC/Checksum (optional)\n"));
969 if (dstatus & STATUS_F2_PKT_AVAILABLE) {
970 spierrstats->f2pktavailable++;
971 sd_trace(("Packet is available/ready in F2 TX FIFO\n"));
972 sd_trace(("Packet length = %d\n", sd->dwordmode ?
973 ((dstatus & STATUS_F2_PKT_LEN_MASK) >> (STATUS_F2_PKT_LEN_SHIFT - 2)) :
974 ((dstatus & STATUS_F2_PKT_LEN_MASK) >> STATUS_F2_PKT_LEN_SHIFT)));
977 if (dstatus & STATUS_F3_PKT_AVAILABLE) {
978 spierrstats->f3pktavailable++;
979 sd_err(("Packet is available/ready in F3 TX FIFO\n"));
980 sd_err(("Packet length = %d\n",
981 (dstatus & STATUS_F3_PKT_LEN_MASK) >> STATUS_F3_PKT_LEN_SHIFT));
988 sdioh_abort(sdioh_info_t *sd, uint func)
994 sdioh_start(sdioh_info_t *sd, int stage)
1000 sdioh_stop(sdioh_info_t *sd)
1006 sdioh_waitlockfree(sdioh_info_t *sd)
1013 * Private/Static work routines
1016 bcmspi_host_init(sdioh_info_t *sd)
1019 /* Default power on mode */
1020 sd->sd_mode = SDIOH_MODE_SPI;
1021 sd->polled_mode = TRUE;
1022 sd->host_init_done = TRUE;
1023 sd->card_init_done = FALSE;
1024 sd->adapter_slot = 1;
1030 get_client_blocksize(sdioh_info_t *sd)
1035 /* Find F1/F2/F3 max packet size */
1036 if ((status = bcmspi_card_regread(sd, 0, SPID_F1_INFO_REG,
1037 8, regdata)) != SUCCESS) {
1041 sd_trace(("pkt_size regdata[0] = 0x%x, regdata[1] = 0x%x\n",
1042 regdata[0], regdata[1]));
1044 sd->client_block_size[1] = (regdata[0] & F1_MAX_PKT_SIZE) >> 2;
1045 sd_trace(("Func1 blocksize = %d\n", sd->client_block_size[1]));
1046 ASSERT(sd->client_block_size[1] == BLOCK_SIZE_F1);
1048 sd->client_block_size[2] = ((regdata[0] >> 16) & F2_MAX_PKT_SIZE) >> 2;
1049 sd_trace(("Func2 blocksize = %d\n", sd->client_block_size[2]));
1050 ASSERT(sd->client_block_size[2] == BLOCK_SIZE_F2);
1052 sd->client_block_size[3] = (regdata[1] & F3_MAX_PKT_SIZE) >> 2;
1053 sd_trace(("Func3 blocksize = %d\n", sd->client_block_size[3]));
1054 ASSERT(sd->client_block_size[3] == BLOCK_SIZE_F3);
1060 bcmspi_client_init(sdioh_info_t *sd)
1062 uint32 status_en_reg = 0;
1063 sd_trace(("%s: Powering up slot %d\n", __FUNCTION__, sd->adapter_slot));
1065 #ifndef BCMSPI_ANDROID
1067 if (!spi_start_clock(sd, (uint16)sd_divisor)) {
1068 sd_err(("spi_start_clock failed\n"));
1072 /* Start at ~400KHz clock rate for initialization */
1073 if (!spi_start_clock(sd, 128)) {
1074 sd_err(("spi_start_clock failed\n"));
1078 #endif /* !BCMSPI_ANDROID */
1080 if (!bcmspi_host_device_init_adapt(sd)) {
1081 sd_err(("bcmspi_host_device_init_adapt failed\n"));
1085 if (!bcmspi_test_card(sd)) {
1086 sd_err(("bcmspi_test_card failed\n"));
1090 sd->num_funcs = SPI_MAX_IOFUNCS;
1092 get_client_blocksize(sd);
1094 /* Apply resync pattern cmd with all zeros to reset spi-bkplane F1 logic */
1095 bcmspi_resync_f1(sd);
1097 sd->dwordmode = FALSE;
1099 bcmspi_card_regread(sd, 0, SPID_STATUS_ENABLE, 1, &status_en_reg);
1101 sd_trace(("%s: Enabling interrupt with dstatus \n", __FUNCTION__));
1102 status_en_reg |= INTR_WITH_STATUS;
1104 if (bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_STATUS_ENABLE, 1,
1105 status_en_reg & 0xff) != SUCCESS) {
1106 sd_err(("%s: Unable to set response delay for all fun's.\n", __FUNCTION__));
1111 #ifndef BCMSPI_ANDROID
1112 /* After configuring for High-Speed mode, set the desired clock rate. */
1113 if (!spi_start_clock(sd, 4)) {
1114 sd_err(("spi_start_clock failed\n"));
1117 #endif /* !BCMSPI_ANDROID */
1120 /* check to see if the response delay needs to be programmed properly */
1122 uint32 f1_respdelay = 0;
1123 bcmspi_card_regread(sd, 0, SPID_RESP_DELAY_F1, 1, &f1_respdelay);
1124 if ((f1_respdelay == 0) || (f1_respdelay == 0xFF)) {
1125 /* older sdiodevice core and has no separte resp delay for each of */
1126 sd_err(("older corerev < 4 so use the same resp delay for all funcs\n"));
1127 sd->resp_delay_new = FALSE;
1130 /* older sdiodevice core and has no separte resp delay for each of */
1132 sd->resp_delay_new = TRUE;
1133 sd_err(("new corerev >= 4 so set the resp delay for each of the funcs\n"));
1134 sd_trace(("resp delay for funcs f0(%d), f1(%d), f2(%d), f3(%d)\n",
1135 GSPI_F0_RESP_DELAY, GSPI_F1_RESP_DELAY,
1136 GSPI_F2_RESP_DELAY, GSPI_F3_RESP_DELAY));
1137 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F0, 1,
1138 GSPI_F0_RESP_DELAY);
1139 if (ret_val != SUCCESS) {
1140 sd_err(("%s: Unable to set response delay for F0\n", __FUNCTION__));
1143 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F1, 1,
1144 GSPI_F1_RESP_DELAY);
1145 if (ret_val != SUCCESS) {
1146 sd_err(("%s: Unable to set response delay for F1\n", __FUNCTION__));
1149 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F2, 1,
1150 GSPI_F2_RESP_DELAY);
1151 if (ret_val != SUCCESS) {
1152 sd_err(("%s: Unable to set response delay for F2\n", __FUNCTION__));
1155 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F3, 1,
1156 GSPI_F3_RESP_DELAY);
1157 if (ret_val != SUCCESS) {
1158 sd_err(("%s: Unable to set response delay for F2\n", __FUNCTION__));
1165 sd->card_init_done = TRUE;
1167 /* get the device rev to program the prop respdelays */
1173 bcmspi_set_highspeed_mode(sdioh_info_t *sd, bool hsmode)
1178 if ((status = bcmspi_card_regread(sd, 0, SPID_CONFIG,
1179 4, ®data)) != SUCCESS)
1182 sd_trace(("In %s spih-ctrl = 0x%x \n", __FUNCTION__, regdata));
1185 if (hsmode == TRUE) {
1186 sd_trace(("Attempting to enable High-Speed mode.\n"));
1188 if (regdata & HIGH_SPEED_MODE) {
1189 sd_trace(("Device is already in High-Speed mode.\n"));
1192 regdata |= HIGH_SPEED_MODE;
1193 sd_trace(("Writing %08x to device at %08x\n", regdata, SPID_CONFIG));
1194 if ((status = bcmspi_card_regwrite(sd, 0, SPID_CONFIG,
1195 4, regdata)) != SUCCESS) {
1200 sd_trace(("Attempting to disable High-Speed mode.\n"));
1202 if (regdata & HIGH_SPEED_MODE) {
1203 regdata &= ~HIGH_SPEED_MODE;
1204 sd_trace(("Writing %08x to device at %08x\n", regdata, SPID_CONFIG));
1205 if ((status = bcmspi_card_regwrite(sd, 0, SPID_CONFIG,
1206 4, regdata)) != SUCCESS)
1210 sd_trace(("Device is already in Low-Speed mode.\n"));
1214 #ifndef BCMSPI_ANDROID
1215 spi_controller_highspeed_mode(sd, hsmode);
1216 #endif /* !BCMSPI_ANDROID */
1221 #define bcmspi_find_curr_mode(sd) { \
1223 status = bcmspi_card_regread_fixedaddr(sd, 0, SPID_TEST_READ, 4, ®data); \
1225 if ((regdata == 0xad) || (regdata == 0x5b) || \
1226 (regdata == 0x5d) || (regdata == 0x5a)) \
1229 status = bcmspi_card_regread_fixedaddr(sd, 0, SPID_TEST_READ, 4, ®data); \
1231 if ((regdata == 0xad) || (regdata == 0x5b) || \
1232 (regdata == 0x5d) || (regdata == 0x5a)) \
1234 sd_trace(("Silicon testability issue: regdata = 0x%x." \
1235 " Expected 0xad, 0x5a, 0x5b or 0x5d.\n", regdata)); \
1236 OSL_DELAY(100000); \
1239 #define INIT_ADAPT_LOOP 100
1241 /* Adapt clock-phase-speed-bitwidth between host and device */
1243 bcmspi_host_device_init_adapt(sdioh_info_t *sd)
1245 uint32 wrregdata, regdata = 0;
1249 /* Due to a silicon testability issue, the first command from the Host
1250 * to the device will get corrupted (first bit will be lost). So the
1251 * Host should poll the device with a safe read request. ie: The Host
1252 * should try to read F0 addr 0x14 using the Fixed address mode
1253 * (This will prevent a unintended write command to be detected by device)
1255 for (i = 0; i < INIT_ADAPT_LOOP; i++) {
1256 /* If device was not power-cycled it will stay in 32bit mode with
1257 * response-delay-all bit set. Alternate the iteration so that
1258 * read either with or without response-delay for F0 to succeed.
1260 bcmspi_find_curr_mode(sd);
1261 sd->resp_delay_all = (i & 0x1) ? TRUE : FALSE;
1263 bcmspi_find_curr_mode(sd);
1264 sd->dwordmode = TRUE;
1266 bcmspi_find_curr_mode(sd);
1267 sd->dwordmode = FALSE;
1270 /* Bail out, device not detected */
1271 if (i == INIT_ADAPT_LOOP)
1274 /* Softreset the spid logic */
1275 if ((sd->dwordmode) || (sd->wordlen == 4)) {
1276 bcmspi_card_regwrite(sd, 0, SPID_RESET_BP, 1, RESET_ON_WLAN_BP_RESET|RESET_SPI);
1277 bcmspi_card_regread(sd, 0, SPID_RESET_BP, 1, ®data);
1278 sd_trace(("reset reg read = 0x%x\n", regdata));
1279 sd_trace(("dwordmode = %d, wordlen = %d, resp_delay_all = %d\n", sd->dwordmode,
1280 sd->wordlen, sd->resp_delay_all));
1281 /* Restore default state after softreset */
1283 sd->dwordmode = FALSE;
1286 if (sd->wordlen == 4) {
1287 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) !=
1290 if (regdata == TEST_RO_DATA_32BIT_LE) {
1291 sd_trace(("Spid is already in 32bit LE mode. Value read = 0x%x\n",
1293 sd_trace(("Spid power was left on.\n"));
1295 sd_err(("Spid power was left on but signature read failed."
1296 " Value read = 0x%x\n", regdata));
1302 #define CTRL_REG_DEFAULT 0x00010430 /* according to the host m/c */
1304 wrregdata = (CTRL_REG_DEFAULT);
1306 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) != SUCCESS)
1308 sd_trace(("(we are still in 16bit mode) 32bit READ LE regdata = 0x%x\n", regdata));
1311 wrregdata |= (CLOCK_PHASE | CLOCK_POLARITY);
1312 wrregdata &= ~HIGH_SPEED_MODE;
1313 bcmspi_card_regwrite(sd, 0, SPID_CONFIG, 4, wrregdata);
1316 for (i = 0; i < INIT_ADAPT_LOOP; i++) {
1317 if ((regdata == 0xfdda7d5b) || (regdata == 0xfdda7d5a)) {
1318 sd_trace(("0xfeedbead was leftshifted by 1-bit.\n"));
1319 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4,
1320 ®data)) != SUCCESS)
1326 #ifndef CUSTOMER_HW4
1327 /* Change to host controller intr-polarity of active-low */
1328 wrregdata &= ~INTR_POLARITY;
1330 /* Change to host controller intr-polarity of active-high */
1331 wrregdata |= INTR_POLARITY;
1333 sd_trace(("(we are still in 16bit mode) 32bit Write LE reg-ctrl-data = 0x%x\n",
1335 /* Change to 32bit mode */
1336 wrregdata |= WORD_LENGTH_32;
1337 bcmspi_card_regwrite(sd, 0, SPID_CONFIG, 4, wrregdata);
1339 /* Change command/data packaging in 32bit LE mode */
1342 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) != SUCCESS)
1345 if (regdata == TEST_RO_DATA_32BIT_LE) {
1346 sd_trace(("Read spid passed. Value read = 0x%x\n", regdata));
1347 sd_trace(("Spid had power-on cycle OR spi was soft-resetted \n"));
1349 sd_err(("Stale spid reg values read as it was kept powered. Value read ="
1350 "0x%x\n", regdata));
1360 bcmspi_test_card(sdioh_info_t *sd)
1365 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) != SUCCESS)
1368 if (regdata == (TEST_RO_DATA_32BIT_LE))
1369 sd_trace(("32bit LE regdata = 0x%x\n", regdata));
1371 sd_trace(("Incorrect 32bit LE regdata = 0x%x\n", regdata));
1376 #define RW_PATTERN1 0xA0A1A2A3
1377 #define RW_PATTERN2 0x4B5B6B7B
1379 regdata = RW_PATTERN1;
1380 if ((status = bcmspi_card_regwrite(sd, 0, SPID_TEST_RW, 4, regdata)) != SUCCESS)
1383 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_RW, 4, ®data)) != SUCCESS)
1385 if (regdata != RW_PATTERN1) {
1386 sd_err(("Write-Read spid failed. Value wrote = 0x%x, Value read = 0x%x\n",
1387 RW_PATTERN1, regdata));
1390 sd_trace(("R/W spid passed. Value read = 0x%x\n", regdata));
1392 regdata = RW_PATTERN2;
1393 if ((status = bcmspi_card_regwrite(sd, 0, SPID_TEST_RW, 4, regdata)) != SUCCESS)
1396 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_RW, 4, ®data)) != SUCCESS)
1398 if (regdata != RW_PATTERN2) {
1399 sd_err(("Write-Read spid failed. Value wrote = 0x%x, Value read = 0x%x\n",
1400 RW_PATTERN2, regdata));
1403 sd_trace(("R/W spid passed. Value read = 0x%x\n", regdata));
1409 bcmspi_driver_init(sdioh_info_t *sd)
1411 sd_trace(("%s\n", __FUNCTION__));
1412 if ((bcmspi_host_init(sd)) != SUCCESS) {
1416 if (bcmspi_client_init(sd) != SUCCESS) {
1423 /* Read device reg */
1425 bcmspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
1428 uint32 cmd_arg, dstatus;
1433 sd_trace(("Reg access on F2 will generate error indication in dstatus bits.\n"));
1436 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 0);
1437 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
1438 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1439 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1440 cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize == BLOCK_SIZE_F2 ? 0 : regsize);
1442 sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d\n",
1443 __FUNCTION__, cmd_arg, func, regaddr, regsize));
1445 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, regsize)) != SUCCESS)
1448 bcmspi_cmd_getdstatus(sd, &dstatus);
1450 sd_trace(("dstatus =0x%x\n", dstatus));
1456 bcmspi_card_regread_fixedaddr(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
1466 sd_trace(("Reg access on F2 will generate error indication in dstatus bits.\n"));
1469 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 0);
1470 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 0); /* Fixed access */
1471 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1472 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1473 cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize);
1475 sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d\n",
1476 __FUNCTION__, cmd_arg, func, regaddr, regsize));
1478 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, regsize)) != SUCCESS)
1481 sd_trace(("%s: RD result=0x%x\n", __FUNCTION__, *data));
1483 bcmspi_cmd_getdstatus(sd, &dstatus);
1484 sd_trace(("dstatus =0x%x\n", dstatus));
1488 /* write a device register */
1490 bcmspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 data)
1493 uint32 cmd_arg, dstatus;
1499 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
1500 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
1501 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1502 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1503 cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize == BLOCK_SIZE_F2 ? 0 : regsize);
1505 sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d data=0x%x\n",
1506 __FUNCTION__, cmd_arg, func, regaddr, regsize, data));
1508 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, regsize)) != SUCCESS)
1511 bcmspi_cmd_getdstatus(sd, &dstatus);
1513 sd_trace(("dstatus=0x%x\n", dstatus));
1518 /* write a device register - 1 byte */
1520 bcmspi_card_bytewrite(sdioh_info_t *sd, int func, uint32 regaddr, uint8 *byte)
1525 uint32 data = (uint32)(*byte);
1528 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1529 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
1530 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1531 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
1532 cmd_arg = SFIELD(cmd_arg, SPI_LEN, 1);
1534 sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x data=0x%x\n",
1535 __FUNCTION__, cmd_arg, func, regaddr, data));
1537 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, 1)) != SUCCESS)
1540 bcmspi_cmd_getdstatus(sd, &dstatus);
1542 sd_trace(("dstatus =0x%x\n", dstatus));
1548 bcmspi_cmd_getdstatus(sdioh_info_t *sd, uint32 *dstatus_buffer)
1550 *dstatus_buffer = sd->card_dstatus;
1553 /* 'data' is of type uint32 whereas other buffers are of type uint8 */
1555 bcmspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd_arg,
1556 uint32 *data, uint32 datalen)
1559 uint8 resp_delay = 0;
1563 uint32 dstatus_idx = 0;
1564 uint16 templen, buslen, len, *ptr = NULL;
1566 sd_trace(("spi cmd = 0x%x\n", cmd_arg));
1569 spilen = GFIELD(cmd_arg, SPI_LEN);
1570 if ((GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_0) ||
1571 (GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_1))
1572 dstatus_idx = spilen * 3;
1574 if ((GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_2) &&
1575 (GFIELD(cmd_arg, SPI_RW_FLAG) == 1)) {
1576 spilen = spilen << 2;
1577 dstatus_idx = (spilen % 16) ? (16 - (spilen % 16)) : 0;
1578 /* convert len to mod16 size */
1579 spilen = ROUNDUP(spilen, 16);
1580 cmd_arg = SFIELD(cmd_arg, SPI_LEN, (spilen >> 2));
1584 /* Set up and issue the SPI command. MSByte goes out on bus first. Increase datalen
1585 * according to the wordlen mode(16/32bit) the device is in.
1587 if (sd->wordlen == 4) { /* 32bit spid */
1588 *(uint32 *)spi_outbuf = SPISWAP_WD4(cmd_arg);
1590 datalen += (4 - (datalen & 0x3));
1591 } else if (sd->wordlen == 2) { /* 16bit spid */
1592 *(uint32 *)spi_outbuf = SPISWAP_WD2(cmd_arg);
1596 datalen = ROUNDUP(datalen, 4);
1598 sd_err(("Host is %d bit spid, could not create SPI command.\n",
1603 /* for Write, put the data into the output buffer */
1604 if (GFIELD(cmd_arg, SPI_RW_FLAG) == 1) {
1605 /* We send len field of hw-header always a mod16 size, both from host and dongle */
1607 if (GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_2) {
1608 ptr = (uint16 *)&data[0];
1610 /* ASSERT(*ptr == ~*(ptr + 1)); */
1611 templen = ROUNDUP(templen, 16);
1613 sd_trace(("actual tx len = %d\n", (uint16)(~*(ptr+1))));
1618 for (i = 0; i < datalen/4; i++) {
1619 if (sd->wordlen == 4) { /* 32bit spid */
1620 *(uint32 *)&spi_outbuf[i * 4 + CMDLEN] =
1621 SPISWAP_WD4(data[i]);
1622 } else if (sd->wordlen == 2) { /* 16bit spid */
1623 *(uint32 *)&spi_outbuf[i * 4 + CMDLEN] =
1624 SPISWAP_WD2(data[i]);
1630 /* Append resp-delay number of bytes and clock them out for F0/1/2 reads. */
1631 if ((GFIELD(cmd_arg, SPI_RW_FLAG) == 0)) {
1632 int func = GFIELD(cmd_arg, SPI_FUNCTION);
1635 if (sd->resp_delay_new)
1636 resp_delay = GSPI_F0_RESP_DELAY;
1638 resp_delay = sd->resp_delay_all ? F0_RESPONSE_DELAY : 0;
1641 if (sd->resp_delay_new)
1642 resp_delay = GSPI_F1_RESP_DELAY;
1644 resp_delay = F1_RESPONSE_DELAY;
1647 if (sd->resp_delay_new)
1648 resp_delay = GSPI_F2_RESP_DELAY;
1650 resp_delay = sd->resp_delay_all ? F2_RESPONSE_DELAY : 0;
1656 /* Program response delay */
1657 if (sd->resp_delay_new == FALSE)
1658 bcmspi_prog_resp_delay(sd, func, resp_delay);
1661 /* +4 for cmd and +4 for dstatus */
1662 hostlen = datalen + 8 + resp_delay;
1663 hostlen += dstatus_idx;
1664 #ifdef BCMSPI_ANDROID
1666 sd_err(("Unaligned data len %d, hostlen %d\n",
1668 #endif /* BCMSPI_ANDROID */
1669 hostlen += (4 - (hostlen & 0x3));
1670 #ifdef BCMSPI_ANDROID
1672 #endif /* BCMSPI_ANDROID */
1673 spi_sendrecv(sd, spi_outbuf, spi_inbuf, hostlen);
1675 /* for Read, get the data into the input buffer */
1677 if (GFIELD(cmd_arg, SPI_RW_FLAG) == 0) { /* if read cmd */
1678 for (j = 0; j < datalen/4; j++) {
1679 if (sd->wordlen == 4) { /* 32bit spid */
1680 data[j] = SPISWAP_WD4(*(uint32 *)&spi_inbuf[j * 4 +
1681 CMDLEN + resp_delay]);
1682 } else if (sd->wordlen == 2) { /* 16bit spid */
1683 data[j] = SPISWAP_WD2(*(uint32 *)&spi_inbuf[j * 4 +
1684 CMDLEN + resp_delay]);
1688 if ((DWORDMODE_ON) && (GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_2)) {
1689 ptr = (uint16 *)&data[0];
1691 buslen = len = ~(*(ptr + 1));
1692 buslen = ROUNDUP(buslen, 16);
1693 /* populate actual len in hw-header */
1694 if (templen == buslen)
1700 /* Restore back the len field of the hw header */
1702 if ((GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_2) &&
1703 (GFIELD(cmd_arg, SPI_RW_FLAG) == 1)) {
1704 ptr = (uint16 *)&data[0];
1705 *ptr = (uint16)(~*(ptr+1));
1709 dstatus_idx += (datalen + CMDLEN + resp_delay);
1710 /* Last 4bytes are dstatus. Device is configured to return status bits. */
1711 if (sd->wordlen == 4) { /* 32bit spid */
1712 sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf[dstatus_idx]);
1713 } else if (sd->wordlen == 2) { /* 16bit spid */
1714 sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf[dstatus_idx]);
1716 sd_err(("Host is %d bit machine, could not read SPI dstatus.\n",
1720 if (sd->card_dstatus == 0xffffffff) {
1721 sd_err(("looks like not a GSPI device or device is not powered.\n"));
1724 err = bcmspi_update_stats(sd, cmd_arg);
1731 bcmspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
1732 uint32 addr, int nbytes, uint32 *data)
1736 bool write = rw == SDIOH_READ ? 0 : 1;
1745 ASSERT(nbytes <= sd->client_block_size[func]);
1747 if (write) sd->t_cnt++; else sd->r_cnt++;
1750 /* Frame len check limited by gSPI. */
1751 if ((nbytes > 2000) && write) {
1752 sd_trace((">2KB write: F2 wr of %d bytes\n", nbytes));
1754 /* ASSERT(nbytes <= 2048); Fix bigger len gspi issue and uncomment. */
1755 /* If F2 fifo on device is not ready to receive data, don't do F2 transfer */
1758 /* check F2 ready with cached one */
1759 bcmspi_cmd_getdstatus(sd, &dstatus);
1760 if ((dstatus & STATUS_F2_RX_READY) == 0) {
1761 retries = WAIT_F2RXFIFORDY;
1763 while (retries-- && !enable) {
1764 OSL_DELAY(WAIT_F2RXFIFORDY_DELAY * 1000);
1765 bcmspi_card_regread(sd, SPI_FUNC_0, SPID_STATUS_REG, 4,
1767 if (dstatus & STATUS_F2_RX_READY)
1771 struct spierrstats_t *spierrstats = &sd->spierrstats;
1772 spierrstats->f2rxnotready++;
1773 sd_err(("F2 FIFO is not ready to receive data.\n"));
1776 sd_trace(("No of retries on F2 ready %d\n",
1777 (WAIT_F2RXFIFORDY - retries)));
1782 /* F2 transfers happen on 0 addr */
1783 addr = (func == 2) ? 0 : addr;
1785 /* In pio mode buffer is read using fixed address fifo in func 1 */
1786 if ((func == 1) && (fifo))
1787 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 0);
1789 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);
1791 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1792 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, addr);
1793 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, write);
1794 spilen = sd->data_xfer_count = MIN(sd->client_block_size[func], nbytes);
1795 if ((sd->dwordmode == TRUE) && (GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_2)) {
1796 /* convert len to mod4 size */
1797 spilen = spilen + ((spilen & 0x3) ? (4 - (spilen & 0x3)): 0);
1798 cmd_arg = SFIELD(cmd_arg, SPI_LEN, (spilen >> 2));
1800 cmd_arg = SFIELD(cmd_arg, SPI_LEN, spilen);
1802 if ((func == 2) && (fifo == 1)) {
1803 sd_data(("%s: %s func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
1804 __FUNCTION__, write ? "Wr" : "Rd", func, "INCR",
1805 addr, nbytes, sd->r_cnt, sd->t_cnt));
1808 sd_trace(("%s cmd_arg = 0x%x\n", __FUNCTION__, cmd_arg));
1809 sd_data(("%s: %s func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
1810 __FUNCTION__, write ? "Wd" : "Rd", func, "INCR",
1811 addr, nbytes, sd->r_cnt, sd->t_cnt));
1814 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, nbytes)) != SUCCESS) {
1815 sd_err(("%s: cmd_issue failed for %s\n", __FUNCTION__,
1816 (write ? "write" : "read")));
1820 /* gSPI expects that hw-header-len is equal to spi-command-len */
1821 if ((func == 2) && (rw == SDIOH_WRITE) && (sd->dwordmode == FALSE)) {
1822 ASSERT((uint16)sd->data_xfer_count == (uint16)(*data & 0xffff));
1823 ASSERT((uint16)sd->data_xfer_count == (uint16)(~((*data & 0xffff0000) >> 16)));
1826 if ((nbytes > 2000) && !write) {
1827 sd_trace((">2KB read: F2 rd of %d bytes\n", nbytes));
1833 /* Reset and re-initialize the device */
1835 sdioh_sdio_reset(sdioh_info_t *si)
1837 si->card_init_done = FALSE;
1838 return bcmspi_client_init(si);
1842 sdioh_gpioouten(sdioh_info_t *sd, uint32 gpio)
1844 return SDIOH_API_RC_FAIL;
1848 sdioh_gpioout(sdioh_info_t *sd, uint32 gpio, bool enab)
1850 return SDIOH_API_RC_FAIL;
1854 sdioh_gpioin(sdioh_info_t *sd, uint32 gpio)
1860 sdioh_gpio_init(sdioh_info_t *sd)
1862 return SDIOH_API_RC_FAIL;