2 * SDIO Host Controller Spec header file
3 * Register map and definitions for the Standard Host Controller
5 * Copyright (C) 1999-2011, Broadcom Corporation
7 * Unless you and Broadcom execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2 (the "GPL"),
10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
11 * following added to such license:
13 * As a special exception, the copyright holders of this software give you
14 * permission to link this software with independent modules, and to copy and
15 * distribute the resulting executable under terms of your choice, provided that
16 * you also meet, for each linked independent module, the terms and conditions of
17 * the license of that module. An independent module is a module which is not
18 * derived from this software. The special exception does not apply to any
19 * modifications of the software.
21 * Notwithstanding the above, under no circumstances may you combine this
22 * software in any way with any other Broadcom software provided under a license
23 * other than the GPL, without Broadcom's express prior written consent.
25 * $Id: sdioh.h,v 13.17.2.3 2011-01-08 05:28:21 $
31 #define SD_SysAddr 0x000
32 #define SD_BlockSize 0x004
33 #define SD_BlockCount 0x006
36 #define SD_TransferMode 0x00C
37 #define SD_Command 0x00E
38 #define SD_Response0 0x010
39 #define SD_Response1 0x012
40 #define SD_Response2 0x014
41 #define SD_Response3 0x016
42 #define SD_Response4 0x018
43 #define SD_Response5 0x01A
44 #define SD_Response6 0x01C
45 #define SD_Response7 0x01E
46 #define SD_BufferDataPort0 0x020
47 #define SD_BufferDataPort1 0x022
48 #define SD_PresentState 0x024
49 #define SD_HostCntrl 0x028
50 #define SD_PwrCntrl 0x029
51 #define SD_BlockGapCntrl 0x02A
52 #define SD_WakeupCntrl 0x02B
53 #define SD_ClockCntrl 0x02C
54 #define SD_TimeoutCntrl 0x02E
55 #define SD_SoftwareReset 0x02F
56 #define SD_IntrStatus 0x030
57 #define SD_ErrorIntrStatus 0x032
58 #define SD_IntrStatusEnable 0x034
59 #define SD_ErrorIntrStatusEnable 0x036
60 #define SD_IntrSignalEnable 0x038
61 #define SD_ErrorIntrSignalEnable 0x03A
62 #define SD_CMD12ErrorStatus 0x03C
63 #define SD_Capabilities 0x040
64 #define SD_Capabilities_Reserved 0x044
65 #define SD_MaxCurCap 0x048
66 #define SD_MaxCurCap_Reserved 0x04C
67 #define SD_ADMA_ErrStatus 0x054
68 #define SD_ADMA_SysAddr 0x58
69 #define SD_SlotInterruptStatus 0x0FC
70 #define SD_HostControllerVersion 0x0FE
72 /* SD specific registers in PCI config space */
73 #define SD_SlotInfo 0x40
77 #define SD_Capabilities3 0x044
79 /* HC 3.0 specific registers and offsets */
80 #define SD3_HostCntrl2 0x03E
81 /* preset regsstart and count */
82 #define SD3_PresetValStart 0x060
83 #define SD3_PresetValCount 8
84 /* preset-indiv regs */
85 #define SD3_PresetVal_init 0x060
86 #define SD3_PresetVal_default 0x062
87 #define SD3_PresetVal_HS 0x064
88 #define SD3_PresetVal_SDR12 0x066
89 #define SD3_PresetVal_SDR25 0x068
90 #define SD3_PresetVal_SDR50 0x06a
91 #define SD3_PresetVal_SDR104 0x06c
92 #define SD3_PresetVal_DDR50 0x06e
94 /* preset value indices */
95 #define SD3_PRESETVAL_INITIAL_IX 0
96 #define SD3_PRESETVAL_DESPEED_IX 1
97 #define SD3_PRESETVAL_HISPEED_IX 2
98 #define SD3_PRESETVAL_SDR12_IX 3
99 #define SD3_PRESETVAL_SDR25_IX 4
100 #define SD3_PRESETVAL_SDR50_IX 5
101 #define SD3_PRESETVAL_SDR104_IX 6
102 #define SD3_PRESETVAL_DDR50_IX 7
106 /* SD_Capabilities reg (0x040) */
107 #define CAP_TO_CLKFREQ_M BITFIELD_MASK(6)
108 #define CAP_TO_CLKFREQ_S 0
109 #define CAP_TO_CLKUNIT_M BITFIELD_MASK(1)
110 #define CAP_TO_CLKUNIT_S 7
111 /* #ifndef SDHOST3 */
112 /* #define CAP_BASECLK_M BITFIELD_MASK(6) */
113 /* #define CAP_BASECLK_S 8 */
115 /* Note: for sdio-2.0 case, this mask has to be 6 bits, but msb 2
116 bits are reserved. going ahead with 8 bits, as it is req for 3.0
118 #define CAP_BASECLK_M BITFIELD_MASK(8)
119 #define CAP_BASECLK_S 8
121 #define CAP_MAXBLOCK_M BITFIELD_MASK(2)
122 #define CAP_MAXBLOCK_S 16
123 #define CAP_ADMA2_M BITFIELD_MASK(1)
124 #define CAP_ADMA2_S 19
125 #define CAP_ADMA1_M BITFIELD_MASK(1)
126 #define CAP_ADMA1_S 20
127 #define CAP_HIGHSPEED_M BITFIELD_MASK(1)
128 #define CAP_HIGHSPEED_S 21
129 #define CAP_DMA_M BITFIELD_MASK(1)
131 #define CAP_SUSPEND_M BITFIELD_MASK(1)
132 #define CAP_SUSPEND_S 23
133 #define CAP_VOLT_3_3_M BITFIELD_MASK(1)
134 #define CAP_VOLT_3_3_S 24
135 #define CAP_VOLT_3_0_M BITFIELD_MASK(1)
136 #define CAP_VOLT_3_0_S 25
137 #define CAP_VOLT_1_8_M BITFIELD_MASK(1)
138 #define CAP_VOLT_1_8_S 26
139 #define CAP_64BIT_HOST_M BITFIELD_MASK(1)
140 #define CAP_64BIT_HOST_S 28
144 #define CAP_ASYNCINT_SUP_M BITFIELD_MASK(1)
145 #define CAP_ASYNCINT_SUP_S 29
147 #define CAP_SLOTTYPE_M BITFIELD_MASK(2)
148 #define CAP_SLOTTYPE_S 30
150 #define CAP3_MSBits_OFFSET (32)
151 /* note: following are caps MSB32 bits.
152 So the bits start from 0, instead of 32. that is why
153 CAP3_MSBits_OFFSET is subtracted.
155 #define CAP3_SDR50_SUP_M BITFIELD_MASK(1)
156 #define CAP3_SDR50_SUP_S (32 - CAP3_MSBits_OFFSET)
158 #define CAP3_SDR104_SUP_M BITFIELD_MASK(1)
159 #define CAP3_SDR104_SUP_S (33 - CAP3_MSBits_OFFSET)
161 #define CAP3_DDR50_SUP_M BITFIELD_MASK(1)
162 #define CAP3_DDR50_SUP_S (34 - CAP3_MSBits_OFFSET)
164 /* for knowing the clk caps in a single read */
165 #define CAP3_30CLKCAP_M BITFIELD_MASK(3)
166 #define CAP3_30CLKCAP_S (32 - CAP3_MSBits_OFFSET)
168 #define CAP3_DRIVTYPE_A_M BITFIELD_MASK(1)
169 #define CAP3_DRIVTYPE_A_S (36 - CAP3_MSBits_OFFSET)
171 #define CAP3_DRIVTYPE_C_M BITFIELD_MASK(1)
172 #define CAP3_DRIVTYPE_C_S (37 - CAP3_MSBits_OFFSET)
174 #define CAP3_DRIVTYPE_D_M BITFIELD_MASK(1)
175 #define CAP3_DRIVTYPE_D_S (38 - CAP3_MSBits_OFFSET)
177 #define CAP3_RETUNING_TC_M BITFIELD_MASK(4)
178 #define CAP3_RETUNING_TC_S (40 - CAP3_MSBits_OFFSET)
180 #define CAP3_TUNING_SDR50_M BITFIELD_MASK(1)
181 #define CAP3_TUNING_SDR50_S (45 - CAP3_MSBits_OFFSET)
183 #define CAP3_RETUNING_MODES_M BITFIELD_MASK(2)
184 #define CAP3_RETUNING_MODES_S (46 - CAP3_MSBits_OFFSET)
186 #define CAP3_CLK_MULT_M BITFIELD_MASK(8)
187 #define CAP3_CLK_MULT_S (48 - CAP3_MSBits_OFFSET)
189 #define PRESET_DRIVR_SELECT_M BITFIELD_MASK(2)
190 #define PRESET_DRIVR_SELECT_S 14
192 #define PRESET_CLK_DIV_M BITFIELD_MASK(10)
193 #define PRESET_CLK_DIV_S 0
197 /* SD_MaxCurCap reg (0x048) */
198 #define CAP_CURR_3_3_M BITFIELD_MASK(8)
199 #define CAP_CURR_3_3_S 0
200 #define CAP_CURR_3_0_M BITFIELD_MASK(8)
201 #define CAP_CURR_3_0_S 8
202 #define CAP_CURR_1_8_M BITFIELD_MASK(8)
203 #define CAP_CURR_1_8_S 16
205 /* SD_SysAddr: Offset 0x0000, Size 4 bytes */
207 /* SD_BlockSize: Offset 0x004, Size 2 bytes */
208 #define BLKSZ_BLKSZ_M BITFIELD_MASK(12)
209 #define BLKSZ_BLKSZ_S 0
210 #define BLKSZ_BNDRY_M BITFIELD_MASK(3)
211 #define BLKSZ_BNDRY_S 12
213 /* SD_BlockCount: Offset 0x006, size 2 bytes */
215 /* SD_Arg0: Offset 0x008, size = 4 bytes */
216 /* SD_TransferMode Offset 0x00C, size = 2 bytes */
217 #define XFER_DMA_ENABLE_M BITFIELD_MASK(1)
218 #define XFER_DMA_ENABLE_S 0
219 #define XFER_BLK_COUNT_EN_M BITFIELD_MASK(1)
220 #define XFER_BLK_COUNT_EN_S 1
221 #define XFER_CMD_12_EN_M BITFIELD_MASK(1)
222 #define XFER_CMD_12_EN_S 2
223 #define XFER_DATA_DIRECTION_M BITFIELD_MASK(1)
224 #define XFER_DATA_DIRECTION_S 4
225 #define XFER_MULTI_BLOCK_M BITFIELD_MASK(1)
226 #define XFER_MULTI_BLOCK_S 5
228 /* SD_Command: Offset 0x00E, size = 2 bytes */
229 /* resp_type field */
230 #define RESP_TYPE_NONE 0
231 #define RESP_TYPE_136 1
232 #define RESP_TYPE_48 2
233 #define RESP_TYPE_48_BUSY 3
235 #define CMD_TYPE_NORMAL 0
236 #define CMD_TYPE_SUSPEND 1
237 #define CMD_TYPE_RESUME 2
238 #define CMD_TYPE_ABORT 3
240 #define CMD_RESP_TYPE_M BITFIELD_MASK(2) /* Bits [0-1] - Response type */
241 #define CMD_RESP_TYPE_S 0
242 #define CMD_CRC_EN_M BITFIELD_MASK(1) /* Bit 3 - CRC enable */
243 #define CMD_CRC_EN_S 3
244 #define CMD_INDEX_EN_M BITFIELD_MASK(1) /* Bit 4 - Enable index checking */
245 #define CMD_INDEX_EN_S 4
246 #define CMD_DATA_EN_M BITFIELD_MASK(1) /* Bit 5 - Using DAT line */
247 #define CMD_DATA_EN_S 5
248 #define CMD_TYPE_M BITFIELD_MASK(2) /* Bit [6-7] - Normal, abort, resume, etc
251 #define CMD_INDEX_M BITFIELD_MASK(6) /* Bits [8-13] - Command number */
252 #define CMD_INDEX_S 8
254 /* SD_BufferDataPort0 : Offset 0x020, size = 2 or 4 bytes */
255 /* SD_BufferDataPort1 : Offset 0x022, size = 2 bytes */
256 /* SD_PresentState : Offset 0x024, size = 4 bytes */
257 #define PRES_CMD_INHIBIT_M BITFIELD_MASK(1) /* Bit 0 May use CMD */
258 #define PRES_CMD_INHIBIT_S 0
259 #define PRES_DAT_INHIBIT_M BITFIELD_MASK(1) /* Bit 1 May use DAT */
260 #define PRES_DAT_INHIBIT_S 1
261 #define PRES_DAT_BUSY_M BITFIELD_MASK(1) /* Bit 2 DAT is busy */
262 #define PRES_DAT_BUSY_S 2
263 #define PRES_PRESENT_RSVD_M BITFIELD_MASK(5) /* Bit [3-7] rsvd */
264 #define PRES_PRESENT_RSVD_S 3
265 #define PRES_WRITE_ACTIVE_M BITFIELD_MASK(1) /* Bit 8 Write is active */
266 #define PRES_WRITE_ACTIVE_S 8
267 #define PRES_READ_ACTIVE_M BITFIELD_MASK(1) /* Bit 9 Read is active */
268 #define PRES_READ_ACTIVE_S 9
269 #define PRES_WRITE_DATA_RDY_M BITFIELD_MASK(1) /* Bit 10 Write buf is avail */
270 #define PRES_WRITE_DATA_RDY_S 10
271 #define PRES_READ_DATA_RDY_M BITFIELD_MASK(1) /* Bit 11 Read buf data avail */
272 #define PRES_READ_DATA_RDY_S 11
273 #define PRES_CARD_PRESENT_M BITFIELD_MASK(1) /* Bit 16 Card present - debounced */
274 #define PRES_CARD_PRESENT_S 16
275 #define PRES_CARD_STABLE_M BITFIELD_MASK(1) /* Bit 17 Debugging */
276 #define PRES_CARD_STABLE_S 17
277 #define PRES_CARD_PRESENT_RAW_M BITFIELD_MASK(1) /* Bit 18 Not debounced */
278 #define PRES_CARD_PRESENT_RAW_S 18
279 #define PRES_WRITE_ENABLED_M BITFIELD_MASK(1) /* Bit 19 Write protected? */
280 #define PRES_WRITE_ENABLED_S 19
281 #define PRES_DAT_SIGNAL_M BITFIELD_MASK(4) /* Bit [20-23] Debugging */
282 #define PRES_DAT_SIGNAL_S 20
283 #define PRES_CMD_SIGNAL_M BITFIELD_MASK(1) /* Bit 24 Debugging */
284 #define PRES_CMD_SIGNAL_S 24
286 /* SD_HostCntrl: Offset 0x028, size = 1 bytes */
287 #define HOST_LED_M BITFIELD_MASK(1) /* Bit 0 LED On/Off */
289 #define HOST_DATA_WIDTH_M BITFIELD_MASK(1) /* Bit 1 4 bit enable */
290 #define HOST_DATA_WIDTH_S 1
291 #define HOST_HI_SPEED_EN_M BITFIELD_MASK(1) /* Bit 2 High speed vs low speed */
292 #define HOST_DMA_SEL_S 3
293 #define HOST_DMA_SEL_M BITFIELD_MASK(2) /* Bit 4:3 DMA Select */
294 #define HOST_HI_SPEED_EN_S 2
298 #define HOSTCtrl2_PRESVAL_EN_M BITFIELD_MASK(1) /* 1 bit */
299 #define HOSTCtrl2_PRESVAL_EN_S 15 /* bit# */
301 #define HOSTCtrl2_ASYINT_EN_M BITFIELD_MASK(1) /* 1 bit */
302 #define HOSTCtrl2_ASYINT_EN_S 14 /* bit# */
304 #define HOSTCtrl2_SAMPCLK_SEL_M BITFIELD_MASK(1) /* 1 bit */
305 #define HOSTCtrl2_SAMPCLK_SEL_S 7 /* bit# */
307 #define HOSTCtrl2_EXEC_TUNING_M BITFIELD_MASK(1) /* 1 bit */
308 #define HOSTCtrl2_EXEC_TUNING_S 6 /* bit# */
310 #define HOSTCtrl2_DRIVSTRENGTH_SEL_M BITFIELD_MASK(2) /* 2 bit */
311 #define HOSTCtrl2_DRIVSTRENGTH_SEL_S 4 /* bit# */
313 #define HOSTCtrl2_1_8SIG_EN_M BITFIELD_MASK(1) /* 1 bit */
314 #define HOSTCtrl2_1_8SIG_EN_S 3 /* bit# */
316 #define HOSTCtrl2_UHSMODE_SEL_M BITFIELD_MASK(3) /* 3 bit */
317 #define HOSTCtrl2_UHSMODE_SEL_S 0 /* bit# */
321 #define HOST_CONTR_VER_3 (2)
324 #define SD1_MODE 0x1 /* SD Host Cntrlr Spec */
325 #define SD4_MODE 0x2 /* SD Host Cntrlr Spec */
327 /* SD_PwrCntrl: Offset 0x029, size = 1 bytes */
328 #define PWR_BUS_EN_M BITFIELD_MASK(1) /* Bit 0 Power the bus */
329 #define PWR_BUS_EN_S 0
330 #define PWR_VOLTS_M BITFIELD_MASK(3) /* Bit [1-3] Voltage Select */
331 #define PWR_VOLTS_S 1
333 /* SD_SoftwareReset: Offset 0x02F, size = 1 byte */
334 #define SW_RESET_ALL_M BITFIELD_MASK(1) /* Bit 0 Reset All */
335 #define SW_RESET_ALL_S 0
336 #define SW_RESET_CMD_M BITFIELD_MASK(1) /* Bit 1 CMD Line Reset */
337 #define SW_RESET_CMD_S 1
338 #define SW_RESET_DAT_M BITFIELD_MASK(1) /* Bit 2 DAT Line Reset */
339 #define SW_RESET_DAT_S 2
341 /* SD_IntrStatus: Offset 0x030, size = 2 bytes */
342 /* Defs also serve SD_IntrStatusEnable and SD_IntrSignalEnable */
343 #define INTSTAT_CMD_COMPLETE_M BITFIELD_MASK(1) /* Bit 0 */
344 #define INTSTAT_CMD_COMPLETE_S 0
345 #define INTSTAT_XFER_COMPLETE_M BITFIELD_MASK(1)
346 #define INTSTAT_XFER_COMPLETE_S 1
347 #define INTSTAT_BLOCK_GAP_EVENT_M BITFIELD_MASK(1)
348 #define INTSTAT_BLOCK_GAP_EVENT_S 2
349 #define INTSTAT_DMA_INT_M BITFIELD_MASK(1)
350 #define INTSTAT_DMA_INT_S 3
351 #define INTSTAT_BUF_WRITE_READY_M BITFIELD_MASK(1)
352 #define INTSTAT_BUF_WRITE_READY_S 4
353 #define INTSTAT_BUF_READ_READY_M BITFIELD_MASK(1)
354 #define INTSTAT_BUF_READ_READY_S 5
355 #define INTSTAT_CARD_INSERTION_M BITFIELD_MASK(1)
356 #define INTSTAT_CARD_INSERTION_S 6
357 #define INTSTAT_CARD_REMOVAL_M BITFIELD_MASK(1)
358 #define INTSTAT_CARD_REMOVAL_S 7
359 #define INTSTAT_CARD_INT_M BITFIELD_MASK(1)
360 #define INTSTAT_CARD_INT_S 8
361 #define INTSTAT_ERROR_INT_M BITFIELD_MASK(1) /* Bit 15 */
362 #define INTSTAT_ERROR_INT_S 15
366 #define INTSTAT_RETUNING_INT_M BITFIELD_MASK(1) /* Bit 12 */
367 #define INTSTAT_RETUNING_INT_S 12
370 /* SD_ErrorIntrStatus: Offset 0x032, size = 2 bytes */
371 /* Defs also serve SD_ErrorIntrStatusEnable and SD_ErrorIntrSignalEnable */
372 #define ERRINT_CMD_TIMEOUT_M BITFIELD_MASK(1)
373 #define ERRINT_CMD_TIMEOUT_S 0
374 #define ERRINT_CMD_CRC_M BITFIELD_MASK(1)
375 #define ERRINT_CMD_CRC_S 1
376 #define ERRINT_CMD_ENDBIT_M BITFIELD_MASK(1)
377 #define ERRINT_CMD_ENDBIT_S 2
378 #define ERRINT_CMD_INDEX_M BITFIELD_MASK(1)
379 #define ERRINT_CMD_INDEX_S 3
380 #define ERRINT_DATA_TIMEOUT_M BITFIELD_MASK(1)
381 #define ERRINT_DATA_TIMEOUT_S 4
382 #define ERRINT_DATA_CRC_M BITFIELD_MASK(1)
383 #define ERRINT_DATA_CRC_S 5
384 #define ERRINT_DATA_ENDBIT_M BITFIELD_MASK(1)
385 #define ERRINT_DATA_ENDBIT_S 6
386 #define ERRINT_CURRENT_LIMIT_M BITFIELD_MASK(1)
387 #define ERRINT_CURRENT_LIMIT_S 7
388 #define ERRINT_AUTO_CMD12_M BITFIELD_MASK(1)
389 #define ERRINT_AUTO_CMD12_S 8
390 #define ERRINT_VENDOR_M BITFIELD_MASK(4)
391 #define ERRINT_VENDOR_S 12
392 #define ERRINT_ADMA_M BITFIELD_MASK(1)
393 #define ERRINT_ADMA_S 9
395 /* Also provide definitions in "normal" form to allow combined masks */
396 #define ERRINT_CMD_TIMEOUT_BIT 0x0001
397 #define ERRINT_CMD_CRC_BIT 0x0002
398 #define ERRINT_CMD_ENDBIT_BIT 0x0004
399 #define ERRINT_CMD_INDEX_BIT 0x0008
400 #define ERRINT_DATA_TIMEOUT_BIT 0x0010
401 #define ERRINT_DATA_CRC_BIT 0x0020
402 #define ERRINT_DATA_ENDBIT_BIT 0x0040
403 #define ERRINT_CURRENT_LIMIT_BIT 0x0080
404 #define ERRINT_AUTO_CMD12_BIT 0x0100
405 #define ERRINT_ADMA_BIT 0x0200
407 /* Masks to select CMD vs. DATA errors */
408 #define ERRINT_CMD_ERRS (ERRINT_CMD_TIMEOUT_BIT | ERRINT_CMD_CRC_BIT |\
409 ERRINT_CMD_ENDBIT_BIT | ERRINT_CMD_INDEX_BIT)
410 #define ERRINT_DATA_ERRS (ERRINT_DATA_TIMEOUT_BIT | ERRINT_DATA_CRC_BIT |\
411 ERRINT_DATA_ENDBIT_BIT | ERRINT_ADMA_BIT)
412 #define ERRINT_TRANSFER_ERRS (ERRINT_CMD_ERRS | ERRINT_DATA_ERRS)
414 /* SD_WakeupCntr_BlockGapCntrl : Offset 0x02A , size = bytes */
415 /* SD_ClockCntrl : Offset 0x02C , size = bytes */
416 /* SD_SoftwareReset_TimeoutCntrl : Offset 0x02E , size = bytes */
417 /* SD_IntrStatus : Offset 0x030 , size = bytes */
418 /* SD_ErrorIntrStatus : Offset 0x032 , size = bytes */
419 /* SD_IntrStatusEnable : Offset 0x034 , size = bytes */
420 /* SD_ErrorIntrStatusEnable : Offset 0x036 , size = bytes */
421 /* SD_IntrSignalEnable : Offset 0x038 , size = bytes */
422 /* SD_ErrorIntrSignalEnable : Offset 0x03A , size = bytes */
423 /* SD_CMD12ErrorStatus : Offset 0x03C , size = bytes */
424 /* SD_Capabilities : Offset 0x040 , size = bytes */
425 /* SD_MaxCurCap : Offset 0x048 , size = bytes */
426 /* SD_MaxCurCap_Reserved: Offset 0x04C , size = bytes */
427 /* SD_SlotInterruptStatus: Offset 0x0FC , size = bytes */
428 /* SD_HostControllerVersion : Offset 0x0FE , size = bytes */
430 #endif /* _SDIOH_H */
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