3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/types.h>
32 #include "tables_nphy.h"
33 #include "radio_2055.h"
34 #include "radio_2056.h"
35 #include "radio_2057.h"
45 struct nphy_iqcal_params {
63 enum b43_nphy_rf_sequence {
67 B43_RFSEQ_UPDATE_GAINH,
68 B43_RFSEQ_UPDATE_GAINL,
69 B43_RFSEQ_UPDATE_GAINU,
87 static inline bool b43_nphy_ipa(struct b43_wldev *dev)
89 enum ieee80211_band band = b43_current_band(dev->wl);
90 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
91 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
94 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
95 static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
97 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
98 B43_NPHY_RFSEQCA_RXEN_SHIFT;
101 /**************************************************
102 * RF (just without b43_nphy_rf_control_intc_override)
103 **************************************************/
105 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
106 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
107 enum b43_nphy_rf_sequence seq)
109 static const u16 trigger[] = {
110 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
111 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
112 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
113 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
114 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
115 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
118 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
120 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
122 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
123 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
124 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
125 for (i = 0; i < 200; i++) {
126 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
130 b43err(dev->wl, "RF sequence status timeout\n");
132 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
135 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
136 static void b43_nphy_rf_control_override_rev7(struct b43_wldev *dev, u16 field,
137 u16 value, u8 core, bool off,
140 const struct nphy_rf_control_override_rev7 *e;
141 u16 en_addrs[3][2] = {
142 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
149 /* Remember: we can get NULL! */
150 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
152 for (i = 0; i < 2; i++) {
153 if (override >= ARRAY_SIZE(en_addrs)) {
154 b43err(dev->wl, "Invalid override value %d\n", override);
157 en_addr = en_addrs[override][i];
159 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
162 b43_phy_mask(dev, en_addr, ~en_mask);
163 if (e) /* Do it safer, better than wl */
164 b43_phy_mask(dev, val_addr, ~e->val_mask);
166 if (!core || (core & (1 << i))) {
167 b43_phy_set(dev, en_addr, en_mask);
169 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
175 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
176 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
177 u16 value, u8 core, bool off)
180 u8 index = fls(field);
181 u8 addr, en_addr, val_addr;
182 /* we expect only one bit set */
183 B43_WARN_ON(field & (~(1 << (index - 1))));
185 if (dev->phy.rev >= 3) {
186 const struct nphy_rf_control_override_rev3 *rf_ctrl;
187 for (i = 0; i < 2; i++) {
188 if (index == 0 || index == 16) {
190 "Unsupported RF Ctrl Override call\n");
194 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
195 en_addr = B43_PHY_N((i == 0) ?
196 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
197 val_addr = B43_PHY_N((i == 0) ?
198 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
201 b43_phy_mask(dev, en_addr, ~(field));
202 b43_phy_mask(dev, val_addr,
203 ~(rf_ctrl->val_mask));
205 if (core == 0 || ((1 << i) & core)) {
206 b43_phy_set(dev, en_addr, field);
207 b43_phy_maskset(dev, val_addr,
208 ~(rf_ctrl->val_mask),
209 (value << rf_ctrl->val_shift));
214 const struct nphy_rf_control_override_rev2 *rf_ctrl;
216 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
219 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
222 for (i = 0; i < 2; i++) {
223 if (index <= 1 || index == 16) {
225 "Unsupported RF Ctrl Override call\n");
229 if (index == 2 || index == 10 ||
230 (index >= 13 && index <= 15)) {
234 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
235 addr = B43_PHY_N((i == 0) ?
236 rf_ctrl->addr0 : rf_ctrl->addr1);
239 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
240 (value << rf_ctrl->shift));
242 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
243 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
244 B43_NPHY_RFCTL_CMD_START);
246 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
251 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
252 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
258 B43_WARN_ON(dev->phy.rev < 3);
259 B43_WARN_ON(field > 4);
261 for (i = 0; i < 2; i++) {
262 if ((core == 1 && i == 1) || (core == 2 && !i))
266 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
267 b43_phy_set(dev, reg, 0x400);
271 b43_phy_write(dev, reg, 0);
272 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
276 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
277 0xFC3F, (value << 6));
278 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
280 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
281 B43_NPHY_RFCTL_CMD_START);
282 for (j = 0; j < 100; j++) {
283 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
291 "intc override timeout\n");
292 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
295 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
296 0xFC3F, (value << 6));
297 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
299 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
300 B43_NPHY_RFCTL_CMD_RXTX);
301 for (j = 0; j < 100; j++) {
302 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
310 "intc override timeout\n");
311 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
316 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
323 b43_phy_maskset(dev, reg, ~tmp, val);
326 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
333 b43_phy_maskset(dev, reg, ~tmp, val);
336 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
343 b43_phy_maskset(dev, reg, ~tmp, val);
349 /**************************************************
351 **************************************************/
353 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
354 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
357 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
358 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
361 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
362 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
364 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
365 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
368 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
369 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
373 if (dev->dev->core_rev == 16)
374 b43_mac_suspend(dev);
376 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
377 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
378 B43_NPHY_CLASSCTL_WAITEDEN);
381 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
383 if (dev->dev->core_rev == 16)
389 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
390 static void b43_nphy_reset_cca(struct b43_wldev *dev)
394 b43_phy_force_clock(dev, 1);
395 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
396 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
398 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
399 b43_phy_force_clock(dev, 0);
400 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
403 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
404 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
406 struct b43_phy *phy = &dev->phy;
407 struct b43_phy_n *nphy = phy->n;
410 static const u16 clip[] = { 0xFFFF, 0xFFFF };
411 if (nphy->deaf_count++ == 0) {
412 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
413 b43_nphy_classifier(dev, 0x7, 0);
414 b43_nphy_read_clip_detection(dev, nphy->clip_state);
415 b43_nphy_write_clip_detection(dev, clip);
417 b43_nphy_reset_cca(dev);
419 if (--nphy->deaf_count == 0) {
420 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
421 b43_nphy_write_clip_detection(dev, nphy->clip_state);
426 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
427 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
429 struct b43_phy_n *nphy = dev->phy.n;
436 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
438 if (nphy->hang_avoid)
439 b43_nphy_stay_in_carrier_search(dev, 1);
441 if (nphy->gain_boost) {
442 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
446 tmp = 40370 - 315 * dev->phy.channel;
447 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
448 tmp = 23242 - 224 * dev->phy.channel;
449 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
456 for (i = 0; i < 2; i++) {
457 if (nphy->elna_gain_config) {
458 data[0] = 19 + gain[i];
459 data[1] = 25 + gain[i];
460 data[2] = 25 + gain[i];
461 data[3] = 25 + gain[i];
463 data[0] = lna_gain[0] + gain[i];
464 data[1] = lna_gain[1] + gain[i];
465 data[2] = lna_gain[2] + gain[i];
466 data[3] = lna_gain[3] + gain[i];
468 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
470 minmax[i] = 23 + gain[i];
473 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
474 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
475 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
476 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
478 if (nphy->hang_avoid)
479 b43_nphy_stay_in_carrier_search(dev, 0);
482 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
483 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
484 u8 *events, u8 *delays, u8 length)
486 struct b43_phy_n *nphy = dev->phy.n;
488 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
489 u16 offset1 = cmd << 4;
490 u16 offset2 = offset1 + 0x80;
492 if (nphy->hang_avoid)
493 b43_nphy_stay_in_carrier_search(dev, true);
495 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
496 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
498 for (i = length; i < 16; i++) {
499 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
500 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
503 if (nphy->hang_avoid)
504 b43_nphy_stay_in_carrier_search(dev, false);
507 /**************************************************
509 **************************************************/
511 /* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
512 static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
514 struct b43_phy *phy = &dev->phy;
517 if (phy->radio_rev == 5) {
518 b43_phy_mask(dev, 0x342, ~0x2);
520 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
521 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
524 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
526 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
527 if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
528 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
531 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
532 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
533 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
535 if (phy->radio_rev == 5) {
536 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
537 b43_radio_mask(dev, 0x1ca, ~0x2);
539 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
540 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
541 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
548 /* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
549 static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
551 struct b43_phy *phy = &dev->phy;
552 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
553 phy->radio_rev == 6);
557 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
558 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
560 b43_radio_write(dev, 0x1AE, 0x61);
561 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
563 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
564 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
565 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
567 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
568 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
570 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
571 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
573 b43_radio_write(dev, 0x1AE, 0x69);
574 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
576 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
577 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
578 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
580 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
581 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
583 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
584 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
585 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
587 b43_radio_write(dev, 0x1AE, 0x73);
588 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
589 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
591 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
592 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
594 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
597 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
598 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
602 static void b43_radio_2057_init_pre(struct b43_wldev *dev)
604 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
605 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
606 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
607 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
608 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
611 static void b43_radio_2057_init_post(struct b43_wldev *dev)
613 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
615 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
616 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
618 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
619 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
621 if (dev->phy.n->init_por) {
622 b43_radio_2057_rcal(dev);
623 b43_radio_2057_rccal(dev);
625 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
627 dev->phy.n->init_por = false;
630 /* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
631 static void b43_radio_2057_init(struct b43_wldev *dev)
633 b43_radio_2057_init_pre(dev);
634 r2057_upload_inittabs(dev);
635 b43_radio_2057_init_post(dev);
638 /**************************************************
640 **************************************************/
642 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
643 const struct b43_nphy_channeltab_entry_rev3 *e)
645 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
646 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
647 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
648 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
649 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
650 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
651 e->radio_syn_pll_loopfilter1);
652 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
653 e->radio_syn_pll_loopfilter2);
654 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
655 e->radio_syn_pll_loopfilter3);
656 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
657 e->radio_syn_pll_loopfilter4);
658 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
659 e->radio_syn_pll_loopfilter5);
660 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
661 e->radio_syn_reserved_addr27);
662 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
663 e->radio_syn_reserved_addr28);
664 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
665 e->radio_syn_reserved_addr29);
666 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
667 e->radio_syn_logen_vcobuf1);
668 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
669 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
670 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
672 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
673 e->radio_rx0_lnaa_tune);
674 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
675 e->radio_rx0_lnag_tune);
677 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
678 e->radio_tx0_intpaa_boost_tune);
679 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
680 e->radio_tx0_intpag_boost_tune);
681 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
682 e->radio_tx0_pada_boost_tune);
683 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
684 e->radio_tx0_padg_boost_tune);
685 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
686 e->radio_tx0_pgaa_boost_tune);
687 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
688 e->radio_tx0_pgag_boost_tune);
689 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
690 e->radio_tx0_mixa_boost_tune);
691 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
692 e->radio_tx0_mixg_boost_tune);
694 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
695 e->radio_rx1_lnaa_tune);
696 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
697 e->radio_rx1_lnag_tune);
699 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
700 e->radio_tx1_intpaa_boost_tune);
701 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
702 e->radio_tx1_intpag_boost_tune);
703 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
704 e->radio_tx1_pada_boost_tune);
705 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
706 e->radio_tx1_padg_boost_tune);
707 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
708 e->radio_tx1_pgaa_boost_tune);
709 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
710 e->radio_tx1_pgag_boost_tune);
711 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
712 e->radio_tx1_mixa_boost_tune);
713 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
714 e->radio_tx1_mixg_boost_tune);
717 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
718 static void b43_radio_2056_setup(struct b43_wldev *dev,
719 const struct b43_nphy_channeltab_entry_rev3 *e)
721 struct ssb_sprom *sprom = dev->dev->bus_sprom;
722 enum ieee80211_band band = b43_current_band(dev->wl);
726 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
727 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
729 B43_WARN_ON(dev->phy.rev < 3);
731 b43_chantab_radio_2056_upload(dev, e);
732 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
734 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
735 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
736 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
737 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
738 if (dev->dev->chip_id == 0x4716) {
739 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
740 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
742 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
743 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
746 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
747 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
748 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
749 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
750 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
751 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
754 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
755 for (i = 0; i < 2; i++) {
756 offset = i ? B2056_TX1 : B2056_TX0;
757 if (dev->phy.rev >= 5) {
759 offset | B2056_TX_PADG_IDAC, 0xcc);
761 if (dev->dev->chip_id == 0x4716) {
777 offset | B2056_TX_INTPAG_IMAIN_STAT,
780 offset | B2056_TX_INTPAG_IAUX_STAT,
783 offset | B2056_TX_INTPAG_CASCBIAS,
786 offset | B2056_TX_INTPAG_BOOST_TUNE,
789 offset | B2056_TX_PGAG_BOOST_TUNE,
792 offset | B2056_TX_PADG_BOOST_TUNE,
795 offset | B2056_TX_MIXG_BOOST_TUNE,
798 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
800 offset | B2056_TX_INTPAG_IMAIN_STAT,
803 offset | B2056_TX_INTPAG_IAUX_STAT,
806 offset | B2056_TX_INTPAG_CASCBIAS,
809 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
811 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
812 u16 freq = dev->phy.channel_freq;
818 } else if (freq < 5340) {
823 } else if (freq < 5650) {
832 pgaa_boost = -(freq - 18) / 36 + 168;
838 for (i = 0; i < 2; i++) {
839 offset = i ? B2056_TX1 : B2056_TX0;
842 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
844 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
846 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
848 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
850 offset | B2056_TX_TXSPARE1, 0x30);
852 offset | B2056_TX_PA_SPARE2, 0xee);
854 offset | B2056_TX_PADA_CASCBIAS, 0x03);
856 offset | B2056_TX_INTPAA_IAUX_STAT, 0x50);
858 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x50);
860 offset | B2056_TX_INTPAA_CASCBIAS, 0x30);
865 /* VCO calibration */
866 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
867 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
868 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
869 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
870 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
874 static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
876 struct b43_phy *phy = &dev->phy;
882 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
883 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
886 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
888 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
890 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
892 b43err(dev->wl, "Radio recalibration timeout\n");
896 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
897 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
898 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
900 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
905 static void b43_radio_init2056_pre(struct b43_wldev *dev)
907 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
908 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
909 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
910 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
911 B43_NPHY_RFCTL_CMD_OEPORFORCE);
912 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
913 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
914 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
915 B43_NPHY_RFCTL_CMD_CHIP0PU);
918 static void b43_radio_init2056_post(struct b43_wldev *dev)
920 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
921 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
922 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
924 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
925 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
926 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
927 if (dev->phy.n->init_por)
928 b43_radio_2056_rcal(dev);
932 * Initialize a Broadcom 2056 N-radio
933 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
935 static void b43_radio_init2056(struct b43_wldev *dev)
937 b43_radio_init2056_pre(dev);
938 b2056_upload_inittabs(dev, 0, 0);
939 b43_radio_init2056_post(dev);
941 dev->phy.n->init_por = false;
944 /**************************************************
946 **************************************************/
948 static void b43_chantab_radio_upload(struct b43_wldev *dev,
949 const struct b43_nphy_channeltab_entry_rev2 *e)
951 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
952 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
953 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
954 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
955 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
957 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
958 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
959 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
960 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
961 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
963 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
964 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
965 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
966 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
967 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
969 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
970 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
971 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
972 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
973 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
975 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
976 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
977 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
978 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
979 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
981 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
982 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
985 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
986 static void b43_radio_2055_setup(struct b43_wldev *dev,
987 const struct b43_nphy_channeltab_entry_rev2 *e)
989 B43_WARN_ON(dev->phy.rev >= 3);
991 b43_chantab_radio_upload(dev, e);
993 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
994 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
995 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
996 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
1000 static void b43_radio_init2055_pre(struct b43_wldev *dev)
1002 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1003 ~B43_NPHY_RFCTL_CMD_PORFORCE);
1004 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1005 B43_NPHY_RFCTL_CMD_CHIP0PU |
1006 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1007 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1008 B43_NPHY_RFCTL_CMD_PORFORCE);
1011 static void b43_radio_init2055_post(struct b43_wldev *dev)
1013 struct b43_phy_n *nphy = dev->phy.n;
1014 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1015 bool workaround = false;
1017 if (sprom->revision < 4)
1018 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
1019 && dev->dev->board_type == SSB_BOARD_CB2_4321
1020 && dev->dev->board_rev >= 0x41);
1023 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
1025 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1027 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1028 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1030 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1031 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1032 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1033 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1034 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1036 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
1037 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
1038 b43err(dev->wl, "radio post init timeout\n");
1039 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1040 b43_switch_channel(dev, dev->phy.channel);
1041 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1042 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1043 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1044 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1045 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1046 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1047 if (!nphy->gain_boost) {
1048 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1049 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1051 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1052 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1058 * Initialize a Broadcom 2055 N-radio
1059 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1061 static void b43_radio_init2055(struct b43_wldev *dev)
1063 b43_radio_init2055_pre(dev);
1064 if (b43_status(dev) < B43_STAT_INITIALIZED) {
1065 /* Follow wl, not specs. Do not force uploading all regs */
1066 b2055_upload_inittab(dev, 0, 0);
1068 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1069 b2055_upload_inittab(dev, ghz5, 0);
1071 b43_radio_init2055_post(dev);
1074 /**************************************************
1076 **************************************************/
1078 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1079 static int b43_nphy_load_samples(struct b43_wldev *dev,
1080 struct b43_c32 *samples, u16 len) {
1081 struct b43_phy_n *nphy = dev->phy.n;
1085 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1087 b43err(dev->wl, "allocation for samples loading failed\n");
1090 if (nphy->hang_avoid)
1091 b43_nphy_stay_in_carrier_search(dev, 1);
1093 for (i = 0; i < len; i++) {
1094 data[i] = (samples[i].i & 0x3FF << 10);
1095 data[i] |= samples[i].q & 0x3FF;
1097 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1100 if (nphy->hang_avoid)
1101 b43_nphy_stay_in_carrier_search(dev, 0);
1105 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1106 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1110 u16 bw, len, rot, angle;
1111 struct b43_c32 *samples;
1114 bw = (dev->phy.is_40mhz) ? 40 : 20;
1118 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1123 if (dev->phy.is_40mhz)
1129 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1131 b43err(dev->wl, "allocation for samples generation failed\n");
1134 rot = (((freq * 36) / bw) << 16) / 100;
1137 for (i = 0; i < len; i++) {
1138 samples[i] = b43_cordic(angle);
1140 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1141 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1144 i = b43_nphy_load_samples(dev, samples, len);
1146 return (i < 0) ? 0 : len;
1149 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1150 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1151 u16 wait, bool iqmode, bool dac_test)
1153 struct b43_phy_n *nphy = dev->phy.n;
1158 if (nphy->hang_avoid)
1159 b43_nphy_stay_in_carrier_search(dev, true);
1161 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1162 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1163 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1166 if (!dev->phy.is_40mhz)
1170 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1172 if (nphy->hang_avoid)
1173 b43_nphy_stay_in_carrier_search(dev, false);
1175 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1177 if (loops != 0xFFFF)
1178 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1180 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1182 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1184 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1186 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1188 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1189 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1192 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1194 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1196 for (i = 0; i < 100; i++) {
1197 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
1204 b43err(dev->wl, "run samples timeout\n");
1206 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1209 /**************************************************
1211 **************************************************/
1213 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1214 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1216 enum n_rail_type rail,
1217 enum n_rssi_type rssi_type)
1220 bool core1or5 = (core == 1) || (core == 5);
1221 bool core2or5 = (core == 2) || (core == 5);
1223 offset = clamp_val(offset, -32, 31);
1224 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1226 switch (rssi_type) {
1228 if (core1or5 && rail == N_RAIL_I)
1229 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1230 if (core1or5 && rail == N_RAIL_Q)
1231 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1232 if (core2or5 && rail == N_RAIL_I)
1233 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1234 if (core2or5 && rail == N_RAIL_Q)
1235 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1238 if (core1or5 && rail == N_RAIL_I)
1239 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1240 if (core1or5 && rail == N_RAIL_Q)
1241 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1242 if (core2or5 && rail == N_RAIL_I)
1243 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1244 if (core2or5 && rail == N_RAIL_Q)
1245 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1248 if (core1or5 && rail == N_RAIL_I)
1249 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1250 if (core1or5 && rail == N_RAIL_Q)
1251 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1252 if (core2or5 && rail == N_RAIL_I)
1253 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1254 if (core2or5 && rail == N_RAIL_Q)
1255 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1258 if (core1or5 && rail == N_RAIL_I)
1259 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1260 if (core1or5 && rail == N_RAIL_Q)
1261 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1262 if (core2or5 && rail == N_RAIL_I)
1263 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1264 if (core2or5 && rail == N_RAIL_Q)
1265 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1268 if (core1or5 && rail == N_RAIL_I)
1269 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1270 if (core1or5 && rail == N_RAIL_Q)
1271 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1272 if (core2or5 && rail == N_RAIL_I)
1273 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1274 if (core2or5 && rail == N_RAIL_Q)
1275 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1277 case N_RSSI_TSSI_2G:
1279 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1281 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1283 case N_RSSI_TSSI_5G:
1285 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1287 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1292 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1293 enum n_rssi_type rssi_type)
1299 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1300 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1301 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1302 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1303 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1304 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1305 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1306 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1308 for (i = 0; i < 2; i++) {
1309 if ((code == 1 && i == 1) || (code == 2 && !i))
1313 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1314 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1316 if (rssi_type == N_RSSI_W1 ||
1317 rssi_type == N_RSSI_W2 ||
1318 rssi_type == N_RSSI_NB) {
1320 B43_NPHY_AFECTL_C1 :
1322 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1325 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1326 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1327 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1329 if (rssi_type == N_RSSI_W1)
1330 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1331 else if (rssi_type == N_RSSI_W2)
1335 b43_phy_set(dev, reg, val);
1338 B43_NPHY_TXF_40CO_B1S0 :
1339 B43_NPHY_TXF_40CO_B32S1;
1340 b43_phy_set(dev, reg, 0x0020);
1342 if (rssi_type == N_RSSI_TBD)
1344 else if (rssi_type == N_RSSI_IQ)
1350 B43_NPHY_AFECTL_C1 :
1353 b43_phy_maskset(dev, reg, 0xFCFF, val);
1354 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1356 if (rssi_type != N_RSSI_IQ &&
1357 rssi_type != N_RSSI_TBD) {
1358 enum ieee80211_band band =
1359 b43_current_band(dev->wl);
1361 if (b43_nphy_ipa(dev))
1362 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1365 reg = (i == 0) ? 0x2000 : 0x3000;
1366 reg |= B2055_PADDRV;
1367 b43_radio_write16(dev, reg, val);
1370 B43_NPHY_AFECTL_OVER1 :
1371 B43_NPHY_AFECTL_OVER;
1372 b43_phy_set(dev, reg, 0x0200);
1379 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1380 enum n_rssi_type rssi_type)
1383 bool rssi_w1_w2_nb = false;
1385 switch (rssi_type) {
1390 rssi_w1_w2_nb = true;
1402 val = (val << 12) | (val << 14);
1403 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1404 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1406 if (rssi_w1_w2_nb) {
1407 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1408 (rssi_type + 1) << 4);
1409 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1410 (rssi_type + 1) << 4);
1414 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1415 if (rssi_w1_w2_nb) {
1416 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1417 ~(B43_NPHY_RFCTL_CMD_RXEN |
1418 B43_NPHY_RFCTL_CMD_CORESEL));
1419 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1424 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1425 ~B43_NPHY_RFCTL_CMD_START);
1427 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1430 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1431 if (rssi_w1_w2_nb) {
1432 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1433 ~(B43_NPHY_RFCTL_CMD_RXEN |
1434 B43_NPHY_RFCTL_CMD_CORESEL),
1435 (B43_NPHY_RFCTL_CMD_RXEN |
1436 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1437 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1442 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1443 B43_NPHY_RFCTL_CMD_START);
1445 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1450 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1451 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1452 enum n_rssi_type type)
1454 if (dev->phy.rev >= 3)
1455 b43_nphy_rev3_rssi_select(dev, code, type);
1457 b43_nphy_rev2_rssi_select(dev, code, type);
1460 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1461 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1462 enum n_rssi_type rssi_type, u8 *buf)
1465 for (i = 0; i < 2; i++) {
1466 if (rssi_type == N_RSSI_NB) {
1468 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1470 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1473 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1475 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1476 0xFC, buf[2 * i + 1]);
1480 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1483 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1484 0xF3, buf[2 * i + 1] << 2);
1489 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1490 static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1495 u16 save_regs_phy[9];
1498 if (dev->phy.rev >= 3) {
1499 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1500 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1501 save_regs_phy[2] = b43_phy_read(dev,
1502 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1503 save_regs_phy[3] = b43_phy_read(dev,
1504 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1505 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1506 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1507 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1508 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1509 save_regs_phy[8] = 0;
1511 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1512 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1513 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1514 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1515 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1516 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1517 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1518 save_regs_phy[7] = 0;
1519 save_regs_phy[8] = 0;
1522 b43_nphy_rssi_select(dev, 5, rssi_type);
1524 if (dev->phy.rev < 2) {
1525 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1526 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1529 for (i = 0; i < 4; i++)
1532 for (i = 0; i < nsamp; i++) {
1533 if (dev->phy.rev < 2) {
1534 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1535 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1537 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1538 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1541 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1542 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1543 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1544 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1546 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1547 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1549 if (dev->phy.rev < 2)
1550 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1552 if (dev->phy.rev >= 3) {
1553 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1554 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1555 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1557 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1559 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1560 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1561 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1562 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1564 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1565 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1566 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1567 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1568 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1569 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1570 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1576 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1577 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1579 struct b43_phy_n *nphy = dev->phy.n;
1581 u16 saved_regs_phy_rfctl[2];
1582 u16 saved_regs_phy[13];
1583 u16 regs_to_store[] = {
1584 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1585 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1586 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1587 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1589 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1590 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1596 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1600 s32 results[8][4] = { };
1601 s32 results_min[4] = { };
1602 s32 poll_results[4] = { };
1604 u16 *rssical_radio_regs = NULL;
1605 u16 *rssical_phy_regs = NULL;
1607 u16 r; /* routing */
1609 int core, i, j, vcm;
1611 class = b43_nphy_classifier(dev, 0, 0);
1612 b43_nphy_classifier(dev, 7, 4);
1613 b43_nphy_read_clip_detection(dev, clip_state);
1614 b43_nphy_write_clip_detection(dev, clip_off);
1616 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1617 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1618 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1619 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1621 b43_nphy_rf_control_intc_override(dev, 0, 0, 7);
1622 b43_nphy_rf_control_intc_override(dev, 1, 1, 7);
1623 b43_nphy_rf_control_override(dev, 0x1, 0, 0, false);
1624 b43_nphy_rf_control_override(dev, 0x2, 1, 0, false);
1625 b43_nphy_rf_control_override(dev, 0x80, 1, 0, false);
1626 b43_nphy_rf_control_override(dev, 0x40, 1, 0, false);
1628 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1629 b43_nphy_rf_control_override(dev, 0x20, 0, 0, false);
1630 b43_nphy_rf_control_override(dev, 0x10, 1, 0, false);
1632 b43_nphy_rf_control_override(dev, 0x10, 0, 0, false);
1633 b43_nphy_rf_control_override(dev, 0x20, 1, 0, false);
1636 rx_core_state = b43_nphy_get_rx_core_state(dev);
1637 for (core = 0; core < 2; core++) {
1638 if (!(rx_core_state & (1 << core)))
1640 r = core ? B2056_RX1 : B2056_RX0;
1641 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
1643 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
1646 /* Grab RSSI results for every possible VCM */
1647 for (vcm = 0; vcm < 8; vcm++) {
1648 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1650 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
1653 /* Find out which VCM got the best results */
1654 for (i = 0; i < 4; i += 2) {
1656 s32 mind = 0x100000;
1661 for (vcm = 0; vcm < 8; vcm++) {
1662 currd = results[vcm][i] * results[vcm][i] +
1663 results[vcm][i + 1] * results[vcm][i];
1668 if (results[vcm][i] < minpoll)
1669 minpoll = results[vcm][i];
1672 results_min[i] = minpoll;
1675 /* Select the best VCM */
1676 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1679 for (i = 0; i < 4; i++) {
1682 offset[i] = -results[vcm_final][i];
1684 offset[i] = -((abs(offset[i]) + 4) / 8);
1686 offset[i] = (offset[i] + 4) / 8;
1687 if (results_min[i] == 248)
1689 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1690 (i / 2 == 0) ? 1 : 2,
1691 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
1696 for (core = 0; core < 2; core++) {
1697 if (!(rx_core_state & (1 << core)))
1699 for (i = 0; i < 2; i++) {
1700 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1702 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1704 b43_nphy_poll_rssi(dev, i, poll_results, 8);
1705 for (j = 0; j < 4; j++) {
1706 if (j / 2 == core) {
1707 offset[j] = 232 - poll_results[j];
1709 offset[j] = -(abs(offset[j] + 4) / 8);
1711 offset[j] = (offset[j] + 4) / 8;
1712 b43_nphy_scale_offset_rssi(dev, 0,
1713 offset[2 * core], core + 1, j % 2, i);
1719 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1720 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1722 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1724 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1725 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1726 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1728 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1729 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
1730 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1732 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1733 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1735 /* Store for future configuration */
1736 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1737 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1738 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1740 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1741 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1743 rssical_radio_regs[0] = b43_radio_read(dev, 0x602B);
1744 rssical_radio_regs[0] = b43_radio_read(dev, 0x702B);
1745 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1746 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1747 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1748 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1749 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1750 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1751 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1752 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1753 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1754 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1755 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1756 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1758 /* Remember for which channel we store configuration */
1759 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1760 nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
1762 nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
1764 /* End of calibration, restore configuration */
1765 b43_nphy_classifier(dev, 7, class);
1766 b43_nphy_write_clip_detection(dev, clip_state);
1769 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1770 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
1775 u16 class, override;
1776 u8 regs_save_radio[2];
1777 u16 regs_save_phy[2];
1784 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1785 s32 results_min[4] = { };
1786 u8 vcm_final[4] = { };
1787 s32 results[4][4] = { };
1788 s32 miniq[4][2] = { };
1790 if (type == N_RSSI_NB) {
1793 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
1801 class = b43_nphy_classifier(dev, 0, 0);
1802 b43_nphy_classifier(dev, 7, 4);
1803 b43_nphy_read_clip_detection(dev, clip_state);
1804 b43_nphy_write_clip_detection(dev, clip_off);
1806 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1811 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1812 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1813 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1814 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1816 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1817 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1818 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1819 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1821 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1822 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1823 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1824 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1825 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1826 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1828 b43_nphy_rssi_select(dev, 5, type);
1829 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
1830 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
1832 for (vcm = 0; vcm < 4; vcm++) {
1834 for (j = 0; j < 4; j++)
1836 if (type != N_RSSI_W2)
1837 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1838 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
1839 if (type == N_RSSI_W1 || type == N_RSSI_W2)
1840 for (j = 0; j < 2; j++)
1841 miniq[vcm][j] = min(results[vcm][2 * j],
1842 results[vcm][2 * j + 1]);
1845 for (i = 0; i < 4; i++) {
1846 s32 mind = 0x100000;
1850 for (vcm = 0; vcm < 4; vcm++) {
1851 if (type == N_RSSI_NB)
1852 currd = abs(results[vcm][i] - code * 8);
1854 currd = abs(miniq[vcm][i / 2] - code * 8);
1861 if (results[vcm][i] < minpoll)
1862 minpoll = results[vcm][i];
1864 results_min[i] = minpoll;
1865 vcm_final[i] = minvcm;
1868 if (type != N_RSSI_W2)
1869 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1871 for (i = 0; i < 4; i++) {
1872 offset[i] = (code * 8) - results[vcm_final[i]][i];
1875 offset[i] = -((abs(offset[i]) + 4) / 8);
1877 offset[i] = (offset[i] + 4) / 8;
1879 if (results_min[i] == 248)
1880 offset[i] = code - 32;
1882 core = (i / 2) ? 2 : 1;
1883 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
1885 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
1889 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1890 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
1894 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
1897 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
1900 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
1903 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
1909 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
1912 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
1915 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
1919 b43_nphy_rssi_select(dev, 0, type);
1921 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1922 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1923 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1924 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1926 b43_nphy_classifier(dev, 7, class);
1927 b43_nphy_write_clip_detection(dev, clip_state);
1928 /* Specs don't say about reset here, but it makes wl and b43 dumps
1929 identical, it really seems wl performs this */
1930 b43_nphy_reset_cca(dev);
1935 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1937 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1939 if (dev->phy.rev >= 3) {
1940 b43_nphy_rev3_rssi_cal(dev);
1942 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
1943 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
1944 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
1948 /**************************************************
1950 **************************************************/
1952 static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1954 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1959 struct nphy_gain_ctl_workaround_entry *e;
1960 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1961 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1963 /* Prepare values */
1964 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1965 & B43_NPHY_BANDCTL_5GHZ;
1966 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
1967 sprom->boardflags_lo & B43_BFL_EXTLNA;
1968 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1969 if (ghz5 && dev->phy.rev >= 5)
1974 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1976 /* Set Clip 2 detect */
1977 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1978 B43_NPHY_C1_CGAINI_CL2DETECT);
1979 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1980 B43_NPHY_C2_CGAINI_CL2DETECT);
1982 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1984 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1986 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1987 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1988 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1989 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1990 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1992 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1994 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1996 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1998 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1999 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2001 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2002 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2003 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2004 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2005 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2006 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2007 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2008 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2009 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2010 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2011 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2012 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2014 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
2015 b43_phy_write(dev, 0x2A7, e->init_gain);
2016 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2019 /* TODO: check defines. Do not match variables names */
2020 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
2021 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
2022 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
2023 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
2024 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
2025 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
2027 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
2028 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
2029 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
2030 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2031 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2032 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2033 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2034 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2035 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2036 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2039 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2041 struct b43_phy_n *nphy = dev->phy.n;
2046 u8 rfseq_events[3] = { 6, 8, 7 };
2047 u8 rfseq_delays[3] = { 10, 30, 1 };
2049 /* Set Clip 2 detect */
2050 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2051 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2053 /* Set narrowband clip threshold */
2054 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2055 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2057 if (!dev->phy.is_40mhz) {
2058 /* Set dwell lengths */
2059 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2060 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2061 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2062 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2065 /* Set wideband clip 2 threshold */
2066 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2067 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2068 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2069 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2071 if (!dev->phy.is_40mhz) {
2072 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2073 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2074 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2075 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2076 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2077 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2078 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2079 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2082 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2084 if (nphy->gain_boost) {
2085 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2091 code = dev->phy.is_40mhz ? 6 : 7;
2094 /* Set HPVGA2 index */
2095 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2096 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2097 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2098 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2100 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2101 /* specs say about 2 loops, but wl does 4 */
2102 for (i = 0; i < 4; i++)
2103 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2105 b43_nphy_adjust_lna_gain_table(dev);
2107 if (nphy->elna_gain_config) {
2108 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2109 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2110 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2111 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2112 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2114 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2115 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2116 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2117 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2118 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2120 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2121 /* specs say about 2 loops, but wl does 4 */
2122 for (i = 0; i < 4; i++)
2123 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2124 (code << 8 | 0x74));
2127 if (dev->phy.rev == 2) {
2128 for (i = 0; i < 4; i++) {
2129 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2130 (0x0400 * i) + 0x0020);
2131 for (j = 0; j < 21; j++) {
2132 tmp = j * (i < 2 ? 3 : 1);
2134 B43_NPHY_TABLE_DATALO, tmp);
2139 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2140 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2141 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2142 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2144 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2145 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2148 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2149 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2151 if (dev->phy.rev >= 7)
2153 else if (dev->phy.rev >= 3)
2154 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2156 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
2159 /* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2160 static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2163 offset = (dev->phy.is_40mhz) ? 0x159 : 0x154;
2164 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2167 static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2169 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2170 struct b43_phy *phy = &dev->phy;
2172 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2174 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2176 u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2177 u8 ntab7_138_146[] = { 0x11, 0x11 };
2178 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2180 u16 lpf_20, lpf_40, lpf_11b;
2181 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2182 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2183 bool rccal_ovrd = false;
2185 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2186 u16 bias, conv, filt;
2191 if (phy->rev == 7) {
2192 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2193 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2194 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2195 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2196 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2197 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2198 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2199 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2200 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2201 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2202 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2203 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2204 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2205 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2206 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2207 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2208 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2210 if (phy->rev <= 8) {
2211 b43_phy_write(dev, 0x23F, 0x1B0);
2212 b43_phy_write(dev, 0x240, 0x1B0);
2215 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2217 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2218 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2219 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2221 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2222 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2223 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2225 if (b43_nphy_ipa(dev))
2226 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2227 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2229 b43_phy_maskset(dev, 0x299, 0x3FFF, 0x4000);
2230 b43_phy_maskset(dev, 0x29D, 0x3FFF, 0x4000);
2232 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2233 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2234 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2235 if (b43_nphy_ipa(dev)) {
2236 if ((phy->radio_rev == 5 && phy->is_40mhz) ||
2237 phy->radio_rev == 7 || phy->radio_rev == 8) {
2238 bcap_val = b43_radio_read(dev, 0x16b);
2239 scap_val = b43_radio_read(dev, 0x16a);
2240 scap_val_11b = scap_val;
2241 bcap_val_11b = bcap_val;
2242 if (phy->radio_rev == 5 && phy->is_40mhz) {
2243 scap_val_11n_20 = scap_val;
2244 bcap_val_11n_20 = bcap_val;
2245 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2247 } else { /* Rev 7/8 */
2250 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2251 scap_val_11n_20 = 0xc;
2252 bcap_val_11n_20 = 0xc;
2253 scap_val_11n_40 = 0xa;
2254 bcap_val_11n_40 = 0xa;
2256 scap_val_11n_20 = 0x14;
2257 bcap_val_11n_20 = 0x14;
2258 scap_val_11n_40 = 0xf;
2259 bcap_val_11n_40 = 0xf;
2265 if (phy->radio_rev == 5) {
2268 bcap_val = b43_radio_read(dev, 0x16b);
2269 scap_val = b43_radio_read(dev, 0x16a);
2270 scap_val_11b = scap_val;
2271 bcap_val_11b = bcap_val;
2272 scap_val_11n_20 = 0x11;
2273 scap_val_11n_40 = 0x11;
2274 bcap_val_11n_20 = 0x13;
2275 bcap_val_11n_40 = 0x13;
2280 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2281 (scap_val_11b << 3) |
2283 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2284 (scap_val_11n_20 << 3) |
2286 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2287 (scap_val_11n_40 << 3) |
2289 for (core = 0; core < 2; core++) {
2290 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2292 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2294 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2296 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2298 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2300 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2302 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2304 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2307 b43_nphy_rf_control_override_rev7(dev, 16, 1, 3, false, 2);
2309 b43_phy_write(dev, 0x32F, 0x3);
2310 if (phy->radio_rev == 4 || phy->radio_rev == 6)
2311 b43_nphy_rf_control_override_rev7(dev, 4, 1, 3, false, 0);
2313 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2314 if (sprom->revision &&
2315 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2316 b43_radio_write(dev, 0x5, 0x05);
2317 b43_radio_write(dev, 0x6, 0x30);
2318 b43_radio_write(dev, 0x7, 0x00);
2319 b43_radio_set(dev, 0x4f, 0x1);
2320 b43_radio_set(dev, 0xd4, 0x1);
2329 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2330 for (core = 0; core < 2; core++) {
2332 b43_radio_write(dev, 0x5F, bias);
2333 b43_radio_write(dev, 0x64, conv);
2334 b43_radio_write(dev, 0x66, filt);
2336 b43_radio_write(dev, 0xE8, bias);
2337 b43_radio_write(dev, 0xE9, conv);
2338 b43_radio_write(dev, 0xEB, filt);
2344 if (b43_nphy_ipa(dev)) {
2345 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2346 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2347 phy->radio_rev == 6) {
2348 for (core = 0; core < 2; core++) {
2350 b43_radio_write(dev, 0x51,
2353 b43_radio_write(dev, 0xd6,
2357 if (phy->radio_rev == 3) {
2358 for (core = 0; core < 2; core++) {
2360 b43_radio_write(dev, 0x64,
2362 b43_radio_write(dev, 0x5F,
2364 b43_radio_write(dev, 0x66,
2366 b43_radio_write(dev, 0x59,
2368 b43_radio_write(dev, 0x80,
2371 b43_radio_write(dev, 0x69,
2373 b43_radio_write(dev, 0xE8,
2375 b43_radio_write(dev, 0xEB,
2377 b43_radio_write(dev, 0xDE,
2379 b43_radio_write(dev, 0x105,
2383 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2384 if (!phy->is_40mhz) {
2385 b43_radio_write(dev, 0x5F, 0x14);
2386 b43_radio_write(dev, 0xE8, 0x12);
2388 b43_radio_write(dev, 0x5F, 0x16);
2389 b43_radio_write(dev, 0xE8, 0x16);
2393 u16 freq = phy->channel_freq;
2394 if ((freq >= 5180 && freq <= 5230) ||
2395 (freq >= 5745 && freq <= 5805)) {
2396 b43_radio_write(dev, 0x7D, 0xFF);
2397 b43_radio_write(dev, 0xFE, 0xFF);
2401 if (phy->radio_rev != 5) {
2402 for (core = 0; core < 2; core++) {
2404 b43_radio_write(dev, 0x5c, 0x61);
2405 b43_radio_write(dev, 0x51, 0x70);
2407 b43_radio_write(dev, 0xe1, 0x61);
2408 b43_radio_write(dev, 0xd6, 0x70);
2414 if (phy->radio_rev == 4) {
2415 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2416 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2417 for (core = 0; core < 2; core++) {
2419 b43_radio_write(dev, 0x1a1, 0x00);
2420 b43_radio_write(dev, 0x1a2, 0x3f);
2421 b43_radio_write(dev, 0x1a6, 0x3f);
2423 b43_radio_write(dev, 0x1a7, 0x00);
2424 b43_radio_write(dev, 0x1ab, 0x3f);
2425 b43_radio_write(dev, 0x1ac, 0x3f);
2429 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2430 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2431 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2432 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2434 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2435 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2436 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2437 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2438 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2439 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2441 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2442 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2443 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2444 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2447 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2449 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2450 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2451 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2452 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2453 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2454 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2455 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2457 if (!phy->is_40mhz) {
2458 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2459 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2461 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2462 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2465 b43_nphy_gain_ctl_workarounds(dev);
2468 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2469 aux_adc_vmid_rev7_core0);
2470 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2471 aux_adc_vmid_rev7_core1);
2472 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2474 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2479 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2481 struct b43_phy_n *nphy = dev->phy.n;
2482 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2485 u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
2486 u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
2488 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2490 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2491 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2492 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2497 b43_phy_write(dev, 0x23f, 0x1f8);
2498 b43_phy_write(dev, 0x240, 0x1f8);
2500 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2502 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2504 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2505 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2506 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2507 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2508 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2509 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
2511 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
2512 b43_phy_write(dev, 0x2AE, 0x000C);
2515 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2516 ARRAY_SIZE(tx2rx_events));
2519 if (b43_nphy_ipa(dev))
2520 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2521 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2522 if (nphy->hw_phyrxchain != 3 &&
2523 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2524 if (b43_nphy_ipa(dev)) {
2525 rx2tx_delays[5] = 59;
2526 rx2tx_delays[6] = 1;
2527 rx2tx_events[7] = 0x1F;
2529 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
2530 ARRAY_SIZE(rx2tx_events));
2533 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2535 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
2537 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
2539 if (!dev->phy.is_40mhz) {
2540 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2541 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2543 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2544 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2547 b43_nphy_gain_ctl_workarounds(dev);
2549 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2550 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
2554 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2555 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2556 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2557 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2558 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2559 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2560 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2561 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2562 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2563 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2564 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2565 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2567 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2569 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2570 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2571 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2572 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2576 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2577 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2578 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2580 if (dev->phy.rev == 4 &&
2581 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2582 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2584 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2588 /* Dropped probably-always-true condition */
2589 b43_phy_write(dev, 0x224, 0x03eb);
2590 b43_phy_write(dev, 0x225, 0x03eb);
2591 b43_phy_write(dev, 0x226, 0x0341);
2592 b43_phy_write(dev, 0x227, 0x0341);
2593 b43_phy_write(dev, 0x228, 0x042b);
2594 b43_phy_write(dev, 0x229, 0x042b);
2595 b43_phy_write(dev, 0x22a, 0x0381);
2596 b43_phy_write(dev, 0x22b, 0x0381);
2597 b43_phy_write(dev, 0x22c, 0x042b);
2598 b43_phy_write(dev, 0x22d, 0x042b);
2599 b43_phy_write(dev, 0x22e, 0x0381);
2600 b43_phy_write(dev, 0x22f, 0x0381);
2602 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2603 ; /* TODO: 0x0080000000000000 HF */
2606 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2608 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2609 struct b43_phy *phy = &dev->phy;
2610 struct b43_phy_n *nphy = phy->n;
2612 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2613 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
2615 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2616 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
2618 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
2619 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
2624 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2625 nphy->band5g_pwrgain) {
2626 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2627 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
2629 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2630 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2633 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2634 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
2635 if (dev->phy.rev < 3) {
2636 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2637 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2640 if (dev->phy.rev < 2) {
2641 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2642 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2643 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2644 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2645 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2646 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2649 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2650 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2651 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2652 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
2654 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2655 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2657 b43_nphy_gain_ctl_workarounds(dev);
2659 if (dev->phy.rev < 2) {
2660 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2661 b43_hf_write(dev, b43_hf_read(dev) |
2663 } else if (dev->phy.rev == 2) {
2664 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2665 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2668 if (dev->phy.rev < 2)
2669 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2670 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2672 /* Set phase track alpha and beta */
2673 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2674 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2675 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2676 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2677 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2678 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2680 if (dev->phy.rev < 3) {
2681 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2682 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2683 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2684 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2685 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2688 if (dev->phy.rev == 2)
2689 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2690 B43_NPHY_FINERX2_CGC_DECGC);
2693 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2694 static void b43_nphy_workarounds(struct b43_wldev *dev)
2696 struct b43_phy *phy = &dev->phy;
2697 struct b43_phy_n *nphy = phy->n;
2699 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2700 b43_nphy_classifier(dev, 1, 0);
2702 b43_nphy_classifier(dev, 1, 1);
2704 if (nphy->hang_avoid)
2705 b43_nphy_stay_in_carrier_search(dev, 1);
2707 b43_phy_set(dev, B43_NPHY_IQFLIP,
2708 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2710 if (dev->phy.rev >= 7)
2711 b43_nphy_workarounds_rev7plus(dev);
2712 else if (dev->phy.rev >= 3)
2713 b43_nphy_workarounds_rev3plus(dev);
2715 b43_nphy_workarounds_rev1_2(dev);
2717 if (nphy->hang_avoid)
2718 b43_nphy_stay_in_carrier_search(dev, 0);
2721 /**************************************************
2723 **************************************************/
2726 * Transmits a known value for LO calibration
2727 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2729 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2730 bool iqmode, bool dac_test)
2732 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2735 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2739 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2740 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2742 struct b43_phy_n *nphy = dev->phy.n;
2744 bool override = false;
2747 if (nphy->txrx_chain == 0) {
2750 } else if (nphy->txrx_chain == 1) {
2755 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2756 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2760 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2761 B43_NPHY_RFSEQMODE_CAOVER);
2763 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2764 ~B43_NPHY_RFSEQMODE_CAOVER);
2767 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2768 static void b43_nphy_stop_playback(struct b43_wldev *dev)
2770 struct b43_phy_n *nphy = dev->phy.n;
2773 if (nphy->hang_avoid)
2774 b43_nphy_stay_in_carrier_search(dev, 1);
2776 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2778 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2780 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
2782 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
2784 if (nphy->bb_mult_save & 0x80000000) {
2785 tmp = nphy->bb_mult_save & 0xFFFF;
2786 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
2787 nphy->bb_mult_save = 0;
2790 if (nphy->hang_avoid)
2791 b43_nphy_stay_in_carrier_search(dev, 0);
2794 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2795 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2796 struct nphy_txgains target,
2797 struct nphy_iqcal_params *params)
2802 if (dev->phy.rev >= 3) {
2803 params->txgm = target.txgm[core];
2804 params->pga = target.pga[core];
2805 params->pad = target.pad[core];
2806 params->ipa = target.ipa[core];
2807 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2808 (params->pad << 4) | (params->ipa);
2809 for (j = 0; j < 5; j++)
2810 params->ncorr[j] = 0x79;
2812 gain = (target.pad[core]) | (target.pga[core] << 4) |
2813 (target.txgm[core] << 8);
2815 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2817 for (i = 0; i < 9; i++)
2818 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2822 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2823 params->pga = tbl_iqcal_gainparams[indx][i][2];
2824 params->pad = tbl_iqcal_gainparams[indx][i][3];
2825 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2827 for (j = 0; j < 4; j++)
2828 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2832 /**************************************************
2834 **************************************************/
2836 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
2840 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
2843 return B43_TXPWR_RES_DONE;
2846 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
2847 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
2849 struct b43_phy_n *nphy = dev->phy.n;
2851 u16 bmask, val, tmp;
2852 enum ieee80211_band band = b43_current_band(dev->wl);
2854 if (nphy->hang_avoid)
2855 b43_nphy_stay_in_carrier_search(dev, 1);
2857 nphy->txpwrctrl = enable;
2859 if (dev->phy.rev >= 3 &&
2860 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
2861 (B43_NPHY_TXPCTL_CMD_COEFF |
2862 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
2863 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
2864 /* We disable enabled TX pwr ctl, save it's state */
2865 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
2866 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
2867 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
2868 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
2871 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
2872 for (i = 0; i < 84; i++)
2873 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2875 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
2876 for (i = 0; i < 84; i++)
2877 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2879 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2880 if (dev->phy.rev >= 3)
2881 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2882 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
2884 if (dev->phy.rev >= 3) {
2885 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2886 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2888 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2891 if (dev->phy.rev == 2)
2892 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2893 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
2894 else if (dev->phy.rev < 2)
2895 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2896 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
2898 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2899 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
2901 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
2903 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
2906 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
2907 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2908 /* wl does useless check for "enable" param here */
2909 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2910 if (dev->phy.rev >= 3) {
2911 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2913 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2915 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
2917 if (band == IEEE80211_BAND_5GHZ) {
2918 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2919 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
2920 if (dev->phy.rev > 1)
2921 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2922 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
2926 if (dev->phy.rev >= 3) {
2927 if (nphy->tx_pwr_idx[0] != 128 &&
2928 nphy->tx_pwr_idx[1] != 128) {
2929 /* Recover TX pwr ctl state */
2930 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2931 ~B43_NPHY_TXPCTL_CMD_INIT,
2932 nphy->tx_pwr_idx[0]);
2933 if (dev->phy.rev > 1)
2934 b43_phy_maskset(dev,
2935 B43_NPHY_TXPCTL_INIT,
2936 ~0xff, nphy->tx_pwr_idx[1]);
2940 if (dev->phy.rev >= 3) {
2941 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
2942 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
2944 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
2947 if (dev->phy.rev == 2)
2948 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
2949 else if (dev->phy.rev < 2)
2950 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
2952 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2953 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
2955 if (b43_nphy_ipa(dev)) {
2956 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
2957 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
2961 if (nphy->hang_avoid)
2962 b43_nphy_stay_in_carrier_search(dev, 0);
2965 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
2966 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
2968 struct b43_phy_n *nphy = dev->phy.n;
2969 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2971 u8 txpi[2], bbmult, i;
2972 u16 tmp, radio_gain, dac_gain;
2973 u16 freq = dev->phy.channel_freq;
2975 /* u32 gaintbl; rev3+ */
2977 if (nphy->hang_avoid)
2978 b43_nphy_stay_in_carrier_search(dev, 1);
2980 if (dev->phy.rev >= 7) {
2981 txpi[0] = txpi[1] = 30;
2982 } else if (dev->phy.rev >= 3) {
2985 } else if (sprom->revision < 4) {
2989 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2990 txpi[0] = sprom->txpid2g[0];
2991 txpi[1] = sprom->txpid2g[1];
2992 } else if (freq >= 4900 && freq < 5100) {
2993 txpi[0] = sprom->txpid5gl[0];
2994 txpi[1] = sprom->txpid5gl[1];
2995 } else if (freq >= 5100 && freq < 5500) {
2996 txpi[0] = sprom->txpid5g[0];
2997 txpi[1] = sprom->txpid5g[1];
2998 } else if (freq >= 5500) {
2999 txpi[0] = sprom->txpid5gh[0];
3000 txpi[1] = sprom->txpid5gh[1];
3006 if (dev->phy.rev < 7 &&
3007 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
3008 txpi[0] = txpi[1] = 91;
3011 for (i = 0; i < 2; i++) {
3012 nphy->txpwrindex[i].index_internal = txpi[i];
3013 nphy->txpwrindex[i].index_internal_save = txpi[i];
3017 for (i = 0; i < 2; i++) {
3018 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
3020 if (dev->phy.rev >= 3)
3021 radio_gain = (txgain >> 16) & 0x1FFFF;
3023 radio_gain = (txgain >> 16) & 0x1FFF;
3025 if (dev->phy.rev >= 7)
3026 dac_gain = (txgain >> 8) & 0x7;
3028 dac_gain = (txgain >> 8) & 0x3F;
3029 bbmult = txgain & 0xFF;
3031 if (dev->phy.rev >= 3) {
3033 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3035 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3037 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3041 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3043 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
3045 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
3047 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
3049 tmp = (tmp & 0x00FF) | (bbmult << 8);
3051 tmp = (tmp & 0xFF00) | bbmult;
3052 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
3054 if (b43_nphy_ipa(dev)) {
3056 u16 reg = (i == 0) ?
3057 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
3058 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3060 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3061 b43_phy_set(dev, reg, 0x4);
3065 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
3067 if (nphy->hang_avoid)
3068 b43_nphy_stay_in_carrier_search(dev, 0);
3071 static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3073 struct b43_phy *phy = &dev->phy;
3076 u16 r; /* routing */
3078 if (phy->rev >= 7) {
3079 for (core = 0; core < 2; core++) {
3080 r = core ? 0x190 : 0x170;
3081 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3082 b43_radio_write(dev, r + 0x5, 0x5);
3083 b43_radio_write(dev, r + 0x9, 0xE);
3085 b43_radio_write(dev, r + 0xA, 0);
3087 b43_radio_write(dev, r + 0xB, 1);
3089 b43_radio_write(dev, r + 0xB, 0x31);
3091 b43_radio_write(dev, r + 0x5, 0x9);
3092 b43_radio_write(dev, r + 0x9, 0xC);
3093 b43_radio_write(dev, r + 0xB, 0x0);
3095 b43_radio_write(dev, r + 0xA, 1);
3097 b43_radio_write(dev, r + 0xA, 0x31);
3099 b43_radio_write(dev, r + 0x6, 0);
3100 b43_radio_write(dev, r + 0x7, 0);
3101 b43_radio_write(dev, r + 0x8, 3);
3102 b43_radio_write(dev, r + 0xC, 0);
3105 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3106 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3108 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3109 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3110 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3112 for (core = 0; core < 2; core++) {
3113 r = core ? B2056_TX1 : B2056_TX0;
3115 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3116 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3117 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3118 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3119 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3120 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3121 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3122 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3123 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3126 b43_radio_write(dev, r | B2056_TX_TSSIA,
3129 b43_radio_write(dev, r | B2056_TX_TSSIG,
3132 b43_radio_write(dev, r | B2056_TX_TSSIG,
3134 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3137 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3139 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3140 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3141 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3149 * Stop radio and transmit known signal. Then check received signal strength to
3150 * get TSSI (Transmit Signal Strength Indicator).
3151 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3153 static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3155 struct b43_phy *phy = &dev->phy;
3156 struct b43_phy_n *nphy = dev->phy.n;
3161 /* TODO: check if we can transmit */
3163 if (b43_nphy_ipa(dev))
3164 b43_nphy_ipa_internal_tssi_setup(dev);
3167 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, false, 0);
3168 else if (phy->rev >= 3)
3169 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, false);
3171 b43_nphy_stop_playback(dev);
3172 b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3174 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3175 b43_nphy_stop_playback(dev);
3176 b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3179 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, true, 0);
3180 else if (phy->rev >= 3)
3181 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, true);
3183 if (phy->rev >= 3) {
3184 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3185 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3187 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3188 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3190 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3191 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3194 /* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3195 static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3197 struct b43_phy_n *nphy = dev->phy.n;
3202 for (i = 0; i < 4; i++)
3203 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3205 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3209 if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
3213 idx = dev->phy.is_40mhz ? 52 : 4;
3217 idx = dev->phy.is_40mhz ? 76 : 28;
3220 idx = dev->phy.is_40mhz ? 84 : 36;
3223 idx = dev->phy.is_40mhz ? 92 : 44;
3227 for (i = 0; i < 20; i++) {
3228 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3229 nphy->tx_power_offset[idx];
3234 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3241 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3242 static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3244 struct b43_phy_n *nphy = dev->phy.n;
3245 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3247 s16 a1[2], b0[2], b1[2];
3253 u16 freq = dev->phy.channel_freq;
3255 u16 r; /* routing */
3258 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3259 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3260 b43_read32(dev, B43_MMIO_MACCTL);
3264 if (nphy->hang_avoid)
3265 b43_nphy_stay_in_carrier_search(dev, true);
3267 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3268 if (dev->phy.rev >= 3)
3269 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3270 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3272 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3273 B43_NPHY_TXPCTL_CMD_PCTLEN);
3275 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3276 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3278 if (sprom->revision < 4) {
3279 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3280 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3281 target[0] = target[1] = 52;
3282 a1[0] = a1[1] = -424;
3283 b0[0] = b0[1] = 5612;
3284 b1[0] = b1[1] = -1393;
3286 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3287 for (c = 0; c < 2; c++) {
3288 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3289 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3290 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3291 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3292 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3294 } else if (freq >= 4900 && freq < 5100) {
3295 for (c = 0; c < 2; c++) {
3296 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3297 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3298 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3299 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3300 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3302 } else if (freq >= 5100 && freq < 5500) {
3303 for (c = 0; c < 2; c++) {
3304 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3305 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3306 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3307 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3308 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3310 } else if (freq >= 5500) {
3311 for (c = 0; c < 2; c++) {
3312 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3313 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3314 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3315 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3316 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3319 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3320 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3321 target[0] = target[1] = 52;
3322 a1[0] = a1[1] = -424;
3323 b0[0] = b0[1] = 5612;
3324 b1[0] = b1[1] = -1393;
3327 /* target[0] = target[1] = nphy->tx_power_max; */
3329 if (dev->phy.rev >= 3) {
3330 if (sprom->fem.ghz2.tssipos)
3331 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3332 if (dev->phy.rev >= 7) {
3333 for (c = 0; c < 2; c++) {
3334 r = c ? 0x190 : 0x170;
3335 if (b43_nphy_ipa(dev))
3336 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3339 if (b43_nphy_ipa(dev)) {
3340 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3341 b43_radio_write(dev,
3342 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3343 b43_radio_write(dev,
3344 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3346 b43_radio_write(dev,
3347 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3348 b43_radio_write(dev,
3349 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3354 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3355 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3356 b43_read32(dev, B43_MMIO_MACCTL);
3360 if (dev->phy.rev >= 7) {
3361 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3362 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3363 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3364 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3366 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3367 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3368 if (dev->phy.rev > 1)
3369 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3370 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3373 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3374 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3376 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3377 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3378 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3379 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3380 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3381 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3382 B43_NPHY_TXPCTL_ITSSI_BINF);
3383 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3384 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3385 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3387 for (c = 0; c < 2; c++) {
3388 for (i = 0; i < 64; i++) {
3389 num = 8 * (16 * b0[c] + b1[c] * i);
3390 den = 32768 + a1[c] * i;
3391 pwr = max((4 * num + den / 2) / den, -8);
3392 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3393 pwr = max(pwr, target[c] + 1);
3396 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3399 b43_nphy_tx_prepare_adjusted_power_table(dev);
3401 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3402 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
3405 if (nphy->hang_avoid)
3406 b43_nphy_stay_in_carrier_search(dev, false);
3409 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3411 struct b43_phy *phy = &dev->phy;
3413 const u32 *table = NULL;
3418 table = b43_nphy_get_tx_gain_table(dev);
3419 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3420 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3422 if (phy->rev >= 3) {
3424 nphy->gmval = (table[0] >> 16) & 0x7000;
3427 for (i = 0; i < 128; i++) {
3428 pga_gain = (table[i] >> 24) & 0xF;
3429 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3431 b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
3435 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3437 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3443 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3444 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
3446 struct b43_phy_n *nphy = dev->phy.n;
3447 enum ieee80211_band band;
3451 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3452 B43_NPHY_RFCTL_INTC1);
3453 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3454 B43_NPHY_RFCTL_INTC2);
3455 band = b43_current_band(dev->wl);
3456 if (dev->phy.rev >= 3) {
3457 if (band == IEEE80211_BAND_5GHZ)
3462 if (band == IEEE80211_BAND_5GHZ)
3467 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3468 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3470 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3471 nphy->rfctrl_intc1_save);
3472 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3473 nphy->rfctrl_intc2_save);
3477 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
3478 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
3482 if (dev->phy.rev >= 3) {
3483 if (b43_nphy_ipa(dev)) {
3485 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3486 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3490 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
3491 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3495 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3496 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3497 u16 samps, u8 time, bool wait)
3502 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3503 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3505 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
3507 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
3509 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3511 for (i = 1000; i; i--) {
3512 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3513 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3514 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3515 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3516 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3517 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3518 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3519 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3521 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3522 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3523 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3524 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3525 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3526 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3531 memset(est, 0, sizeof(*est));
3534 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
3535 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3536 struct b43_phy_n_iq_comp *pcomp)
3539 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3540 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3541 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3542 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
3544 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3545 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3546 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3547 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3552 /* Ready but not used anywhere */
3553 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
3554 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3556 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3558 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3560 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3561 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3563 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3564 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3566 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3567 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3568 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3569 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3570 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3571 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3572 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3573 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3576 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
3577 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3580 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3582 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3584 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3585 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3587 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3588 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3590 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3591 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3592 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3593 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3594 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3595 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3596 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3597 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3599 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3600 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3602 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3603 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3604 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3605 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3606 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3607 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3608 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3609 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3610 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
3613 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3614 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3616 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3617 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3620 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
3621 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
3622 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3631 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
3632 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
3636 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3637 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
3643 int iq_nbits, qq_nbits;
3647 struct nphy_iq_est est;
3648 struct b43_phy_n_iq_comp old;
3649 struct b43_phy_n_iq_comp new = { };
3655 b43_nphy_rx_iq_coeffs(dev, false, &old);
3656 b43_nphy_rx_iq_coeffs(dev, true, &new);
3657 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3660 for (i = 0; i < 2; i++) {
3661 if (i == 0 && (mask & 1)) {
3665 } else if (i == 1 && (mask & 2)) {
3678 iq_nbits = fls(abs(iq));
3681 arsh = iq_nbits - 20;
3683 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3686 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3695 brsh = qq_nbits - 11;
3697 b = (qq << (31 - qq_nbits));
3700 b = (qq << (31 - qq_nbits));
3707 b = int_sqrt(b / tmp - a * a) - (1 << 10);
3709 if (i == 0 && (mask & 0x1)) {
3710 if (dev->phy.rev >= 3) {
3717 } else if (i == 1 && (mask & 0x2)) {
3718 if (dev->phy.rev >= 3) {
3731 b43_nphy_rx_iq_coeffs(dev, true, &new);
3734 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3735 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3738 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
3740 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3741 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3742 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3743 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
3746 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3747 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3749 struct b43_phy_n *nphy = dev->phy.n;
3751 u8 channel = dev->phy.channel;
3752 int tone[2] = { 57, 58 };
3753 u32 noise[2] = { 0x3FF, 0x3FF };
3755 B43_WARN_ON(dev->phy.rev < 3);
3757 if (nphy->hang_avoid)
3758 b43_nphy_stay_in_carrier_search(dev, 1);
3760 if (nphy->gband_spurwar_en) {
3761 /* TODO: N PHY Adjust Analog Pfbw (7) */
3762 if (channel == 11 && dev->phy.is_40mhz)
3763 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
3765 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3766 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
3769 if (nphy->aband_spurwar_en) {
3770 if (channel == 54) {
3773 } else if (channel == 38 || channel == 102 || channel == 118) {
3774 if (0 /* FIXME */) {
3781 } else if (channel == 134) {
3784 } else if (channel == 151) {
3787 } else if (channel == 153 || channel == 161) {
3795 if (!tone[0] && !noise[0])
3796 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
3798 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3801 if (nphy->hang_avoid)
3802 b43_nphy_stay_in_carrier_search(dev, 0);
3805 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
3806 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
3808 struct b43_phy_n *nphy = dev->phy.n;
3811 u32 cur_real, cur_imag, real_part, imag_part;
3815 if (nphy->hang_avoid)
3816 b43_nphy_stay_in_carrier_search(dev, true);
3818 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3820 for (i = 0; i < 2; i++) {
3821 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
3822 (buffer[i * 2 + 1] & 0x3FF);
3823 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3824 (((i + 26) << 10) | 320));
3825 for (j = 0; j < 128; j++) {
3826 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3827 ((tmp >> 16) & 0xFFFF));
3828 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3833 for (i = 0; i < 2; i++) {
3834 tmp = buffer[5 + i];
3835 real_part = (tmp >> 8) & 0xFF;
3836 imag_part = (tmp & 0xFF);
3837 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3838 (((i + 26) << 10) | 448));
3840 if (dev->phy.rev >= 3) {
3841 cur_real = real_part;
3842 cur_imag = imag_part;
3843 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
3846 for (j = 0; j < 128; j++) {
3847 if (dev->phy.rev < 3) {
3848 cur_real = (real_part * loscale[j] + 128) >> 8;
3849 cur_imag = (imag_part * loscale[j] + 128) >> 8;
3850 tmp = ((cur_real & 0xFF) << 8) |
3853 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3854 ((tmp >> 16) & 0xFFFF));
3855 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3860 if (dev->phy.rev >= 3) {
3861 b43_shm_write16(dev, B43_SHM_SHARED,
3862 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
3863 b43_shm_write16(dev, B43_SHM_SHARED,
3864 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
3867 if (nphy->hang_avoid)
3868 b43_nphy_stay_in_carrier_search(dev, false);
3872 * Restore RSSI Calibration
3873 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
3875 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
3877 struct b43_phy_n *nphy = dev->phy.n;
3879 u16 *rssical_radio_regs = NULL;
3880 u16 *rssical_phy_regs = NULL;
3882 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3883 if (!nphy->rssical_chanspec_2G.center_freq)
3885 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
3886 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
3888 if (!nphy->rssical_chanspec_5G.center_freq)
3890 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
3891 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
3894 /* TODO use some definitions */
3895 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
3896 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
3898 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
3899 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
3900 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
3901 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
3903 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
3904 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
3905 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
3906 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
3908 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
3909 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
3910 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
3911 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
3914 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
3915 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
3917 struct b43_phy_n *nphy = dev->phy.n;
3918 u16 *save = nphy->tx_rx_cal_radio_saveregs;
3922 if (dev->phy.rev >= 3) {
3923 for (i = 0; i < 2; i++) {
3924 tmp = (i == 0) ? 0x2000 : 0x3000;
3927 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
3928 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
3929 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
3930 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
3931 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
3932 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
3933 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
3934 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
3935 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
3936 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
3937 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
3939 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3940 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
3941 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3942 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3943 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3944 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3945 if (nphy->ipa5g_on) {
3946 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
3947 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
3949 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3950 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
3952 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3954 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
3955 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3956 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3957 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3958 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3959 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
3960 if (nphy->ipa2g_on) {
3961 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
3962 b43_radio_write16(dev, tmp | B2055_XOCTL2,
3963 (dev->phy.rev < 5) ? 0x11 : 0x01);
3965 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3966 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3969 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
3970 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
3971 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
3974 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
3975 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
3977 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
3978 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
3980 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
3981 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
3983 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
3984 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
3986 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
3987 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
3989 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
3990 B43_NPHY_BANDCTL_5GHZ)) {
3991 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
3992 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
3994 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
3995 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
3998 if (dev->phy.rev < 2) {
3999 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
4000 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
4002 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
4003 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
4008 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
4009 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4011 struct b43_phy_n *nphy = dev->phy.n;
4015 u16 tmp = nphy->txcal_bbmult;
4020 for (i = 0; i < 18; i++) {
4021 scale = (ladder_lo[i].percent * tmp) / 100;
4022 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
4023 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
4025 scale = (ladder_iq[i].percent * tmp) / 100;
4026 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
4027 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
4031 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4032 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4035 for (i = 0; i < 15; i++)
4036 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4037 tbl_tx_filter_coef_rev4[2][i]);
4040 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4041 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4044 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
4045 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
4047 for (i = 0; i < 3; i++)
4048 for (j = 0; j < 15; j++)
4049 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4050 tbl_tx_filter_coef_rev4[i][j]);
4052 if (dev->phy.is_40mhz) {
4053 for (j = 0; j < 15; j++)
4054 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4055 tbl_tx_filter_coef_rev4[3][j]);
4056 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4057 for (j = 0; j < 15; j++)
4058 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4059 tbl_tx_filter_coef_rev4[5][j]);
4062 if (dev->phy.channel == 14)
4063 for (j = 0; j < 15; j++)
4064 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4065 tbl_tx_filter_coef_rev4[6][j]);
4068 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4069 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4071 struct b43_phy_n *nphy = dev->phy.n;
4074 struct nphy_txgains target;
4075 const u32 *table = NULL;
4077 if (!nphy->txpwrctrl) {
4080 if (nphy->hang_avoid)
4081 b43_nphy_stay_in_carrier_search(dev, true);
4082 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
4083 if (nphy->hang_avoid)
4084 b43_nphy_stay_in_carrier_search(dev, false);
4086 for (i = 0; i < 2; ++i) {
4087 if (dev->phy.rev >= 3) {
4088 target.ipa[i] = curr_gain[i] & 0x000F;
4089 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4090 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4091 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4093 target.ipa[i] = curr_gain[i] & 0x0003;
4094 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4095 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4096 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4102 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4103 B43_NPHY_TXPCTL_STAT_BIDX) >>
4104 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4105 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4106 B43_NPHY_TXPCTL_STAT_BIDX) >>
4107 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4109 for (i = 0; i < 2; ++i) {
4110 table = b43_nphy_get_tx_gain_table(dev);
4111 if (dev->phy.rev >= 3) {
4112 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4113 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4114 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4115 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4117 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4118 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4119 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4120 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4128 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4129 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4131 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4133 if (dev->phy.rev >= 3) {
4134 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4135 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4136 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4137 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4138 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
4139 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4140 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
4141 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4142 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4143 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4144 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4145 b43_nphy_reset_cca(dev);
4147 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4148 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4149 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
4150 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4151 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
4152 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4153 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4157 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4158 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4160 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4163 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4164 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4165 if (dev->phy.rev >= 3) {
4166 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4167 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4169 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4171 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4173 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4175 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4177 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
4178 b43_phy_mask(dev, B43_NPHY_BBCFG,
4179 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4181 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
4183 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
4185 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
4187 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
4188 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4189 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4191 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
4192 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
4193 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
4195 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4196 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4197 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4198 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4200 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4201 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4202 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4204 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
4205 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
4208 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
4209 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
4212 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
4213 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4214 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4215 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4219 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4220 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4224 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4225 static void b43_nphy_save_cal(struct b43_wldev *dev)
4227 struct b43_phy_n *nphy = dev->phy.n;
4229 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4230 u16 *txcal_radio_regs = NULL;
4231 struct b43_chanspec *iqcal_chanspec;
4234 if (nphy->hang_avoid)
4235 b43_nphy_stay_in_carrier_search(dev, 1);
4237 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4238 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4239 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4240 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4241 table = nphy->cal_cache.txcal_coeffs_2G;
4243 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4244 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4245 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4246 table = nphy->cal_cache.txcal_coeffs_5G;
4249 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4250 /* TODO use some definitions */
4251 if (dev->phy.rev >= 3) {
4252 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4253 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4254 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4255 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4256 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4257 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4258 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4259 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4261 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4262 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4263 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4264 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4266 iqcal_chanspec->center_freq = dev->phy.channel_freq;
4267 iqcal_chanspec->channel_type = dev->phy.channel_type;
4268 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
4270 if (nphy->hang_avoid)
4271 b43_nphy_stay_in_carrier_search(dev, 0);
4274 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4275 static void b43_nphy_restore_cal(struct b43_wldev *dev)
4277 struct b43_phy_n *nphy = dev->phy.n;
4284 u16 *txcal_radio_regs = NULL;
4285 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4287 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4288 if (!nphy->iqcal_chanspec_2G.center_freq)
4290 table = nphy->cal_cache.txcal_coeffs_2G;
4291 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4293 if (!nphy->iqcal_chanspec_5G.center_freq)
4295 table = nphy->cal_cache.txcal_coeffs_5G;
4296 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4299 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
4301 for (i = 0; i < 4; i++) {
4302 if (dev->phy.rev >= 3)
4308 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4309 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4310 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
4312 if (dev->phy.rev < 2)
4313 b43_nphy_tx_iq_workaround(dev);
4315 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4316 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4317 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4319 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4320 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4323 /* TODO use some definitions */
4324 if (dev->phy.rev >= 3) {
4325 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4326 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4327 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4328 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4329 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4330 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4331 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4332 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4334 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4335 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4336 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4337 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4339 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4342 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4343 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4344 struct nphy_txgains target,
4345 bool full, bool mphase)
4347 struct b43_phy_n *nphy = dev->phy.n;
4353 u16 tmp, core, type, count, max, numb, last = 0, cmd;
4361 struct nphy_iqcal_params params[2];
4362 bool updated[2] = { };
4364 b43_nphy_stay_in_carrier_search(dev, true);
4366 if (dev->phy.rev >= 4) {
4367 avoid = nphy->hang_avoid;
4368 nphy->hang_avoid = false;
4371 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
4373 for (i = 0; i < 2; i++) {
4374 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]);
4375 gain[i] = params[i].cal_gain;
4378 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
4380 b43_nphy_tx_cal_radio_setup(dev);
4381 b43_nphy_tx_cal_phy_setup(dev);
4383 phy6or5x = dev->phy.rev >= 6 ||
4384 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4385 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4387 if (dev->phy.is_40mhz) {
4388 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4389 tbl_tx_iqlo_cal_loft_ladder_40);
4390 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4391 tbl_tx_iqlo_cal_iqimb_ladder_40);
4393 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4394 tbl_tx_iqlo_cal_loft_ladder_20);
4395 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4396 tbl_tx_iqlo_cal_iqimb_ladder_20);
4400 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4402 if (!dev->phy.is_40mhz)
4407 if (nphy->mphase_cal_phase_id > 2)
4408 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
4409 0xFFFF, 0, true, false);
4411 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
4414 if (nphy->mphase_cal_phase_id > 2) {
4415 table = nphy->mphase_txcal_bestcoeffs;
4417 if (dev->phy.rev < 3)
4420 if (!full && nphy->txiqlocal_coeffsvalid) {
4421 table = nphy->txiqlocal_bestc;
4423 if (dev->phy.rev < 3)
4427 if (dev->phy.rev >= 3) {
4428 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4429 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4431 table = tbl_tx_iqlo_cal_startcoefs;
4432 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4437 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
4440 if (dev->phy.rev >= 3)
4441 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4443 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4445 if (dev->phy.rev >= 3)
4446 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4448 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4452 count = nphy->mphase_txcal_cmdidx;
4454 (u16)(count + nphy->mphase_txcal_numcmds));
4460 for (; count < numb; count++) {
4462 if (dev->phy.rev >= 3)
4463 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4465 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4467 if (dev->phy.rev >= 3)
4468 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4470 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4473 core = (cmd & 0x3000) >> 12;
4474 type = (cmd & 0x0F00) >> 8;
4476 if (phy6or5x && updated[core] == 0) {
4477 b43_nphy_update_tx_cal_ladder(dev, core);
4478 updated[core] = true;
4481 tmp = (params[core].ncorr[type] << 8) | 0x66;
4482 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4484 if (type == 1 || type == 3 || type == 4) {
4485 buffer[0] = b43_ntab_read(dev,
4486 B43_NTAB16(15, 69 + core));
4487 diq_start = buffer[0];
4489 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4493 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4494 for (i = 0; i < 2000; i++) {
4495 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4501 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4503 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4506 if (type == 1 || type == 3 || type == 4)
4507 buffer[0] = diq_start;
4511 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4513 last = (dev->phy.rev < 3) ? 6 : 7;
4515 if (!mphase || nphy->mphase_cal_phase_id == last) {
4516 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
4517 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
4518 if (dev->phy.rev < 3) {
4524 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4526 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
4528 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4530 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4533 if (dev->phy.rev < 3)
4535 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4536 nphy->txiqlocal_bestc);
4537 nphy->txiqlocal_coeffsvalid = true;
4538 nphy->txiqlocal_chanspec.center_freq =
4539 dev->phy.channel_freq;
4540 nphy->txiqlocal_chanspec.channel_type =
4541 dev->phy.channel_type;
4544 if (dev->phy.rev < 3)
4546 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4547 nphy->mphase_txcal_bestcoeffs);
4550 b43_nphy_stop_playback(dev);
4551 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4554 b43_nphy_tx_cal_phy_cleanup(dev);
4555 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
4557 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4558 b43_nphy_tx_iq_workaround(dev);
4560 if (dev->phy.rev >= 4)
4561 nphy->hang_avoid = avoid;
4563 b43_nphy_stay_in_carrier_search(dev, false);
4568 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
4569 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4571 struct b43_phy_n *nphy = dev->phy.n;
4576 if (!nphy->txiqlocal_coeffsvalid ||
4577 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
4578 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
4581 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4582 for (i = 0; i < 4; i++) {
4583 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4590 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4591 nphy->txiqlocal_bestc);
4592 for (i = 0; i < 4; i++)
4594 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4596 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4597 &nphy->txiqlocal_bestc[5]);
4598 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4599 &nphy->txiqlocal_bestc[5]);
4603 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
4604 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4605 struct nphy_txgains target, u8 type, bool debug)
4607 struct b43_phy_n *nphy = dev->phy.n;
4612 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
4614 enum ieee80211_band band;
4618 u16 lna[3] = { 3, 3, 1 };
4619 u16 hpf1[3] = { 7, 2, 0 };
4620 u16 hpf2[3] = { 2, 0, 0 };
4624 struct nphy_iqcal_params cal_params[2];
4625 struct nphy_iq_est est;
4627 bool playtone = true;
4630 b43_nphy_stay_in_carrier_search(dev, 1);
4632 if (dev->phy.rev < 2)
4633 b43_nphy_reapply_tx_cal_coeffs(dev);
4634 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4635 for (i = 0; i < 2; i++) {
4636 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4637 cal_gain[i] = cal_params[i].cal_gain;
4639 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
4641 for (i = 0; i < 2; i++) {
4643 rfctl[0] = B43_NPHY_RFCTL_INTC1;
4644 rfctl[1] = B43_NPHY_RFCTL_INTC2;
4645 afectl_core = B43_NPHY_AFECTL_C1;
4647 rfctl[0] = B43_NPHY_RFCTL_INTC2;
4648 rfctl[1] = B43_NPHY_RFCTL_INTC1;
4649 afectl_core = B43_NPHY_AFECTL_C2;
4652 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4653 tmp[2] = b43_phy_read(dev, afectl_core);
4654 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4655 tmp[4] = b43_phy_read(dev, rfctl[0]);
4656 tmp[5] = b43_phy_read(dev, rfctl[1]);
4658 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4659 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
4660 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4661 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4663 b43_phy_set(dev, afectl_core, 0x0006);
4664 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4666 band = b43_current_band(dev->wl);
4668 if (nphy->rxcalparams & 0xFF000000) {
4669 if (band == IEEE80211_BAND_5GHZ)
4670 b43_phy_write(dev, rfctl[0], 0x140);
4672 b43_phy_write(dev, rfctl[0], 0x110);
4674 if (band == IEEE80211_BAND_5GHZ)
4675 b43_phy_write(dev, rfctl[0], 0x180);
4677 b43_phy_write(dev, rfctl[0], 0x120);
4680 if (band == IEEE80211_BAND_5GHZ)
4681 b43_phy_write(dev, rfctl[1], 0x148);
4683 b43_phy_write(dev, rfctl[1], 0x114);
4685 if (nphy->rxcalparams & 0x10000) {
4686 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4688 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4692 for (j = 0; j < 4; j++) {
4698 if (power[1] > 10000) {
4703 if (power[0] > 10000) {
4713 cur_lna = lna[index];
4714 cur_hpf1 = hpf1[index];
4715 cur_hpf2 = hpf2[index];
4716 cur_hpf += desired - hweight32(power[index]);
4717 cur_hpf = clamp_val(cur_hpf, 0, 10);
4724 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4726 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
4728 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4729 b43_nphy_stop_playback(dev);
4732 ret = b43_nphy_tx_tone(dev, 4000,
4733 (nphy->rxcalparams & 0xFFFF),
4737 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4743 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4752 power[i] = ((real + imag) / 1024) + 1;
4754 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4756 b43_nphy_stop_playback(dev);
4763 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
4764 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
4765 b43_phy_write(dev, rfctl[1], tmp[5]);
4766 b43_phy_write(dev, rfctl[0], tmp[4]);
4767 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
4768 b43_phy_write(dev, afectl_core, tmp[2]);
4769 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
4775 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
4776 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4777 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4779 b43_nphy_stay_in_carrier_search(dev, 0);
4784 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
4785 struct nphy_txgains target, u8 type, bool debug)
4790 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
4791 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
4792 struct nphy_txgains target, u8 type, bool debug)
4794 if (dev->phy.rev >= 3)
4795 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
4797 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
4800 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
4801 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
4803 struct b43_phy *phy = &dev->phy;
4804 struct b43_phy_n *nphy = phy->n;
4805 /* u16 buf[16]; it's rev3+ */
4807 nphy->phyrxchain = mask;
4809 if (0 /* FIXME clk */)
4812 b43_mac_suspend(dev);
4814 if (nphy->hang_avoid)
4815 b43_nphy_stay_in_carrier_search(dev, true);
4817 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4818 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
4820 if ((mask & 0x3) != 0x3) {
4821 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
4822 if (dev->phy.rev >= 3) {
4826 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
4827 if (dev->phy.rev >= 3) {
4832 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4834 if (nphy->hang_avoid)
4835 b43_nphy_stay_in_carrier_search(dev, false);
4837 b43_mac_enable(dev);
4840 /**************************************************
4842 **************************************************/
4845 * Upload the N-PHY tables.
4846 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
4848 static void b43_nphy_tables_init(struct b43_wldev *dev)
4850 if (dev->phy.rev < 3)
4851 b43_nphy_rev0_1_2_tables_init(dev);
4853 b43_nphy_rev3plus_tables_init(dev);
4856 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
4857 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
4859 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
4861 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
4863 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
4865 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
4867 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
4870 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
4871 static void b43_nphy_bphy_init(struct b43_wldev *dev)
4877 for (i = 0; i < 16; i++) {
4878 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
4882 for (i = 0; i < 16; i++) {
4883 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
4886 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
4889 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
4890 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
4892 if (dev->phy.rev >= 3) {
4895 if (0 /* FIXME */) {
4896 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
4897 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
4898 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
4899 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
4902 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
4903 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
4905 switch (dev->dev->bus_type) {
4906 #ifdef CONFIG_B43_BCMA
4908 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
4912 #ifdef CONFIG_B43_SSB
4914 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
4920 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
4921 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
4922 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
4926 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
4927 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
4928 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
4929 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
4934 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
4935 static int b43_phy_initn(struct b43_wldev *dev)
4937 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4938 struct b43_phy *phy = &dev->phy;
4939 struct b43_phy_n *nphy = phy->n;
4941 struct nphy_txgains target;
4943 enum ieee80211_band tmp2;
4947 bool do_cal = false;
4949 if ((dev->phy.rev >= 3) &&
4950 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
4951 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
4952 switch (dev->dev->bus_type) {
4953 #ifdef CONFIG_B43_BCMA
4955 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
4956 BCMA_CC_CHIPCTL, 0x40);
4959 #ifdef CONFIG_B43_SSB
4961 chipco_set32(&dev->dev->sdev->bus->chipco,
4962 SSB_CHIPCO_CHIPCTL, 0x40);
4967 nphy->deaf_count = 0;
4968 b43_nphy_tables_init(dev);
4969 nphy->crsminpwr_adjusted = false;
4970 nphy->noisevars_adjusted = false;
4972 /* Clear all overrides */
4973 if (dev->phy.rev >= 3) {
4974 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
4975 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4976 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
4977 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
4979 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4981 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
4982 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
4983 if (dev->phy.rev < 6) {
4984 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
4985 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
4987 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
4988 ~(B43_NPHY_RFSEQMODE_CAOVER |
4989 B43_NPHY_RFSEQMODE_TROVER));
4990 if (dev->phy.rev >= 3)
4991 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
4992 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
4994 if (dev->phy.rev <= 2) {
4995 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
4996 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
4997 ~B43_NPHY_BPHY_CTL3_SCALE,
4998 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
5000 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
5001 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
5003 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
5004 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5005 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
5006 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
5008 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
5009 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
5010 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
5011 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
5013 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
5014 b43_nphy_update_txrx_chain(dev);
5017 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
5018 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
5021 tmp2 = b43_current_band(dev->wl);
5022 if (b43_nphy_ipa(dev)) {
5023 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
5024 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
5025 nphy->papd_epsilon_offset[0] << 7);
5026 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
5027 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
5028 nphy->papd_epsilon_offset[1] << 7);
5029 b43_nphy_int_pa_set_tx_dig_filters(dev);
5030 } else if (phy->rev >= 5) {
5031 b43_nphy_ext_pa_set_tx_dig_filters(dev);
5034 b43_nphy_workarounds(dev);
5036 /* Reset CCA, in init code it differs a little from standard way */
5037 b43_phy_force_clock(dev, 1);
5038 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5039 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5040 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
5041 b43_phy_force_clock(dev, 0);
5043 b43_mac_phy_clock_set(dev, true);
5045 b43_nphy_pa_override(dev, false);
5046 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5047 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5048 b43_nphy_pa_override(dev, true);
5050 b43_nphy_classifier(dev, 0, 0);
5051 b43_nphy_read_clip_detection(dev, clip);
5052 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5053 b43_nphy_bphy_init(dev);
5055 tx_pwr_state = nphy->txpwrctrl;
5056 b43_nphy_tx_power_ctrl(dev, false);
5057 b43_nphy_tx_power_fix(dev);
5058 b43_nphy_tx_power_ctl_idle_tssi(dev);
5059 b43_nphy_tx_power_ctl_setup(dev);
5060 b43_nphy_tx_gain_table_upload(dev);
5062 if (nphy->phyrxchain != 3)
5063 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
5064 if (nphy->mphase_cal_phase_id > 0)
5065 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5067 do_rssi_cal = false;
5068 if (phy->rev >= 3) {
5069 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5070 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
5072 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
5075 b43_nphy_rssi_cal(dev);
5077 b43_nphy_restore_rssi_cal(dev);
5079 b43_nphy_rssi_cal(dev);
5082 if (!((nphy->measure_hold & 0x6) != 0)) {
5083 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5084 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
5086 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
5092 target = b43_nphy_get_tx_gains(dev);
5094 if (nphy->antsel_type == 2)
5095 b43_nphy_superswitch_init(dev, true);
5096 if (nphy->perical != 2) {
5097 b43_nphy_rssi_cal(dev);
5098 if (phy->rev >= 3) {
5099 nphy->cal_orig_pwr_idx[0] =
5100 nphy->txpwrindex[0].index_internal;
5101 nphy->cal_orig_pwr_idx[1] =
5102 nphy->txpwrindex[1].index_internal;
5103 /* TODO N PHY Pre Calibrate TX Gain */
5104 target = b43_nphy_get_tx_gains(dev);
5106 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5107 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5108 b43_nphy_save_cal(dev);
5109 } else if (nphy->mphase_cal_phase_id == 0)
5110 ;/* N PHY Periodic Calibration with arg 3 */
5112 b43_nphy_restore_cal(dev);
5116 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
5117 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
5118 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5119 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5120 if (phy->rev >= 3 && phy->rev <= 6)
5121 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
5122 b43_nphy_tx_lp_fbw(dev);
5124 b43_nphy_spur_workaround(dev);
5129 /**************************************************
5130 * Channel switching ops.
5131 **************************************************/
5133 static void b43_chantab_phy_upload(struct b43_wldev *dev,
5134 const struct b43_phy_n_sfo_cfg *e)
5136 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5137 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5138 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5139 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5140 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5141 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5144 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5145 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5147 switch (dev->dev->bus_type) {
5148 #ifdef CONFIG_B43_BCMA
5150 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5154 #ifdef CONFIG_B43_SSB
5162 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
5163 static void b43_nphy_channel_setup(struct b43_wldev *dev,
5164 const struct b43_phy_n_sfo_cfg *e,
5165 struct ieee80211_channel *new_channel)
5167 struct b43_phy *phy = &dev->phy;
5168 struct b43_phy_n *nphy = dev->phy.n;
5169 int ch = new_channel->hw_value;
5175 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5176 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
5177 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5178 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
5179 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
5180 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5181 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
5182 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
5183 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
5184 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
5185 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
5186 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
5187 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
5190 b43_chantab_phy_upload(dev, e);
5192 if (new_channel->hw_value == 14) {
5193 b43_nphy_classifier(dev, 2, 0);
5194 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5196 b43_nphy_classifier(dev, 2, 2);
5197 if (new_channel->band == IEEE80211_BAND_2GHZ)
5198 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5201 if (!nphy->txpwrctrl)
5202 b43_nphy_tx_power_fix(dev);
5204 if (dev->phy.rev < 3)
5205 b43_nphy_adjust_lna_gain_table(dev);
5207 b43_nphy_tx_lp_fbw(dev);
5209 if (dev->phy.rev >= 3 &&
5210 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5212 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5214 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
5215 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5217 } else { /* 40MHz */
5218 if (nphy->aband_spurwar_en &&
5219 (ch == 38 || ch == 102 || ch == 118))
5220 avoid = dev->dev->chip_id == 0x4716;
5223 b43_nphy_pmu_spur_avoid(dev, avoid);
5225 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5226 dev->dev->chip_id == 43225) {
5227 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5228 avoid ? 0x5341 : 0x8889);
5229 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5232 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5233 ; /* TODO: reset PLL */
5236 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5238 b43_phy_mask(dev, B43_NPHY_BBCFG,
5239 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5241 b43_nphy_reset_cca(dev);
5243 /* wl sets useless phy_isspuravoid here */
5246 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5249 b43_nphy_spur_workaround(dev);
5252 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
5253 static int b43_nphy_set_channel(struct b43_wldev *dev,
5254 struct ieee80211_channel *channel,
5255 enum nl80211_channel_type channel_type)
5257 struct b43_phy *phy = &dev->phy;
5259 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5260 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
5264 if (dev->phy.rev >= 3) {
5265 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5266 channel->center_freq);
5270 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5276 /* Channel is set later in common code, but we need to set it on our
5277 own to let this function's subcalls work properly. */
5278 phy->channel = channel->hw_value;
5279 phy->channel_freq = channel->center_freq;
5281 if (b43_channel_type_is_40mhz(phy->channel_type) !=
5282 b43_channel_type_is_40mhz(channel_type))
5283 ; /* TODO: BMAC BW Set (channel_type) */
5285 if (channel_type == NL80211_CHAN_HT40PLUS)
5286 b43_phy_set(dev, B43_NPHY_RXCTL,
5287 B43_NPHY_RXCTL_BSELU20);
5288 else if (channel_type == NL80211_CHAN_HT40MINUS)
5289 b43_phy_mask(dev, B43_NPHY_RXCTL,
5290 ~B43_NPHY_RXCTL_BSELU20);
5292 if (dev->phy.rev >= 3) {
5293 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
5294 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
5295 b43_radio_2056_setup(dev, tabent_r3);
5296 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
5298 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
5299 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
5300 b43_radio_2055_setup(dev, tabent_r2);
5301 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
5307 /**************************************************
5309 **************************************************/
5311 static int b43_nphy_op_allocate(struct b43_wldev *dev)
5313 struct b43_phy_n *nphy;
5315 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5323 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
5325 struct b43_phy *phy = &dev->phy;
5326 struct b43_phy_n *nphy = phy->n;
5327 struct ssb_sprom *sprom = dev->dev->bus_sprom;
5329 memset(nphy, 0, sizeof(*nphy));
5331 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
5332 nphy->spur_avoid = (phy->rev >= 3) ?
5333 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
5334 nphy->init_por = true;
5335 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5336 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5337 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
5338 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
5339 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5340 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5341 nphy->tx_pwr_idx[0] = 128;
5342 nphy->tx_pwr_idx[1] = 128;
5344 /* Hardware TX power control and 5GHz power gain */
5345 nphy->txpwrctrl = false;
5346 nphy->pwg_gain_5ghz = false;
5347 if (dev->phy.rev >= 3 ||
5348 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5349 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5350 nphy->txpwrctrl = true;
5351 nphy->pwg_gain_5ghz = true;
5352 } else if (sprom->revision >= 4) {
5353 if (dev->phy.rev >= 2 &&
5354 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5355 nphy->txpwrctrl = true;
5356 #ifdef CONFIG_B43_SSB
5357 if (dev->dev->bus_type == B43_BUS_SSB &&
5358 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5359 struct pci_dev *pdev =
5360 dev->dev->sdev->bus->host_pci;
5361 if (pdev->device == 0x4328 ||
5362 pdev->device == 0x432a)
5363 nphy->pwg_gain_5ghz = true;
5366 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5367 nphy->pwg_gain_5ghz = true;
5371 if (dev->phy.rev >= 3) {
5372 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5373 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5376 nphy->init_por = true;
5379 static void b43_nphy_op_free(struct b43_wldev *dev)
5381 struct b43_phy *phy = &dev->phy;
5382 struct b43_phy_n *nphy = phy->n;
5388 static int b43_nphy_op_init(struct b43_wldev *dev)
5390 return b43_phy_initn(dev);
5393 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5396 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5397 /* OFDM registers are onnly available on A/G-PHYs */
5398 b43err(dev->wl, "Invalid OFDM PHY access at "
5399 "0x%04X on N-PHY\n", offset);
5402 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5403 /* Ext-G registers are only available on G-PHYs */
5404 b43err(dev->wl, "Invalid EXT-G PHY access at "
5405 "0x%04X on N-PHY\n", offset);
5408 #endif /* B43_DEBUG */
5411 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5413 check_phyreg(dev, reg);
5414 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5415 return b43_read16(dev, B43_MMIO_PHY_DATA);
5418 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5420 check_phyreg(dev, reg);
5421 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5422 b43_write16(dev, B43_MMIO_PHY_DATA, value);
5425 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5428 check_phyreg(dev, reg);
5429 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5430 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
5433 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5435 /* Register 1 is a 32-bit register. */
5436 B43_WARN_ON(reg == 1);
5437 /* N-PHY needs 0x100 for read access */
5440 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5441 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5444 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5446 /* Register 1 is a 32-bit register. */
5447 B43_WARN_ON(reg == 1);
5449 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5450 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5453 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
5454 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
5457 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5458 b43err(dev->wl, "MAC not suspended\n");
5461 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5462 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
5463 if (dev->phy.rev >= 7) {
5465 } else if (dev->phy.rev >= 3) {
5466 b43_radio_mask(dev, 0x09, ~0x2);
5468 b43_radio_write(dev, 0x204D, 0);
5469 b43_radio_write(dev, 0x2053, 0);
5470 b43_radio_write(dev, 0x2058, 0);
5471 b43_radio_write(dev, 0x205E, 0);
5472 b43_radio_mask(dev, 0x2062, ~0xF0);
5473 b43_radio_write(dev, 0x2064, 0);
5475 b43_radio_write(dev, 0x304D, 0);
5476 b43_radio_write(dev, 0x3053, 0);
5477 b43_radio_write(dev, 0x3058, 0);
5478 b43_radio_write(dev, 0x305E, 0);
5479 b43_radio_mask(dev, 0x3062, ~0xF0);
5480 b43_radio_write(dev, 0x3064, 0);
5483 if (dev->phy.rev >= 7) {
5484 b43_radio_2057_init(dev);
5485 b43_switch_channel(dev, dev->phy.channel);
5486 } else if (dev->phy.rev >= 3) {
5487 b43_radio_init2056(dev);
5488 b43_switch_channel(dev, dev->phy.channel);
5490 b43_radio_init2055(dev);
5495 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
5496 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5498 u16 override = on ? 0x0 : 0x7FFF;
5499 u16 core = on ? 0xD : 0x00FD;
5501 if (dev->phy.rev >= 3) {
5503 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5504 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5505 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5506 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5508 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5509 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5510 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5511 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5514 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5518 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5519 unsigned int new_channel)
5521 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5522 enum nl80211_channel_type channel_type =
5523 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5525 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5526 if ((new_channel < 1) || (new_channel > 14))
5529 if (new_channel > 200)
5533 return b43_nphy_set_channel(dev, channel, channel_type);
5536 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5538 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5543 const struct b43_phy_operations b43_phyops_n = {
5544 .allocate = b43_nphy_op_allocate,
5545 .free = b43_nphy_op_free,
5546 .prepare_structs = b43_nphy_op_prepare_structs,
5547 .init = b43_nphy_op_init,
5548 .phy_read = b43_nphy_op_read,
5549 .phy_write = b43_nphy_op_write,
5550 .phy_maskset = b43_nphy_op_maskset,
5551 .radio_read = b43_nphy_op_radio_read,
5552 .radio_write = b43_nphy_op_radio_write,
5553 .software_rfkill = b43_nphy_op_software_rfkill,
5554 .switch_analog = b43_nphy_op_switch_analog,
5555 .switch_channel = b43_nphy_op_switch_channel,
5556 .get_default_chan = b43_nphy_op_get_default_chan,
5557 .recalc_txpower = b43_nphy_op_recalc_txpower,
5558 .adjust_txpower = b43_nphy_op_adjust_txpower,