drivers/net/wireless/b43/main.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6   Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   Some parts of the code in this file are derived from the ipw2200
  12   driver  Copyright(c) 2003 - 2004 Intel Corporation.
  13
  14   This program is free software; you can redistribute it and/or modify
  15   it under the terms of the GNU General Public License as published by
  16   the Free Software Foundation; either version 2 of the License, or
  17   (at your option) any later version.
  18
  19   This program is distributed in the hope that it will be useful,
  20   but WITHOUT ANY WARRANTY; without even the implied warranty of
  21   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22   GNU General Public License for more details.
  23
  24   You should have received a copy of the GNU General Public License
  25   along with this program; see the file COPYING.  If not, write to
  26   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27   Boston, MA 02110-1301, USA.
  28
  29 */
  30
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/if_arp.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/version.h>
  37 #include <linux/firmware.h>
  38 #include <linux/wireless.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/dma-mapping.h>
  42 #include <asm/unaligned.h>
  43
  44 #include "b43.h"
  45 #include "main.h"
  46 #include "debugfs.h"
  47 #include "phy.h"
  48 #include "dma.h"
  49 #include "pio.h"
  50 #include "sysfs.h"
  51 #include "xmit.h"
  52 #include "sysfs.h"
  53 #include "lo.h"
  54 #include "pcmcia.h"
  55
  56 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  57 MODULE_AUTHOR("Martin Langer");
  58 MODULE_AUTHOR("Stefano Brivio");
  59 MODULE_AUTHOR("Michael Buesch");
  60 MODULE_LICENSE("GPL");
  61
  62 extern char *nvram_get(char *name);
  63
  64 #if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
  65 static int modparam_pio;
  66 module_param_named(pio, modparam_pio, int, 0444);
  67 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  68 #elif defined(CONFIG_B43_DMA)
  69 # define modparam_pio   0
  70 #elif defined(CONFIG_B43_PIO)
  71 # define modparam_pio   1
  72 #endif
  73
  74 static int modparam_bad_frames_preempt;
  75 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  76 MODULE_PARM_DESC(bad_frames_preempt,
  77                  "enable(1) / disable(0) Bad Frames Preemption");
  78
  79 static int modparam_short_retry = B43_DEFAULT_SHORT_RETRY_LIMIT;
  80 module_param_named(short_retry, modparam_short_retry, int, 0444);
  81 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
  82
  83 static int modparam_long_retry = B43_DEFAULT_LONG_RETRY_LIMIT;
  84 module_param_named(long_retry, modparam_long_retry, int, 0444);
  85 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
  86
  87 static char modparam_fwpostfix[16];
  88 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  89 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  90
  91 static int modparam_hwpctl;
  92 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  93 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  94
  95 static int modparam_nohwcrypt;
  96 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  97 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  98
  99 static const struct ssb_device_id b43_ssb_tbl[] = {
 100         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
 101         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
 102         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
 103         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
 104         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
 105         SSB_DEVTABLE_END
 106 };
 107
 108 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
 109
 110 /* Channel and ratetables are shared for all devices.
 111  * They can't be const, because ieee80211 puts some precalculated
 112  * data in there. This data is the same for all devices, so we don't
 113  * get concurrency issues */
 114 #define RATETAB_ENT(_rateid, _flags) \
 115         {                                                       \
 116                 .rate   = B43_RATE_TO_BASE100KBPS(_rateid),     \
 117                 .val    = (_rateid),                            \
 118                 .val2   = (_rateid),                            \
 119                 .flags  = (_flags),                             \
 120         }
 121 static struct ieee80211_rate __b43_ratetable[] = {
 122         RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
 123         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
 124         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
 125         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
 126         RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
 127         RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
 128         RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
 129         RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
 130         RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
 131         RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
 132         RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
 133         RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
 134 };
 135
 136 #define b43_a_ratetable         (__b43_ratetable + 4)
 137 #define b43_a_ratetable_size    8
 138 #define b43_b_ratetable         (__b43_ratetable + 0)
 139 #define b43_b_ratetable_size    4
 140 #define b43_g_ratetable         (__b43_ratetable + 0)
 141 #define b43_g_ratetable_size    12
 142
 143 #define CHANTAB_ENT(_chanid, _freq) \
 144         {                                                       \
 145                 .chan   = (_chanid),                            \
 146                 .freq   = (_freq),                              \
 147                 .val    = (_chanid),                            \
 148                 .flag   = IEEE80211_CHAN_W_SCAN |               \
 149                           IEEE80211_CHAN_W_ACTIVE_SCAN |        \
 150                           IEEE80211_CHAN_W_IBSS,                \
 151                 .power_level    = 0xFF,                         \
 152                 .antenna_max    = 0xFF,                         \
 153         }
 154 static struct ieee80211_channel b43_bg_chantable[] = {
 155         CHANTAB_ENT(1, 2412),
 156         CHANTAB_ENT(2, 2417),
 157         CHANTAB_ENT(3, 2422),
 158         CHANTAB_ENT(4, 2427),
 159         CHANTAB_ENT(5, 2432),
 160         CHANTAB_ENT(6, 2437),
 161         CHANTAB_ENT(7, 2442),
 162         CHANTAB_ENT(8, 2447),
 163         CHANTAB_ENT(9, 2452),
 164         CHANTAB_ENT(10, 2457),
 165         CHANTAB_ENT(11, 2462),
 166         CHANTAB_ENT(12, 2467),
 167         CHANTAB_ENT(13, 2472),
 168         CHANTAB_ENT(14, 2484),
 169 };
 170
 171 #define b43_bg_chantable_size   ARRAY_SIZE(b43_bg_chantable)
 172 static struct ieee80211_channel b43_a_chantable[] = {
 173         CHANTAB_ENT(36, 5180),
 174         CHANTAB_ENT(40, 5200),
 175         CHANTAB_ENT(44, 5220),
 176         CHANTAB_ENT(48, 5240),
 177         CHANTAB_ENT(52, 5260),
 178         CHANTAB_ENT(56, 5280),
 179         CHANTAB_ENT(60, 5300),
 180         CHANTAB_ENT(64, 5320),
 181         CHANTAB_ENT(149, 5745),
 182         CHANTAB_ENT(153, 5765),
 183         CHANTAB_ENT(157, 5785),
 184         CHANTAB_ENT(161, 5805),
 185         CHANTAB_ENT(165, 5825),
 186 };
 187
 188 #define b43_a_chantable_size    ARRAY_SIZE(b43_a_chantable)
 189
 190 static void b43_wireless_core_exit(struct b43_wldev *dev);
 191 static int b43_wireless_core_init(struct b43_wldev *dev);
 192 static void b43_wireless_core_stop(struct b43_wldev *dev);
 193 static int b43_wireless_core_start(struct b43_wldev *dev);
 194
 195 static int b43_ratelimit(struct b43_wl *wl)
 196 {
 197         if (!wl || !wl->current_dev)
 198                 return 1;
 199         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
 200                 return 1;
 201         /* We are up and running.
 202          * Ratelimit the messages to avoid DoS over the net. */
 203         return net_ratelimit();
 204 }
 205
 206 void b43info(struct b43_wl *wl, const char *fmt, ...)
 207 {
 208         va_list args;
 209
 210         if (!b43_ratelimit(wl))
 211                 return;
 212         va_start(args, fmt);
 213         printk(KERN_INFO "b43-%s: ",
 214                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 215         vprintk(fmt, args);
 216         va_end(args);
 217 }
 218
 219 void b43err(struct b43_wl *wl, const char *fmt, ...)
 220 {
 221         va_list args;
 222
 223         if (!b43_ratelimit(wl))
 224                 return;
 225         va_start(args, fmt);
 226         printk(KERN_ERR "b43-%s ERROR: ",
 227                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 228         vprintk(fmt, args);
 229         va_end(args);
 230 }
 231
 232 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 233 {
 234         va_list args;
 235
 236         if (!b43_ratelimit(wl))
 237                 return;
 238         va_start(args, fmt);
 239         printk(KERN_WARNING "b43-%s warning: ",
 240                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 241         vprintk(fmt, args);
 242         va_end(args);
 243 }
 244
 245 #if B43_DEBUG
 246 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 247 {
 248         va_list args;
 249
 250         va_start(args, fmt);
 251         printk(KERN_DEBUG "b43-%s debug: ",
 252                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 253         vprintk(fmt, args);
 254         va_end(args);
 255 }
 256 #endif /* DEBUG */
 257
 258 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
 259 {
 260         u32 macctl;
 261
 262         B43_WARN_ON(offset % 4 != 0);
 263
 264         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 265         if (macctl & B43_MACCTL_BE)
 266                 val = swab32(val);
 267
 268         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
 269         mmiowb();
 270         b43_write32(dev, B43_MMIO_RAM_DATA, val);
 271 }
 272
 273 static inline
 274     void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
 275 {
 276         u32 control;
 277
 278         /* "offset" is the WORD offset. */
 279
 280         control = routing;
 281         control <<= 16;
 282         control |= offset;
 283         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
 284 }
 285
 286 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
 287 {
 288         u32 ret;
 289
 290         if (routing == B43_SHM_SHARED) {
 291                 B43_WARN_ON(offset & 0x0001);
 292                 if (offset & 0x0003) {
 293                         /* Unaligned access */
 294                         b43_shm_control_word(dev, routing, offset >> 2);
 295                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 296                         ret <<= 16;
 297                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 298                         ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
 299
 300                         return ret;
 301                 }
 302                 offset >>= 2;
 303         }
 304         b43_shm_control_word(dev, routing, offset);
 305         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
 306
 307         return ret;
 308 }
 309
 310 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
 311 {
 312         u16 ret;
 313
 314         if (routing == B43_SHM_SHARED) {
 315                 B43_WARN_ON(offset & 0x0001);
 316                 if (offset & 0x0003) {
 317                         /* Unaligned access */
 318                         b43_shm_control_word(dev, routing, offset >> 2);
 319                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 320
 321                         return ret;
 322                 }
 323                 offset >>= 2;
 324         }
 325         b43_shm_control_word(dev, routing, offset);
 326         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
 327
 328         return ret;
 329 }
 330
 331 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
 332 {
 333         if (routing == B43_SHM_SHARED) {
 334                 B43_WARN_ON(offset & 0x0001);
 335                 if (offset & 0x0003) {
 336                         /* Unaligned access */
 337                         b43_shm_control_word(dev, routing, offset >> 2);
 338                         mmiowb();
 339                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
 340                                     (value >> 16) & 0xffff);
 341                         mmiowb();
 342                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 343                         mmiowb();
 344                         b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
 345                         return;
 346                 }
 347                 offset >>= 2;
 348         }
 349         b43_shm_control_word(dev, routing, offset);
 350         mmiowb();
 351         b43_write32(dev, B43_MMIO_SHM_DATA, value);
 352 }
 353
 354 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
 355 {
 356         if (routing == B43_SHM_SHARED) {
 357                 B43_WARN_ON(offset & 0x0001);
 358                 if (offset & 0x0003) {
 359                         /* Unaligned access */
 360                         b43_shm_control_word(dev, routing, offset >> 2);
 361                         mmiowb();
 362                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
 363                         return;
 364                 }
 365                 offset >>= 2;
 366         }
 367         b43_shm_control_word(dev, routing, offset);
 368         mmiowb();
 369         b43_write16(dev, B43_MMIO_SHM_DATA, value);
 370 }
 371
 372 /* Read HostFlags */
 373 u32 b43_hf_read(struct b43_wldev * dev)
 374 {
 375         u32 ret;
 376
 377         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
 378         ret <<= 16;
 379         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
 380
 381         return ret;
 382 }
 383
 384 /* Write HostFlags */
 385 void b43_hf_write(struct b43_wldev *dev, u32 value)
 386 {
 387         b43_shm_write16(dev, B43_SHM_SHARED,
 388                         B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
 389         b43_shm_write16(dev, B43_SHM_SHARED,
 390                         B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
 391 }
 392
 393 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
 394 {
 395         /* We need to be careful. As we read the TSF from multiple
 396          * registers, we should take care of register overflows.
 397          * In theory, the whole tsf read process should be atomic.
 398          * We try to be atomic here, by restaring the read process,
 399          * if any of the high registers changed (overflew).
 400          */
 401         if (dev->dev->id.revision >= 3) {
 402                 u32 low, high, high2;
 403
 404                 do {
 405                         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 406                         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
 407                         high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 408                 } while (unlikely(high != high2));
 409
 410                 *tsf = high;
 411                 *tsf <<= 32;
 412                 *tsf |= low;
 413         } else {
 414                 u64 tmp;
 415                 u16 v0, v1, v2, v3;
 416                 u16 test1, test2, test3;
 417
 418                 do {
 419                         v3 = b43_read16(dev, B43_MMIO_TSF_3);
 420                         v2 = b43_read16(dev, B43_MMIO_TSF_2);
 421                         v1 = b43_read16(dev, B43_MMIO_TSF_1);
 422                         v0 = b43_read16(dev, B43_MMIO_TSF_0);
 423
 424                         test3 = b43_read16(dev, B43_MMIO_TSF_3);
 425                         test2 = b43_read16(dev, B43_MMIO_TSF_2);
 426                         test1 = b43_read16(dev, B43_MMIO_TSF_1);
 427                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 428
 429                 *tsf = v3;
 430                 *tsf <<= 48;
 431                 tmp = v2;
 432                 tmp <<= 32;
 433                 *tsf |= tmp;
 434                 tmp = v1;
 435                 tmp <<= 16;
 436                 *tsf |= tmp;
 437                 *tsf |= v0;
 438         }
 439 }
 440
 441 static void b43_time_lock(struct b43_wldev *dev)
 442 {
 443         u32 macctl;
 444
 445         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 446         macctl |= B43_MACCTL_TBTTHOLD;
 447         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 448         /* Commit the write */
 449         b43_read32(dev, B43_MMIO_MACCTL);
 450 }
 451
 452 static void b43_time_unlock(struct b43_wldev *dev)
 453 {
 454         u32 macctl;
 455
 456         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 457         macctl &= ~B43_MACCTL_TBTTHOLD;
 458         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 459         /* Commit the write */
 460         b43_read32(dev, B43_MMIO_MACCTL);
 461 }
 462
 463 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
 464 {
 465         /* Be careful with the in-progress timer.
 466          * First zero out the low register, so we have a full
 467          * register-overflow duration to complete the operation.
 468          */
 469         if (dev->dev->id.revision >= 3) {
 470                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 471                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 472
 473                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
 474                 mmiowb();
 475                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
 476                 mmiowb();
 477                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
 478         } else {
 479                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 480                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 481                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 482                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 483
 484                 b43_write16(dev, B43_MMIO_TSF_0, 0);
 485                 mmiowb();
 486                 b43_write16(dev, B43_MMIO_TSF_3, v3);
 487                 mmiowb();
 488                 b43_write16(dev, B43_MMIO_TSF_2, v2);
 489                 mmiowb();
 490                 b43_write16(dev, B43_MMIO_TSF_1, v1);
 491                 mmiowb();
 492                 b43_write16(dev, B43_MMIO_TSF_0, v0);
 493         }
 494 }
 495
 496 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
 497 {
 498         b43_time_lock(dev);
 499         b43_tsf_write_locked(dev, tsf);
 500         b43_time_unlock(dev);
 501 }
 502
 503 static
 504 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
 505 {
 506         static const u8 zero_addr[ETH_ALEN] = { 0 };
 507         u16 data;
 508
 509         if (!mac)
 510                 mac = zero_addr;
 511
 512         offset |= 0x0020;
 513         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
 514
 515         data = mac[0];
 516         data |= mac[1] << 8;
 517         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 518         data = mac[2];
 519         data |= mac[3] << 8;
 520         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 521         data = mac[4];
 522         data |= mac[5] << 8;
 523         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 524 }
 525
 526 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
 527 {
 528         const u8 *mac;
 529         const u8 *bssid;
 530         u8 mac_bssid[ETH_ALEN * 2];
 531         int i;
 532         u32 tmp;
 533
 534         bssid = dev->wl->bssid;
 535         mac = dev->wl->mac_addr;
 536
 537         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
 538
 539         memcpy(mac_bssid, mac, ETH_ALEN);
 540         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 541
 542         /* Write our MAC address and BSSID to template ram */
 543         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 544                 tmp = (u32) (mac_bssid[i + 0]);
 545                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
 546                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
 547                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
 548                 b43_ram_write(dev, 0x20 + i, tmp);
 549         }
 550 }
 551
 552 static void b43_upload_card_macaddress(struct b43_wldev *dev)
 553 {
 554         b43_write_mac_bssid_templates(dev);
 555         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
 556 }
 557
 558 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
 559 {
 560         /* slot_time is in usec. */
 561         if (dev->phy.type != B43_PHYTYPE_G)
 562                 return;
 563         b43_write16(dev, 0x684, 510 + slot_time);
 564         b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
 565 }
 566
 567 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
 568 {
 569         b43_set_slot_time(dev, 9);
 570         dev->short_slot = 1;
 571 }
 572
 573 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
 574 {
 575         b43_set_slot_time(dev, 20);
 576         dev->short_slot = 0;
 577 }
 578
 579 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
 580  * Returns the _previously_ enabled IRQ mask.
 581  */
 582 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
 583 {
 584         u32 old_mask;
 585
 586         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 587         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
 588
 589         return old_mask;
 590 }
 591
 592 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
 593  * Returns the _previously_ enabled IRQ mask.
 594  */
 595 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
 596 {
 597         u32 old_mask;
 598
 599         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 600         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
 601
 602         return old_mask;
 603 }
 604
 605 /* Synchronize IRQ top- and bottom-half.
 606  * IRQs must be masked before calling this.
 607  * This must not be called with the irq_lock held.
 608  */
 609 static void b43_synchronize_irq(struct b43_wldev *dev)
 610 {
 611         synchronize_irq(dev->dev->irq);
 612         tasklet_kill(&dev->isr_tasklet);
 613 }
 614
 615 /* DummyTransmission function, as documented on
 616  * http://bcm-specs.sipsolutions.net/DummyTransmission
 617  */
 618 void b43_dummy_transmission(struct b43_wldev *dev)
 619 {
 620         struct b43_phy *phy = &dev->phy;
 621         unsigned int i, max_loop;
 622         u16 value;
 623         u32 buffer[5] = {
 624                 0x00000000,
 625                 0x00D40000,
 626                 0x00000000,
 627                 0x01000000,
 628                 0x00000000,
 629         };
 630
 631         switch (phy->type) {
 632         case B43_PHYTYPE_A:
 633                 max_loop = 0x1E;
 634                 buffer[0] = 0x000201CC;
 635                 break;
 636         case B43_PHYTYPE_B:
 637         case B43_PHYTYPE_G:
 638                 max_loop = 0xFA;
 639                 buffer[0] = 0x000B846E;
 640                 break;
 641         default:
 642                 B43_WARN_ON(1);
 643                 return;
 644         }
 645
 646         for (i = 0; i < 5; i++)
 647                 b43_ram_write(dev, i * 4, buffer[i]);
 648
 649         /* Commit writes */
 650         b43_read32(dev, B43_MMIO_MACCTL);
 651
 652         b43_write16(dev, 0x0568, 0x0000);
 653         b43_write16(dev, 0x07C0, 0x0000);
 654         value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
 655         b43_write16(dev, 0x050C, value);
 656         b43_write16(dev, 0x0508, 0x0000);
 657         b43_write16(dev, 0x050A, 0x0000);
 658         b43_write16(dev, 0x054C, 0x0000);
 659         b43_write16(dev, 0x056A, 0x0014);
 660         b43_write16(dev, 0x0568, 0x0826);
 661         b43_write16(dev, 0x0500, 0x0000);
 662         b43_write16(dev, 0x0502, 0x0030);
 663
 664         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 665                 b43_radio_write16(dev, 0x0051, 0x0017);
 666         for (i = 0x00; i < max_loop; i++) {
 667                 value = b43_read16(dev, 0x050E);
 668                 if (value & 0x0080)
 669                         break;
 670                 udelay(10);
 671         }
 672         for (i = 0x00; i < 0x0A; i++) {
 673                 value = b43_read16(dev, 0x050E);
 674                 if (value & 0x0400)
 675                         break;
 676                 udelay(10);
 677         }
 678         for (i = 0x00; i < 0x0A; i++) {
 679                 value = b43_read16(dev, 0x0690);
 680                 if (!(value & 0x0100))
 681                         break;
 682                 udelay(10);
 683         }
 684         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 685                 b43_radio_write16(dev, 0x0051, 0x0037);
 686 }
 687
 688 static void key_write(struct b43_wldev *dev,
 689                       u8 index, u8 algorithm, const u8 * key)
 690 {
 691         unsigned int i;
 692         u32 offset;
 693         u16 value;
 694         u16 kidx;
 695
 696         /* Key index/algo block */
 697         kidx = b43_kidx_to_fw(dev, index);
 698         value = ((kidx << 4) | algorithm);
 699         b43_shm_write16(dev, B43_SHM_SHARED,
 700                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
 701
 702         /* Write the key to the Key Table Pointer offset */
 703         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
 704         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
 705                 value = key[i];
 706                 value |= (u16) (key[i + 1]) << 8;
 707                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
 708         }
 709 }
 710
 711 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
 712 {
 713         u32 addrtmp[2] = { 0, 0, };
 714         u8 per_sta_keys_start = 8;
 715
 716         if (b43_new_kidx_api(dev))
 717                 per_sta_keys_start = 4;
 718
 719         B43_WARN_ON(index < per_sta_keys_start);
 720         /* We have two default TX keys and possibly two default RX keys.
 721          * Physical mac 0 is mapped to physical key 4 or 8, depending
 722          * on the firmware version.
 723          * So we must adjust the index here.
 724          */
 725         index -= per_sta_keys_start;
 726
 727         if (addr) {
 728                 addrtmp[0] = addr[0];
 729                 addrtmp[0] |= ((u32) (addr[1]) << 8);
 730                 addrtmp[0] |= ((u32) (addr[2]) << 16);
 731                 addrtmp[0] |= ((u32) (addr[3]) << 24);
 732                 addrtmp[1] = addr[4];
 733                 addrtmp[1] |= ((u32) (addr[5]) << 8);
 734         }
 735
 736         if (dev->dev->id.revision >= 5) {
 737                 /* Receive match transmitter address mechanism */
 738                 b43_shm_write32(dev, B43_SHM_RCMTA,
 739                                 (index * 2) + 0, addrtmp[0]);
 740                 b43_shm_write16(dev, B43_SHM_RCMTA,
 741                                 (index * 2) + 1, addrtmp[1]);
 742         } else {
 743                 /* RXE (Receive Engine) and
 744                  * PSM (Programmable State Machine) mechanism
 745                  */
 746                 if (index < 8) {
 747                         /* TODO write to RCM 16, 19, 22 and 25 */
 748                 } else {
 749                         b43_shm_write32(dev, B43_SHM_SHARED,
 750                                         B43_SHM_SH_PSM + (index * 6) + 0,
 751                                         addrtmp[0]);
 752                         b43_shm_write16(dev, B43_SHM_SHARED,
 753                                         B43_SHM_SH_PSM + (index * 6) + 4,
 754                                         addrtmp[1]);
 755                 }
 756         }
 757 }
 758
 759 static void do_key_write(struct b43_wldev *dev,
 760                          u8 index, u8 algorithm,
 761                          const u8 * key, size_t key_len, const u8 * mac_addr)
 762 {
 763         u8 buf[B43_SEC_KEYSIZE] = { 0, };
 764         u8 per_sta_keys_start = 8;
 765
 766         if (b43_new_kidx_api(dev))
 767                 per_sta_keys_start = 4;
 768
 769         B43_WARN_ON(index >= dev->max_nr_keys);
 770         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
 771
 772         if (index >= per_sta_keys_start)
 773                 keymac_write(dev, index, NULL); /* First zero out mac. */
 774         if (key)
 775                 memcpy(buf, key, key_len);
 776         key_write(dev, index, algorithm, buf);
 777         if (index >= per_sta_keys_start)
 778                 keymac_write(dev, index, mac_addr);
 779
 780         dev->key[index].algorithm = algorithm;
 781 }
 782
 783 static int b43_key_write(struct b43_wldev *dev,
 784                          int index, u8 algorithm,
 785                          const u8 * key, size_t key_len,
 786                          const u8 * mac_addr,
 787                          struct ieee80211_key_conf *keyconf)
 788 {
 789         int i;
 790         int sta_keys_start;
 791
 792         if (key_len > B43_SEC_KEYSIZE)
 793                 return -EINVAL;
 794         for (i = 0; i < dev->max_nr_keys; i++) {
 795                 /* Check that we don't already have this key. */
 796                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
 797         }
 798         if (index < 0) {
 799                 /* Either pairwise key or address is 00:00:00:00:00:00
 800                  * for transmit-only keys. Search the index. */
 801                 if (b43_new_kidx_api(dev))
 802                         sta_keys_start = 4;
 803                 else
 804                         sta_keys_start = 8;
 805                 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
 806                         if (!dev->key[i].keyconf) {
 807                                 /* found empty */
 808                                 index = i;
 809                                 break;
 810                         }
 811                 }
 812                 if (index < 0) {
 813                         b43err(dev->wl, "Out of hardware key memory\n");
 814                         return -ENOSPC;
 815                 }
 816         } else
 817                 B43_WARN_ON(index > 3);
 818
 819         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
 820         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 821                 /* Default RX key */
 822                 B43_WARN_ON(mac_addr);
 823                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
 824         }
 825         keyconf->hw_key_idx = index;
 826         dev->key[index].keyconf = keyconf;
 827
 828         return 0;
 829 }
 830
 831 static int b43_key_clear(struct b43_wldev *dev, int index)
 832 {
 833         if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
 834                 return -EINVAL;
 835         do_key_write(dev, index, B43_SEC_ALGO_NONE,
 836                      NULL, B43_SEC_KEYSIZE, NULL);
 837         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 838                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
 839                              NULL, B43_SEC_KEYSIZE, NULL);
 840         }
 841         dev->key[index].keyconf = NULL;
 842
 843         return 0;
 844 }
 845
 846 static void b43_clear_keys(struct b43_wldev *dev)
 847 {
 848         int i;
 849
 850         for (i = 0; i < dev->max_nr_keys; i++)
 851                 b43_key_clear(dev, i);
 852 }
 853
 854 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
 855 {
 856         u32 macctl;
 857         u16 ucstat;
 858         bool hwps;
 859         bool awake;
 860         int i;
 861
 862         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
 863                     (ps_flags & B43_PS_DISABLED));
 864         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
 865
 866         if (ps_flags & B43_PS_ENABLED) {
 867                 hwps = 1;
 868         } else if (ps_flags & B43_PS_DISABLED) {
 869                 hwps = 0;
 870         } else {
 871                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
 872                 //      and thus is not an AP and we are associated, set bit 25
 873         }
 874         if (ps_flags & B43_PS_AWAKE) {
 875                 awake = 1;
 876         } else if (ps_flags & B43_PS_ASLEEP) {
 877                 awake = 0;
 878         } else {
 879                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
 880                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
 881                 //      successful, set bit26
 882         }
 883
 884 /* FIXME: For now we force awake-on and hwps-off */
 885         hwps = 0;
 886         awake = 1;
 887
 888         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 889         if (hwps)
 890                 macctl |= B43_MACCTL_HWPS;
 891         else
 892                 macctl &= ~B43_MACCTL_HWPS;
 893         if (awake)
 894                 macctl |= B43_MACCTL_AWAKE;
 895         else
 896                 macctl &= ~B43_MACCTL_AWAKE;
 897         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 898         /* Commit write */
 899         b43_read32(dev, B43_MMIO_MACCTL);
 900         if (awake && dev->dev->id.revision >= 5) {
 901                 /* Wait for the microcode to wake up. */
 902                 for (i = 0; i < 100; i++) {
 903                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
 904                                                 B43_SHM_SH_UCODESTAT);
 905                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
 906                                 break;
 907                         udelay(10);
 908                 }
 909         }
 910 }
 911
 912 /* Turn the Analog ON/OFF */
 913 static void b43_switch_analog(struct b43_wldev *dev, int on)
 914 {
 915         b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
 916 }
 917
 918 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
 919 {
 920         u32 tmslow;
 921         u32 macctl;
 922
 923         flags |= B43_TMSLOW_PHYCLKEN;
 924         flags |= B43_TMSLOW_PHYRESET;
 925         ssb_device_enable(dev->dev, flags);
 926         msleep(2);              /* Wait for the PLL to turn on. */
 927
 928         /* Now take the PHY out of Reset again */
 929         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 930         tmslow |= SSB_TMSLOW_FGC;
 931         tmslow &= ~B43_TMSLOW_PHYRESET;
 932         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 933         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 934         msleep(1);
 935         tmslow &= ~SSB_TMSLOW_FGC;
 936         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 937         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 938         msleep(1);
 939
 940         /* Turn Analog ON */
 941         b43_switch_analog(dev, 1);
 942
 943         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 944         macctl &= ~B43_MACCTL_GMODE;
 945         if (flags & B43_TMSLOW_GMODE)
 946                 macctl |= B43_MACCTL_GMODE;
 947         macctl |= B43_MACCTL_IHR_ENABLED;
 948         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 949 }
 950
 951 static void handle_irq_transmit_status(struct b43_wldev *dev)
 952 {
 953         u32 v0, v1;
 954         u16 tmp;
 955         struct b43_txstatus stat;
 956
 957         while (1) {
 958                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 959                 if (!(v0 & 0x00000001))
 960                         break;
 961                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 962
 963                 stat.cookie = (v0 >> 16);
 964                 stat.seq = (v1 & 0x0000FFFF);
 965                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
 966                 tmp = (v0 & 0x0000FFFF);
 967                 stat.frame_count = ((tmp & 0xF000) >> 12);
 968                 stat.rts_count = ((tmp & 0x0F00) >> 8);
 969                 stat.supp_reason = ((tmp & 0x001C) >> 2);
 970                 stat.pm_indicated = !!(tmp & 0x0080);
 971                 stat.intermediate = !!(tmp & 0x0040);
 972                 stat.for_ampdu = !!(tmp & 0x0020);
 973                 stat.acked = !!(tmp & 0x0002);
 974
 975                 b43_handle_txstatus(dev, &stat);
 976         }
 977 }
 978
 979 static void drain_txstatus_queue(struct b43_wldev *dev)
 980 {
 981         u32 dummy;
 982
 983         if (dev->dev->id.revision < 5)
 984                 return;
 985         /* Read all entries from the microcode TXstatus FIFO
 986          * and throw them away.
 987          */
 988         while (1) {
 989                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 990                 if (!(dummy & 0x00000001))
 991                         break;
 992                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 993         }
 994 }
 995
 996 static u32 b43_jssi_read(struct b43_wldev *dev)
 997 {
 998         u32 val = 0;
 999
1000         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1001         val <<= 16;
1002         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1003
1004         return val;
1005 }
1006
1007 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1008 {
1009         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1010         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1011 }
1012
1013 static void b43_generate_noise_sample(struct b43_wldev *dev)
1014 {
1015         b43_jssi_write(dev, 0x7F7F7F7F);
1016         b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1017                     b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1018                     | (1 << 4));
1019         B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1020 }
1021
1022 static void b43_calculate_link_quality(struct b43_wldev *dev)
1023 {
1024         /* Top half of Link Quality calculation. */
1025
1026         if (dev->noisecalc.calculation_running)
1027                 return;
1028         dev->noisecalc.channel_at_start = dev->phy.channel;
1029         dev->noisecalc.calculation_running = 1;
1030         dev->noisecalc.nr_samples = 0;
1031
1032         b43_generate_noise_sample(dev);
1033 }
1034
1035 static void handle_irq_noise(struct b43_wldev *dev)
1036 {
1037         struct b43_phy *phy = &dev->phy;
1038         u16 tmp;
1039         u8 noise[4];
1040         u8 i, j;
1041         s32 average;
1042
1043         /* Bottom half of Link Quality calculation. */
1044
1045         B43_WARN_ON(!dev->noisecalc.calculation_running);
1046         if (dev->noisecalc.channel_at_start != phy->channel)
1047                 goto drop_calculation;
1048         *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1049         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1050             noise[2] == 0x7F || noise[3] == 0x7F)
1051                 goto generate_new;
1052
1053         /* Get the noise samples. */
1054         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1055         i = dev->noisecalc.nr_samples;
1056         noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1057         noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1058         noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1059         noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1060         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1061         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1062         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1063         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1064         dev->noisecalc.nr_samples++;
1065         if (dev->noisecalc.nr_samples == 8) {
1066                 /* Calculate the Link Quality by the noise samples. */
1067                 average = 0;
1068                 for (i = 0; i < 8; i++) {
1069                         for (j = 0; j < 4; j++)
1070                                 average += dev->noisecalc.samples[i][j];
1071                 }
1072                 average /= (8 * 4);
1073                 average *= 125;
1074                 average += 64;
1075                 average /= 128;
1076                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1077                 tmp = (tmp / 128) & 0x1F;
1078                 if (tmp >= 8)
1079                         average += 2;
1080                 else
1081                         average -= 25;
1082                 if (tmp == 8)
1083                         average -= 72;
1084                 else
1085                         average -= 48;
1086
1087                 dev->stats.link_noise = average;
1088               drop_calculation:
1089                 dev->noisecalc.calculation_running = 0;
1090                 return;
1091         }
1092       generate_new:
1093         b43_generate_noise_sample(dev);
1094 }
1095
1096 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1097 {
1098         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1099                 ///TODO: PS TBTT
1100         } else {
1101                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1102                         b43_power_saving_ctl_bits(dev, 0);
1103         }
1104         dev->reg124_set_0x4 = 0;
1105         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1106                 dev->reg124_set_0x4 = 1;
1107 }
1108
1109 static void handle_irq_atim_end(struct b43_wldev *dev)
1110 {
1111         if (!dev->reg124_set_0x4 /*FIXME rename this variable */ )
1112                 return;
1113         b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1114                     b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1115                     | 0x4);
1116 }
1117
1118 static void handle_irq_pmq(struct b43_wldev *dev)
1119 {
1120         u32 tmp;
1121
1122         //TODO: AP mode.
1123
1124         while (1) {
1125                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1126                 if (!(tmp & 0x00000008))
1127                         break;
1128         }
1129         /* 16bit write is odd, but correct. */
1130         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1131 }
1132
1133 static void b43_write_template_common(struct b43_wldev *dev,
1134                                       const u8 * data, u16 size,
1135                                       u16 ram_offset,
1136                                       u16 shm_size_offset, u8 rate)
1137 {
1138         u32 i, tmp;
1139         struct b43_plcp_hdr4 plcp;
1140
1141         plcp.data = 0;
1142         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1143         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1144         ram_offset += sizeof(u32);
1145         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1146          * So leave the first two bytes of the next write blank.
1147          */
1148         tmp = (u32) (data[0]) << 16;
1149         tmp |= (u32) (data[1]) << 24;
1150         b43_ram_write(dev, ram_offset, tmp);
1151         ram_offset += sizeof(u32);
1152         for (i = 2; i < size; i += sizeof(u32)) {
1153                 tmp = (u32) (data[i + 0]);
1154                 if (i + 1 < size)
1155                         tmp |= (u32) (data[i + 1]) << 8;
1156                 if (i + 2 < size)
1157                         tmp |= (u32) (data[i + 2]) << 16;
1158                 if (i + 3 < size)
1159                         tmp |= (u32) (data[i + 3]) << 24;
1160                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1161         }
1162         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1163                         size + sizeof(struct b43_plcp_hdr6));
1164 }
1165
1166 static void b43_write_beacon_template(struct b43_wldev *dev,
1167                                       u16 ram_offset,
1168                                       u16 shm_size_offset, u8 rate)
1169 {
1170         int len;
1171         const u8 *data;
1172
1173         B43_WARN_ON(!dev->cached_beacon);
1174         len = min((size_t) dev->cached_beacon->len,
1175                   0x200 - sizeof(struct b43_plcp_hdr6));
1176         data = (const u8 *)(dev->cached_beacon->data);
1177         b43_write_template_common(dev, data,
1178                                   len, ram_offset, shm_size_offset, rate);
1179 }
1180
1181 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1182                                       u16 shm_offset, u16 size, u8 rate)
1183 {
1184         struct b43_plcp_hdr4 plcp;
1185         u32 tmp;
1186         __le16 dur;
1187
1188         plcp.data = 0;
1189         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1190         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1191                                                dev->wl->if_id, size,
1192                                                B43_RATE_TO_BASE100KBPS(rate));
1193         /* Write PLCP in two parts and timing for packet transfer */
1194         tmp = le32_to_cpu(plcp.data);
1195         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1196         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1197         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1198 }
1199
1200 /* Instead of using custom probe response template, this function
1201  * just patches custom beacon template by:
1202  * 1) Changing packet type
1203  * 2) Patching duration field
1204  * 3) Stripping TIM
1205  */
1206 static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1207                                    u16 * dest_size, u8 rate)
1208 {
1209         const u8 *src_data;
1210         u8 *dest_data;
1211         u16 src_size, elem_size, src_pos, dest_pos;
1212         __le16 dur;
1213         struct ieee80211_hdr *hdr;
1214
1215         B43_WARN_ON(!dev->cached_beacon);
1216         src_size = dev->cached_beacon->len;
1217         src_data = (const u8 *)dev->cached_beacon->data;
1218
1219         if (unlikely(src_size < 0x24)) {
1220                 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
1221                 return NULL;
1222         }
1223
1224         dest_data = kmalloc(src_size, GFP_ATOMIC);
1225         if (unlikely(!dest_data))
1226                 return NULL;
1227
1228         /* 0x24 is offset of first variable-len Information-Element
1229          * in beacon frame.
1230          */
1231         memcpy(dest_data, src_data, 0x24);
1232         src_pos = dest_pos = 0x24;
1233         for (; src_pos < src_size - 2; src_pos += elem_size) {
1234                 elem_size = src_data[src_pos + 1] + 2;
1235                 if (src_data[src_pos] != 0x05) {        /* TIM */
1236                         memcpy(dest_data + dest_pos, src_data + src_pos,
1237                                elem_size);
1238                         dest_pos += elem_size;
1239                 }
1240         }
1241         *dest_size = dest_pos;
1242         hdr = (struct ieee80211_hdr *)dest_data;
1243
1244         /* Set the frame control. */
1245         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1246                                          IEEE80211_STYPE_PROBE_RESP);
1247         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1248                                                dev->wl->if_id, *dest_size,
1249                                                B43_RATE_TO_BASE100KBPS(rate));
1250         hdr->duration_id = dur;
1251
1252         return dest_data;
1253 }
1254
1255 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1256                                           u16 ram_offset,
1257                                           u16 shm_size_offset, u8 rate)
1258 {
1259         u8 *probe_resp_data;
1260         u16 size;
1261
1262         B43_WARN_ON(!dev->cached_beacon);
1263         size = dev->cached_beacon->len;
1264         probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1265         if (unlikely(!probe_resp_data))
1266                 return;
1267
1268         /* Looks like PLCP headers plus packet timings are stored for
1269          * all possible basic rates
1270          */
1271         b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1272         b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1273         b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1274         b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1275
1276         size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1277         b43_write_template_common(dev, probe_resp_data,
1278                                   size, ram_offset, shm_size_offset, rate);
1279         kfree(probe_resp_data);
1280 }
1281
1282 static int b43_refresh_cached_beacon(struct b43_wldev *dev,
1283                                      struct sk_buff *beacon)
1284 {
1285         if (dev->cached_beacon)
1286                 kfree_skb(dev->cached_beacon);
1287         dev->cached_beacon = beacon;
1288
1289         return 0;
1290 }
1291
1292 static void b43_update_templates(struct b43_wldev *dev)
1293 {
1294         u32 status;
1295
1296         B43_WARN_ON(!dev->cached_beacon);
1297
1298         b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1299         b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1300         b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
1301
1302         status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1303         status |= 0x03;
1304         b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1305 }
1306
1307 static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
1308 {
1309         int err;
1310
1311         err = b43_refresh_cached_beacon(dev, beacon);
1312         if (unlikely(err))
1313                 return;
1314         b43_update_templates(dev);
1315 }
1316
1317 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1318 {
1319         u32 tmp;
1320         u16 i, len;
1321
1322         len = min((u16) ssid_len, (u16) 0x100);
1323         for (i = 0; i < len; i += sizeof(u32)) {
1324                 tmp = (u32) (ssid[i + 0]);
1325                 if (i + 1 < len)
1326                         tmp |= (u32) (ssid[i + 1]) << 8;
1327                 if (i + 2 < len)
1328                         tmp |= (u32) (ssid[i + 2]) << 16;
1329                 if (i + 3 < len)
1330                         tmp |= (u32) (ssid[i + 3]) << 24;
1331                 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1332         }
1333         b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1334 }
1335
1336 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1337 {
1338         b43_time_lock(dev);
1339         if (dev->dev->id.revision >= 3) {
1340                 b43_write32(dev, 0x188, (beacon_int << 16));
1341         } else {
1342                 b43_write16(dev, 0x606, (beacon_int >> 6));
1343                 b43_write16(dev, 0x610, beacon_int);
1344         }
1345         b43_time_unlock(dev);
1346 }
1347
1348 static void handle_irq_beacon(struct b43_wldev *dev)
1349 {
1350         u32 status;
1351
1352         if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1353                 return;
1354
1355         dev->irq_savedstate &= ~B43_IRQ_BEACON;
1356         status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1357
1358         if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1359                 /* ACK beacon IRQ. */
1360                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1361                 dev->irq_savedstate |= B43_IRQ_BEACON;
1362                 if (dev->cached_beacon)
1363                         kfree_skb(dev->cached_beacon);
1364                 dev->cached_beacon = NULL;
1365                 return;
1366         }
1367         if (!(status & 0x1)) {
1368                 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1369                 status |= 0x1;
1370                 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1371         }
1372         if (!(status & 0x2)) {
1373                 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1374                 status |= 0x2;
1375                 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1376         }
1377 }
1378
1379 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1380 {
1381         //TODO
1382 }
1383
1384 /* Interrupt handler bottom-half */
1385 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1386 {
1387         u32 reason;
1388         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1389         u32 merged_dma_reason = 0;
1390         int i;
1391         unsigned long flags;
1392
1393         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1394
1395         B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1396
1397         reason = dev->irq_reason;
1398         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1399                 dma_reason[i] = dev->dma_reason[i];
1400                 merged_dma_reason |= dma_reason[i];
1401         }
1402
1403         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1404                 b43err(dev->wl, "MAC transmission error\n");
1405
1406         if (unlikely(reason & B43_IRQ_PHY_TXERR))
1407                 b43err(dev->wl, "PHY transmission error\n");
1408
1409         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1410                                           B43_DMAIRQ_NONFATALMASK))) {
1411                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1412                         b43err(dev->wl, "Fatal DMA error: "
1413                                "0x%08X, 0x%08X, 0x%08X, "
1414                                "0x%08X, 0x%08X, 0x%08X\n",
1415                                dma_reason[0], dma_reason[1],
1416                                dma_reason[2], dma_reason[3],
1417                                dma_reason[4], dma_reason[5]);
1418                         b43_controller_restart(dev, "DMA error");
1419                         mmiowb();
1420                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1421                         return;
1422                 }
1423                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1424                         b43err(dev->wl, "DMA error: "
1425                                "0x%08X, 0x%08X, 0x%08X, "
1426                                "0x%08X, 0x%08X, 0x%08X\n",
1427                                dma_reason[0], dma_reason[1],
1428                                dma_reason[2], dma_reason[3],
1429                                dma_reason[4], dma_reason[5]);
1430                 }
1431         }
1432
1433         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1434                 handle_irq_ucode_debug(dev);
1435         if (reason & B43_IRQ_TBTT_INDI)
1436                 handle_irq_tbtt_indication(dev);
1437         if (reason & B43_IRQ_ATIM_END)
1438                 handle_irq_atim_end(dev);
1439         if (reason & B43_IRQ_BEACON)
1440                 handle_irq_beacon(dev);
1441         if (reason & B43_IRQ_PMQ)
1442                 handle_irq_pmq(dev);
1443         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1444                 ;/* TODO */
1445         if (reason & B43_IRQ_NOISESAMPLE_OK)
1446                 handle_irq_noise(dev);
1447
1448         /* Check the DMA reason registers for received data. */
1449         if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1450                 if (b43_using_pio(dev))
1451                         b43_pio_rx(dev->pio.queue0);
1452                 else
1453                         b43_dma_rx(dev->dma.rx_ring0);
1454         }
1455         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1456         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1457         if (dma_reason[3] & B43_DMAIRQ_RX_DONE) {
1458                 if (b43_using_pio(dev))
1459                         b43_pio_rx(dev->pio.queue3);
1460                 else
1461                         b43_dma_rx(dev->dma.rx_ring3);
1462         }
1463         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1464         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1465
1466         if (reason & B43_IRQ_TX_OK)
1467                 handle_irq_transmit_status(dev);
1468
1469         b43_interrupt_enable(dev, dev->irq_savedstate);
1470         mmiowb();
1471         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1472 }
1473
1474 static void pio_irq_workaround(struct b43_wldev *dev, u16 base, int queueidx)
1475 {
1476         u16 rxctl;
1477
1478         rxctl = b43_read16(dev, base + B43_PIO_RXCTL);
1479         if (rxctl & B43_PIO_RXCTL_DATAAVAILABLE)
1480                 dev->dma_reason[queueidx] |= B43_DMAIRQ_RX_DONE;
1481         else
1482                 dev->dma_reason[queueidx] &= ~B43_DMAIRQ_RX_DONE;
1483 }
1484
1485 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1486 {
1487         if (b43_using_pio(dev) &&
1488             (dev->dev->id.revision < 3) &&
1489             (!(reason & B43_IRQ_PIO_WORKAROUND))) {
1490                 /* Apply a PIO specific workaround to the dma_reasons */
1491                 pio_irq_workaround(dev, B43_MMIO_PIO1_BASE, 0);
1492                 pio_irq_workaround(dev, B43_MMIO_PIO2_BASE, 1);
1493                 pio_irq_workaround(dev, B43_MMIO_PIO3_BASE, 2);
1494                 pio_irq_workaround(dev, B43_MMIO_PIO4_BASE, 3);
1495         }
1496
1497         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1498
1499         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1500         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1501         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1502         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1503         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1504         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1505 }
1506
1507 /* Interrupt handler top-half */
1508 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1509 {
1510         irqreturn_t ret = IRQ_NONE;
1511         struct b43_wldev *dev = dev_id;
1512         u32 reason;
1513
1514         if (!dev)
1515                 return IRQ_NONE;
1516
1517         spin_lock(&dev->wl->irq_lock);
1518
1519         if (b43_status(dev) < B43_STAT_STARTED)
1520                 goto out;
1521         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1522         if (reason == 0xffffffff)       /* shared IRQ */
1523                 goto out;
1524         ret = IRQ_HANDLED;
1525         reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1526         if (!reason)
1527                 goto out;
1528
1529         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1530             & 0x0001DC00;
1531         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1532             & 0x0000DC00;
1533         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1534             & 0x0000DC00;
1535         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1536             & 0x0001DC00;
1537         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1538             & 0x0000DC00;
1539         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1540             & 0x0000DC00;
1541
1542         b43_interrupt_ack(dev, reason);
1543         /* disable all IRQs. They are enabled again in the bottom half. */
1544         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1545         /* save the reason code and call our bottom half. */
1546         dev->irq_reason = reason;
1547         tasklet_schedule(&dev->isr_tasklet);
1548       out:
1549         mmiowb();
1550         spin_unlock(&dev->wl->irq_lock);
1551
1552         return ret;
1553 }
1554
1555 static void b43_release_firmware(struct b43_wldev *dev)
1556 {
1557         release_firmware(dev->fw.ucode);
1558         dev->fw.ucode = NULL;
1559         release_firmware(dev->fw.pcm);
1560         dev->fw.pcm = NULL;
1561         release_firmware(dev->fw.initvals);
1562         dev->fw.initvals = NULL;
1563         release_firmware(dev->fw.initvals_band);
1564         dev->fw.initvals_band = NULL;
1565 }
1566
1567 static void b43_print_fw_helptext(struct b43_wl *wl)
1568 {
1569         b43err(wl, "You must go to "
1570                "http://linuxwireless.org/en/users/Drivers/bcm43xx#devicefirmware "
1571                "and download the correct firmware (version 4).\n");
1572 }
1573
1574 static int do_request_fw(struct b43_wldev *dev,
1575                          const char *name,
1576                          const struct firmware **fw)
1577 {
1578         char path[sizeof(modparam_fwpostfix) + 32];
1579         struct b43_fw_header *hdr;
1580         u32 size;
1581         int err;
1582
1583         if (!name)
1584                 return 0;
1585
1586         snprintf(path, ARRAY_SIZE(path),
1587                  "b43%s/%s.fw",
1588                  modparam_fwpostfix, name);
1589         err = request_firmware(fw, path, dev->dev->dev);
1590         if (err) {
1591                 b43err(dev->wl, "Firmware file \"%s\" not found "
1592                        "or load failed.\n", path);
1593                 return err;
1594         }
1595         if ((*fw)->size < sizeof(struct b43_fw_header))
1596                 goto err_format;
1597         hdr = (struct b43_fw_header *)((*fw)->data);
1598         switch (hdr->type) {
1599         case B43_FW_TYPE_UCODE:
1600         case B43_FW_TYPE_PCM:
1601                 size = be32_to_cpu(hdr->size);
1602                 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1603                         goto err_format;
1604                 /* fallthrough */
1605         case B43_FW_TYPE_IV:
1606                 if (hdr->ver != 1)
1607                         goto err_format;
1608                 break;
1609         default:
1610                 goto err_format;
1611         }
1612
1613         return err;
1614
1615 err_format:
1616         b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1617         return -EPROTO;
1618 }
1619
1620 static int b43_request_firmware(struct b43_wldev *dev)
1621 {
1622         struct b43_firmware *fw = &dev->fw;
1623         const u8 rev = dev->dev->id.revision;
1624         const char *filename;
1625         u32 tmshigh;
1626         int err;
1627
1628         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1629         if (!fw->ucode) {
1630                 if ((rev >= 5) && (rev <= 10))
1631                         filename = "ucode5";
1632                 else if ((rev >= 11) && (rev <= 12))
1633                         filename = "ucode11";
1634                 else if (rev >= 13)
1635                         filename = "ucode13";
1636                 else
1637                         goto err_no_ucode;
1638                 err = do_request_fw(dev, filename, &fw->ucode);
1639                 if (err)
1640                         goto err_load;
1641         }
1642         if (!fw->pcm) {
1643                 if ((rev >= 5) && (rev <= 10))
1644                         filename = "pcm5";
1645                 else if (rev >= 11)
1646                         filename = NULL;
1647                 else
1648                         goto err_no_pcm;
1649                 err = do_request_fw(dev, filename, &fw->pcm);
1650                 if (err)
1651                         goto err_load;
1652         }
1653         if (!fw->initvals) {
1654                 switch (dev->phy.type) {
1655                 case B43_PHYTYPE_A:
1656                         if ((rev >= 5) && (rev <= 10)) {
1657                                 if (tmshigh & B43_TMSHIGH_GPHY)
1658                                         filename = "a0g1initvals5";
1659                                 else
1660                                         filename = "a0g0initvals5";
1661                         } else
1662                                 goto err_no_initvals;
1663                         break;
1664                 case B43_PHYTYPE_G:
1665                         if ((rev >= 5) && (rev <= 10))
1666                                 filename = "b0g0initvals5";
1667                         else if (rev >= 13)
1668                                 filename = "lp0initvals13";
1669                         else
1670                                 goto err_no_initvals;
1671                         break;
1672                 default:
1673                         goto err_no_initvals;
1674                 }
1675                 err = do_request_fw(dev, filename, &fw->initvals);
1676                 if (err)
1677                         goto err_load;
1678         }
1679         if (!fw->initvals_band) {
1680                 switch (dev->phy.type) {
1681                 case B43_PHYTYPE_A:
1682                         if ((rev >= 5) && (rev <= 10)) {
1683                                 if (tmshigh & B43_TMSHIGH_GPHY)
1684                                         filename = "a0g1bsinitvals5";
1685                                 else
1686                                         filename = "a0g0bsinitvals5";
1687                         } else if (rev >= 11)
1688                                 filename = NULL;
1689                         else
1690                                 goto err_no_initvals;
1691                         break;
1692                 case B43_PHYTYPE_G:
1693                         if ((rev >= 5) && (rev <= 10))
1694                                 filename = "b0g0bsinitvals5";
1695                         else if (rev >= 11)
1696                                 filename = NULL;
1697                         else
1698                                 goto err_no_initvals;
1699                         break;
1700                 default:
1701                         goto err_no_initvals;
1702                 }
1703                 err = do_request_fw(dev, filename, &fw->initvals_band);
1704                 if (err)
1705                         goto err_load;
1706         }
1707
1708         return 0;
1709
1710 err_load:
1711         b43_print_fw_helptext(dev->wl);
1712         goto error;
1713
1714 err_no_ucode:
1715         err = -ENODEV;
1716         b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1717         goto error;
1718
1719 err_no_pcm:
1720         err = -ENODEV;
1721         b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1722         goto error;
1723
1724 err_no_initvals:
1725         err = -ENODEV;
1726         b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1727                "core rev %u\n", dev->phy.type, rev);
1728         goto error;
1729
1730 error:
1731         b43_release_firmware(dev);
1732         return err;
1733 }
1734
1735 static int b43_upload_microcode(struct b43_wldev *dev)
1736 {
1737         const size_t hdr_len = sizeof(struct b43_fw_header);
1738         const __be32 *data;
1739         unsigned int i, len;
1740         u16 fwrev, fwpatch, fwdate, fwtime;
1741         u32 tmp;
1742         int err = 0;
1743
1744         /* Upload Microcode. */
1745         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1746         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1747         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1748         for (i = 0; i < len; i++) {
1749                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1750                 udelay(10);
1751         }
1752
1753         if (dev->fw.pcm) {
1754                 /* Upload PCM data. */
1755                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1756                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1757                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1758                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1759                 /* No need for autoinc bit in SHM_HW */
1760                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1761                 for (i = 0; i < len; i++) {
1762                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1763                         udelay(10);
1764                 }
1765         }
1766
1767         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1768         b43_write32(dev, B43_MMIO_MACCTL,
1769                     B43_MACCTL_PSM_RUN |
1770                     B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1771
1772         /* Wait for the microcode to load and respond */
1773         i = 0;
1774         while (1) {
1775                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1776                 if (tmp == B43_IRQ_MAC_SUSPENDED)
1777                         break;
1778                 i++;
1779                 if (i >= 50) {
1780                         b43err(dev->wl, "Microcode not responding\n");
1781                         b43_print_fw_helptext(dev->wl);
1782                         err = -ENODEV;
1783                         goto out;
1784                 }
1785                 udelay(10);
1786         }
1787         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
1788
1789         /* Get and check the revisions. */
1790         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1791         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1792         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1793         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1794
1795         if (fwrev <= 0x128) {
1796                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1797                        "binary drivers older than version 4.x is unsupported. "
1798                        "You must upgrade your firmware files.\n");
1799                 b43_print_fw_helptext(dev->wl);
1800                 b43_write32(dev, B43_MMIO_MACCTL, 0);
1801                 err = -EOPNOTSUPP;
1802                 goto out;
1803         }
1804         b43dbg(dev->wl, "Loading firmware version %u.%u "
1805                "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1806                fwrev, fwpatch,
1807                (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1808                (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1809
1810         dev->fw.rev = fwrev;
1811         dev->fw.patch = fwpatch;
1812
1813       out:
1814         return err;
1815 }
1816
1817 static int b43_write_initvals(struct b43_wldev *dev,
1818                               const struct b43_iv *ivals,
1819                               size_t count,
1820                               size_t array_size)
1821 {
1822         const struct b43_iv *iv;
1823         u16 offset;
1824         size_t i;
1825         bool bit32;
1826
1827         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1828         iv = ivals;
1829         for (i = 0; i < count; i++) {
1830                 if (array_size < sizeof(iv->offset_size))
1831                         goto err_format;
1832                 array_size -= sizeof(iv->offset_size);
1833                 offset = be16_to_cpu(iv->offset_size);
1834                 bit32 = !!(offset & B43_IV_32BIT);
1835                 offset &= B43_IV_OFFSET_MASK;
1836                 if (offset >= 0x1000)
1837                         goto err_format;
1838                 if (bit32) {
1839                         u32 value;
1840
1841                         if (array_size < sizeof(iv->data.d32))
1842                                 goto err_format;
1843                         array_size -= sizeof(iv->data.d32);
1844
1845                         value = be32_to_cpu(get_unaligned(&iv->data.d32));
1846                         b43_write32(dev, offset, value);
1847
1848                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1849                                                         sizeof(__be16) +
1850                                                         sizeof(__be32));
1851                 } else {
1852                         u16 value;
1853
1854                         if (array_size < sizeof(iv->data.d16))
1855                                 goto err_format;
1856                         array_size -= sizeof(iv->data.d16);
1857
1858                         value = be16_to_cpu(iv->data.d16);
1859                         b43_write16(dev, offset, value);
1860
1861                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1862                                                         sizeof(__be16) +
1863                                                         sizeof(__be16));
1864                 }
1865         }
1866         if (array_size)
1867                 goto err_format;
1868
1869         return 0;
1870
1871 err_format:
1872         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1873         b43_print_fw_helptext(dev->wl);
1874
1875         return -EPROTO;
1876 }
1877
1878 static int b43_upload_initvals(struct b43_wldev *dev)
1879 {
1880         const size_t hdr_len = sizeof(struct b43_fw_header);
1881         const struct b43_fw_header *hdr;
1882         struct b43_firmware *fw = &dev->fw;
1883         const struct b43_iv *ivals;
1884         size_t count;
1885         int err;
1886
1887         hdr = (const struct b43_fw_header *)(fw->initvals->data);
1888         ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1889         count = be32_to_cpu(hdr->size);
1890         err = b43_write_initvals(dev, ivals, count,
1891                                  fw->initvals->size - hdr_len);
1892         if (err)
1893                 goto out;
1894         if (fw->initvals_band) {
1895                 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1896                 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1897                 count = be32_to_cpu(hdr->size);
1898                 err = b43_write_initvals(dev, ivals, count,
1899                                          fw->initvals_band->size - hdr_len);
1900                 if (err)
1901                         goto out;
1902         }
1903 out:
1904
1905         return err;
1906 }
1907
1908 /* Initialize the GPIOs
1909  * http://bcm-specs.sipsolutions.net/GPIO
1910  */
1911 static int b43_gpio_init(struct b43_wldev *dev)
1912 {
1913         struct ssb_bus *bus = dev->dev->bus;
1914         struct ssb_device *gpiodev, *pcidev = NULL;
1915         u32 mask, set;
1916
1917         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1918                     & ~B43_MACCTL_GPOUTSMSK);
1919
1920         b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1921                     | 0x000F);
1922
1923         mask = 0x0000001F;
1924         set = 0x0000000F;
1925         if (dev->dev->bus->chip_id == 0x4301) {
1926                 mask |= 0x0060;
1927                 set |= 0x0060;
1928         }
1929         if (0 /* FIXME: conditional unknown */ ) {
1930                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1931                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1932                             | 0x0100);
1933                 mask |= 0x0180;
1934                 set |= 0x0180;
1935         }
1936         if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL) {
1937                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1938                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1939                             | 0x0200);
1940                 mask |= 0x0200;
1941                 set |= 0x0200;
1942         }
1943         if (dev->dev->id.revision >= 2)
1944                 mask |= 0x0010; /* FIXME: This is redundant. */
1945
1946 #ifdef CONFIG_SSB_DRIVER_PCICORE
1947         pcidev = bus->pcicore.dev;
1948 #endif
1949         gpiodev = bus->chipco.dev ? : pcidev;
1950         if (!gpiodev)
1951                 return 0;
1952         ssb_write32(gpiodev, B43_GPIO_CONTROL,
1953                     (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1954                      & mask) | set);
1955
1956         return 0;
1957 }
1958
1959 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1960 static void b43_gpio_cleanup(struct b43_wldev *dev)
1961 {
1962         struct ssb_bus *bus = dev->dev->bus;
1963         struct ssb_device *gpiodev, *pcidev = NULL;
1964
1965 #ifdef CONFIG_SSB_DRIVER_PCICORE
1966         pcidev = bus->pcicore.dev;
1967 #endif
1968         gpiodev = bus->chipco.dev ? : pcidev;
1969         if (!gpiodev)
1970                 return;
1971         ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1972 }
1973
1974 /* http://bcm-specs.sipsolutions.net/EnableMac */
1975 void b43_mac_enable(struct b43_wldev *dev)
1976 {
1977         dev->mac_suspended--;
1978         B43_WARN_ON(dev->mac_suspended < 0);
1979         if (dev->mac_suspended == 0) {
1980                 b43_write32(dev, B43_MMIO_MACCTL,
1981                             b43_read32(dev, B43_MMIO_MACCTL)
1982                             | B43_MACCTL_ENABLED);
1983                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1984                             B43_IRQ_MAC_SUSPENDED);
1985                 /* Commit writes */
1986                 b43_read32(dev, B43_MMIO_MACCTL);
1987                 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1988                 b43_power_saving_ctl_bits(dev, 0);
1989         }
1990 }
1991
1992 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1993 void b43_mac_suspend(struct b43_wldev *dev)
1994 {
1995         int i;
1996         u32 tmp;
1997
1998         B43_WARN_ON(dev->mac_suspended < 0);
1999         if (dev->mac_suspended == 0) {
2000                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2001                 b43_write32(dev, B43_MMIO_MACCTL,
2002                             b43_read32(dev, B43_MMIO_MACCTL)
2003                             & ~B43_MACCTL_ENABLED);
2004                 /* force pci to flush the write */
2005                 b43_read32(dev, B43_MMIO_MACCTL);
2006                 for (i = 10000; i; i--) {
2007                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2008                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2009                                 goto out;
2010                         udelay(1);
2011                 }
2012                 b43err(dev->wl, "MAC suspend failed\n");
2013         }
2014       out:
2015         dev->mac_suspended++;
2016 }
2017
2018 static void b43_adjust_opmode(struct b43_wldev *dev)
2019 {
2020         struct b43_wl *wl = dev->wl;
2021         u32 ctl;
2022         u16 cfp_pretbtt;
2023
2024         ctl = b43_read32(dev, B43_MMIO_MACCTL);
2025         /* Reset status to STA infrastructure mode. */
2026         ctl &= ~B43_MACCTL_AP;
2027         ctl &= ~B43_MACCTL_KEEP_CTL;
2028         ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2029         ctl &= ~B43_MACCTL_KEEP_BAD;
2030         ctl &= ~B43_MACCTL_PROMISC;
2031         ctl &= ~B43_MACCTL_BEACPROMISC;
2032         ctl |= B43_MACCTL_INFRA;
2033
2034         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2035                 ctl |= B43_MACCTL_AP;
2036         else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2037                 ctl &= ~B43_MACCTL_INFRA;
2038
2039         if (wl->filter_flags & FIF_CONTROL)
2040                 ctl |= B43_MACCTL_KEEP_CTL;
2041         if (wl->filter_flags & FIF_FCSFAIL)
2042                 ctl |= B43_MACCTL_KEEP_BAD;
2043         if (wl->filter_flags & FIF_PLCPFAIL)
2044                 ctl |= B43_MACCTL_KEEP_BADPLCP;
2045         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2046                 ctl |= B43_MACCTL_PROMISC;
2047         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2048                 ctl |= B43_MACCTL_BEACPROMISC;
2049
2050         /* Workaround: On old hardware the HW-MAC-address-filter
2051          * doesn't work properly, so always run promisc in filter
2052          * it in software. */
2053         if (dev->dev->id.revision <= 4)
2054                 ctl |= B43_MACCTL_PROMISC;
2055
2056         b43_write32(dev, B43_MMIO_MACCTL, ctl);
2057
2058         cfp_pretbtt = 2;
2059         if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2060                 if (dev->dev->bus->chip_id == 0x4306 &&
2061                     dev->dev->bus->chip_rev == 3)
2062                         cfp_pretbtt = 100;
2063                 else
2064                         cfp_pretbtt = 50;
2065         }
2066         b43_write16(dev, 0x612, cfp_pretbtt);
2067 }
2068
2069 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2070 {
2071         u16 offset;
2072
2073         if (is_ofdm) {
2074                 offset = 0x480;
2075                 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2076         } else {
2077                 offset = 0x4C0;
2078                 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2079         }
2080         b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2081                         b43_shm_read16(dev, B43_SHM_SHARED, offset));
2082 }
2083
2084 static void b43_rate_memory_init(struct b43_wldev *dev)
2085 {
2086         switch (dev->phy.type) {
2087         case B43_PHYTYPE_A:
2088         case B43_PHYTYPE_G:
2089                 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2090                 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2091                 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2092                 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2093                 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2094                 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2095                 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2096                 if (dev->phy.type == B43_PHYTYPE_A)
2097                         break;
2098                 /* fallthrough */
2099         case B43_PHYTYPE_B:
2100                 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2101                 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2102                 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2103                 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2104                 break;
2105         default:
2106                 B43_WARN_ON(1);
2107         }
2108 }
2109
2110 /* Set the TX-Antenna for management frames sent by firmware. */
2111 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2112 {
2113         u16 ant = 0;
2114         u16 tmp;
2115
2116         switch (antenna) {
2117         case B43_ANTENNA0:
2118                 ant |= B43_TX4_PHY_ANT0;
2119                 break;
2120         case B43_ANTENNA1:
2121                 ant |= B43_TX4_PHY_ANT1;
2122                 break;
2123         case B43_ANTENNA_AUTO:
2124                 ant |= B43_TX4_PHY_ANTLAST;
2125                 break;
2126         default:
2127                 B43_WARN_ON(1);
2128         }
2129
2130         /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2131
2132         /* For Beacons */
2133         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2134         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2135         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2136         /* For ACK/CTS */
2137         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2138         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2139         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2140         /* For Probe Resposes */
2141         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2142         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2143         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2144 }
2145
2146 /* This is the opposite of b43_chip_init() */
2147 static void b43_chip_exit(struct b43_wldev *dev)
2148 {
2149         b43_radio_turn_off(dev, 1);
2150         b43_leds_exit(dev);
2151         b43_gpio_cleanup(dev);
2152         /* firmware is released later */
2153 }
2154
2155 /* Initialize the chip
2156  * http://bcm-specs.sipsolutions.net/ChipInit
2157  */
2158 static int b43_chip_init(struct b43_wldev *dev)
2159 {
2160         struct b43_phy *phy = &dev->phy;
2161         int err, tmp;
2162         u32 value32;
2163         u16 value16;
2164
2165         b43_write32(dev, B43_MMIO_MACCTL,
2166                     B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2167
2168         err = b43_request_firmware(dev);
2169         if (err)
2170                 goto out;
2171         err = b43_upload_microcode(dev);
2172         if (err)
2173                 goto out;       /* firmware is released later */
2174
2175         err = b43_gpio_init(dev);
2176         if (err)
2177                 goto out;       /* firmware is released later */
2178         b43_leds_init(dev);
2179
2180         err = b43_upload_initvals(dev);
2181         if (err)
2182                 goto err_leds_exit;
2183         b43_radio_turn_on(dev);
2184
2185         b43_write16(dev, 0x03E6, 0x0000);
2186         err = b43_phy_init(dev);
2187         if (err)
2188                 goto err_radio_off;
2189
2190         /* Select initial Interference Mitigation. */
2191         tmp = phy->interfmode;
2192         phy->interfmode = B43_INTERFMODE_NONE;
2193         b43_radio_set_interference_mitigation(dev, tmp);
2194
2195         b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2196         b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2197
2198         if (phy->type == B43_PHYTYPE_B) {
2199                 value16 = b43_read16(dev, 0x005E);
2200                 value16 |= 0x0004;
2201                 b43_write16(dev, 0x005E, value16);
2202         }
2203         b43_write32(dev, 0x0100, 0x01000000);
2204         if (dev->dev->id.revision < 5)
2205                 b43_write32(dev, 0x010C, 0x01000000);
2206
2207         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2208                     & ~B43_MACCTL_INFRA);
2209         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2210                     | B43_MACCTL_INFRA);
2211
2212         if (b43_using_pio(dev)) {
2213                 b43_write32(dev, 0x0210, 0x00000100);
2214                 b43_write32(dev, 0x0230, 0x00000100);
2215                 b43_write32(dev, 0x0250, 0x00000100);
2216                 b43_write32(dev, 0x0270, 0x00000100);
2217                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0034, 0x0000);
2218         }
2219
2220         /* Probe Response Timeout value */
2221         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2222         b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2223
2224         /* Initially set the wireless operation mode. */
2225         b43_adjust_opmode(dev);
2226
2227         if (dev->dev->id.revision < 3) {
2228                 b43_write16(dev, 0x060E, 0x0000);
2229                 b43_write16(dev, 0x0610, 0x8000);
2230                 b43_write16(dev, 0x0604, 0x0000);
2231                 b43_write16(dev, 0x0606, 0x0200);
2232         } else {
2233                 b43_write32(dev, 0x0188, 0x80000000);
2234                 b43_write32(dev, 0x018C, 0x02000000);
2235         }
2236         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2237         b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2238         b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2239         b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2240         b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2241         b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2242         b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2243
2244         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2245         value32 |= 0x00100000;
2246         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2247
2248         b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2249                     dev->dev->bus->chipco.fast_pwrup_delay);
2250
2251         err = 0;
2252         b43dbg(dev->wl, "Chip initialized\n");
2253 out:
2254         return err;
2255
2256 err_radio_off:
2257         b43_radio_turn_off(dev, 1);
2258 err_leds_exit:
2259         b43_leds_exit(dev);
2260         b43_gpio_cleanup(dev);
2261         return err;
2262 }
2263
2264 static void b43_periodic_every120sec(struct b43_wldev *dev)
2265 {
2266         struct b43_phy *phy = &dev->phy;
2267
2268         if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2269                 return;
2270
2271         b43_mac_suspend(dev);
2272         b43_lo_g_measure(dev);
2273         b43_mac_enable(dev);
2274         if (b43_has_hardware_pctl(phy))
2275                 b43_lo_g_ctl_mark_all_unused(dev);
2276 }
2277
2278 static void b43_periodic_every60sec(struct b43_wldev *dev)
2279 {
2280         struct b43_phy *phy = &dev->phy;
2281
2282         if (!b43_has_hardware_pctl(phy))
2283                 b43_lo_g_ctl_mark_all_unused(dev);
2284         if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
2285                 b43_mac_suspend(dev);
2286                 b43_calc_nrssi_slope(dev);
2287                 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2288                         u8 old_chan = phy->channel;
2289
2290                         /* VCO Calibration */
2291                         if (old_chan >= 8)
2292                                 b43_radio_selectchannel(dev, 1, 0);
2293                         else
2294                                 b43_radio_selectchannel(dev, 13, 0);
2295                         b43_radio_selectchannel(dev, old_chan, 0);
2296                 }
2297                 b43_mac_enable(dev);
2298         }
2299 }
2300
2301 static void b43_periodic_every30sec(struct b43_wldev *dev)
2302 {
2303         /* Update device statistics. */
2304         b43_calculate_link_quality(dev);
2305 }
2306
2307 static void b43_periodic_every15sec(struct b43_wldev *dev)
2308 {
2309         struct b43_phy *phy = &dev->phy;
2310
2311         if (phy->type == B43_PHYTYPE_G) {
2312                 //TODO: update_aci_moving_average
2313                 if (phy->aci_enable && phy->aci_wlan_automatic) {
2314                         b43_mac_suspend(dev);
2315                         if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2316                                 if (0 /*TODO: bunch of conditions */ ) {
2317                                         b43_radio_set_interference_mitigation
2318                                             (dev, B43_INTERFMODE_MANUALWLAN);
2319                                 }
2320                         } else if (1 /*TODO*/) {
2321                                 /*
2322                                    if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2323                                    b43_radio_set_interference_mitigation(dev,
2324                                    B43_INTERFMODE_NONE);
2325                                    }
2326                                  */
2327                         }
2328                         b43_mac_enable(dev);
2329                 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2330                            phy->rev == 1) {
2331                         //TODO: implement rev1 workaround
2332                 }
2333         }
2334         b43_phy_xmitpower(dev); //FIXME: unless scanning?
2335         //TODO for APHY (temperature?)
2336 }
2337
2338 static void do_periodic_work(struct b43_wldev *dev)
2339 {
2340         unsigned int state;
2341
2342         state = dev->periodic_state;
2343         if (state % 8 == 0)
2344                 b43_periodic_every120sec(dev);
2345         if (state % 4 == 0)
2346                 b43_periodic_every60sec(dev);
2347         if (state % 2 == 0)
2348                 b43_periodic_every30sec(dev);
2349         b43_periodic_every15sec(dev);
2350 }
2351
2352 /* Estimate a "Badness" value based on the periodic work
2353  * state-machine state. "Badness" is worse (bigger), if the
2354  * periodic work will take longer.
2355  */
2356 static int estimate_periodic_work_badness(unsigned int state)
2357 {
2358         int badness = 0;
2359
2360         if (state % 8 == 0)     /* every 120 sec */
2361                 badness += 10;
2362         if (state % 4 == 0)     /* every 60 sec */
2363                 badness += 5;
2364         if (state % 2 == 0)     /* every 30 sec */
2365                 badness += 1;
2366
2367 #define BADNESS_LIMIT   4
2368         return badness;
2369 }
2370
2371 static void b43_periodic_work_handler(struct work_struct *work)
2372 {
2373         struct b43_wldev *dev =
2374             container_of(work, struct b43_wldev, periodic_work.work);
2375         unsigned long flags, delay;
2376         u32 savedirqs = 0;
2377         int badness;
2378
2379         mutex_lock(&dev->wl->mutex);
2380
2381         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2382                 goto out;
2383         if (b43_debug(dev, B43_DBG_PWORK_STOP))
2384                 goto out_requeue;
2385
2386         badness = estimate_periodic_work_badness(dev->periodic_state);
2387         if (badness > BADNESS_LIMIT) {
2388                 spin_lock_irqsave(&dev->wl->irq_lock, flags);
2389                 /* Suspend TX as we don't want to transmit packets while
2390                  * we recalibrate the hardware. */
2391                 b43_tx_suspend(dev);
2392                 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2393                 /* Periodic work will take a long time, so we want it to
2394                  * be preemtible and release the spinlock. */
2395                 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
2396                 b43_synchronize_irq(dev);
2397
2398                 do_periodic_work(dev);
2399
2400                 spin_lock_irqsave(&dev->wl->irq_lock, flags);
2401                 b43_interrupt_enable(dev, savedirqs);
2402                 b43_tx_resume(dev);
2403                 mmiowb();
2404                 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
2405         } else {
2406                 /* Take the global driver lock. This will lock any operation. */
2407                 spin_lock_irqsave(&dev->wl->irq_lock, flags);
2408
2409                 do_periodic_work(dev);
2410
2411                 mmiowb();
2412                 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
2413         }
2414         dev->periodic_state++;
2415 out_requeue:
2416         if (b43_debug(dev, B43_DBG_PWORK_FAST))
2417                 delay = msecs_to_jiffies(50);
2418         else
2419                 delay = round_jiffies(HZ * 15);
2420         queue_delayed_work(dev->wl->hw->workqueue, &dev->periodic_work, delay);
2421 out:
2422         mutex_unlock(&dev->wl->mutex);
2423 }
2424
2425 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2426 {
2427         struct delayed_work *work = &dev->periodic_work;
2428
2429         dev->periodic_state = 0;
2430         INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2431         queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2432 }
2433
2434 /* Validate access to the chip (SHM) */
2435 static int b43_validate_chipaccess(struct b43_wldev *dev)
2436 {
2437         u32 value;
2438         u32 shm_backup;
2439
2440         shm_backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2441         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2442         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2443                 goto error;
2444         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2445         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2446                 goto error;
2447         b43_shm_write32(dev, B43_SHM_SHARED, 0, shm_backup);
2448
2449         value = b43_read32(dev, B43_MMIO_MACCTL);
2450         if ((value | B43_MACCTL_GMODE) !=
2451             (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2452                 goto error;
2453
2454         value = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2455         if (value)
2456                 goto error;
2457
2458         return 0;
2459       error:
2460         b43err(dev->wl, "Failed to validate the chipaccess\n");
2461         return -ENODEV;
2462 }
2463
2464 static void b43_security_init(struct b43_wldev *dev)
2465 {
2466         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2467         B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2468         dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2469         /* KTP is a word address, but we address SHM bytewise.
2470          * So multiply by two.
2471          */
2472         dev->ktp *= 2;
2473         if (dev->dev->id.revision >= 5) {
2474                 /* Number of RCMTA address slots */
2475                 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2476         }
2477         b43_clear_keys(dev);
2478 }
2479
2480 static int b43_rng_read(struct hwrng *rng, u32 * data)
2481 {
2482         struct b43_wl *wl = (struct b43_wl *)rng->priv;
2483         unsigned long flags;
2484
2485         /* Don't take wl->mutex here, as it could deadlock with
2486          * hwrng internal locking. It's not needed to take
2487          * wl->mutex here, anyway. */
2488
2489         spin_lock_irqsave(&wl->irq_lock, flags);
2490         *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2491         spin_unlock_irqrestore(&wl->irq_lock, flags);
2492
2493         return (sizeof(u16));
2494 }
2495
2496 static void b43_rng_exit(struct b43_wl *wl)
2497 {
2498         if (wl->rng_initialized)
2499                 hwrng_unregister(&wl->rng);
2500 }
2501
2502 static int b43_rng_init(struct b43_wl *wl)
2503 {
2504         int err;
2505
2506         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2507                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2508         wl->rng.name = wl->rng_name;
2509         wl->rng.data_read = b43_rng_read;
2510         wl->rng.priv = (unsigned long)wl;
2511         wl->rng_initialized = 1;
2512         err = hwrng_register(&wl->rng);
2513         if (err) {
2514                 wl->rng_initialized = 0;
2515                 b43err(wl, "Failed to register the random "
2516                        "number generator (%d)\n", err);
2517         }
2518
2519         return err;
2520 }
2521
2522 static int b43_tx(struct ieee80211_hw *hw,
2523                   struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2524 {
2525         struct b43_wl *wl = hw_to_b43_wl(hw);
2526         struct b43_wldev *dev = wl->current_dev;
2527         int err = -ENODEV;
2528         unsigned long flags;
2529
2530         if (unlikely(!dev))
2531                 goto out;
2532         if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2533                 goto out;
2534         /* DMA-TX is done without a global lock. */
2535         if (b43_using_pio(dev)) {
2536                 spin_lock_irqsave(&wl->irq_lock, flags);
2537                 err = b43_pio_tx(dev, skb, ctl);
2538                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2539         } else
2540                 err = b43_dma_tx(dev, skb, ctl);
2541       out:
2542         if (unlikely(err))
2543                 return NETDEV_TX_BUSY;
2544         return NETDEV_TX_OK;
2545 }
2546
2547 static int b43_conf_tx(struct ieee80211_hw *hw,
2548                        int queue,
2549                        const struct ieee80211_tx_queue_params *params)
2550 {
2551         return 0;
2552 }
2553
2554 static int b43_get_tx_stats(struct ieee80211_hw *hw,
2555                             struct ieee80211_tx_queue_stats *stats)
2556 {
2557         struct b43_wl *wl = hw_to_b43_wl(hw);
2558         struct b43_wldev *dev = wl->current_dev;
2559         unsigned long flags;
2560         int err = -ENODEV;
2561
2562         if (!dev)
2563                 goto out;
2564         spin_lock_irqsave(&wl->irq_lock, flags);
2565         if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2566                 if (b43_using_pio(dev))
2567                         b43_pio_get_tx_stats(dev, stats);
2568                 else
2569                         b43_dma_get_tx_stats(dev, stats);
2570                 err = 0;
2571         }
2572         spin_unlock_irqrestore(&wl->irq_lock, flags);
2573       out:
2574         return err;
2575 }
2576
2577 static int b43_get_stats(struct ieee80211_hw *hw,
2578                          struct ieee80211_low_level_stats *stats)
2579 {
2580         struct b43_wl *wl = hw_to_b43_wl(hw);
2581         unsigned long flags;
2582
2583         spin_lock_irqsave(&wl->irq_lock, flags);
2584         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2585         spin_unlock_irqrestore(&wl->irq_lock, flags);
2586
2587         return 0;
2588 }
2589
2590 static const char *phymode_to_string(unsigned int phymode)
2591 {
2592         switch (phymode) {
2593         case B43_PHYMODE_A:
2594                 return "A";
2595         case B43_PHYMODE_B:
2596                 return "B";
2597         case B43_PHYMODE_G:
2598                 return "G";
2599         default:
2600                 B43_WARN_ON(1);
2601         }
2602         return "";
2603 }
2604
2605 static int find_wldev_for_phymode(struct b43_wl *wl,
2606                                   unsigned int phymode,
2607                                   struct b43_wldev **dev, bool * gmode)
2608 {
2609         struct b43_wldev *d;
2610
2611         list_for_each_entry(d, &wl->devlist, list) {
2612                 if (d->phy.possible_phymodes & phymode) {
2613                         /* Ok, this device supports the PHY-mode.
2614                          * Now figure out how the gmode bit has to be
2615                          * set to support it. */
2616                         if (phymode == B43_PHYMODE_A)
2617                                 *gmode = 0;
2618                         else
2619                                 *gmode = 1;
2620                         *dev = d;
2621
2622                         return 0;
2623                 }
2624         }
2625
2626         return -ESRCH;
2627 }
2628
2629 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2630 {
2631         struct ssb_device *sdev = dev->dev;
2632         u32 tmslow;
2633
2634         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2635         tmslow &= ~B43_TMSLOW_GMODE;
2636         tmslow |= B43_TMSLOW_PHYRESET;
2637         tmslow |= SSB_TMSLOW_FGC;
2638         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2639         msleep(1);
2640
2641         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2642         tmslow &= ~SSB_TMSLOW_FGC;
2643         tmslow |= B43_TMSLOW_PHYRESET;
2644         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2645         msleep(1);
2646 }
2647
2648 /* Expects wl->mutex locked */
2649 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2650 {
2651         struct b43_wldev *up_dev;
2652         struct b43_wldev *down_dev;
2653         int err;
2654         bool gmode = 0;
2655         int prev_status;
2656
2657         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2658         if (err) {
2659                 b43err(wl, "Could not find a device for %s-PHY mode\n",
2660                        phymode_to_string(new_mode));
2661                 return err;
2662         }
2663         if ((up_dev == wl->current_dev) &&
2664             (!!wl->current_dev->phy.gmode == !!gmode)) {
2665                 /* This device is already running. */
2666                 return 0;
2667         }
2668         b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2669                phymode_to_string(new_mode));
2670         down_dev = wl->current_dev;
2671
2672         prev_status = b43_status(down_dev);
2673         /* Shutdown the currently running core. */
2674         if (prev_status >= B43_STAT_STARTED)
2675                 b43_wireless_core_stop(down_dev);
2676         if (prev_status >= B43_STAT_INITIALIZED)
2677                 b43_wireless_core_exit(down_dev);
2678
2679         if (down_dev != up_dev) {
2680                 /* We switch to a different core, so we put PHY into
2681                  * RESET on the old core. */
2682                 b43_put_phy_into_reset(down_dev);
2683         }
2684
2685         /* Now start the new core. */
2686         up_dev->phy.gmode = gmode;
2687         if (prev_status >= B43_STAT_INITIALIZED) {
2688                 err = b43_wireless_core_init(up_dev);
2689                 if (err) {
2690                         b43err(wl, "Fatal: Could not initialize device for "
2691                                "newly selected %s-PHY mode\n",
2692                                phymode_to_string(new_mode));
2693                         goto init_failure;
2694                 }
2695         }
2696         if (prev_status >= B43_STAT_STARTED) {
2697                 err = b43_wireless_core_start(up_dev);
2698                 if (err) {
2699                         b43err(wl, "Fatal: Coult not start device for "
2700                                "newly selected %s-PHY mode\n",
2701                                phymode_to_string(new_mode));
2702                         b43_wireless_core_exit(up_dev);
2703                         goto init_failure;
2704                 }
2705         }
2706         B43_WARN_ON(b43_status(up_dev) != prev_status);
2707
2708         wl->current_dev = up_dev;
2709
2710         return 0;
2711       init_failure:
2712         /* Whoops, failed to init the new core. No core is operating now. */
2713         wl->current_dev = NULL;
2714         return err;
2715 }
2716
2717 static int b43_antenna_from_ieee80211(u8 antenna)
2718 {
2719         switch (antenna) {
2720         case 0:         /* default/diversity */
2721                 return B43_ANTENNA_DEFAULT;
2722         case 1:         /* Antenna 0 */
2723                 return B43_ANTENNA0;
2724         case 2:         /* Antenna 1 */
2725                 return B43_ANTENNA1;
2726         default:
2727                 return B43_ANTENNA_DEFAULT;
2728         }
2729 }
2730
2731 static int b43_dev_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2732 {
2733         struct b43_wl *wl = hw_to_b43_wl(hw);
2734         struct b43_wldev *dev;
2735         struct b43_phy *phy;
2736         unsigned long flags;
2737         unsigned int new_phymode = 0xFFFF;
2738         int antenna_tx;
2739         int antenna_rx;
2740         int err = 0;
2741         u32 savedirqs;
2742
2743         antenna_tx = b43_antenna_from_ieee80211(conf->antenna_sel_tx);
2744         antenna_rx = b43_antenna_from_ieee80211(conf->antenna_sel_rx);
2745
2746         mutex_lock(&wl->mutex);
2747
2748         /* Switch the PHY mode (if necessary). */
2749         switch (conf->phymode) {
2750         case MODE_IEEE80211A:
2751                 new_phymode = B43_PHYMODE_A;
2752                 break;
2753         case MODE_IEEE80211B:
2754                 new_phymode = B43_PHYMODE_B;
2755                 break;
2756         case MODE_IEEE80211G:
2757                 new_phymode = B43_PHYMODE_G;
2758                 break;
2759         default:
2760                 B43_WARN_ON(1);
2761         }
2762         err = b43_switch_phymode(wl, new_phymode);
2763         if (err)
2764                 goto out_unlock_mutex;
2765         dev = wl->current_dev;
2766         phy = &dev->phy;
2767
2768         /* Disable IRQs while reconfiguring the device.
2769          * This makes it possible to drop the spinlock throughout
2770          * the reconfiguration process. */
2771         spin_lock_irqsave(&wl->irq_lock, flags);
2772         if (b43_status(dev) < B43_STAT_STARTED) {
2773                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2774                 goto out_unlock_mutex;
2775         }
2776         savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2777         spin_unlock_irqrestore(&wl->irq_lock, flags);
2778         b43_synchronize_irq(dev);
2779
2780         /* Switch to the requested channel.
2781          * The firmware takes care of races with the TX handler. */
2782         if (conf->channel_val != phy->channel)
2783                 b43_radio_selectchannel(dev, conf->channel_val, 0);
2784
2785         /* Enable/Disable ShortSlot timing. */
2786         if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2787             dev->short_slot) {
2788                 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2789                 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2790                         b43_short_slot_timing_enable(dev);
2791                 else
2792                         b43_short_slot_timing_disable(dev);
2793         }
2794
2795         /* Adjust the desired TX power level. */
2796         if (conf->power_level != 0) {
2797                 if (conf->power_level != phy->power_level) {
2798                         phy->power_level = conf->power_level;
2799                         b43_phy_xmitpower(dev);
2800                 }
2801         }
2802
2803         /* Antennas for RX and management frame TX. */
2804         b43_mgmtframe_txantenna(dev, antenna_tx);
2805         b43_set_rx_antenna(dev, antenna_rx);
2806
2807         /* Update templates for AP mode. */
2808         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2809                 b43_set_beacon_int(dev, conf->beacon_int);
2810
2811         if (!!conf->radio_enabled != phy->radio_on) {
2812                 if (conf->radio_enabled) {
2813                         b43_radio_turn_on(dev);
2814                         b43info(dev->wl, "Radio turned on by software\n");
2815                         if (!dev->radio_hw_enable) {
2816                                 b43info(dev->wl, "The hardware RF-kill button "
2817                                         "still turns the radio physically off. "
2818                                         "Press the button to turn it on.\n");
2819                         }
2820                 } else {
2821                         b43_radio_turn_off(dev, 0);
2822                         b43info(dev->wl, "Radio turned off by software\n");
2823                 }
2824         }
2825
2826         spin_lock_irqsave(&wl->irq_lock, flags);
2827         b43_interrupt_enable(dev, savedirqs);
2828         mmiowb();
2829         spin_unlock_irqrestore(&wl->irq_lock, flags);
2830       out_unlock_mutex:
2831         mutex_unlock(&wl->mutex);
2832
2833         return err;
2834 }
2835
2836 static int b43_dev_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2837                            const u8 *local_addr, const u8 *addr,
2838                            struct ieee80211_key_conf *key)
2839 {
2840         struct b43_wl *wl = hw_to_b43_wl(hw);
2841         struct b43_wldev *dev = wl->current_dev;
2842         unsigned long flags;
2843         u8 algorithm;
2844         u8 index;
2845         int err = -EINVAL;
2846         DECLARE_MAC_BUF(mac);
2847
2848         if (modparam_nohwcrypt)
2849                 return -ENOSPC; /* User disabled HW-crypto */
2850
2851         if (!dev)
2852                 return -ENODEV;
2853         switch (key->alg) {
2854         case ALG_NONE:
2855                 algorithm = B43_SEC_ALGO_NONE;
2856                 break;
2857         case ALG_WEP:
2858                 if (key->keylen == 5)
2859                         algorithm = B43_SEC_ALGO_WEP40;
2860                 else
2861                         algorithm = B43_SEC_ALGO_WEP104;
2862                 break;
2863         case ALG_TKIP:
2864                 algorithm = B43_SEC_ALGO_TKIP;
2865                 break;
2866         case ALG_CCMP:
2867                 algorithm = B43_SEC_ALGO_AES;
2868                 break;
2869         default:
2870                 B43_WARN_ON(1);
2871                 goto out;
2872         }
2873
2874         index = (u8) (key->keyidx);
2875         if (index > 3)
2876                 goto out;
2877
2878         mutex_lock(&wl->mutex);
2879         spin_lock_irqsave(&wl->irq_lock, flags);
2880
2881         if (b43_status(dev) < B43_STAT_INITIALIZED) {
2882                 err = -ENODEV;
2883                 goto out_unlock;
2884         }
2885
2886         switch (cmd) {
2887         case SET_KEY:
2888                 if (algorithm == B43_SEC_ALGO_TKIP) {
2889                         /* FIXME: No TKIP hardware encryption for now. */
2890                         err = -EOPNOTSUPP;
2891                         goto out_unlock;
2892                 }
2893
2894                 if (is_broadcast_ether_addr(addr)) {
2895                         /* addr is FF:FF:FF:FF:FF:FF for default keys */
2896                         err = b43_key_write(dev, index, algorithm,
2897                                             key->key, key->keylen, NULL, key);
2898                 } else {
2899                         /*
2900                          * either pairwise key or address is 00:00:00:00:00:00
2901                          * for transmit-only keys
2902                          */
2903                         err = b43_key_write(dev, -1, algorithm,
2904                                             key->key, key->keylen, addr, key);
2905                 }
2906                 if (err)
2907                         goto out_unlock;
2908
2909                 if (algorithm == B43_SEC_ALGO_WEP40 ||
2910                     algorithm == B43_SEC_ALGO_WEP104) {
2911                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2912                 } else {
2913                         b43_hf_write(dev,
2914                                      b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2915                 }
2916                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2917                 break;
2918         case DISABLE_KEY: {
2919                 err = b43_key_clear(dev, key->hw_key_idx);
2920                 if (err)
2921                         goto out_unlock;
2922                 break;
2923         }
2924         default:
2925                 B43_WARN_ON(1);
2926         }
2927 out_unlock:
2928         spin_unlock_irqrestore(&wl->irq_lock, flags);
2929         mutex_unlock(&wl->mutex);
2930 out:
2931         if (!err) {
2932                 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2933                        "mac: %s\n",
2934                        cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2935                        print_mac(mac, addr));
2936         }
2937         return err;
2938 }
2939
2940 static void b43_configure_filter(struct ieee80211_hw *hw,
2941                                  unsigned int changed, unsigned int *fflags,
2942                                  int mc_count, struct dev_addr_list *mc_list)
2943 {
2944         struct b43_wl *wl = hw_to_b43_wl(hw);
2945         struct b43_wldev *dev = wl->current_dev;
2946         unsigned long flags;
2947
2948         if (!dev) {
2949                 *fflags = 0;
2950                 return;
2951         }
2952
2953         spin_lock_irqsave(&wl->irq_lock, flags);
2954         *fflags &= FIF_PROMISC_IN_BSS |
2955                   FIF_ALLMULTI |
2956                   FIF_FCSFAIL |
2957                   FIF_PLCPFAIL |
2958                   FIF_CONTROL |
2959                   FIF_OTHER_BSS |
2960                   FIF_BCN_PRBRESP_PROMISC;
2961
2962         changed &= FIF_PROMISC_IN_BSS |
2963                    FIF_ALLMULTI |
2964                    FIF_FCSFAIL |
2965                    FIF_PLCPFAIL |
2966                    FIF_CONTROL |
2967                    FIF_OTHER_BSS |
2968                    FIF_BCN_PRBRESP_PROMISC;
2969
2970         wl->filter_flags = *fflags;
2971
2972         if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2973                 b43_adjust_opmode(dev);
2974         spin_unlock_irqrestore(&wl->irq_lock, flags);
2975 }
2976
2977 static int b43_config_interface(struct ieee80211_hw *hw,
2978                                 int if_id, struct ieee80211_if_conf *conf)
2979 {
2980         struct b43_wl *wl = hw_to_b43_wl(hw);
2981         struct b43_wldev *dev = wl->current_dev;
2982         unsigned long flags;
2983
2984         if (!dev)
2985                 return -ENODEV;
2986         mutex_lock(&wl->mutex);
2987         spin_lock_irqsave(&wl->irq_lock, flags);
2988         B43_WARN_ON(wl->if_id != if_id);
2989         if (conf->bssid)
2990                 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2991         else
2992                 memset(wl->bssid, 0, ETH_ALEN);
2993         if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2994                 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2995                         B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2996                         b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2997                         if (conf->beacon)
2998                                 b43_refresh_templates(dev, conf->beacon);
2999                 }
3000                 b43_write_mac_bssid_templates(dev);
3001         }
3002         spin_unlock_irqrestore(&wl->irq_lock, flags);
3003         mutex_unlock(&wl->mutex);
3004
3005         return 0;
3006 }
3007
3008 /* Locking: wl->mutex */
3009 static void b43_wireless_core_stop(struct b43_wldev *dev)
3010 {
3011         struct b43_wl *wl = dev->wl;
3012         unsigned long flags;
3013
3014         if (b43_status(dev) < B43_STAT_STARTED)
3015                 return;
3016         b43_set_status(dev, B43_STAT_INITIALIZED);
3017
3018         mutex_unlock(&wl->mutex);
3019         /* Must unlock as it would otherwise deadlock. No races here.
3020          * Cancel the possibly running self-rearming periodic work. */
3021         cancel_delayed_work_sync(&dev->periodic_work);
3022         mutex_lock(&wl->mutex);
3023
3024         ieee80211_stop_queues(wl->hw);  //FIXME this could cause a deadlock, as mac80211 seems buggy.
3025
3026         /* Disable and sync interrupts. */
3027         spin_lock_irqsave(&wl->irq_lock, flags);
3028         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3029         b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3030         spin_unlock_irqrestore(&wl->irq_lock, flags);
3031         b43_synchronize_irq(dev);
3032
3033         b43_mac_suspend(dev);
3034         free_irq(dev->dev->irq, dev);
3035         b43dbg(wl, "Wireless interface stopped\n");
3036 }
3037
3038 /* Locking: wl->mutex */
3039 static int b43_wireless_core_start(struct b43_wldev *dev)
3040 {
3041         int err;
3042
3043         B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3044
3045         drain_txstatus_queue(dev);
3046         err = request_irq(dev->dev->irq, b43_interrupt_handler,
3047                           IRQF_SHARED, KBUILD_MODNAME, dev);
3048         if (err) {
3049                 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3050                 goto out;
3051         }
3052
3053         /* We are ready to run. */
3054         b43_set_status(dev, B43_STAT_STARTED);
3055
3056         /* Start data flow (TX/RX). */
3057         b43_mac_enable(dev);
3058         b43_interrupt_enable(dev, dev->irq_savedstate);
3059         ieee80211_start_queues(dev->wl->hw);
3060
3061         /* Start maintainance work */
3062         b43_periodic_tasks_setup(dev);
3063
3064         b43dbg(dev->wl, "Wireless interface started\n");
3065       out:
3066         return err;
3067 }
3068
3069 /* Get PHY and RADIO versioning numbers */
3070 static int b43_phy_versioning(struct b43_wldev *dev)
3071 {
3072         struct b43_phy *phy = &dev->phy;
3073         u32 tmp;
3074         u8 analog_type;
3075         u8 phy_type;
3076         u8 phy_rev;
3077         u16 radio_manuf;
3078         u16 radio_ver;
3079         u16 radio_rev;
3080         int unsupported = 0;
3081
3082         /* Get PHY versioning */
3083         tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3084         analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3085         phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3086         phy_rev = (tmp & B43_PHYVER_VERSION);
3087         switch (phy_type) {
3088         case B43_PHYTYPE_A:
3089                 if (phy_rev >= 4)
3090                         unsupported = 1;
3091                 break;
3092         case B43_PHYTYPE_B:
3093                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3094                     && phy_rev != 7)
3095                         unsupported = 1;
3096                 break;
3097         case B43_PHYTYPE_G:
3098                 if (phy_rev > 8)
3099                         unsupported = 1;
3100                 break;
3101         default:
3102                 unsupported = 1;
3103         };
3104         if (unsupported) {
3105                 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3106                        "(Analog %u, Type %u, Revision %u)\n",
3107                        analog_type, phy_type, phy_rev);
3108                 return -EOPNOTSUPP;
3109         }
3110         b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3111                analog_type, phy_type, phy_rev);
3112
3113         /* Get RADIO versioning */
3114         if (dev->dev->bus->chip_id == 0x4317) {
3115                 if (dev->dev->bus->chip_rev == 0)
3116                         tmp = 0x3205017F;
3117                 else if (dev->dev->bus->chip_rev == 1)
3118                         tmp = 0x4205017F;
3119                 else
3120                         tmp = 0x5205017F;
3121         } else {
3122                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3123                 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3124                 tmp <<= 16;
3125                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3126                 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3127         }
3128         radio_manuf = (tmp & 0x00000FFF);
3129         radio_ver = (tmp & 0x0FFFF000) >> 12;
3130         radio_rev = (tmp & 0xF0000000) >> 28;
3131         switch (phy_type) {
3132         case B43_PHYTYPE_A:
3133                 if (radio_ver != 0x2060)
3134                         unsupported = 1;
3135                 if (radio_rev != 1)
3136                         unsupported = 1;
3137                 if (radio_manuf != 0x17F)
3138                         unsupported = 1;
3139                 break;
3140         case B43_PHYTYPE_B:
3141                 if ((radio_ver & 0xFFF0) != 0x2050)
3142                         unsupported = 1;
3143                 break;
3144         case B43_PHYTYPE_G:
3145                 if (radio_ver != 0x2050)
3146                         unsupported = 1;
3147                 break;
3148         default:
3149                 B43_WARN_ON(1);
3150         }
3151         if (unsupported) {
3152                 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3153                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3154                        radio_manuf, radio_ver, radio_rev);
3155                 return -EOPNOTSUPP;
3156         }
3157         b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3158                radio_manuf, radio_ver, radio_rev);
3159
3160         phy->radio_manuf = radio_manuf;
3161         phy->radio_ver = radio_ver;
3162         phy->radio_rev = radio_rev;
3163
3164         phy->analog = analog_type;
3165         phy->type = phy_type;
3166         phy->rev = phy_rev;
3167
3168         return 0;
3169 }
3170
3171 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3172                                       struct b43_phy *phy)
3173 {
3174         struct b43_txpower_lo_control *lo;
3175         int i;
3176
3177         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3178         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3179
3180         /* Flags */
3181         phy->locked = 0;
3182
3183         phy->aci_enable = 0;
3184         phy->aci_wlan_automatic = 0;
3185         phy->aci_hw_rssi = 0;
3186
3187         phy->radio_off_context.valid = 0;
3188
3189         lo = phy->lo_control;
3190         if (lo) {
3191                 memset(lo, 0, sizeof(*(phy->lo_control)));
3192                 lo->rebuild = 1;
3193                 lo->tx_bias = 0xFF;
3194         }
3195         phy->max_lb_gain = 0;
3196         phy->trsw_rx_gain = 0;
3197         phy->txpwr_offset = 0;
3198
3199         /* NRSSI */
3200         phy->nrssislope = 0;
3201         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3202                 phy->nrssi[i] = -1000;
3203         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3204                 phy->nrssi_lt[i] = i;
3205
3206         phy->lofcal = 0xFFFF;
3207         phy->initval = 0xFFFF;
3208
3209         spin_lock_init(&phy->lock);
3210         phy->interfmode = B43_INTERFMODE_NONE;
3211         phy->channel = 0xFF;
3212
3213         phy->hardware_power_control = !!modparam_hwpctl;
3214 }
3215
3216 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3217 {
3218         /* Flags */
3219         dev->reg124_set_0x4 = 0;
3220         /* Assume the radio is enabled. If it's not enabled, the state will
3221          * immediately get fixed on the first periodic work run. */
3222         dev->radio_hw_enable = 1;
3223
3224         /* Stats */
3225         memset(&dev->stats, 0, sizeof(dev->stats));
3226
3227         setup_struct_phy_for_init(dev, &dev->phy);
3228
3229         /* IRQ related flags */
3230         dev->irq_reason = 0;
3231         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3232         dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3233
3234         dev->mac_suspended = 1;
3235
3236         /* Noise calculation context */
3237         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3238 }
3239
3240 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3241 {
3242         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3243         u32 hf;
3244
3245         if (!(sprom->r1.boardflags_lo & B43_BFL_BTCOEXIST))
3246                 return;
3247         if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3248                 return;
3249
3250         hf = b43_hf_read(dev);
3251         if (sprom->r1.boardflags_lo & B43_BFL_BTCMOD)
3252                 hf |= B43_HF_BTCOEXALT;
3253         else
3254                 hf |= B43_HF_BTCOEX;
3255         b43_hf_write(dev, hf);
3256         //TODO
3257 }
3258
3259 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3260 {                               //TODO
3261 }
3262
3263 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3264 {
3265 #ifdef CONFIG_SSB_DRIVER_PCICORE
3266         struct ssb_bus *bus = dev->dev->bus;
3267         u32 tmp;
3268
3269         if (bus->pcicore.dev &&
3270             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3271             bus->pcicore.dev->id.revision <= 5) {
3272                 /* IMCFGLO timeouts workaround. */
3273                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3274                 tmp &= ~SSB_IMCFGLO_REQTO;
3275                 tmp &= ~SSB_IMCFGLO_SERTO;
3276                 switch (bus->bustype) {
3277                 case SSB_BUSTYPE_PCI:
3278                 case SSB_BUSTYPE_PCMCIA:
3279                         tmp |= 0x32;
3280                         break;
3281                 case SSB_BUSTYPE_SSB:
3282                         tmp |= 0x53;
3283                         break;
3284                 }
3285                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3286         }
3287 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3288 }
3289
3290 /* Shutdown a wireless core */
3291 /* Locking: wl->mutex */
3292 static void b43_wireless_core_exit(struct b43_wldev *dev)
3293 {
3294         struct b43_phy *phy = &dev->phy;
3295
3296         B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3297         if (b43_status(dev) != B43_STAT_INITIALIZED)
3298                 return;
3299         b43_set_status(dev, B43_STAT_UNINIT);
3300
3301         mutex_unlock(&dev->wl->mutex);
3302         b43_rfkill_exit(dev);
3303         mutex_lock(&dev->wl->mutex);
3304
3305         b43_rng_exit(dev->wl);
3306         b43_pio_free(dev);
3307         b43_dma_free(dev);
3308         b43_chip_exit(dev);
3309         b43_radio_turn_off(dev, 1);
3310         b43_switch_analog(dev, 0);
3311         if (phy->dyn_tssi_tbl)
3312                 kfree(phy->tssi2dbm);
3313         kfree(phy->lo_control);
3314         phy->lo_control = NULL;
3315         ssb_device_disable(dev->dev, 0);
3316         ssb_bus_may_powerdown(dev->dev->bus);
3317 }
3318
3319 /* Initialize a wireless core */
3320 static int b43_wireless_core_init(struct b43_wldev *dev)
3321 {
3322         struct b43_wl *wl = dev->wl;
3323         struct ssb_bus *bus = dev->dev->bus;
3324         struct ssb_sprom *sprom = &bus->sprom;
3325         struct b43_phy *phy = &dev->phy;
3326         int err;
3327         u32 hf, tmp;
3328
3329         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3330
3331         err = ssb_bus_powerup(bus, 0);
3332         if (err)
3333                 goto out;
3334         if (!ssb_device_is_enabled(dev->dev)) {
3335                 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3336                 b43_wireless_core_reset(dev, tmp);
3337         }
3338
3339         if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3340                 phy->lo_control =
3341                     kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3342                 if (!phy->lo_control) {
3343                         err = -ENOMEM;
3344                         goto err_busdown;
3345                 }
3346         }
3347         setup_struct_wldev_for_init(dev);
3348
3349         err = b43_phy_init_tssi2dbm_table(dev);
3350         if (err)
3351                 goto err_kfree_lo_control;
3352
3353         /* Enable IRQ routing to this device. */
3354         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3355
3356         b43_imcfglo_timeouts_workaround(dev);
3357         b43_bluetooth_coext_disable(dev);
3358         b43_phy_early_init(dev);
3359         err = b43_chip_init(dev);
3360         if (err)
3361                 goto err_kfree_tssitbl;
3362         b43_shm_write16(dev, B43_SHM_SHARED,
3363                         B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3364         hf = b43_hf_read(dev);
3365         if (phy->type == B43_PHYTYPE_G) {
3366                 hf |= B43_HF_SYMW;
3367                 if (phy->rev == 1)
3368                         hf |= B43_HF_GDCW;
3369                 if (sprom->r1.boardflags_lo & B43_BFL_PACTRL)
3370                         hf |= B43_HF_OFDMPABOOST;
3371         } else if (phy->type == B43_PHYTYPE_B) {
3372                 hf |= B43_HF_SYMW;
3373                 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3374                         hf &= ~B43_HF_GDCW;
3375         }
3376         b43_hf_write(dev, hf);
3377
3378         /* Short/Long Retry Limit.
3379          * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
3380          * the chip-internal counter.
3381          */
3382         tmp = limit_value(modparam_short_retry, 0, 0xF);
3383         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, tmp);
3384         tmp = limit_value(modparam_long_retry, 0, 0xF);
3385         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, tmp);
3386
3387         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3388         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3389
3390         /* Disable sending probe responses from firmware.
3391          * Setting the MaxTime to one usec will always trigger
3392          * a timeout, so we never send any probe resp.
3393          * A timeout of zero is infinite. */
3394         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3395
3396         b43_rate_memory_init(dev);
3397
3398         /* Minimum Contention Window */
3399         if (phy->type == B43_PHYTYPE_B) {
3400                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3401         } else {
3402                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3403         }
3404         /* Maximum Contention Window */
3405         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3406
3407         do {
3408                 if (b43_using_pio(dev)) {
3409                         err = b43_pio_init(dev);
3410                 } else {
3411                         err = b43_dma_init(dev);
3412                         if (!err)
3413                                 b43_qos_init(dev);
3414                 }
3415         } while (err == -EAGAIN);
3416         if (err)
3417                 goto err_chip_exit;
3418
3419 //FIXME
3420 #if 1
3421         b43_write16(dev, 0x0612, 0x0050);
3422         b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3423         b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3424 #endif
3425
3426         b43_bluetooth_coext_enable(dev);
3427
3428         ssb_bus_powerup(bus, 1);        /* Enable dynamic PCTL */
3429         memset(wl->bssid, 0, ETH_ALEN);
3430         memset(wl->mac_addr, 0, ETH_ALEN);
3431         b43_upload_card_macaddress(dev);
3432         b43_security_init(dev);
3433         b43_rfkill_init(dev);
3434         b43_rng_init(wl);
3435
3436         b43_set_status(dev, B43_STAT_INITIALIZED);
3437
3438       out:
3439         return err;
3440
3441       err_chip_exit:
3442         b43_chip_exit(dev);
3443       err_kfree_tssitbl:
3444         if (phy->dyn_tssi_tbl)
3445                 kfree(phy->tssi2dbm);
3446       err_kfree_lo_control:
3447         kfree(phy->lo_control);
3448         phy->lo_control = NULL;
3449       err_busdown:
3450         ssb_bus_may_powerdown(bus);
3451         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3452         return err;
3453 }
3454
3455 static int b43_add_interface(struct ieee80211_hw *hw,
3456                              struct ieee80211_if_init_conf *conf)
3457 {
3458         struct b43_wl *wl = hw_to_b43_wl(hw);
3459         struct b43_wldev *dev;
3460         unsigned long flags;
3461         int err = -EOPNOTSUPP;
3462
3463         /* TODO: allow WDS/AP devices to coexist */
3464
3465         if (conf->type != IEEE80211_IF_TYPE_AP &&
3466             conf->type != IEEE80211_IF_TYPE_STA &&
3467             conf->type != IEEE80211_IF_TYPE_WDS &&
3468             conf->type != IEEE80211_IF_TYPE_IBSS)
3469                 return -EOPNOTSUPP;
3470
3471         mutex_lock(&wl->mutex);
3472         if (wl->operating)
3473                 goto out_mutex_unlock;
3474
3475         b43dbg(wl, "Adding Interface type %d\n", conf->type);
3476
3477         dev = wl->current_dev;
3478         wl->operating = 1;
3479         wl->if_id = conf->if_id;
3480         wl->if_type = conf->type;
3481         memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3482
3483         spin_lock_irqsave(&wl->irq_lock, flags);
3484         b43_adjust_opmode(dev);
3485         b43_upload_card_macaddress(dev);
3486         spin_unlock_irqrestore(&wl->irq_lock, flags);
3487
3488         err = 0;
3489  out_mutex_unlock:
3490         mutex_unlock(&wl->mutex);
3491
3492         return err;
3493 }
3494
3495 static void b43_remove_interface(struct ieee80211_hw *hw,
3496                                  struct ieee80211_if_init_conf *conf)
3497 {
3498         struct b43_wl *wl = hw_to_b43_wl(hw);
3499         struct b43_wldev *dev = wl->current_dev;
3500         unsigned long flags;
3501
3502         b43dbg(wl, "Removing Interface type %d\n", conf->type);
3503
3504         mutex_lock(&wl->mutex);
3505
3506         B43_WARN_ON(!wl->operating);
3507         B43_WARN_ON(wl->if_id != conf->if_id);
3508
3509         wl->operating = 0;
3510
3511         spin_lock_irqsave(&wl->irq_lock, flags);
3512         b43_adjust_opmode(dev);
3513         memset(wl->mac_addr, 0, ETH_ALEN);
3514         b43_upload_card_macaddress(dev);
3515         spin_unlock_irqrestore(&wl->irq_lock, flags);
3516
3517         mutex_unlock(&wl->mutex);
3518 }
3519
3520 static int b43_start(struct ieee80211_hw *hw)
3521 {
3522         struct b43_wl *wl = hw_to_b43_wl(hw);
3523         struct b43_wldev *dev = wl->current_dev;
3524         int did_init = 0;
3525         int err;
3526
3527         mutex_lock(&wl->mutex);
3528
3529         if (b43_status(dev) < B43_STAT_INITIALIZED) {
3530                 err = b43_wireless_core_init(dev);
3531                 if (err)
3532                         goto out_mutex_unlock;
3533                 did_init = 1;
3534         }
3535
3536         if (b43_status(dev) < B43_STAT_STARTED) {
3537                 err = b43_wireless_core_start(dev);
3538                 if (err) {
3539                         if (did_init)
3540                                 b43_wireless_core_exit(dev);
3541                         goto out_mutex_unlock;
3542                 }
3543         }
3544
3545  out_mutex_unlock:
3546         mutex_unlock(&wl->mutex);
3547
3548         return err;
3549 }
3550
3551 void b43_stop(struct ieee80211_hw *hw)
3552 {
3553         struct b43_wl *wl = hw_to_b43_wl(hw);
3554         struct b43_wldev *dev = wl->current_dev;
3555
3556         mutex_lock(&wl->mutex);
3557         if (b43_status(dev) >= B43_STAT_STARTED)
3558                 b43_wireless_core_stop(dev);
3559         b43_wireless_core_exit(dev);
3560         mutex_unlock(&wl->mutex);
3561 }
3562
3563 static const struct ieee80211_ops b43_hw_ops = {
3564         .tx = b43_tx,
3565         .conf_tx = b43_conf_tx,
3566         .add_interface = b43_add_interface,
3567         .remove_interface = b43_remove_interface,
3568         .config = b43_dev_config,
3569         .config_interface = b43_config_interface,
3570         .configure_filter = b43_configure_filter,
3571         .set_key = b43_dev_set_key,
3572         .get_stats = b43_get_stats,
3573         .get_tx_stats = b43_get_tx_stats,
3574         .start = b43_start,
3575         .stop = b43_stop,
3576 };
3577
3578 /* Hard-reset the chip. Do not call this directly.
3579  * Use b43_controller_restart()
3580  */
3581 static void b43_chip_reset(struct work_struct *work)
3582 {
3583         struct b43_wldev *dev =
3584             container_of(work, struct b43_wldev, restart_work);
3585         struct b43_wl *wl = dev->wl;
3586         int err = 0;
3587         int prev_status;
3588
3589         mutex_lock(&wl->mutex);
3590
3591         prev_status = b43_status(dev);
3592         /* Bring the device down... */
3593         if (prev_status >= B43_STAT_STARTED)
3594                 b43_wireless_core_stop(dev);
3595         if (prev_status >= B43_STAT_INITIALIZED)
3596                 b43_wireless_core_exit(dev);
3597
3598         /* ...and up again. */
3599         if (prev_status >= B43_STAT_INITIALIZED) {
3600                 err = b43_wireless_core_init(dev);
3601                 if (err)
3602                         goto out;
3603         }
3604         if (prev_status >= B43_STAT_STARTED) {
3605                 err = b43_wireless_core_start(dev);
3606                 if (err) {
3607                         b43_wireless_core_exit(dev);
3608                         goto out;
3609                 }
3610         }
3611       out:
3612         mutex_unlock(&wl->mutex);
3613         if (err)
3614                 b43err(wl, "Controller restart FAILED\n");
3615         else
3616                 b43info(wl, "Controller restarted\n");
3617 }
3618
3619 static int b43_setup_modes(struct b43_wldev *dev,
3620                            int have_aphy, int have_bphy, int have_gphy)
3621 {
3622         struct ieee80211_hw *hw = dev->wl->hw;
3623         struct ieee80211_hw_mode *mode;
3624         struct b43_phy *phy = &dev->phy;
3625         int cnt = 0;
3626         int err;
3627
3628 /*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3629         have_aphy = 0;
3630
3631         phy->possible_phymodes = 0;
3632         for (; 1; cnt++) {
3633                 if (have_aphy) {
3634                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3635                         mode = &phy->hwmodes[cnt];
3636
3637                         mode->mode = MODE_IEEE80211A;
3638                         mode->num_channels = b43_a_chantable_size;
3639                         mode->channels = b43_a_chantable;
3640                         mode->num_rates = b43_a_ratetable_size;
3641                         mode->rates = b43_a_ratetable;
3642                         err = ieee80211_register_hwmode(hw, mode);
3643                         if (err)
3644                                 return err;
3645
3646                         phy->possible_phymodes |= B43_PHYMODE_A;
3647                         have_aphy = 0;
3648                         continue;
3649                 }
3650                 if (have_bphy) {
3651                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3652                         mode = &phy->hwmodes[cnt];
3653
3654                         mode->mode = MODE_IEEE80211B;
3655                         mode->num_channels = b43_bg_chantable_size;
3656                         mode->channels = b43_bg_chantable;
3657                         mode->num_rates = b43_b_ratetable_size;
3658                         mode->rates = b43_b_ratetable;
3659                         err = ieee80211_register_hwmode(hw, mode);
3660                         if (err)
3661                                 return err;
3662
3663                         phy->possible_phymodes |= B43_PHYMODE_B;
3664                         have_bphy = 0;
3665                         continue;
3666                 }
3667                 if (have_gphy) {
3668                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3669                         mode = &phy->hwmodes[cnt];
3670
3671                         mode->mode = MODE_IEEE80211G;
3672                         mode->num_channels = b43_bg_chantable_size;
3673                         mode->channels = b43_bg_chantable;
3674                         mode->num_rates = b43_g_ratetable_size;
3675                         mode->rates = b43_g_ratetable;
3676                         err = ieee80211_register_hwmode(hw, mode);
3677                         if (err)
3678                                 return err;
3679
3680                         phy->possible_phymodes |= B43_PHYMODE_G;
3681                         have_gphy = 0;
3682                         continue;
3683                 }
3684                 break;
3685         }
3686
3687         return 0;
3688 }
3689
3690 static void b43_wireless_core_detach(struct b43_wldev *dev)
3691 {
3692         b43_rfkill_free(dev);
3693         /* We release firmware that late to not be required to re-request
3694          * is all the time when we reinit the core. */
3695         b43_release_firmware(dev);
3696 }
3697
3698 static int b43_wireless_core_attach(struct b43_wldev *dev)
3699 {
3700         struct b43_wl *wl = dev->wl;
3701         struct ssb_bus *bus = dev->dev->bus;
3702         struct pci_dev *pdev = bus->host_pci;
3703         int err;
3704         int have_aphy = 0, have_bphy = 0, have_gphy = 0;
3705         u32 tmp;
3706
3707         /* Do NOT do any device initialization here.
3708          * Do it in wireless_core_init() instead.
3709          * This function is for gathering basic information about the HW, only.
3710          * Also some structs may be set up here. But most likely you want to have
3711          * that in core_init(), too.
3712          */
3713
3714         err = ssb_bus_powerup(bus, 0);
3715         if (err) {
3716                 b43err(wl, "Bus powerup failed\n");
3717                 goto out;
3718         }
3719         /* Get the PHY type. */
3720         if (dev->dev->id.revision >= 5) {
3721                 u32 tmshigh;
3722
3723                 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3724                 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY);
3725                 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY);
3726                 if (!have_aphy && !have_gphy)
3727                         have_bphy = 1;
3728         } else if (dev->dev->id.revision == 4) {
3729                 have_gphy = 1;
3730                 have_aphy = 1;
3731         } else
3732                 have_bphy = 1;
3733
3734         dev->phy.gmode = (have_gphy || have_bphy);
3735         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3736         b43_wireless_core_reset(dev, tmp);
3737
3738         err = b43_phy_versioning(dev);
3739         if (err)
3740                 goto err_powerdown;
3741         /* Check if this device supports multiband. */
3742         if (!pdev ||
3743             (pdev->device != 0x4312 &&
3744              pdev->device != 0x4319 && pdev->device != 0x4324)) {
3745                 /* No multiband support. */
3746                 have_aphy = 0;
3747                 have_bphy = 0;
3748                 have_gphy = 0;
3749                 switch (dev->phy.type) {
3750                 case B43_PHYTYPE_A:
3751                         have_aphy = 1;
3752                         break;
3753                 case B43_PHYTYPE_B:
3754                         have_bphy = 1;
3755                         break;
3756                 case B43_PHYTYPE_G:
3757                         have_gphy = 1;
3758                         break;
3759                 default:
3760                         B43_WARN_ON(1);
3761                 }
3762         }
3763         dev->phy.gmode = (have_gphy || have_bphy);
3764         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3765         b43_wireless_core_reset(dev, tmp);
3766
3767         err = b43_validate_chipaccess(dev);
3768         if (err)
3769                 goto err_powerdown;
3770         err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy);
3771         if (err)
3772                 goto err_powerdown;
3773
3774         /* Now set some default "current_dev" */
3775         if (!wl->current_dev)
3776                 wl->current_dev = dev;
3777         INIT_WORK(&dev->restart_work, b43_chip_reset);
3778         b43_rfkill_alloc(dev);
3779
3780         b43_radio_turn_off(dev, 1);
3781         b43_switch_analog(dev, 0);
3782         ssb_device_disable(dev->dev, 0);
3783         ssb_bus_may_powerdown(bus);
3784
3785 out:
3786         return err;
3787
3788 err_powerdown:
3789         ssb_bus_may_powerdown(bus);
3790         return err;
3791 }
3792
3793 static void b43_one_core_detach(struct ssb_device *dev)
3794 {
3795         struct b43_wldev *wldev;
3796         struct b43_wl *wl;
3797
3798         wldev = ssb_get_drvdata(dev);
3799         wl = wldev->wl;
3800         cancel_work_sync(&wldev->restart_work);
3801         b43_debugfs_remove_device(wldev);
3802         b43_wireless_core_detach(wldev);
3803         list_del(&wldev->list);
3804         wl->nr_devs--;
3805         ssb_set_drvdata(dev, NULL);
3806         kfree(wldev);
3807 }
3808
3809 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3810 {
3811         struct b43_wldev *wldev;
3812         struct pci_dev *pdev;
3813         int err = -ENOMEM;
3814
3815         if (!list_empty(&wl->devlist)) {
3816                 /* We are not the first core on this chip. */
3817                 pdev = dev->bus->host_pci;
3818                 /* Only special chips support more than one wireless
3819                  * core, although some of the other chips have more than
3820                  * one wireless core as well. Check for this and
3821                  * bail out early.
3822                  */
3823                 if (!pdev ||
3824                     ((pdev->device != 0x4321) &&
3825                      (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3826                         b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3827                         return -ENODEV;
3828                 }
3829         }
3830
3831         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3832         if (!wldev)
3833                 goto out;
3834
3835         wldev->dev = dev;
3836         wldev->wl = wl;
3837         b43_set_status(wldev, B43_STAT_UNINIT);
3838         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3839         tasklet_init(&wldev->isr_tasklet,
3840                      (void (*)(unsigned long))b43_interrupt_tasklet,
3841                      (unsigned long)wldev);
3842         if (modparam_pio)
3843                 wldev->__using_pio = 1;
3844         INIT_LIST_HEAD(&wldev->list);
3845
3846         err = b43_wireless_core_attach(wldev);
3847         if (err)
3848                 goto err_kfree_wldev;
3849
3850         list_add(&wldev->list, &wl->devlist);
3851         wl->nr_devs++;
3852         ssb_set_drvdata(dev, wldev);
3853         b43_debugfs_add_device(wldev);
3854
3855       out:
3856         return err;
3857
3858       err_kfree_wldev:
3859         kfree(wldev);
3860         return err;
3861 }
3862
3863 static void b43_sprom_fixup(struct ssb_bus *bus)
3864 {
3865         /* boardflags workarounds */
3866         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3867             bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3868                 bus->sprom.r1.boardflags_lo |= B43_BFL_BTCOEXIST;
3869         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3870             bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3871                 bus->sprom.r1.boardflags_lo |= B43_BFL_PACTRL;
3872
3873         /* Handle case when gain is not set in sprom */
3874         if (bus->sprom.r1.antenna_gain_a == 0xFF)
3875                 bus->sprom.r1.antenna_gain_a = 2;
3876         if (bus->sprom.r1.antenna_gain_bg == 0xFF)
3877                 bus->sprom.r1.antenna_gain_bg = 2;
3878
3879         /* Convert Antennagain values to Q5.2 */
3880         bus->sprom.r1.antenna_gain_a <<= 2;
3881         bus->sprom.r1.antenna_gain_bg <<= 2;
3882 }
3883
3884 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3885 {
3886         struct ieee80211_hw *hw = wl->hw;
3887
3888         ssb_set_devtypedata(dev, NULL);
3889         ieee80211_free_hw(hw);
3890 }
3891
3892 static int b43_wireless_init(struct ssb_device *dev)
3893 {
3894         struct ssb_sprom *sprom = &dev->bus->sprom;
3895         struct ieee80211_hw *hw;
3896         struct b43_wl *wl;
3897         int err = -ENOMEM;
3898
3899         b43_sprom_fixup(dev->bus);
3900
3901         hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3902         if (!hw) {
3903                 b43err(NULL, "Could not allocate ieee80211 device\n");
3904                 goto out;
3905         }
3906
3907         /* fill hw info */
3908         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
3909         hw->max_signal = 100;
3910         hw->max_rssi = -110;
3911         hw->max_noise = -110;
3912         hw->queues = 1;         /* FIXME: hardware has more queues */
3913         SET_IEEE80211_DEV(hw, dev->dev);
3914         if (is_valid_ether_addr(sprom->r1.et1mac))
3915                 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.et1mac);
3916         else
3917                 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.il0mac);
3918
3919         /* Get and initialize struct b43_wl */
3920         wl = hw_to_b43_wl(hw);
3921         memset(wl, 0, sizeof(*wl));
3922         wl->hw = hw;
3923         spin_lock_init(&wl->irq_lock);
3924         spin_lock_init(&wl->leds_lock);
3925         mutex_init(&wl->mutex);
3926         INIT_LIST_HEAD(&wl->devlist);
3927
3928         ssb_set_devtypedata(dev, wl);
3929         b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3930         err = 0;
3931       out:
3932         return err;
3933 }
3934
3935 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3936 {
3937         struct b43_wl *wl;
3938         int err;
3939         int first = 0;
3940
3941         wl = ssb_get_devtypedata(dev);
3942         if (!wl) {
3943                 /* Probing the first core. Must setup common struct b43_wl */
3944                 first = 1;
3945                 err = b43_wireless_init(dev);
3946                 if (err)
3947                         goto out;
3948                 wl = ssb_get_devtypedata(dev);
3949                 B43_WARN_ON(!wl);
3950         }
3951         err = b43_one_core_attach(dev, wl);
3952         if (err)
3953                 goto err_wireless_exit;
3954
3955         if (first) {
3956                 err = ieee80211_register_hw(wl->hw);
3957                 if (err)
3958                         goto err_one_core_detach;
3959         }
3960
3961       out:
3962         return err;
3963
3964       err_one_core_detach:
3965         b43_one_core_detach(dev);
3966       err_wireless_exit:
3967         if (first)
3968                 b43_wireless_exit(dev, wl);
3969         return err;
3970 }
3971
3972 static void b43_remove(struct ssb_device *dev)
3973 {
3974         struct b43_wl *wl = ssb_get_devtypedata(dev);
3975         struct b43_wldev *wldev = ssb_get_drvdata(dev);
3976
3977         B43_WARN_ON(!wl);
3978         if (wl->current_dev == wldev)
3979                 ieee80211_unregister_hw(wl->hw);
3980
3981         b43_one_core_detach(dev);
3982
3983         if (list_empty(&wl->devlist)) {
3984                 /* Last core on the chip unregistered.
3985                  * We can destroy common struct b43_wl.
3986                  */
3987                 b43_wireless_exit(dev, wl);
3988         }
3989 }
3990
3991 /* Perform a hardware reset. This can be called from any context. */
3992 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
3993 {
3994         /* Must avoid requeueing, if we are in shutdown. */
3995         if (b43_status(dev) < B43_STAT_INITIALIZED)
3996                 return;
3997         b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
3998         queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3999 }
4000
4001 #ifdef CONFIG_PM
4002
4003 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4004 {
4005         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4006         struct b43_wl *wl = wldev->wl;
4007
4008         b43dbg(wl, "Suspending...\n");
4009
4010         mutex_lock(&wl->mutex);
4011         wldev->suspend_init_status = b43_status(wldev);
4012         if (wldev->suspend_init_status >= B43_STAT_STARTED)
4013                 b43_wireless_core_stop(wldev);
4014         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4015                 b43_wireless_core_exit(wldev);
4016         mutex_unlock(&wl->mutex);
4017
4018         b43dbg(wl, "Device suspended.\n");
4019
4020         return 0;
4021 }
4022
4023 static int b43_resume(struct ssb_device *dev)
4024 {
4025         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4026         struct b43_wl *wl = wldev->wl;
4027         int err = 0;
4028
4029         b43dbg(wl, "Resuming...\n");
4030
4031         mutex_lock(&wl->mutex);
4032         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4033                 err = b43_wireless_core_init(wldev);
4034                 if (err) {
4035                         b43err(wl, "Resume failed at core init\n");
4036                         goto out;
4037                 }
4038         }
4039         if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4040                 err = b43_wireless_core_start(wldev);
4041                 if (err) {
4042                         b43_wireless_core_exit(wldev);
4043                         b43err(wl, "Resume failed at core start\n");
4044                         goto out;
4045                 }
4046         }
4047         mutex_unlock(&wl->mutex);
4048
4049         b43dbg(wl, "Device resumed.\n");
4050       out:
4051         return err;
4052 }
4053
4054 #else /* CONFIG_PM */
4055 # define b43_suspend    NULL
4056 # define b43_resume     NULL
4057 #endif /* CONFIG_PM */
4058
4059 static struct ssb_driver b43_ssb_driver = {
4060         .name           = KBUILD_MODNAME,
4061         .id_table       = b43_ssb_tbl,
4062         .probe          = b43_probe,
4063         .remove         = b43_remove,
4064         .suspend        = b43_suspend,
4065         .resume         = b43_resume,
4066 };
4067
4068 static int __init b43_init(void)
4069 {
4070         int err;
4071
4072         b43_debugfs_init();
4073         err = b43_pcmcia_init();
4074         if (err)
4075                 goto err_dfs_exit;
4076         err = ssb_driver_register(&b43_ssb_driver);
4077         if (err)
4078                 goto err_pcmcia_exit;
4079
4080         return err;
4081
4082 err_pcmcia_exit:
4083         b43_pcmcia_exit();
4084 err_dfs_exit:
4085         b43_debugfs_exit();
4086         return err;
4087 }
4088
4089 static void __exit b43_exit(void)
4090 {
4091         ssb_driver_unregister(&b43_ssb_driver);
4092         b43_pcmcia_exit();
4093         b43_debugfs_exit();
4094 }
4095
4096 module_init(b43_init)
4097 module_exit(b43_exit)