2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
26 static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
28 extern struct hal_percal_data iq_cal_multi_sample;
29 extern struct hal_percal_data iq_cal_single_sample;
30 extern struct hal_percal_data adc_gain_cal_multi_sample;
31 extern struct hal_percal_data adc_gain_cal_single_sample;
32 extern struct hal_percal_data adc_dc_cal_multi_sample;
33 extern struct hal_percal_data adc_dc_cal_single_sample;
34 extern struct hal_percal_data adc_init_dc_cal;
36 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
37 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
38 enum ath9k_ht_macmode macmode);
39 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
40 struct ar5416_eeprom *pEepData,
42 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
43 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
45 /********************/
46 /* Helper Functions */
47 /********************/
49 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
51 if (ah->ah_curchan != NULL)
52 return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
54 return clks / CLOCK_RATE[ATH9K_MODE_11B];
57 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
59 struct ath9k_channel *chan = ah->ah_curchan;
61 if (chan && IS_CHAN_HT40(chan))
62 return ath9k_hw_mac_usec(ah, clks) / 2;
64 return ath9k_hw_mac_usec(ah, clks);
67 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
69 if (ah->ah_curchan != NULL)
70 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
73 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
76 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
78 struct ath9k_channel *chan = ah->ah_curchan;
80 if (chan && IS_CHAN_HT40(chan))
81 return ath9k_hw_mac_clks(ah, usecs) * 2;
83 return ath9k_hw_mac_clks(ah, usecs);
86 enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
87 const struct ath9k_channel *chan)
89 if (IS_CHAN_CCK(chan))
90 return ATH9K_MODE_11A;
92 return ATH9K_MODE_11G;
93 return ATH9K_MODE_11A;
96 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
100 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
101 if ((REG_READ(ah, reg) & mask) == val)
104 udelay(AH_TIME_QUANTUM);
106 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
107 "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
108 __func__, reg, REG_READ(ah, reg), mask, val);
113 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
118 for (i = 0, retval = 0; i < n; i++) {
119 retval = (retval << 1) | (val & 1);
125 bool ath9k_get_channel_edges(struct ath_hal *ah,
129 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
131 if (flags & CHANNEL_5GHZ) {
132 *low = pCap->low_5ghz_chan;
133 *high = pCap->high_5ghz_chan;
136 if ((flags & CHANNEL_2GHZ)) {
137 *low = pCap->low_2ghz_chan;
138 *high = pCap->high_2ghz_chan;
144 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
145 struct ath_rate_table *rates,
146 u32 frameLen, u16 rateix,
149 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
152 kbps = rates->info[rateix].ratekbps;
157 switch (rates->info[rateix].phy) {
159 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
160 if (shortPreamble && rates->info[rateix].short_preamble)
162 numBits = frameLen << 3;
163 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
166 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
167 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
168 numBits = OFDM_PLCP_BITS + (frameLen << 3);
169 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
170 txTime = OFDM_SIFS_TIME_QUARTER
171 + OFDM_PREAMBLE_TIME_QUARTER
172 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
173 } else if (ah->ah_curchan &&
174 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
175 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
176 numBits = OFDM_PLCP_BITS + (frameLen << 3);
177 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
178 txTime = OFDM_SIFS_TIME_HALF +
179 OFDM_PREAMBLE_TIME_HALF
180 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
182 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
183 numBits = OFDM_PLCP_BITS + (frameLen << 3);
184 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
185 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
186 + (numSymbols * OFDM_SYMBOL_TIME);
190 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
191 "%s: unknown phy %u (rate ix %u)\n", __func__,
192 rates->info[rateix].phy, rateix);
200 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
202 if (flags & CHANNEL_2GHZ) {
206 return (freq - 2407) / 5;
208 return 15 + ((freq - 2512) / 20);
209 } else if (flags & CHANNEL_5GHZ) {
210 if (ath9k_regd_is_public_safety_sku(ah) &&
211 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
212 return ((freq * 10) +
213 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
214 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
215 return (freq - 4000) / 5;
217 return (freq - 5000) / 5;
223 return (freq - 2407) / 5;
225 if (ath9k_regd_is_public_safety_sku(ah)
226 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
227 return ((freq * 10) +
229 2) ? 5 : 0) - 49400) / 5;
230 } else if (freq > 4900) {
231 return (freq - 4000) / 5;
233 return 15 + ((freq - 2512) / 20);
236 return (freq - 5000) / 5;
240 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
241 struct ath9k_channel *chan,
242 struct chan_centers *centers)
245 struct ath_hal_5416 *ahp = AH5416(ah);
247 if (!IS_CHAN_HT40(chan)) {
248 centers->ctl_center = centers->ext_center =
249 centers->synth_center = chan->channel;
253 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
254 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
255 centers->synth_center =
256 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
259 centers->synth_center =
260 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
264 centers->ctl_center =
265 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
266 centers->ext_center =
267 centers->synth_center + (extoff *
268 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
269 HT40_CHANNEL_CENTER_SHIFT : 15));
277 static void ath9k_hw_read_revisions(struct ath_hal *ah)
281 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
284 val = REG_READ(ah, AR_SREV);
285 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
286 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
287 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
289 if (!AR_SREV_9100(ah))
290 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
292 ah->ah_macRev = val & AR_SREV_REVISION;
294 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
295 ah->ah_isPciExpress = true;
299 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
304 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
306 for (i = 0; i < 8; i++)
307 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
308 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
309 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
311 return ath9k_hw_reverse_bits(val, 8);
314 /************************************/
315 /* HW Attach, Detach, Init Routines */
316 /************************************/
318 static void ath9k_hw_disablepcie(struct ath_hal *ah)
320 if (!AR_SREV_9100(ah))
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
324 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
325 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
326 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
327 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
328 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
329 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
330 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
333 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
336 static bool ath9k_hw_chip_test(struct ath_hal *ah)
338 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
340 u32 patternData[4] = { 0x55555555,
346 for (i = 0; i < 2; i++) {
347 u32 addr = regAddr[i];
350 regHold[i] = REG_READ(ah, addr);
351 for (j = 0; j < 0x100; j++) {
352 wrData = (j << 16) | j;
353 REG_WRITE(ah, addr, wrData);
354 rdData = REG_READ(ah, addr);
355 if (rdData != wrData) {
356 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
357 "%s: address test failed "
358 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
359 __func__, addr, wrData, rdData);
363 for (j = 0; j < 4; j++) {
364 wrData = patternData[j];
365 REG_WRITE(ah, addr, wrData);
366 rdData = REG_READ(ah, addr);
367 if (wrData != rdData) {
368 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
369 "%s: address test failed "
370 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
371 __func__, addr, wrData, rdData);
375 REG_WRITE(ah, regAddr[i], regHold[i]);
381 static const char *ath9k_hw_devname(u16 devid)
384 case AR5416_DEVID_PCI:
385 return "Atheros 5416";
386 case AR5416_DEVID_PCIE:
387 return "Atheros 5418";
388 case AR9160_DEVID_PCI:
389 return "Atheros 9160";
390 case AR9280_DEVID_PCI:
391 case AR9280_DEVID_PCIE:
392 return "Atheros 9280";
398 static void ath9k_hw_set_defaults(struct ath_hal *ah)
402 ah->ah_config.dma_beacon_response_time = 2;
403 ah->ah_config.sw_beacon_response_time = 10;
404 ah->ah_config.additional_swba_backoff = 0;
405 ah->ah_config.ack_6mb = 0x0;
406 ah->ah_config.cwm_ignore_extcca = 0;
407 ah->ah_config.pcie_powersave_enable = 0;
408 ah->ah_config.pcie_l1skp_enable = 0;
409 ah->ah_config.pcie_clock_req = 0;
410 ah->ah_config.pcie_power_reset = 0x100;
411 ah->ah_config.pcie_restore = 0;
412 ah->ah_config.pcie_waen = 0;
413 ah->ah_config.analog_shiftreg = 1;
414 ah->ah_config.ht_enable = 1;
415 ah->ah_config.ofdm_trig_low = 200;
416 ah->ah_config.ofdm_trig_high = 500;
417 ah->ah_config.cck_trig_high = 200;
418 ah->ah_config.cck_trig_low = 100;
419 ah->ah_config.enable_ani = 1;
420 ah->ah_config.noise_immunity_level = 4;
421 ah->ah_config.ofdm_weaksignal_det = 1;
422 ah->ah_config.cck_weaksignal_thr = 0;
423 ah->ah_config.spur_immunity_level = 2;
424 ah->ah_config.firstep_level = 0;
425 ah->ah_config.rssi_thr_high = 40;
426 ah->ah_config.rssi_thr_low = 7;
427 ah->ah_config.diversity_control = 0;
428 ah->ah_config.antenna_switch_swap = 0;
430 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
431 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
432 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
435 ah->ah_config.intr_mitigation = 1;
438 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
439 struct ath_softc *sc,
443 static const u8 defbssidmask[ETH_ALEN] =
444 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
445 struct ath_hal_5416 *ahp;
448 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
450 DPRINTF(sc, ATH_DBG_FATAL,
451 "%s: cannot allocate memory for state block\n",
460 ah->ah_magic = AR5416_MAGIC;
461 ah->ah_countryCode = CTRY_DEFAULT;
462 ah->ah_devid = devid;
463 ah->ah_subvendorid = 0;
466 if ((devid == AR5416_AR9100_DEVID))
467 ah->ah_macVersion = AR_SREV_VERSION_9100;
468 if (!AR_SREV_9100(ah))
469 ah->ah_flags = AH_USE_EEPROM;
471 ah->ah_powerLimit = MAX_RATE_POWER;
472 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
473 ahp->ah_atimWindow = 0;
474 ahp->ah_diversityControl = ah->ah_config.diversity_control;
475 ahp->ah_antennaSwitchSwap =
476 ah->ah_config.antenna_switch_swap;
477 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
478 ahp->ah_beaconInterval = 100;
479 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
480 ahp->ah_slottime = (u32) -1;
481 ahp->ah_acktimeout = (u32) -1;
482 ahp->ah_ctstimeout = (u32) -1;
483 ahp->ah_globaltxtimeout = (u32) -1;
484 memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
486 ahp->ah_gBeaconRate = 0;
491 static int ath9k_hw_rfattach(struct ath_hal *ah)
493 bool rfStatus = false;
496 rfStatus = ath9k_hw_init_rf(ah, &ecode);
498 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
499 "%s: RF setup failed, status %u\n", __func__,
507 static int ath9k_hw_rf_claim(struct ath_hal *ah)
511 REG_WRITE(ah, AR_PHY(0), 0x00000007);
513 val = ath9k_hw_get_radiorev(ah);
514 switch (val & AR_RADIO_SREV_MAJOR) {
516 val = AR_RAD5133_SREV_MAJOR;
518 case AR_RAD5133_SREV_MAJOR:
519 case AR_RAD5122_SREV_MAJOR:
520 case AR_RAD2133_SREV_MAJOR:
521 case AR_RAD2122_SREV_MAJOR:
524 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
525 "%s: 5G Radio Chip Rev 0x%02X is not "
526 "supported by this driver\n",
527 __func__, ah->ah_analog5GhzRev);
531 ah->ah_analog5GhzRev = val;
536 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
541 struct ath_hal_5416 *ahp = AH5416(ah);
544 for (i = 0; i < 3; i++) {
545 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
547 ahp->ah_macaddr[2 * i] = eeval >> 8;
548 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
550 if (sum == 0 || sum == 0xffff * 3) {
551 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
552 "%s: mac address read failed: %pM\n", __func__,
554 return -EADDRNOTAVAIL;
560 static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
563 struct ath_hal_5416 *ahp = AH5416(ah);
565 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
566 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
568 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
569 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
570 ar9280Modes_backoff_13db_rxgain_9280_2,
571 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
572 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
573 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
574 ar9280Modes_backoff_23db_rxgain_9280_2,
575 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
577 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
578 ar9280Modes_original_rxgain_9280_2,
579 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
581 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
582 ar9280Modes_original_rxgain_9280_2,
583 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
586 static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
589 struct ath_hal_5416 *ahp = AH5416(ah);
591 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
592 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
594 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
595 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
596 ar9280Modes_high_power_tx_gain_9280_2,
597 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
599 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
600 ar9280Modes_original_tx_gain_9280_2,
601 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
603 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
604 ar9280Modes_original_tx_gain_9280_2,
605 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
608 static int ath9k_hw_post_attach(struct ath_hal *ah)
612 if (!ath9k_hw_chip_test(ah)) {
613 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
614 "%s: hardware self-test failed\n", __func__);
618 ecode = ath9k_hw_rf_claim(ah);
622 ecode = ath9k_hw_eeprom_attach(ah);
625 ecode = ath9k_hw_rfattach(ah);
629 if (!AR_SREV_9100(ah)) {
630 ath9k_hw_ani_setup(ah);
631 ath9k_hw_ani_attach(ah);
637 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
638 void __iomem *mem, int *status)
640 struct ath_hal_5416 *ahp;
643 #ifndef CONFIG_SLOW_ANT_DIV
648 ahp = ath9k_hw_newstate(devid, sc, mem, status);
654 ath9k_hw_set_defaults(ah);
656 if (ah->ah_config.intr_mitigation != 0)
657 ahp->ah_intrMitigation = true;
659 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
660 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n",
666 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
667 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n",
673 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
674 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
675 ah->ah_config.serialize_regmode =
678 ah->ah_config.serialize_regmode =
683 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
684 "%s: serialize_regmode is %d\n",
685 __func__, ah->ah_config.serialize_regmode);
687 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
688 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
689 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
690 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
691 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
692 "%s: Mac Chip Rev 0x%02x.%x is not supported by "
693 "this driver\n", __func__,
694 ah->ah_macVersion, ah->ah_macRev);
699 if (AR_SREV_9100(ah)) {
700 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
701 ahp->ah_suppCals = IQ_MISMATCH_CAL;
702 ah->ah_isPciExpress = false;
704 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
706 if (AR_SREV_9160_10_OR_LATER(ah)) {
707 if (AR_SREV_9280_10_OR_LATER(ah)) {
708 ahp->ah_iqCalData.calData = &iq_cal_single_sample;
709 ahp->ah_adcGainCalData.calData =
710 &adc_gain_cal_single_sample;
711 ahp->ah_adcDcCalData.calData =
712 &adc_dc_cal_single_sample;
713 ahp->ah_adcDcCalInitData.calData =
716 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
717 ahp->ah_adcGainCalData.calData =
718 &adc_gain_cal_multi_sample;
719 ahp->ah_adcDcCalData.calData =
720 &adc_dc_cal_multi_sample;
721 ahp->ah_adcDcCalInitData.calData =
724 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
727 if (AR_SREV_9160(ah)) {
728 ah->ah_config.enable_ani = 1;
729 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
730 ATH9K_ANI_FIRSTEP_LEVEL);
732 ahp->ah_ani_function = ATH9K_ANI_ALL;
733 if (AR_SREV_9280_10_OR_LATER(ah)) {
734 ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
738 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
739 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
740 ah->ah_macVersion, ah->ah_macRev);
742 if (AR_SREV_9280_20_OR_LATER(ah)) {
743 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
744 ARRAY_SIZE(ar9280Modes_9280_2), 6);
745 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
746 ARRAY_SIZE(ar9280Common_9280_2), 2);
748 if (ah->ah_config.pcie_clock_req) {
749 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
750 ar9280PciePhy_clkreq_off_L1_9280,
751 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
753 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
754 ar9280PciePhy_clkreq_always_on_L1_9280,
755 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
757 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
758 ar9280Modes_fast_clock_9280_2,
759 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
760 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
761 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
762 ARRAY_SIZE(ar9280Modes_9280), 6);
763 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
764 ARRAY_SIZE(ar9280Common_9280), 2);
765 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
766 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
767 ARRAY_SIZE(ar5416Modes_9160), 6);
768 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
769 ARRAY_SIZE(ar5416Common_9160), 2);
770 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
771 ARRAY_SIZE(ar5416Bank0_9160), 2);
772 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
773 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
774 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
775 ARRAY_SIZE(ar5416Bank1_9160), 2);
776 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
777 ARRAY_SIZE(ar5416Bank2_9160), 2);
778 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
779 ARRAY_SIZE(ar5416Bank3_9160), 3);
780 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
781 ARRAY_SIZE(ar5416Bank6_9160), 3);
782 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
783 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
784 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
785 ARRAY_SIZE(ar5416Bank7_9160), 2);
786 if (AR_SREV_9160_11(ah)) {
787 INIT_INI_ARRAY(&ahp->ah_iniAddac,
789 ARRAY_SIZE(ar5416Addac_91601_1), 2);
791 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
792 ARRAY_SIZE(ar5416Addac_9160), 2);
794 } else if (AR_SREV_9100_OR_LATER(ah)) {
795 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
796 ARRAY_SIZE(ar5416Modes_9100), 6);
797 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
798 ARRAY_SIZE(ar5416Common_9100), 2);
799 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
800 ARRAY_SIZE(ar5416Bank0_9100), 2);
801 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
802 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
803 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
804 ARRAY_SIZE(ar5416Bank1_9100), 2);
805 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
806 ARRAY_SIZE(ar5416Bank2_9100), 2);
807 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
808 ARRAY_SIZE(ar5416Bank3_9100), 3);
809 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
810 ARRAY_SIZE(ar5416Bank6_9100), 3);
811 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
812 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
813 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
814 ARRAY_SIZE(ar5416Bank7_9100), 2);
815 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
816 ARRAY_SIZE(ar5416Addac_9100), 2);
818 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
819 ARRAY_SIZE(ar5416Modes), 6);
820 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
821 ARRAY_SIZE(ar5416Common), 2);
822 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
823 ARRAY_SIZE(ar5416Bank0), 2);
824 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
825 ARRAY_SIZE(ar5416BB_RfGain), 3);
826 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
827 ARRAY_SIZE(ar5416Bank1), 2);
828 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
829 ARRAY_SIZE(ar5416Bank2), 2);
830 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
831 ARRAY_SIZE(ar5416Bank3), 3);
832 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
833 ARRAY_SIZE(ar5416Bank6), 3);
834 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
835 ARRAY_SIZE(ar5416Bank6TPC), 3);
836 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
837 ARRAY_SIZE(ar5416Bank7), 2);
838 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
839 ARRAY_SIZE(ar5416Addac), 2);
842 if (ah->ah_isPciExpress)
843 ath9k_hw_configpcipowersave(ah, 0);
845 ath9k_hw_disablepcie(ah);
847 ecode = ath9k_hw_post_attach(ah);
852 if (AR_SREV_9280_20_OR_LATER(ah))
853 ath9k_hw_init_rxgain_ini(ah);
856 if (AR_SREV_9280_20_OR_LATER(ah))
857 ath9k_hw_init_txgain_ini(ah);
859 #ifndef CONFIG_SLOW_ANT_DIV
860 if (ah->ah_devid == AR9280_DEVID_PCI) {
861 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
862 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
864 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
865 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
867 INI_RA(&ahp->ah_iniModes, i, j) =
868 ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
874 if (!ath9k_hw_fill_cap_info(ah)) {
875 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
876 "%s:failed ath9k_hw_fill_cap_info\n", __func__);
881 ecode = ath9k_hw_init_macaddr(ah);
883 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
884 "%s: failed initializing mac address\n",
889 if (AR_SREV_9285(ah))
890 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
892 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
894 ath9k_init_nfcal_hist_buffer(ah);
899 ath9k_hw_detach((struct ath_hal *) ahp);
906 static void ath9k_hw_init_bb(struct ath_hal *ah,
907 struct ath9k_channel *chan)
911 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
912 if (IS_CHAN_CCK(chan))
913 synthDelay = (4 * synthDelay) / 22;
917 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
919 udelay(synthDelay + BASE_ACTIVATE_DELAY);
922 static void ath9k_hw_init_qos(struct ath_hal *ah)
924 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
925 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
927 REG_WRITE(ah, AR_QOS_NO_ACK,
928 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
929 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
930 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
932 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
933 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
934 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
935 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
936 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
939 static void ath9k_hw_init_pll(struct ath_hal *ah,
940 struct ath9k_channel *chan)
944 if (AR_SREV_9100(ah)) {
945 if (chan && IS_CHAN_5GHZ(chan))
950 if (AR_SREV_9280_10_OR_LATER(ah)) {
951 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
953 if (chan && IS_CHAN_HALF_RATE(chan))
954 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
955 else if (chan && IS_CHAN_QUARTER_RATE(chan))
956 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
958 if (chan && IS_CHAN_5GHZ(chan)) {
959 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
962 if (AR_SREV_9280_20(ah)) {
963 if (((chan->channel % 20) == 0)
964 || ((chan->channel % 10) == 0))
970 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
973 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
975 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
977 if (chan && IS_CHAN_HALF_RATE(chan))
978 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
979 else if (chan && IS_CHAN_QUARTER_RATE(chan))
980 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
982 if (chan && IS_CHAN_5GHZ(chan))
983 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
985 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
987 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
989 if (chan && IS_CHAN_HALF_RATE(chan))
990 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
991 else if (chan && IS_CHAN_QUARTER_RATE(chan))
992 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
994 if (chan && IS_CHAN_5GHZ(chan))
995 pll |= SM(0xa, AR_RTC_PLL_DIV);
997 pll |= SM(0xb, AR_RTC_PLL_DIV);
1000 REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1002 udelay(RTC_PLL_SETTLE_DELAY);
1004 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1007 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1009 struct ath_hal_5416 *ahp = AH5416(ah);
1010 int rx_chainmask, tx_chainmask;
1012 rx_chainmask = ahp->ah_rxchainmask;
1013 tx_chainmask = ahp->ah_txchainmask;
1015 switch (rx_chainmask) {
1017 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1018 AR_PHY_SWAP_ALT_CHAIN);
1020 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1021 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1022 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1027 if (!AR_SREV_9280(ah))
1030 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1031 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1037 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1038 if (tx_chainmask == 0x5) {
1039 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1040 AR_PHY_SWAP_ALT_CHAIN);
1042 if (AR_SREV_9100(ah))
1043 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1044 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1047 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, enum ath9k_opmode opmode)
1049 struct ath_hal_5416 *ahp = AH5416(ah);
1051 ahp->ah_maskReg = AR_IMR_TXERR |
1057 if (ahp->ah_intrMitigation)
1058 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1060 ahp->ah_maskReg |= AR_IMR_RXOK;
1062 ahp->ah_maskReg |= AR_IMR_TXOK;
1064 if (opmode == ATH9K_M_HOSTAP)
1065 ahp->ah_maskReg |= AR_IMR_MIB;
1067 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1068 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1070 if (!AR_SREV_9100(ah)) {
1071 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1072 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1073 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1077 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1079 struct ath_hal_5416 *ahp = AH5416(ah);
1081 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1082 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n",
1084 ahp->ah_acktimeout = (u32) -1;
1087 REG_RMW_FIELD(ah, AR_TIME_OUT,
1088 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1089 ahp->ah_acktimeout = us;
1094 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1096 struct ath_hal_5416 *ahp = AH5416(ah);
1098 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1099 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n",
1101 ahp->ah_ctstimeout = (u32) -1;
1104 REG_RMW_FIELD(ah, AR_TIME_OUT,
1105 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1106 ahp->ah_ctstimeout = us;
1111 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1113 struct ath_hal_5416 *ahp = AH5416(ah);
1116 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1117 "%s: bad global tx timeout %u\n", __func__, tu);
1118 ahp->ah_globaltxtimeout = (u32) -1;
1121 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1122 ahp->ah_globaltxtimeout = tu;
1127 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1129 struct ath_hal_5416 *ahp = AH5416(ah);
1131 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
1132 __func__, ahp->ah_miscMode);
1134 if (ahp->ah_miscMode != 0)
1135 REG_WRITE(ah, AR_PCU_MISC,
1136 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1137 if (ahp->ah_slottime != (u32) -1)
1138 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1139 if (ahp->ah_acktimeout != (u32) -1)
1140 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1141 if (ahp->ah_ctstimeout != (u32) -1)
1142 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1143 if (ahp->ah_globaltxtimeout != (u32) -1)
1144 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1147 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1149 return vendorid == ATHEROS_VENDOR_ID ?
1150 ath9k_hw_devname(devid) : NULL;
1153 void ath9k_hw_detach(struct ath_hal *ah)
1155 if (!AR_SREV_9100(ah))
1156 ath9k_hw_ani_detach(ah);
1158 ath9k_hw_rfdetach(ah);
1159 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1163 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1164 void __iomem *mem, int *error)
1166 struct ath_hal *ah = NULL;
1169 case AR5416_DEVID_PCI:
1170 case AR5416_DEVID_PCIE:
1171 case AR9160_DEVID_PCI:
1172 case AR9280_DEVID_PCI:
1173 case AR9280_DEVID_PCIE:
1174 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1177 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1178 "devid=0x%x not supported.\n", devid);
1191 static void ath9k_hw_override_ini(struct ath_hal *ah,
1192 struct ath9k_channel *chan)
1194 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1195 AR_SREV_9280_10_OR_LATER(ah))
1198 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1201 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1202 struct ar5416_eeprom *pEepData,
1205 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1207 switch (ah->ah_devid) {
1208 case AR9280_DEVID_PCI:
1209 if (reg == 0x7894) {
1210 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1211 "ini VAL: %x EEPROM: %x\n", value,
1212 (pBase->version & 0xff));
1214 if ((pBase->version & 0xff) > 0x0a) {
1215 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1218 value &= ~AR_AN_TOP2_PWDCLKIND;
1219 value |= AR_AN_TOP2_PWDCLKIND &
1220 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1222 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1223 "PWDCLKIND Earlier Rev\n");
1226 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1227 "final ini VAL: %x\n", value);
1235 static int ath9k_hw_process_ini(struct ath_hal *ah,
1236 struct ath9k_channel *chan,
1237 enum ath9k_ht_macmode macmode)
1239 int i, regWrites = 0;
1240 struct ath_hal_5416 *ahp = AH5416(ah);
1241 u32 modesIndex, freqIndex;
1244 switch (chan->chanmode) {
1246 case CHANNEL_A_HT20:
1250 case CHANNEL_A_HT40PLUS:
1251 case CHANNEL_A_HT40MINUS:
1256 case CHANNEL_G_HT20:
1261 case CHANNEL_G_HT40PLUS:
1262 case CHANNEL_G_HT40MINUS:
1271 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1273 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1275 ath9k_hw_set_addac(ah, chan);
1277 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1278 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1280 struct ar5416IniArray temp;
1282 sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1283 ahp->ah_iniAddac.ia_columns;
1285 memcpy(ahp->ah_addac5416_21,
1286 ahp->ah_iniAddac.ia_array, addacSize);
1288 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1290 temp.ia_array = ahp->ah_addac5416_21;
1291 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1292 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1293 REG_WRITE_ARRAY(&temp, 1, regWrites);
1296 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1298 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1299 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1300 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1302 #ifdef CONFIG_SLOW_ANT_DIV
1303 if (ah->ah_devid == AR9280_DEVID_PCI)
1304 val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg, val);
1307 REG_WRITE(ah, reg, val);
1309 if (reg >= 0x7800 && reg < 0x78a0
1310 && ah->ah_config.analog_shiftreg) {
1314 DO_DELAY(regWrites);
1317 if (AR_SREV_9280_20_OR_LATER(ah))
1318 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1320 if (AR_SREV_9280_20_OR_LATER(ah))
1321 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1323 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1324 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1325 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1327 REG_WRITE(ah, reg, val);
1329 if (reg >= 0x7800 && reg < 0x78a0
1330 && ah->ah_config.analog_shiftreg) {
1334 DO_DELAY(regWrites);
1337 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1339 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1340 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1344 ath9k_hw_override_ini(ah, chan);
1345 ath9k_hw_set_regs(ah, chan, macmode);
1346 ath9k_hw_init_chain_masks(ah);
1348 status = ath9k_hw_set_txpower(ah, chan,
1349 ath9k_regd_get_ctl(ah, chan),
1350 ath9k_regd_get_antenna_allowed(ah,
1352 chan->maxRegTxPower * 2,
1353 min((u32) MAX_RATE_POWER,
1354 (u32) ah->ah_powerLimit));
1356 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1357 "%s: error init'ing transmit power\n", __func__);
1361 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1362 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1363 "%s: ar5416SetRfRegs failed\n", __func__);
1370 /****************************************/
1371 /* Reset and Channel Switching Routines */
1372 /****************************************/
1374 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1381 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1382 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1384 if (!AR_SREV_9280_10_OR_LATER(ah))
1385 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1386 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1388 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1389 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1391 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1394 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1396 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1399 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1403 regval = REG_READ(ah, AR_AHB_MODE);
1404 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1406 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1407 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1409 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1411 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1412 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1414 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1416 if (AR_SREV_9285(ah)) {
1417 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1418 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1420 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1421 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1425 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1429 val = REG_READ(ah, AR_STA_ID1);
1430 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1432 case ATH9K_M_HOSTAP:
1433 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1434 | AR_STA_ID1_KSRCH_MODE);
1435 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1438 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1439 | AR_STA_ID1_KSRCH_MODE);
1440 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1443 case ATH9K_M_MONITOR:
1444 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1449 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1454 u32 coef_exp, coef_man;
1456 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1457 if ((coef_scaled >> coef_exp) & 0x1)
1460 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1462 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1464 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1465 *coef_exponent = coef_exp - 16;
1468 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1469 struct ath9k_channel *chan)
1471 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1472 u32 clockMhzScaled = 0x64000000;
1473 struct chan_centers centers;
1475 if (IS_CHAN_HALF_RATE(chan))
1476 clockMhzScaled = clockMhzScaled >> 1;
1477 else if (IS_CHAN_QUARTER_RATE(chan))
1478 clockMhzScaled = clockMhzScaled >> 2;
1480 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1481 coef_scaled = clockMhzScaled / centers.synth_center;
1483 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1486 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1487 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1488 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1489 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1491 coef_scaled = (9 * coef_scaled) / 10;
1493 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1496 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1497 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1498 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1499 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1502 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1507 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1508 AR_RTC_FORCE_WAKE_ON_INT);
1510 if (AR_SREV_9100(ah)) {
1511 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1512 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1514 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1516 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1517 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1518 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1519 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1521 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1524 rst_flags = AR_RTC_RC_MAC_WARM;
1525 if (type == ATH9K_RESET_COLD)
1526 rst_flags |= AR_RTC_RC_MAC_COLD;
1529 REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1532 REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1533 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1534 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1535 "%s: RTC stuck in MAC reset\n",
1540 if (!AR_SREV_9100(ah))
1541 REG_WRITE(ah, AR_RC, 0);
1543 ath9k_hw_init_pll(ah, NULL);
1545 if (AR_SREV_9100(ah))
1551 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1553 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1554 AR_RTC_FORCE_WAKE_ON_INT);
1556 REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1557 REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1559 if (!ath9k_hw_wait(ah,
1562 AR_RTC_STATUS_ON)) {
1563 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n",
1568 ath9k_hw_read_revisions(ah);
1570 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1573 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1575 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1576 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1579 case ATH9K_RESET_POWER_ON:
1580 return ath9k_hw_set_reset_power_on(ah);
1582 case ATH9K_RESET_WARM:
1583 case ATH9K_RESET_COLD:
1584 return ath9k_hw_set_reset(ah, type);
1591 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1592 enum ath9k_ht_macmode macmode)
1595 struct ath_hal_5416 *ahp = AH5416(ah);
1597 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1598 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1600 if (IS_CHAN_HT40(chan)) {
1601 phymode |= AR_PHY_FC_DYN2040_EN;
1603 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1604 (chan->chanmode == CHANNEL_G_HT40PLUS))
1605 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1607 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1608 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1610 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1612 ath9k_hw_set11nmac2040(ah, macmode);
1614 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1615 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1618 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1619 struct ath9k_channel *chan)
1621 struct ath_hal_5416 *ahp = AH5416(ah);
1623 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1626 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1629 ahp->ah_chipFullSleep = false;
1631 ath9k_hw_init_pll(ah, chan);
1633 ath9k_hw_set_rfmode(ah, chan);
1638 static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1639 struct ath9k_channel *chan)
1641 if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1642 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1643 "%s: invalid channel %u/0x%x; not marked as "
1644 "2GHz or 5GHz\n", __func__, chan->channel,
1645 chan->channelFlags);
1649 if (!IS_CHAN_OFDM(chan) &&
1650 !IS_CHAN_CCK(chan) &&
1651 !IS_CHAN_HT20(chan) &&
1652 !IS_CHAN_HT40(chan)) {
1653 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1654 "%s: invalid channel %u/0x%x; not marked as "
1655 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1656 __func__, chan->channel, chan->channelFlags);
1660 return ath9k_regd_check_channel(ah, chan);
1663 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1664 struct ath9k_channel *chan,
1665 enum ath9k_ht_macmode macmode)
1667 u32 synthDelay, qnum;
1669 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1670 if (ath9k_hw_numtxpending(ah, qnum)) {
1671 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1672 "%s: Transmit frames pending on queue %d\n",
1678 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1679 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1680 AR_PHY_RFBUS_GRANT_EN)) {
1681 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
1682 "%s: Could not kill baseband RX\n", __func__);
1686 ath9k_hw_set_regs(ah, chan, macmode);
1688 if (AR_SREV_9280_10_OR_LATER(ah)) {
1689 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1690 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1691 "%s: failed to set channel\n", __func__);
1695 if (!(ath9k_hw_set_channel(ah, chan))) {
1696 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1697 "%s: failed to set channel\n", __func__);
1702 if (ath9k_hw_set_txpower(ah, chan,
1703 ath9k_regd_get_ctl(ah, chan),
1704 ath9k_regd_get_antenna_allowed(ah, chan),
1705 chan->maxRegTxPower * 2,
1706 min((u32) MAX_RATE_POWER,
1707 (u32) ah->ah_powerLimit)) != 0) {
1708 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1709 "%s: error init'ing transmit power\n", __func__);
1713 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1714 if (IS_CHAN_CCK(chan))
1715 synthDelay = (4 * synthDelay) / 22;
1719 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1721 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1723 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1724 ath9k_hw_set_delta_slope(ah, chan);
1726 if (AR_SREV_9280_10_OR_LATER(ah))
1727 ath9k_hw_9280_spur_mitigate(ah, chan);
1729 ath9k_hw_spur_mitigate(ah, chan);
1731 if (!chan->oneTimeCalsDone)
1732 chan->oneTimeCalsDone = true;
1737 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1739 int bb_spur = AR_NO_SPUR;
1742 int bb_spur_off, spur_subchannel_sd;
1744 int spur_delta_phase;
1746 int upper, lower, cur_vit_mask;
1749 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1750 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1752 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1753 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1755 int inc[4] = { 0, 100, 0, 0 };
1756 struct chan_centers centers;
1763 bool is2GHz = IS_CHAN_2GHZ(chan);
1765 memset(&mask_m, 0, sizeof(int8_t) * 123);
1766 memset(&mask_p, 0, sizeof(int8_t) * 123);
1768 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1769 freq = centers.synth_center;
1771 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1772 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1773 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1776 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1778 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1780 if (AR_NO_SPUR == cur_bb_spur)
1782 cur_bb_spur = cur_bb_spur - freq;
1784 if (IS_CHAN_HT40(chan)) {
1785 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1786 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1787 bb_spur = cur_bb_spur;
1790 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1791 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1792 bb_spur = cur_bb_spur;
1797 if (AR_NO_SPUR == bb_spur) {
1798 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1799 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1802 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1803 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1806 bin = bb_spur * 320;
1808 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1810 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1811 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1812 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1813 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1814 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1816 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1817 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1818 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1819 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1820 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1821 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1823 if (IS_CHAN_HT40(chan)) {
1825 spur_subchannel_sd = 1;
1826 bb_spur_off = bb_spur + 10;
1828 spur_subchannel_sd = 0;
1829 bb_spur_off = bb_spur - 10;
1832 spur_subchannel_sd = 0;
1833 bb_spur_off = bb_spur;
1836 if (IS_CHAN_HT40(chan))
1838 ((bb_spur * 262144) /
1839 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1842 ((bb_spur * 524288) /
1843 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1845 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1846 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1848 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1849 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1850 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1851 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1853 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1854 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1860 for (i = 0; i < 4; i++) {
1864 for (bp = 0; bp < 30; bp++) {
1865 if ((cur_bin > lower) && (cur_bin < upper)) {
1866 pilot_mask = pilot_mask | 0x1 << bp;
1867 chan_mask = chan_mask | 0x1 << bp;
1872 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1873 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1876 cur_vit_mask = 6100;
1880 for (i = 0; i < 123; i++) {
1881 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1883 /* workaround for gcc bug #37014 */
1884 volatile int tmp = abs(cur_vit_mask - bin);
1890 if (cur_vit_mask < 0)
1891 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1893 mask_p[cur_vit_mask / 100] = mask_amt;
1895 cur_vit_mask -= 100;
1898 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1899 | (mask_m[48] << 26) | (mask_m[49] << 24)
1900 | (mask_m[50] << 22) | (mask_m[51] << 20)
1901 | (mask_m[52] << 18) | (mask_m[53] << 16)
1902 | (mask_m[54] << 14) | (mask_m[55] << 12)
1903 | (mask_m[56] << 10) | (mask_m[57] << 8)
1904 | (mask_m[58] << 6) | (mask_m[59] << 4)
1905 | (mask_m[60] << 2) | (mask_m[61] << 0);
1906 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1907 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1909 tmp_mask = (mask_m[31] << 28)
1910 | (mask_m[32] << 26) | (mask_m[33] << 24)
1911 | (mask_m[34] << 22) | (mask_m[35] << 20)
1912 | (mask_m[36] << 18) | (mask_m[37] << 16)
1913 | (mask_m[48] << 14) | (mask_m[39] << 12)
1914 | (mask_m[40] << 10) | (mask_m[41] << 8)
1915 | (mask_m[42] << 6) | (mask_m[43] << 4)
1916 | (mask_m[44] << 2) | (mask_m[45] << 0);
1917 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1918 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1920 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1921 | (mask_m[18] << 26) | (mask_m[18] << 24)
1922 | (mask_m[20] << 22) | (mask_m[20] << 20)
1923 | (mask_m[22] << 18) | (mask_m[22] << 16)
1924 | (mask_m[24] << 14) | (mask_m[24] << 12)
1925 | (mask_m[25] << 10) | (mask_m[26] << 8)
1926 | (mask_m[27] << 6) | (mask_m[28] << 4)
1927 | (mask_m[29] << 2) | (mask_m[30] << 0);
1928 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1929 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1931 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1932 | (mask_m[2] << 26) | (mask_m[3] << 24)
1933 | (mask_m[4] << 22) | (mask_m[5] << 20)
1934 | (mask_m[6] << 18) | (mask_m[7] << 16)
1935 | (mask_m[8] << 14) | (mask_m[9] << 12)
1936 | (mask_m[10] << 10) | (mask_m[11] << 8)
1937 | (mask_m[12] << 6) | (mask_m[13] << 4)
1938 | (mask_m[14] << 2) | (mask_m[15] << 0);
1939 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1940 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1942 tmp_mask = (mask_p[15] << 28)
1943 | (mask_p[14] << 26) | (mask_p[13] << 24)
1944 | (mask_p[12] << 22) | (mask_p[11] << 20)
1945 | (mask_p[10] << 18) | (mask_p[9] << 16)
1946 | (mask_p[8] << 14) | (mask_p[7] << 12)
1947 | (mask_p[6] << 10) | (mask_p[5] << 8)
1948 | (mask_p[4] << 6) | (mask_p[3] << 4)
1949 | (mask_p[2] << 2) | (mask_p[1] << 0);
1950 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1951 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1953 tmp_mask = (mask_p[30] << 28)
1954 | (mask_p[29] << 26) | (mask_p[28] << 24)
1955 | (mask_p[27] << 22) | (mask_p[26] << 20)
1956 | (mask_p[25] << 18) | (mask_p[24] << 16)
1957 | (mask_p[23] << 14) | (mask_p[22] << 12)
1958 | (mask_p[21] << 10) | (mask_p[20] << 8)
1959 | (mask_p[19] << 6) | (mask_p[18] << 4)
1960 | (mask_p[17] << 2) | (mask_p[16] << 0);
1961 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1962 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1964 tmp_mask = (mask_p[45] << 28)
1965 | (mask_p[44] << 26) | (mask_p[43] << 24)
1966 | (mask_p[42] << 22) | (mask_p[41] << 20)
1967 | (mask_p[40] << 18) | (mask_p[39] << 16)
1968 | (mask_p[38] << 14) | (mask_p[37] << 12)
1969 | (mask_p[36] << 10) | (mask_p[35] << 8)
1970 | (mask_p[34] << 6) | (mask_p[33] << 4)
1971 | (mask_p[32] << 2) | (mask_p[31] << 0);
1972 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1973 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1975 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1976 | (mask_p[59] << 26) | (mask_p[58] << 24)
1977 | (mask_p[57] << 22) | (mask_p[56] << 20)
1978 | (mask_p[55] << 18) | (mask_p[54] << 16)
1979 | (mask_p[53] << 14) | (mask_p[52] << 12)
1980 | (mask_p[51] << 10) | (mask_p[50] << 8)
1981 | (mask_p[49] << 6) | (mask_p[48] << 4)
1982 | (mask_p[47] << 2) | (mask_p[46] << 0);
1983 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1984 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1987 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1989 int bb_spur = AR_NO_SPUR;
1992 int spur_delta_phase;
1994 int upper, lower, cur_vit_mask;
1997 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1998 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2000 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2001 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2003 int inc[4] = { 0, 100, 0, 0 };
2010 bool is2GHz = IS_CHAN_2GHZ(chan);
2012 memset(&mask_m, 0, sizeof(int8_t) * 123);
2013 memset(&mask_p, 0, sizeof(int8_t) * 123);
2015 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2016 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2017 if (AR_NO_SPUR == cur_bb_spur)
2019 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2020 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2021 bb_spur = cur_bb_spur;
2026 if (AR_NO_SPUR == bb_spur)
2031 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2032 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2033 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2034 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2035 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2037 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2039 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2040 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2041 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2042 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2043 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2044 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2046 spur_delta_phase = ((bb_spur * 524288) / 100) &
2047 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2049 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2050 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2052 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2053 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2054 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2055 REG_WRITE(ah, AR_PHY_TIMING11, new);
2061 for (i = 0; i < 4; i++) {
2065 for (bp = 0; bp < 30; bp++) {
2066 if ((cur_bin > lower) && (cur_bin < upper)) {
2067 pilot_mask = pilot_mask | 0x1 << bp;
2068 chan_mask = chan_mask | 0x1 << bp;
2073 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2074 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2077 cur_vit_mask = 6100;
2081 for (i = 0; i < 123; i++) {
2082 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2084 /* workaround for gcc bug #37014 */
2085 volatile int tmp = abs(cur_vit_mask - bin);
2091 if (cur_vit_mask < 0)
2092 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2094 mask_p[cur_vit_mask / 100] = mask_amt;
2096 cur_vit_mask -= 100;
2099 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2100 | (mask_m[48] << 26) | (mask_m[49] << 24)
2101 | (mask_m[50] << 22) | (mask_m[51] << 20)
2102 | (mask_m[52] << 18) | (mask_m[53] << 16)
2103 | (mask_m[54] << 14) | (mask_m[55] << 12)
2104 | (mask_m[56] << 10) | (mask_m[57] << 8)
2105 | (mask_m[58] << 6) | (mask_m[59] << 4)
2106 | (mask_m[60] << 2) | (mask_m[61] << 0);
2107 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2108 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2110 tmp_mask = (mask_m[31] << 28)
2111 | (mask_m[32] << 26) | (mask_m[33] << 24)
2112 | (mask_m[34] << 22) | (mask_m[35] << 20)
2113 | (mask_m[36] << 18) | (mask_m[37] << 16)
2114 | (mask_m[48] << 14) | (mask_m[39] << 12)
2115 | (mask_m[40] << 10) | (mask_m[41] << 8)
2116 | (mask_m[42] << 6) | (mask_m[43] << 4)
2117 | (mask_m[44] << 2) | (mask_m[45] << 0);
2118 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2119 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2121 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2122 | (mask_m[18] << 26) | (mask_m[18] << 24)
2123 | (mask_m[20] << 22) | (mask_m[20] << 20)
2124 | (mask_m[22] << 18) | (mask_m[22] << 16)
2125 | (mask_m[24] << 14) | (mask_m[24] << 12)
2126 | (mask_m[25] << 10) | (mask_m[26] << 8)
2127 | (mask_m[27] << 6) | (mask_m[28] << 4)
2128 | (mask_m[29] << 2) | (mask_m[30] << 0);
2129 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2130 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2132 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2133 | (mask_m[2] << 26) | (mask_m[3] << 24)
2134 | (mask_m[4] << 22) | (mask_m[5] << 20)
2135 | (mask_m[6] << 18) | (mask_m[7] << 16)
2136 | (mask_m[8] << 14) | (mask_m[9] << 12)
2137 | (mask_m[10] << 10) | (mask_m[11] << 8)
2138 | (mask_m[12] << 6) | (mask_m[13] << 4)
2139 | (mask_m[14] << 2) | (mask_m[15] << 0);
2140 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2141 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2143 tmp_mask = (mask_p[15] << 28)
2144 | (mask_p[14] << 26) | (mask_p[13] << 24)
2145 | (mask_p[12] << 22) | (mask_p[11] << 20)
2146 | (mask_p[10] << 18) | (mask_p[9] << 16)
2147 | (mask_p[8] << 14) | (mask_p[7] << 12)
2148 | (mask_p[6] << 10) | (mask_p[5] << 8)
2149 | (mask_p[4] << 6) | (mask_p[3] << 4)
2150 | (mask_p[2] << 2) | (mask_p[1] << 0);
2151 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2152 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2154 tmp_mask = (mask_p[30] << 28)
2155 | (mask_p[29] << 26) | (mask_p[28] << 24)
2156 | (mask_p[27] << 22) | (mask_p[26] << 20)
2157 | (mask_p[25] << 18) | (mask_p[24] << 16)
2158 | (mask_p[23] << 14) | (mask_p[22] << 12)
2159 | (mask_p[21] << 10) | (mask_p[20] << 8)
2160 | (mask_p[19] << 6) | (mask_p[18] << 4)
2161 | (mask_p[17] << 2) | (mask_p[16] << 0);
2162 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2163 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2165 tmp_mask = (mask_p[45] << 28)
2166 | (mask_p[44] << 26) | (mask_p[43] << 24)
2167 | (mask_p[42] << 22) | (mask_p[41] << 20)
2168 | (mask_p[40] << 18) | (mask_p[39] << 16)
2169 | (mask_p[38] << 14) | (mask_p[37] << 12)
2170 | (mask_p[36] << 10) | (mask_p[35] << 8)
2171 | (mask_p[34] << 6) | (mask_p[33] << 4)
2172 | (mask_p[32] << 2) | (mask_p[31] << 0);
2173 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2174 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2176 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2177 | (mask_p[59] << 26) | (mask_p[58] << 24)
2178 | (mask_p[57] << 22) | (mask_p[56] << 20)
2179 | (mask_p[55] << 18) | (mask_p[54] << 16)
2180 | (mask_p[53] << 14) | (mask_p[52] << 12)
2181 | (mask_p[51] << 10) | (mask_p[50] << 8)
2182 | (mask_p[49] << 6) | (mask_p[48] << 4)
2183 | (mask_p[47] << 2) | (mask_p[46] << 0);
2184 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2185 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2188 bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2189 enum ath9k_ht_macmode macmode,
2190 u8 txchainmask, u8 rxchainmask,
2191 enum ath9k_ht_extprotspacing extprotspacing,
2192 bool bChannelChange, int *status)
2195 struct ath_hal_5416 *ahp = AH5416(ah);
2196 struct ath9k_channel *curchan = ah->ah_curchan;
2200 int i, rx_chainmask;
2202 ahp->ah_extprotspacing = extprotspacing;
2203 ahp->ah_txchainmask = txchainmask;
2204 ahp->ah_rxchainmask = rxchainmask;
2206 if (AR_SREV_9280(ah)) {
2207 ahp->ah_txchainmask &= 0x3;
2208 ahp->ah_rxchainmask &= 0x3;
2211 if (ath9k_hw_check_chan(ah, chan) == NULL) {
2212 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2213 "%s: invalid channel %u/0x%x; no mapping\n",
2214 __func__, chan->channel, chan->channelFlags);
2219 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
2225 ath9k_hw_getnf(ah, curchan);
2227 if (bChannelChange &&
2228 (ahp->ah_chipFullSleep != true) &&
2229 (ah->ah_curchan != NULL) &&
2230 (chan->channel != ah->ah_curchan->channel) &&
2231 ((chan->channelFlags & CHANNEL_ALL) ==
2232 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2233 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2234 !IS_CHAN_A_5MHZ_SPACED(ah->
2237 if (ath9k_hw_channel_change(ah, chan, macmode)) {
2238 ath9k_hw_loadnf(ah, ah->ah_curchan);
2239 ath9k_hw_start_nfcal(ah);
2244 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2245 if (saveDefAntenna == 0)
2248 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2250 saveLedState = REG_READ(ah, AR_CFG_LED) &
2251 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2252 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2254 ath9k_hw_mark_phy_inactive(ah);
2256 if (!ath9k_hw_chip_reset(ah, chan)) {
2257 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n",
2263 if (AR_SREV_9280(ah)) {
2264 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2265 AR_GPIO_JTAG_DISABLE);
2267 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
2268 if (IS_CHAN_5GHZ(chan))
2269 ath9k_hw_set_gpio(ah, 9, 0);
2271 ath9k_hw_set_gpio(ah, 9, 1);
2273 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2276 ecode = ath9k_hw_process_ini(ah, chan, macmode);
2282 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2283 ath9k_hw_set_delta_slope(ah, chan);
2285 if (AR_SREV_9280_10_OR_LATER(ah))
2286 ath9k_hw_9280_spur_mitigate(ah, chan);
2288 ath9k_hw_spur_mitigate(ah, chan);
2290 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2291 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2292 "%s: error setting board options\n", __func__);
2297 ath9k_hw_decrease_chain_power(ah, chan);
2299 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2300 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2302 | AR_STA_ID1_RTS_USE_DEF
2304 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2305 | ahp->ah_staId1Defaults);
2306 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2308 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2309 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2311 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2313 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2314 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2315 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2317 REG_WRITE(ah, AR_ISR, ~0);
2319 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2321 if (AR_SREV_9280_10_OR_LATER(ah)) {
2322 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
2327 if (!(ath9k_hw_set_channel(ah, chan))) {
2333 for (i = 0; i < AR_NUM_DCU; i++)
2334 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2336 ahp->ah_intrTxqs = 0;
2337 for (i = 0; i < ah->ah_caps.total_queues; i++)
2338 ath9k_hw_resettxqueue(ah, i);
2340 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2341 ath9k_hw_init_qos(ah);
2343 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2344 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2345 ath9k_enable_rfkill(ah);
2347 ath9k_hw_init_user_settings(ah);
2349 REG_WRITE(ah, AR_STA_ID1,
2350 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2352 ath9k_hw_set_dma(ah);
2354 REG_WRITE(ah, AR_OBS, 8);
2356 if (ahp->ah_intrMitigation) {
2358 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2359 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2362 ath9k_hw_init_bb(ah, chan);
2364 if (!ath9k_hw_init_cal(ah, chan)){
2369 rx_chainmask = ahp->ah_rxchainmask;
2370 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2371 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2372 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2375 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2377 if (AR_SREV_9100(ah)) {
2379 mask = REG_READ(ah, AR_CFG);
2380 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2381 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2382 "%s CFG Byte Swap Set 0x%x\n", __func__,
2386 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2387 REG_WRITE(ah, AR_CFG, mask);
2388 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2389 "%s Setting CFG 0x%x\n", __func__,
2390 REG_READ(ah, AR_CFG));
2394 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2405 /************************/
2406 /* Key Cache Management */
2407 /************************/
2409 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2413 if (entry >= ah->ah_caps.keycache_size) {
2414 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2415 "%s: entry %u out of range\n", __func__, entry);
2419 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2421 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2422 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2423 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2424 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2425 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2426 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2427 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2428 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2430 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2431 u16 micentry = entry + 64;
2433 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2434 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2435 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2436 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2440 if (ah->ah_curchan == NULL)
2446 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2450 if (entry >= ah->ah_caps.keycache_size) {
2451 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2452 "%s: entry %u out of range\n", __func__, entry);
2457 macHi = (mac[5] << 8) | mac[4];
2458 macLo = (mac[3] << 24) |
2463 macLo |= (macHi & 1) << 31;
2468 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2469 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2474 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2475 const struct ath9k_keyval *k,
2476 const u8 *mac, int xorKey)
2478 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2479 u32 key0, key1, key2, key3, key4;
2481 u32 xorMask = xorKey ?
2482 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2483 | ATH9K_KEY_XOR) : 0;
2484 struct ath_hal_5416 *ahp = AH5416(ah);
2486 if (entry >= pCap->keycache_size) {
2487 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2488 "%s: entry %u out of range\n", __func__, entry);
2492 switch (k->kv_type) {
2493 case ATH9K_CIPHER_AES_OCB:
2494 keyType = AR_KEYTABLE_TYPE_AES;
2496 case ATH9K_CIPHER_AES_CCM:
2497 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2498 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2499 "%s: AES-CCM not supported by "
2500 "mac rev 0x%x\n", __func__,
2504 keyType = AR_KEYTABLE_TYPE_CCM;
2506 case ATH9K_CIPHER_TKIP:
2507 keyType = AR_KEYTABLE_TYPE_TKIP;
2508 if (ATH9K_IS_MIC_ENABLED(ah)
2509 && entry + 64 >= pCap->keycache_size) {
2510 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2511 "%s: entry %u inappropriate for TKIP\n",
2516 case ATH9K_CIPHER_WEP:
2517 if (k->kv_len < LEN_WEP40) {
2518 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2519 "%s: WEP key length %u too small\n",
2520 __func__, k->kv_len);
2523 if (k->kv_len <= LEN_WEP40)
2524 keyType = AR_KEYTABLE_TYPE_40;
2525 else if (k->kv_len <= LEN_WEP104)
2526 keyType = AR_KEYTABLE_TYPE_104;
2528 keyType = AR_KEYTABLE_TYPE_128;
2530 case ATH9K_CIPHER_CLR:
2531 keyType = AR_KEYTABLE_TYPE_CLR;
2534 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2535 "%s: cipher %u not supported\n", __func__,
2540 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2541 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2542 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2543 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2544 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2545 if (k->kv_len <= LEN_WEP104)
2548 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2549 u16 micentry = entry + 64;
2551 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2552 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2553 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2554 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2555 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2556 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2557 (void) ath9k_hw_keysetmac(ah, entry, mac);
2559 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2560 u32 mic0, mic1, mic2, mic3, mic4;
2562 mic0 = get_unaligned_le32(k->kv_mic + 0);
2563 mic2 = get_unaligned_le32(k->kv_mic + 4);
2564 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2565 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2566 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2567 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2568 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2569 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2570 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2571 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2572 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2573 AR_KEYTABLE_TYPE_CLR);
2578 mic0 = get_unaligned_le32(k->kv_mic + 0);
2579 mic2 = get_unaligned_le32(k->kv_mic + 4);
2580 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2581 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2582 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2583 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2584 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2585 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2586 AR_KEYTABLE_TYPE_CLR);
2588 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2589 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2590 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2591 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2593 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2594 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2595 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2596 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2597 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2598 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2600 (void) ath9k_hw_keysetmac(ah, entry, mac);
2603 if (ah->ah_curchan == NULL)
2609 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2611 if (entry < ah->ah_caps.keycache_size) {
2612 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2613 if (val & AR_KEYTABLE_VALID)
2619 /******************************/
2620 /* Power Management (Chipset) */
2621 /******************************/
2623 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2625 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2627 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2628 AR_RTC_FORCE_WAKE_EN);
2629 if (!AR_SREV_9100(ah))
2630 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2632 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
2637 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2639 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2641 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2643 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2644 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2645 AR_RTC_FORCE_WAKE_ON_INT);
2647 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2648 AR_RTC_FORCE_WAKE_EN);
2653 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2660 if ((REG_READ(ah, AR_RTC_STATUS) &
2661 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2662 if (ath9k_hw_set_reset_reg(ah,
2663 ATH9K_RESET_POWER_ON) != true) {
2667 if (AR_SREV_9100(ah))
2668 REG_SET_BIT(ah, AR_RTC_RESET,
2671 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2672 AR_RTC_FORCE_WAKE_EN);
2675 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2676 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2677 if (val == AR_RTC_STATUS_ON)
2680 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2681 AR_RTC_FORCE_WAKE_EN);
2684 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2685 "%s: Failed to wakeup in %uus\n",
2686 __func__, POWER_UP_TIME / 20);
2691 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2696 bool ath9k_hw_setpower(struct ath_hal *ah,
2697 enum ath9k_power_mode mode)
2699 struct ath_hal_5416 *ahp = AH5416(ah);
2700 static const char *modes[] = {
2706 int status = true, setChip = true;
2708 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
2709 modes[ahp->ah_powerMode], modes[mode],
2710 setChip ? "set chip " : "");
2713 case ATH9K_PM_AWAKE:
2714 status = ath9k_hw_set_power_awake(ah, setChip);
2716 case ATH9K_PM_FULL_SLEEP:
2717 ath9k_set_power_sleep(ah, setChip);
2718 ahp->ah_chipFullSleep = true;
2720 case ATH9K_PM_NETWORK_SLEEP:
2721 ath9k_set_power_network_sleep(ah, setChip);
2724 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2725 "%s: unknown power mode %u\n", __func__, mode);
2728 ahp->ah_powerMode = mode;
2733 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2735 struct ath_hal_5416 *ahp = AH5416(ah);
2738 if (ah->ah_isPciExpress != true)
2741 if (ah->ah_config.pcie_powersave_enable == 2)
2747 if (AR_SREV_9280_20_OR_LATER(ah)) {
2748 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2749 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2750 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2753 } else if (AR_SREV_9280(ah) &&
2754 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2755 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2756 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2758 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2759 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2760 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2762 if (ah->ah_config.pcie_clock_req)
2763 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2765 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2767 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2768 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2769 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2771 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2775 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2776 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2777 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2778 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2779 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2780 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2781 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2782 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2783 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2784 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2787 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2789 if (ah->ah_config.pcie_waen) {
2790 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2792 if (AR_SREV_9280(ah))
2793 REG_WRITE(ah, AR_WA, 0x0040073f);
2795 REG_WRITE(ah, AR_WA, 0x0000073f);
2799 /**********************/
2800 /* Interrupt Handling */
2801 /**********************/
2803 bool ath9k_hw_intrpend(struct ath_hal *ah)
2807 if (AR_SREV_9100(ah))
2810 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2811 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2814 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2815 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2816 && (host_isr != AR_INTR_SPURIOUS))
2822 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2826 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2828 bool fatal_int = false;
2829 struct ath_hal_5416 *ahp = AH5416(ah);
2831 if (!AR_SREV_9100(ah)) {
2832 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2833 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2834 == AR_RTC_STATUS_ON) {
2835 isr = REG_READ(ah, AR_ISR);
2839 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2840 AR_INTR_SYNC_DEFAULT;
2844 if (!isr && !sync_cause)
2848 isr = REG_READ(ah, AR_ISR);
2852 if (isr & AR_ISR_BCNMISC) {
2854 isr2 = REG_READ(ah, AR_ISR_S2);
2855 if (isr2 & AR_ISR_S2_TIM)
2856 mask2 |= ATH9K_INT_TIM;
2857 if (isr2 & AR_ISR_S2_DTIM)
2858 mask2 |= ATH9K_INT_DTIM;
2859 if (isr2 & AR_ISR_S2_DTIMSYNC)
2860 mask2 |= ATH9K_INT_DTIMSYNC;
2861 if (isr2 & (AR_ISR_S2_CABEND))
2862 mask2 |= ATH9K_INT_CABEND;
2863 if (isr2 & AR_ISR_S2_GTT)
2864 mask2 |= ATH9K_INT_GTT;
2865 if (isr2 & AR_ISR_S2_CST)
2866 mask2 |= ATH9K_INT_CST;
2869 isr = REG_READ(ah, AR_ISR_RAC);
2870 if (isr == 0xffffffff) {
2875 *masked = isr & ATH9K_INT_COMMON;
2877 if (ahp->ah_intrMitigation) {
2878 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2879 *masked |= ATH9K_INT_RX;
2882 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2883 *masked |= ATH9K_INT_RX;
2885 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2889 *masked |= ATH9K_INT_TX;
2891 s0_s = REG_READ(ah, AR_ISR_S0_S);
2892 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2893 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2895 s1_s = REG_READ(ah, AR_ISR_S1_S);
2896 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2897 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2900 if (isr & AR_ISR_RXORN) {
2901 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2902 "%s: receive FIFO overrun interrupt\n",
2906 if (!AR_SREV_9100(ah)) {
2907 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2908 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2909 if (isr5 & AR_ISR_S5_TIM_TIMER)
2910 *masked |= ATH9K_INT_TIM_TIMER;
2917 if (AR_SREV_9100(ah))
2923 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2927 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2928 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2929 "%s: received PCI FATAL interrupt\n",
2932 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2933 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2934 "%s: received PCI PERR interrupt\n",
2938 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2939 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2940 "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n",
2942 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2943 REG_WRITE(ah, AR_RC, 0);
2944 *masked |= ATH9K_INT_FATAL;
2946 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2947 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2948 "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n",
2952 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2953 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2959 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2961 return AH5416(ah)->ah_maskReg;
2964 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2966 struct ath_hal_5416 *ahp = AH5416(ah);
2967 u32 omask = ahp->ah_maskReg;
2969 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2971 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__,
2974 if (omask & ATH9K_INT_GLOBAL) {
2975 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: disable IER\n",
2977 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2978 (void) REG_READ(ah, AR_IER);
2979 if (!AR_SREV_9100(ah)) {
2980 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2981 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2983 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2984 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2988 mask = ints & ATH9K_INT_COMMON;
2991 if (ints & ATH9K_INT_TX) {
2992 if (ahp->ah_txOkInterruptMask)
2993 mask |= AR_IMR_TXOK;
2994 if (ahp->ah_txDescInterruptMask)
2995 mask |= AR_IMR_TXDESC;
2996 if (ahp->ah_txErrInterruptMask)
2997 mask |= AR_IMR_TXERR;
2998 if (ahp->ah_txEolInterruptMask)
2999 mask |= AR_IMR_TXEOL;
3001 if (ints & ATH9K_INT_RX) {
3002 mask |= AR_IMR_RXERR;
3003 if (ahp->ah_intrMitigation)
3004 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3006 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3007 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3008 mask |= AR_IMR_GENTMR;
3011 if (ints & (ATH9K_INT_BMISC)) {
3012 mask |= AR_IMR_BCNMISC;
3013 if (ints & ATH9K_INT_TIM)
3014 mask2 |= AR_IMR_S2_TIM;
3015 if (ints & ATH9K_INT_DTIM)
3016 mask2 |= AR_IMR_S2_DTIM;
3017 if (ints & ATH9K_INT_DTIMSYNC)
3018 mask2 |= AR_IMR_S2_DTIMSYNC;
3019 if (ints & ATH9K_INT_CABEND)
3020 mask2 |= (AR_IMR_S2_CABEND);
3023 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3024 mask |= AR_IMR_BCNMISC;
3025 if (ints & ATH9K_INT_GTT)
3026 mask2 |= AR_IMR_S2_GTT;
3027 if (ints & ATH9K_INT_CST)
3028 mask2 |= AR_IMR_S2_CST;
3031 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__,
3033 REG_WRITE(ah, AR_IMR, mask);
3034 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3036 AR_IMR_S2_DTIMSYNC |
3040 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3041 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3042 ahp->ah_maskReg = ints;
3044 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3045 if (ints & ATH9K_INT_TIM_TIMER)
3046 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3048 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3051 if (ints & ATH9K_INT_GLOBAL) {
3052 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: enable IER\n",
3054 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3055 if (!AR_SREV_9100(ah)) {
3056 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3058 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3061 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3062 AR_INTR_SYNC_DEFAULT);
3063 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3064 AR_INTR_SYNC_DEFAULT);
3066 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3067 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3073 /*******************/
3074 /* Beacon Handling */
3075 /*******************/
3077 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3079 struct ath_hal_5416 *ahp = AH5416(ah);
3082 ahp->ah_beaconInterval = beacon_period;
3084 switch (ah->ah_opmode) {
3086 case ATH9K_M_MONITOR:
3087 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3088 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3089 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3090 flags |= AR_TBTT_TIMER_EN;
3093 REG_SET_BIT(ah, AR_TXCFG,
3094 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3095 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3096 TU_TO_USEC(next_beacon +
3097 (ahp->ah_atimWindow ? ahp->
3098 ah_atimWindow : 1)));
3099 flags |= AR_NDP_TIMER_EN;
3100 case ATH9K_M_HOSTAP:
3101 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3102 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3103 TU_TO_USEC(next_beacon -
3105 dma_beacon_response_time));
3106 REG_WRITE(ah, AR_NEXT_SWBA,
3107 TU_TO_USEC(next_beacon -
3109 sw_beacon_response_time));
3111 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3115 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3116 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3117 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3118 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3120 beacon_period &= ~ATH9K_BEACON_ENA;
3121 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3122 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3123 ath9k_hw_reset_tsf(ah);
3126 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3129 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3130 const struct ath9k_beacon_state *bs)
3132 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3133 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3135 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3137 REG_WRITE(ah, AR_BEACON_PERIOD,
3138 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3139 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3140 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3142 REG_RMW_FIELD(ah, AR_RSSI_THR,
3143 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3145 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3147 if (bs->bs_sleepduration > beaconintval)
3148 beaconintval = bs->bs_sleepduration;
3150 dtimperiod = bs->bs_dtimperiod;
3151 if (bs->bs_sleepduration > dtimperiod)
3152 dtimperiod = bs->bs_sleepduration;
3154 if (beaconintval == dtimperiod)
3155 nextTbtt = bs->bs_nextdtim;
3157 nextTbtt = bs->bs_nexttbtt;
3159 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next DTIM %d\n", __func__,
3161 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next beacon %d\n", __func__,
3163 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: beacon period %d\n", __func__,
3165 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: DTIM period %d\n", __func__,
3168 REG_WRITE(ah, AR_NEXT_DTIM,
3169 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3170 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3172 REG_WRITE(ah, AR_SLEEP1,
3173 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3174 | AR_SLEEP1_ASSUME_DTIM);
3176 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3177 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3179 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3181 REG_WRITE(ah, AR_SLEEP2,
3182 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3184 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3185 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3187 REG_SET_BIT(ah, AR_TIMER_MODE,
3188 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3193 /*******************/
3194 /* HW Capabilities */
3195 /*******************/
3197 bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3199 struct ath_hal_5416 *ahp = AH5416(ah);
3200 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3201 u16 capField = 0, eeval;
3203 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3205 ah->ah_currentRD = eeval;
3207 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3208 ah->ah_currentRDExt = eeval;
3210 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3212 if (ah->ah_opmode != ATH9K_M_HOSTAP &&
3213 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3214 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3215 ah->ah_currentRD += 5;
3216 else if (ah->ah_currentRD == 0x41)
3217 ah->ah_currentRD = 0x43;
3218 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3219 "%s: regdomain mapped to 0x%x\n", __func__,
3223 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3224 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3226 if (eeval & AR5416_OPFLAGS_11A) {
3227 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3228 if (ah->ah_config.ht_enable) {
3229 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3230 set_bit(ATH9K_MODE_11NA_HT20,
3231 pCap->wireless_modes);
3232 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3233 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3234 pCap->wireless_modes);
3235 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3236 pCap->wireless_modes);
3241 if (eeval & AR5416_OPFLAGS_11G) {
3242 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3243 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3244 if (ah->ah_config.ht_enable) {
3245 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3246 set_bit(ATH9K_MODE_11NG_HT20,
3247 pCap->wireless_modes);
3248 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3249 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3250 pCap->wireless_modes);
3251 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3252 pCap->wireless_modes);
3257 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3258 if ((ah->ah_isPciExpress)
3259 || (eeval & AR5416_OPFLAGS_11A)) {
3260 pCap->rx_chainmask =
3261 ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3263 pCap->rx_chainmask =
3264 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3267 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3268 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3270 pCap->low_2ghz_chan = 2312;
3271 pCap->high_2ghz_chan = 2732;
3273 pCap->low_5ghz_chan = 4920;
3274 pCap->high_5ghz_chan = 6100;
3276 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3277 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3278 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3280 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3281 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3282 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3284 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3286 if (ah->ah_config.ht_enable)
3287 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3289 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3291 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3292 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3293 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3294 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3296 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3297 pCap->total_queues =
3298 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3300 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3302 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3303 pCap->keycache_size =
3304 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3306 pCap->keycache_size = AR_KEYTABLE_SIZE;
3308 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3309 pCap->num_mr_retries = 4;
3310 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3312 if (AR_SREV_9280_10_OR_LATER(ah))
3313 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3315 pCap->num_gpio_pins = AR_NUM_GPIO;
3317 if (AR_SREV_9280_10_OR_LATER(ah)) {
3318 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3319 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3321 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3322 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3325 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3326 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3327 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3329 pCap->rts_aggr_limit = (8 * 1024);
3332 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3334 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3335 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3336 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3337 ah->ah_rfkill_gpio =
3338 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3339 ah->ah_rfkill_polarity =
3340 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3342 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3346 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3347 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3348 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3349 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3350 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3351 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3353 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3355 if (AR_SREV_9280(ah))
3356 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3358 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3360 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3362 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3363 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3364 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3365 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3368 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3369 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3372 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3374 pCap->num_antcfg_5ghz =
3375 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_5GHZ);
3376 pCap->num_antcfg_2ghz =
3377 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_2GHZ);
3382 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3383 u32 capability, u32 *result)
3385 struct ath_hal_5416 *ahp = AH5416(ah);
3386 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3389 case ATH9K_CAP_CIPHER:
3390 switch (capability) {
3391 case ATH9K_CIPHER_AES_CCM:
3392 case ATH9K_CIPHER_AES_OCB:
3393 case ATH9K_CIPHER_TKIP:
3394 case ATH9K_CIPHER_WEP:
3395 case ATH9K_CIPHER_MIC:
3396 case ATH9K_CIPHER_CLR:
3401 case ATH9K_CAP_TKIP_MIC:
3402 switch (capability) {
3406 return (ahp->ah_staId1Defaults &
3407 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3410 case ATH9K_CAP_TKIP_SPLIT:
3411 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3413 case ATH9K_CAP_WME_TKIPMIC:
3415 case ATH9K_CAP_PHYCOUNTERS:
3416 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3417 case ATH9K_CAP_DIVERSITY:
3418 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3419 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3421 case ATH9K_CAP_PHYDIAG:
3423 case ATH9K_CAP_MCAST_KEYSRCH:
3424 switch (capability) {
3428 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3431 return (ahp->ah_staId1Defaults &
3432 AR_STA_ID1_MCAST_KSRCH) ? true :
3437 case ATH9K_CAP_TSF_ADJUST:
3438 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3440 case ATH9K_CAP_RFSILENT:
3441 if (capability == 3)
3443 case ATH9K_CAP_ANT_CFG_2GHZ:
3444 *result = pCap->num_antcfg_2ghz;
3446 case ATH9K_CAP_ANT_CFG_5GHZ:
3447 *result = pCap->num_antcfg_5ghz;
3449 case ATH9K_CAP_TXPOW:
3450 switch (capability) {
3454 *result = ah->ah_powerLimit;
3457 *result = ah->ah_maxPowerLevel;
3460 *result = ah->ah_tpScale;
3469 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3470 u32 capability, u32 setting, int *status)
3472 struct ath_hal_5416 *ahp = AH5416(ah);
3476 case ATH9K_CAP_TKIP_MIC:
3478 ahp->ah_staId1Defaults |=
3479 AR_STA_ID1_CRPT_MIC_ENABLE;
3481 ahp->ah_staId1Defaults &=
3482 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3484 case ATH9K_CAP_DIVERSITY:
3485 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3487 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3489 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3490 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3492 case ATH9K_CAP_MCAST_KEYSRCH:
3494 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3496 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3498 case ATH9K_CAP_TSF_ADJUST:
3500 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3502 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3509 /****************************/
3510 /* GPIO / RFKILL / Antennae */
3511 /****************************/
3513 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3517 u32 gpio_shift, tmp;
3520 addr = AR_GPIO_OUTPUT_MUX3;
3522 addr = AR_GPIO_OUTPUT_MUX2;
3524 addr = AR_GPIO_OUTPUT_MUX1;
3526 gpio_shift = (gpio % 6) * 5;
3528 if (AR_SREV_9280_20_OR_LATER(ah)
3529 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3530 REG_RMW(ah, addr, (type << gpio_shift),
3531 (0x1f << gpio_shift));
3533 tmp = REG_READ(ah, addr);
3534 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3535 tmp &= ~(0x1f << gpio_shift);
3536 tmp |= (type << gpio_shift);
3537 REG_WRITE(ah, addr, tmp);
3541 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3545 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3547 gpio_shift = gpio << 1;
3551 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3552 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3555 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3557 if (gpio >= ah->ah_caps.num_gpio_pins)
3560 if (AR_SREV_9280_10_OR_LATER(ah)) {
3562 (REG_READ(ah, AR_GPIO_IN_OUT),
3563 AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
3565 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
3566 AR_GPIO_BIT(gpio)) != 0;
3570 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3575 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3577 gpio_shift = 2 * gpio;
3581 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3582 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3585 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
3587 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3591 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3592 void ath9k_enable_rfkill(struct ath_hal *ah)
3594 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3595 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3597 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3598 AR_GPIO_INPUT_MUX2_RFSILENT);
3600 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3601 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3605 int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
3607 struct ath9k_channel *chan = ah->ah_curchan;
3608 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3610 u32 halNumAntConfig;
3612 halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3613 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
3615 if (cfg < halNumAntConfig) {
3616 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3617 cfg, &ant_config)) {
3618 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3626 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3628 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3631 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
3633 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3636 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3637 enum ath9k_ant_setting settings,
3638 struct ath9k_channel *chan,
3643 struct ath_hal_5416 *ahp = AH5416(ah);
3644 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3646 if (AR_SREV_9280(ah)) {
3647 if (!tx_chainmask_cfg) {
3649 tx_chainmask_cfg = *tx_chainmask;
3650 rx_chainmask_cfg = *rx_chainmask;
3654 case ATH9K_ANT_FIXED_A:
3655 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3656 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3657 *antenna_cfgd = true;
3659 case ATH9K_ANT_FIXED_B:
3660 if (ah->ah_caps.tx_chainmask >
3661 ATH9K_ANTENNA1_CHAINMASK) {
3662 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3664 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3665 *antenna_cfgd = true;
3667 case ATH9K_ANT_VARIABLE:
3668 *tx_chainmask = tx_chainmask_cfg;
3669 *rx_chainmask = rx_chainmask_cfg;
3670 *antenna_cfgd = true;
3676 ahp->ah_diversityControl = settings;
3682 /*********************/
3683 /* General Operation */
3684 /*********************/
3686 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3688 u32 bits = REG_READ(ah, AR_RX_FILTER);
3689 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3691 if (phybits & AR_PHY_ERR_RADAR)
3692 bits |= ATH9K_RX_FILTER_PHYRADAR;
3693 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3694 bits |= ATH9K_RX_FILTER_PHYERR;
3699 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3703 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3705 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3706 phybits |= AR_PHY_ERR_RADAR;
3707 if (bits & ATH9K_RX_FILTER_PHYERR)
3708 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3709 REG_WRITE(ah, AR_PHY_ERR, phybits);
3712 REG_WRITE(ah, AR_RXCFG,
3713 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3715 REG_WRITE(ah, AR_RXCFG,
3716 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3719 bool ath9k_hw_phy_disable(struct ath_hal *ah)
3721 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3724 bool ath9k_hw_disable(struct ath_hal *ah)
3726 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3729 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3732 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3734 struct ath9k_channel *chan = ah->ah_curchan;
3736 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
3738 if (ath9k_hw_set_txpower(ah, chan,
3739 ath9k_regd_get_ctl(ah, chan),
3740 ath9k_regd_get_antenna_allowed(ah, chan),
3741 chan->maxRegTxPower * 2,
3742 min((u32) MAX_RATE_POWER,
3743 (u32) ah->ah_powerLimit)) != 0)
3749 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
3751 struct ath_hal_5416 *ahp = AH5416(ah);
3753 memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
3756 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
3758 struct ath_hal_5416 *ahp = AH5416(ah);
3760 memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3765 void ath9k_hw_setopmode(struct ath_hal *ah)
3767 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3770 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
3772 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3773 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3776 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
3778 struct ath_hal_5416 *ahp = AH5416(ah);
3780 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
3783 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
3785 struct ath_hal_5416 *ahp = AH5416(ah);
3787 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
3789 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3790 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
3795 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
3797 struct ath_hal_5416 *ahp = AH5416(ah);
3799 memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3800 ahp->ah_assocId = assocId;
3802 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3803 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3804 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
3807 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3811 tsf = REG_READ(ah, AR_TSF_U32);
3812 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3817 void ath9k_hw_reset_tsf(struct ath_hal *ah)
3822 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3825 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3826 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n",
3832 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3835 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3837 struct ath_hal_5416 *ahp = AH5416(ah);
3840 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3842 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3847 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3849 struct ath_hal_5416 *ahp = AH5416(ah);
3851 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3852 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n",
3854 ahp->ah_slottime = (u32) -1;
3857 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3858 ahp->ah_slottime = us;
3863 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3867 if (mode == ATH9K_HT_MACMODE_2040 &&
3868 !ah->ah_config.cwm_ignore_extcca)
3869 macmode = AR_2040_JOINED_RX_CLEAR;
3873 REG_WRITE(ah, AR_2040_MODE, macmode);