2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
52 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
53 struct ath_atx_tid *tid, struct sk_buff *skb);
54 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
56 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
57 struct ath_txq *txq, struct list_head *bf_q,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
68 struct ath_atx_tid *tid,
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
82 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
83 __acquires(&txq->axq_lock)
85 spin_lock_bh(&txq->axq_lock);
88 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
89 __releases(&txq->axq_lock)
91 spin_unlock_bh(&txq->axq_lock);
94 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
95 __releases(&txq->axq_lock)
97 struct sk_buff_head q;
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
110 struct ath_atx_ac *ac = tid->ac;
119 list_add_tail(&tid->list, &ac->tid_q);
125 list_add_tail(&ac->list, &txq->axq_acq);
128 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
130 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
131 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
132 sizeof(tx_info->rate_driver_data));
133 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
136 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
138 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
139 seqno << IEEE80211_SEQ_SEQ_SHIFT);
142 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
145 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
146 ARRAY_SIZE(bf->rates));
149 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
154 q = skb_get_queue_mapping(skb);
155 if (txq == sc->tx.uapsdq)
156 txq = sc->tx.txq_map[q];
158 if (txq != sc->tx.txq_map[q])
161 if (WARN_ON(--txq->pending_frames < 0))
162 txq->pending_frames = 0;
165 txq->pending_frames < sc->tx.txq_max_pending[q]) {
166 ieee80211_wake_queue(sc->hw, q);
167 txq->stopped = false;
171 static struct ath_atx_tid *
172 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
174 struct ieee80211_hdr *hdr;
177 hdr = (struct ieee80211_hdr *) skb->data;
178 if (ieee80211_is_data_qos(hdr->frame_control))
179 tidno = ieee80211_get_qos_ctl(hdr)[0];
181 tidno &= IEEE80211_QOS_CTL_TID_MASK;
182 return ATH_AN_2_TID(an, tidno);
185 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
187 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
190 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
194 skb = __skb_dequeue(&tid->retry_q);
196 skb = __skb_dequeue(&tid->buf_q);
201 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
203 struct ath_txq *txq = tid->ac->txq;
206 struct list_head bf_head;
207 struct ath_tx_status ts;
208 struct ath_frame_info *fi;
209 bool sendbar = false;
211 INIT_LIST_HEAD(&bf_head);
213 memset(&ts, 0, sizeof(ts));
215 while ((skb = ath_tid_dequeue(tid))) {
216 fi = get_frame_info(skb);
220 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
222 ath_txq_skb_done(sc, txq, skb);
223 ieee80211_free_txskb(sc->hw, skb);
229 list_add_tail(&bf->list, &bf_head);
230 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
231 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
234 ath_set_rates(tid->an->vif, tid->an->sta, bf);
235 ath_tx_send_normal(sc, txq, NULL, skb);
240 ath_txq_unlock(sc, txq);
241 ath_send_bar(tid, tid->seq_start);
242 ath_txq_lock(sc, txq);
246 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
251 index = ATH_BA_INDEX(tid->seq_start, seqno);
252 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
254 __clear_bit(cindex, tid->tx_buf);
256 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
257 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
258 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
259 if (tid->bar_index >= 0)
264 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
269 index = ATH_BA_INDEX(tid->seq_start, seqno);
270 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
271 __set_bit(cindex, tid->tx_buf);
273 if (index >= ((tid->baw_tail - tid->baw_head) &
274 (ATH_TID_MAX_BUFS - 1))) {
275 tid->baw_tail = cindex;
276 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
281 * TODO: For frame(s) that are in the retry state, we will reuse the
282 * sequence number(s) without setting the retry bit. The
283 * alternative is to give up on these and BAR the receiver's window
286 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
287 struct ath_atx_tid *tid)
292 struct list_head bf_head;
293 struct ath_tx_status ts;
294 struct ath_frame_info *fi;
296 memset(&ts, 0, sizeof(ts));
297 INIT_LIST_HEAD(&bf_head);
299 while ((skb = ath_tid_dequeue(tid))) {
300 fi = get_frame_info(skb);
304 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
308 list_add_tail(&bf->list, &bf_head);
310 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
311 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
314 tid->seq_next = tid->seq_start;
315 tid->baw_tail = tid->baw_head;
319 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
320 struct sk_buff *skb, int count)
322 struct ath_frame_info *fi = get_frame_info(skb);
323 struct ath_buf *bf = fi->bf;
324 struct ieee80211_hdr *hdr;
325 int prev = fi->retries;
327 TX_STAT_INC(txq->axq_qnum, a_retries);
328 fi->retries += count;
333 hdr = (struct ieee80211_hdr *)skb->data;
334 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
335 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
336 sizeof(*hdr), DMA_TO_DEVICE);
339 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
341 struct ath_buf *bf = NULL;
343 spin_lock_bh(&sc->tx.txbuflock);
345 if (unlikely(list_empty(&sc->tx.txbuf))) {
346 spin_unlock_bh(&sc->tx.txbuflock);
350 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
353 spin_unlock_bh(&sc->tx.txbuflock);
358 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
360 spin_lock_bh(&sc->tx.txbuflock);
361 list_add_tail(&bf->list, &sc->tx.txbuf);
362 spin_unlock_bh(&sc->tx.txbuflock);
365 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
369 tbf = ath_tx_get_buffer(sc);
373 ATH_TXBUF_RESET(tbf);
375 tbf->bf_mpdu = bf->bf_mpdu;
376 tbf->bf_buf_addr = bf->bf_buf_addr;
377 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
378 tbf->bf_state = bf->bf_state;
383 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
384 struct ath_tx_status *ts, int txok,
385 int *nframes, int *nbad)
387 struct ath_frame_info *fi;
389 u32 ba[WME_BA_BMP_SIZE >> 5];
396 isaggr = bf_isaggr(bf);
398 seq_st = ts->ts_seqnum;
399 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
403 fi = get_frame_info(bf->bf_mpdu);
404 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
407 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
415 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
416 struct ath_buf *bf, struct list_head *bf_q,
417 struct ath_tx_status *ts, int txok)
419 struct ath_node *an = NULL;
421 struct ieee80211_sta *sta;
422 struct ieee80211_hw *hw = sc->hw;
423 struct ieee80211_hdr *hdr;
424 struct ieee80211_tx_info *tx_info;
425 struct ath_atx_tid *tid = NULL;
426 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
427 struct list_head bf_head;
428 struct sk_buff_head bf_pending;
429 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
430 u32 ba[WME_BA_BMP_SIZE >> 5];
431 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
432 bool rc_update = true, isba;
433 struct ieee80211_tx_rate rates[4];
434 struct ath_frame_info *fi;
436 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
441 hdr = (struct ieee80211_hdr *)skb->data;
443 tx_info = IEEE80211_SKB_CB(skb);
445 memcpy(rates, bf->rates, sizeof(rates));
447 retries = ts->ts_longretry + 1;
448 for (i = 0; i < ts->ts_rateindex; i++)
449 retries += rates[i].count;
453 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
457 INIT_LIST_HEAD(&bf_head);
459 bf_next = bf->bf_next;
461 if (!bf->bf_stale || bf_next != NULL)
462 list_move_tail(&bf->list, &bf_head);
464 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
471 an = (struct ath_node *)sta->drv_priv;
472 tid = ath_get_skb_tid(sc, an, skb);
473 seq_first = tid->seq_start;
474 isba = ts->ts_flags & ATH9K_TX_BA;
477 * The hardware occasionally sends a tx status for the wrong TID.
478 * In this case, the BA status cannot be considered valid and all
479 * subframes need to be retransmitted
481 * Only BlockAcks have a TID and therefore normal Acks cannot be
484 if (isba && tid->tidno != ts->tid)
487 isaggr = bf_isaggr(bf);
488 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
490 if (isaggr && txok) {
491 if (ts->ts_flags & ATH9K_TX_BA) {
492 seq_st = ts->ts_seqnum;
493 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
496 * AR5416 can become deaf/mute when BA
497 * issue happens. Chip needs to be reset.
498 * But AP code may have sychronization issues
499 * when perform internal reset in this routine.
500 * Only enable reset in STA mode for now.
502 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
507 __skb_queue_head_init(&bf_pending);
509 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
511 u16 seqno = bf->bf_state.seqno;
513 txfail = txpending = sendbar = 0;
514 bf_next = bf->bf_next;
517 tx_info = IEEE80211_SKB_CB(skb);
518 fi = get_frame_info(skb);
520 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
522 * Outside of the current BlockAck window,
523 * maybe part of a previous session
526 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
527 /* transmit completion, subframe is
528 * acked by block ack */
530 } else if (!isaggr && txok) {
531 /* transmit completion */
535 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
536 if (txok || !an->sleeping)
537 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
544 bar_index = max_t(int, bar_index,
545 ATH_BA_INDEX(seq_first, seqno));
549 * Make sure the last desc is reclaimed if it
550 * not a holding desc.
552 INIT_LIST_HEAD(&bf_head);
553 if (bf_next != NULL || !bf_last->bf_stale)
554 list_move_tail(&bf->list, &bf_head);
558 * complete the acked-ones/xretried ones; update
561 ath_tx_update_baw(sc, tid, seqno);
563 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
564 memcpy(tx_info->control.rates, rates, sizeof(rates));
565 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
569 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
572 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
573 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
574 ieee80211_sta_eosp(sta);
576 /* retry the un-acked ones */
577 if (bf->bf_next == NULL && bf_last->bf_stale) {
580 tbf = ath_clone_txbuf(sc, bf_last);
582 * Update tx baw and complete the
583 * frame with failed status if we
587 ath_tx_update_baw(sc, tid, seqno);
589 ath_tx_complete_buf(sc, bf, txq,
591 bar_index = max_t(int, bar_index,
592 ATH_BA_INDEX(seq_first, seqno));
600 * Put this buffer to the temporary pending
601 * queue to retain ordering
603 __skb_queue_tail(&bf_pending, skb);
609 /* prepend un-acked frames to the beginning of the pending frame queue */
610 if (!skb_queue_empty(&bf_pending)) {
612 ieee80211_sta_set_buffered(sta, tid->tidno, true);
614 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
616 ath_tx_queue_tid(txq, tid);
618 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
619 tid->ac->clear_ps_filter = true;
623 if (bar_index >= 0) {
624 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
626 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
627 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
629 ath_txq_unlock(sc, txq);
630 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
631 ath_txq_lock(sc, txq);
637 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
640 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
642 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
643 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
646 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
647 struct ath_tx_status *ts, struct ath_buf *bf,
648 struct list_head *bf_head)
650 struct ieee80211_tx_info *info;
653 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
654 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
655 txq->axq_tx_inprogress = false;
658 if (bf_is_ampdu_not_probing(bf))
659 txq->axq_ampdu_depth--;
661 if (!bf_isampdu(bf)) {
663 info = IEEE80211_SKB_CB(bf->bf_mpdu);
664 memcpy(info->control.rates, bf->rates,
665 sizeof(info->control.rates));
666 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
668 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
670 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
672 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) && !flush)
673 ath_txq_schedule(sc, txq);
676 static bool ath_lookup_legacy(struct ath_buf *bf)
679 struct ieee80211_tx_info *tx_info;
680 struct ieee80211_tx_rate *rates;
684 tx_info = IEEE80211_SKB_CB(skb);
685 rates = tx_info->control.rates;
687 for (i = 0; i < 4; i++) {
688 if (!rates[i].count || rates[i].idx < 0)
691 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
698 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
699 struct ath_atx_tid *tid)
702 struct ieee80211_tx_info *tx_info;
703 struct ieee80211_tx_rate *rates;
704 u32 max_4ms_framelen, frmlen;
705 u16 aggr_limit, bt_aggr_limit, legacy = 0;
706 int q = tid->ac->txq->mac80211_qnum;
710 tx_info = IEEE80211_SKB_CB(skb);
714 * Find the lowest frame length among the rate series that will have a
715 * 4ms (or TXOP limited) transmit duration.
717 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
719 for (i = 0; i < 4; i++) {
725 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
730 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
735 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
738 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
739 max_4ms_framelen = min(max_4ms_framelen, frmlen);
743 * limit aggregate size by the minimum rate if rate selected is
744 * not a probe rate, if rate selected is a probe rate then
745 * avoid aggregation of this packet.
747 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
750 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
753 * Override the default aggregation limit for BTCOEX.
755 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
757 aggr_limit = bt_aggr_limit;
760 * h/w can accept aggregates up to 16 bit lengths (65535).
761 * The IE, however can hold up to 65536, which shows up here
762 * as zero. Ignore 65536 since we are constrained by hw.
764 if (tid->an->maxampdu)
765 aggr_limit = min(aggr_limit, tid->an->maxampdu);
771 * Returns the number of delimiters to be added to
772 * meet the minimum required mpdudensity.
774 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
775 struct ath_buf *bf, u16 frmlen,
778 #define FIRST_DESC_NDELIMS 60
779 u32 nsymbits, nsymbols;
782 int width, streams, half_gi, ndelim, mindelim;
783 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
785 /* Select standard number of delimiters based on frame length alone */
786 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
789 * If encryption enabled, hardware requires some more padding between
791 * TODO - this could be improved to be dependent on the rate.
792 * The hardware can keep up at lower rates, but not higher rates
794 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
795 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
796 ndelim += ATH_AGGR_ENCRYPTDELIM;
799 * Add delimiter when using RTS/CTS with aggregation
800 * and non enterprise AR9003 card
802 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
803 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
804 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
807 * Convert desired mpdu density from microeconds to bytes based
808 * on highest rate in rate series (i.e. first rate) to determine
809 * required minimum length for subframe. Take into account
810 * whether high rate is 20 or 40Mhz and half or full GI.
812 * If there is no mpdu density restriction, no further calculation
816 if (tid->an->mpdudensity == 0)
819 rix = bf->rates[0].idx;
820 flags = bf->rates[0].flags;
821 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
822 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
825 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
827 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
832 streams = HT_RC_2_STREAMS(rix);
833 nsymbits = bits_per_symbol[rix % 8][width] * streams;
834 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
836 if (frmlen < minlen) {
837 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
838 ndelim = max(mindelim, ndelim);
844 static struct ath_buf *
845 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
846 struct ath_atx_tid *tid, struct sk_buff_head **q)
848 struct ath_frame_info *fi;
855 if (skb_queue_empty(*q))
862 fi = get_frame_info(skb);
865 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
868 __skb_unlink(skb, *q);
869 ath_txq_skb_done(sc, txq, skb);
870 ieee80211_free_txskb(sc->hw, skb);
874 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
875 seqno = bf->bf_state.seqno;
877 /* do not step over block-ack window */
878 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
881 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
882 struct ath_tx_status ts = {};
883 struct list_head bf_head;
885 INIT_LIST_HEAD(&bf_head);
886 list_add(&bf->list, &bf_head);
887 __skb_unlink(skb, *q);
888 ath_tx_update_baw(sc, tid, seqno);
889 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
901 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
903 struct ath_atx_tid *tid,
904 struct list_head *bf_q,
907 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
908 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
909 int nframes = 0, ndelim;
910 u16 aggr_limit = 0, al = 0, bpad = 0,
911 al_delta, h_baw = tid->baw_size / 2;
912 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
913 struct ieee80211_tx_info *tx_info;
914 struct ath_frame_info *fi;
916 struct sk_buff_head *tid_q;
919 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
921 status = ATH_AGGR_BAW_CLOSED;
926 fi = get_frame_info(skb);
930 ath_set_rates(tid->an->vif, tid->an->sta, bf);
931 aggr_limit = ath_lookup_rate(sc, bf, tid);
934 /* do not exceed aggregation limit */
935 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
937 if (aggr_limit < al + bpad + al_delta ||
938 ath_lookup_legacy(bf) || nframes >= h_baw) {
939 status = ATH_AGGR_LIMITED;
943 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
944 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
948 /* add padding for previous frame to aggregation length */
949 al += bpad + al_delta;
952 * Get the delimiters needed to meet the MPDU
953 * density for this node.
955 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
957 bpad = PADBYTES(al_delta) + (ndelim << 2);
962 /* link buffers of this frame to the aggregate */
964 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
965 bf->bf_state.ndelim = ndelim;
967 __skb_unlink(skb, tid_q);
968 list_add_tail(&bf->list, bf_q);
970 bf_prev->bf_next = bf;
974 } while (ath_tid_has_buffered(tid));
984 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
985 * width - 0 for 20 MHz, 1 for 40 MHz
986 * half_gi - to use 4us v/s 3.6 us for symbol time
988 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
989 int width, int half_gi, bool shortPreamble)
991 u32 nbits, nsymbits, duration, nsymbols;
994 /* find number of symbols: PLCP + data */
995 streams = HT_RC_2_STREAMS(rix);
996 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
997 nsymbits = bits_per_symbol[rix % 8][width] * streams;
998 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1001 duration = SYMBOL_TIME(nsymbols);
1003 duration = SYMBOL_TIME_HALFGI(nsymbols);
1005 /* addup duration for legacy/ht training and signal fields */
1006 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1011 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1013 int streams = HT_RC_2_STREAMS(mcs);
1017 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1018 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1019 bits -= OFDM_PLCP_BITS;
1021 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1028 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1030 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1033 /* 4ms is the default (and maximum) duration */
1034 if (!txop || txop > 4096)
1037 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1038 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1039 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1040 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1041 for (mcs = 0; mcs < 32; mcs++) {
1042 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1043 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1044 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1045 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1049 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1050 struct ath_tx_info *info, int len, bool rts)
1052 struct ath_hw *ah = sc->sc_ah;
1053 struct sk_buff *skb;
1054 struct ieee80211_tx_info *tx_info;
1055 struct ieee80211_tx_rate *rates;
1056 const struct ieee80211_rate *rate;
1057 struct ieee80211_hdr *hdr;
1058 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1059 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1064 tx_info = IEEE80211_SKB_CB(skb);
1066 hdr = (struct ieee80211_hdr *)skb->data;
1068 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1069 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1070 info->rtscts_rate = fi->rtscts_rate;
1072 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1073 bool is_40, is_sgi, is_sp;
1076 if (!rates[i].count || (rates[i].idx < 0))
1080 info->rates[i].Tries = rates[i].count;
1083 * Handle RTS threshold for unaggregated HT frames.
1085 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1086 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1087 unlikely(rts_thresh != (u32) -1)) {
1088 if (!rts_thresh || (len > rts_thresh))
1092 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1093 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1094 info->flags |= ATH9K_TXDESC_RTSENA;
1095 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1096 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1097 info->flags |= ATH9K_TXDESC_CTSENA;
1100 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1101 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1102 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1103 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1105 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1106 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1107 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1109 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1111 info->rates[i].Rate = rix | 0x80;
1112 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1113 ah->txchainmask, info->rates[i].Rate);
1114 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1115 is_40, is_sgi, is_sp);
1116 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1117 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1122 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1123 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1124 !(rate->flags & IEEE80211_RATE_ERP_G))
1125 phy = WLAN_RC_PHY_CCK;
1127 phy = WLAN_RC_PHY_OFDM;
1129 info->rates[i].Rate = rate->hw_value;
1130 if (rate->hw_value_short) {
1131 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1132 info->rates[i].Rate |= rate->hw_value_short;
1137 if (bf->bf_state.bfs_paprd)
1138 info->rates[i].ChSel = ah->txchainmask;
1140 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1141 ah->txchainmask, info->rates[i].Rate);
1143 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1144 phy, rate->bitrate * 100, len, rix, is_sp);
1147 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1148 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1149 info->flags &= ~ATH9K_TXDESC_RTSENA;
1151 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1152 if (info->flags & ATH9K_TXDESC_RTSENA)
1153 info->flags &= ~ATH9K_TXDESC_CTSENA;
1156 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1158 struct ieee80211_hdr *hdr;
1159 enum ath9k_pkt_type htype;
1162 hdr = (struct ieee80211_hdr *)skb->data;
1163 fc = hdr->frame_control;
1165 if (ieee80211_is_beacon(fc))
1166 htype = ATH9K_PKT_TYPE_BEACON;
1167 else if (ieee80211_is_probe_resp(fc))
1168 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1169 else if (ieee80211_is_atim(fc))
1170 htype = ATH9K_PKT_TYPE_ATIM;
1171 else if (ieee80211_is_pspoll(fc))
1172 htype = ATH9K_PKT_TYPE_PSPOLL;
1174 htype = ATH9K_PKT_TYPE_NORMAL;
1179 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1180 struct ath_txq *txq, int len)
1182 struct ath_hw *ah = sc->sc_ah;
1183 struct ath_buf *bf_first = NULL;
1184 struct ath_tx_info info;
1185 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1188 memset(&info, 0, sizeof(info));
1189 info.is_first = true;
1190 info.is_last = true;
1191 info.txpower = MAX_RATE_POWER;
1192 info.qcu = txq->axq_qnum;
1195 struct sk_buff *skb = bf->bf_mpdu;
1196 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1197 struct ath_frame_info *fi = get_frame_info(skb);
1198 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1200 info.type = get_hw_packet_type(skb);
1202 info.link = bf->bf_next->bf_daddr;
1209 info.flags = ATH9K_TXDESC_INTREQ;
1210 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1211 txq == sc->tx.uapsdq)
1212 info.flags |= ATH9K_TXDESC_CLRDMASK;
1214 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1215 info.flags |= ATH9K_TXDESC_NOACK;
1216 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1217 info.flags |= ATH9K_TXDESC_LDPC;
1219 if (bf->bf_state.bfs_paprd)
1220 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1221 ATH9K_TXDESC_PAPRD_S;
1224 * mac80211 doesn't handle RTS threshold for HT because
1225 * the decision has to be taken based on AMPDU length
1226 * and aggregation is done entirely inside ath9k.
1227 * Set the RTS/CTS flag for the first subframe based
1230 if (aggr && (bf == bf_first) &&
1231 unlikely(rts_thresh != (u32) -1)) {
1233 * "len" is the size of the entire AMPDU.
1235 if (!rts_thresh || (len > rts_thresh))
1238 ath_buf_set_rate(sc, bf, &info, len, rts);
1241 info.buf_addr[0] = bf->bf_buf_addr;
1242 info.buf_len[0] = skb->len;
1243 info.pkt_len = fi->framelen;
1244 info.keyix = fi->keyix;
1245 info.keytype = fi->keytype;
1249 info.aggr = AGGR_BUF_FIRST;
1250 else if (bf == bf_first->bf_lastbf)
1251 info.aggr = AGGR_BUF_LAST;
1253 info.aggr = AGGR_BUF_MIDDLE;
1255 info.ndelim = bf->bf_state.ndelim;
1256 info.aggr_len = len;
1259 if (bf == bf_first->bf_lastbf)
1262 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1267 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1268 struct ath_atx_tid *tid)
1271 enum ATH_AGGR_STATUS status;
1272 struct ieee80211_tx_info *tx_info;
1273 struct list_head bf_q;
1277 if (!ath_tid_has_buffered(tid))
1280 INIT_LIST_HEAD(&bf_q);
1282 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1285 * no frames picked up to be aggregated;
1286 * block-ack window is not open.
1288 if (list_empty(&bf_q))
1291 bf = list_first_entry(&bf_q, struct ath_buf, list);
1292 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1293 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1295 if (tid->ac->clear_ps_filter) {
1296 tid->ac->clear_ps_filter = false;
1297 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1299 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1302 /* if only one frame, send as non-aggregate */
1303 if (bf == bf->bf_lastbf) {
1304 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1305 bf->bf_state.bf_type = BUF_AMPDU;
1307 TX_STAT_INC(txq->axq_qnum, a_aggr);
1310 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1311 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1312 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1313 status != ATH_AGGR_BAW_CLOSED);
1316 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1319 struct ath_atx_tid *txtid;
1320 struct ath_node *an;
1323 an = (struct ath_node *)sta->drv_priv;
1324 txtid = ATH_AN_2_TID(an, tid);
1326 /* update ampdu factor/density, they may have changed. This may happen
1327 * in HT IBSS when a beacon with HT-info is received after the station
1328 * has already been added.
1330 if (sta->ht_cap.ht_supported) {
1331 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1332 sta->ht_cap.ampdu_factor);
1333 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1334 an->mpdudensity = density;
1337 txtid->active = true;
1338 txtid->paused = true;
1339 *ssn = txtid->seq_start = txtid->seq_next;
1340 txtid->bar_index = -1;
1342 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1343 txtid->baw_head = txtid->baw_tail = 0;
1348 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1350 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1351 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1352 struct ath_txq *txq = txtid->ac->txq;
1354 ath_txq_lock(sc, txq);
1355 txtid->active = false;
1356 txtid->paused = true;
1357 ath_tx_flush_tid(sc, txtid);
1358 ath_txq_unlock_complete(sc, txq);
1361 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1362 struct ath_node *an)
1364 struct ath_atx_tid *tid;
1365 struct ath_atx_ac *ac;
1366 struct ath_txq *txq;
1370 for (tidno = 0, tid = &an->tid[tidno];
1371 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1379 ath_txq_lock(sc, txq);
1381 buffered = ath_tid_has_buffered(tid);
1384 list_del(&tid->list);
1388 list_del(&ac->list);
1391 ath_txq_unlock(sc, txq);
1393 ieee80211_sta_set_buffered(sta, tidno, buffered);
1397 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1399 struct ath_atx_tid *tid;
1400 struct ath_atx_ac *ac;
1401 struct ath_txq *txq;
1404 for (tidno = 0, tid = &an->tid[tidno];
1405 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1410 ath_txq_lock(sc, txq);
1411 ac->clear_ps_filter = true;
1413 if (!tid->paused && ath_tid_has_buffered(tid)) {
1414 ath_tx_queue_tid(txq, tid);
1415 ath_txq_schedule(sc, txq);
1418 ath_txq_unlock_complete(sc, txq);
1422 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1425 struct ath_atx_tid *tid;
1426 struct ath_node *an;
1427 struct ath_txq *txq;
1429 an = (struct ath_node *)sta->drv_priv;
1430 tid = ATH_AN_2_TID(an, tidno);
1433 ath_txq_lock(sc, txq);
1435 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1436 tid->paused = false;
1438 if (ath_tid_has_buffered(tid)) {
1439 ath_tx_queue_tid(txq, tid);
1440 ath_txq_schedule(sc, txq);
1443 ath_txq_unlock_complete(sc, txq);
1446 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1447 struct ieee80211_sta *sta,
1448 u16 tids, int nframes,
1449 enum ieee80211_frame_release_type reason,
1452 struct ath_softc *sc = hw->priv;
1453 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1454 struct ath_txq *txq = sc->tx.uapsdq;
1455 struct ieee80211_tx_info *info;
1456 struct list_head bf_q;
1457 struct ath_buf *bf_tail = NULL, *bf;
1458 struct sk_buff_head *tid_q;
1462 INIT_LIST_HEAD(&bf_q);
1463 for (i = 0; tids && nframes; i++, tids >>= 1) {
1464 struct ath_atx_tid *tid;
1469 tid = ATH_AN_2_TID(an, i);
1473 ath_txq_lock(sc, tid->ac->txq);
1474 while (nframes > 0) {
1475 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1479 __skb_unlink(bf->bf_mpdu, tid_q);
1480 list_add_tail(&bf->list, &bf_q);
1481 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1482 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1483 bf->bf_state.bf_type &= ~BUF_AGGR;
1485 bf_tail->bf_next = bf;
1490 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1492 if (!ath_tid_has_buffered(tid))
1493 ieee80211_sta_set_buffered(an->sta, i, false);
1495 ath_txq_unlock_complete(sc, tid->ac->txq);
1498 if (list_empty(&bf_q))
1501 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1502 info->flags |= IEEE80211_TX_STATUS_EOSP;
1504 bf = list_first_entry(&bf_q, struct ath_buf, list);
1505 ath_txq_lock(sc, txq);
1506 ath_tx_fill_desc(sc, bf, txq, 0);
1507 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1508 ath_txq_unlock(sc, txq);
1511 /********************/
1512 /* Queue Management */
1513 /********************/
1515 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1517 struct ath_hw *ah = sc->sc_ah;
1518 struct ath9k_tx_queue_info qi;
1519 static const int subtype_txq_to_hwq[] = {
1520 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1521 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1522 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1523 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1527 memset(&qi, 0, sizeof(qi));
1528 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1529 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1530 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1531 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1532 qi.tqi_physCompBuf = 0;
1535 * Enable interrupts only for EOL and DESC conditions.
1536 * We mark tx descriptors to receive a DESC interrupt
1537 * when a tx queue gets deep; otherwise waiting for the
1538 * EOL to reap descriptors. Note that this is done to
1539 * reduce interrupt load and this only defers reaping
1540 * descriptors, never transmitting frames. Aside from
1541 * reducing interrupts this also permits more concurrency.
1542 * The only potential downside is if the tx queue backs
1543 * up in which case the top half of the kernel may backup
1544 * due to a lack of tx descriptors.
1546 * The UAPSD queue is an exception, since we take a desc-
1547 * based intr on the EOSP frames.
1549 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1550 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1552 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1553 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1555 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1556 TXQ_FLAG_TXDESCINT_ENABLE;
1558 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1559 if (axq_qnum == -1) {
1561 * NB: don't print a message, this happens
1562 * normally on parts with too few tx queues
1566 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1567 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1569 txq->axq_qnum = axq_qnum;
1570 txq->mac80211_qnum = -1;
1571 txq->axq_link = NULL;
1572 __skb_queue_head_init(&txq->complete_q);
1573 INIT_LIST_HEAD(&txq->axq_q);
1574 INIT_LIST_HEAD(&txq->axq_acq);
1575 spin_lock_init(&txq->axq_lock);
1577 txq->axq_ampdu_depth = 0;
1578 txq->axq_tx_inprogress = false;
1579 sc->tx.txqsetup |= 1<<axq_qnum;
1581 txq->txq_headidx = txq->txq_tailidx = 0;
1582 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1583 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1585 return &sc->tx.txq[axq_qnum];
1588 int ath_txq_update(struct ath_softc *sc, int qnum,
1589 struct ath9k_tx_queue_info *qinfo)
1591 struct ath_hw *ah = sc->sc_ah;
1593 struct ath9k_tx_queue_info qi;
1595 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1597 ath9k_hw_get_txq_props(ah, qnum, &qi);
1598 qi.tqi_aifs = qinfo->tqi_aifs;
1599 qi.tqi_cwmin = qinfo->tqi_cwmin;
1600 qi.tqi_cwmax = qinfo->tqi_cwmax;
1601 qi.tqi_burstTime = qinfo->tqi_burstTime;
1602 qi.tqi_readyTime = qinfo->tqi_readyTime;
1604 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1605 ath_err(ath9k_hw_common(sc->sc_ah),
1606 "Unable to update hardware queue %u!\n", qnum);
1609 ath9k_hw_resettxqueue(ah, qnum);
1615 int ath_cabq_update(struct ath_softc *sc)
1617 struct ath9k_tx_queue_info qi;
1618 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1619 int qnum = sc->beacon.cabq->axq_qnum;
1621 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1623 * Ensure the readytime % is within the bounds.
1625 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1626 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1627 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1628 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1630 qi.tqi_readyTime = (cur_conf->beacon_interval *
1631 sc->config.cabqReadytime) / 100;
1632 ath_txq_update(sc, qnum, &qi);
1637 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1638 struct list_head *list)
1640 struct ath_buf *bf, *lastbf;
1641 struct list_head bf_head;
1642 struct ath_tx_status ts;
1644 memset(&ts, 0, sizeof(ts));
1645 ts.ts_status = ATH9K_TX_FLUSH;
1646 INIT_LIST_HEAD(&bf_head);
1648 while (!list_empty(list)) {
1649 bf = list_first_entry(list, struct ath_buf, list);
1652 list_del(&bf->list);
1654 ath_tx_return_buffer(sc, bf);
1658 lastbf = bf->bf_lastbf;
1659 list_cut_position(&bf_head, list, &lastbf->list);
1660 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1665 * Drain a given TX queue (could be Beacon or Data)
1667 * This assumes output has been stopped and
1668 * we do not need to block ath_tx_tasklet.
1670 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1672 ath_txq_lock(sc, txq);
1674 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1675 int idx = txq->txq_tailidx;
1677 while (!list_empty(&txq->txq_fifo[idx])) {
1678 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1680 INCR(idx, ATH_TXFIFO_DEPTH);
1682 txq->txq_tailidx = idx;
1685 txq->axq_link = NULL;
1686 txq->axq_tx_inprogress = false;
1687 ath_drain_txq_list(sc, txq, &txq->axq_q);
1689 ath_txq_unlock_complete(sc, txq);
1692 bool ath_drain_all_txq(struct ath_softc *sc)
1694 struct ath_hw *ah = sc->sc_ah;
1695 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1696 struct ath_txq *txq;
1700 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1703 ath9k_hw_abort_tx_dma(ah);
1705 /* Check if any queue remains active */
1706 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1707 if (!ATH_TXQ_SETUP(sc, i))
1710 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1715 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1717 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1718 if (!ATH_TXQ_SETUP(sc, i))
1722 * The caller will resume queues with ieee80211_wake_queues.
1723 * Mark the queue as not stopped to prevent ath_tx_complete
1724 * from waking the queue too early.
1726 txq = &sc->tx.txq[i];
1727 txq->stopped = false;
1728 ath_draintxq(sc, txq);
1734 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1736 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1737 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1740 /* For each axq_acq entry, for each tid, try to schedule packets
1741 * for transmit until ampdu_depth has reached min Q depth.
1743 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1745 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1746 struct ath_atx_tid *tid, *last_tid;
1748 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1749 list_empty(&txq->axq_acq) ||
1750 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1755 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1756 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1758 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1759 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1760 list_del(&ac->list);
1763 while (!list_empty(&ac->tid_q)) {
1764 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1766 list_del(&tid->list);
1772 ath_tx_sched_aggr(sc, txq, tid);
1775 * add tid to round-robin queue if more frames
1776 * are pending for the tid
1778 if (ath_tid_has_buffered(tid))
1779 ath_tx_queue_tid(txq, tid);
1781 if (tid == last_tid ||
1782 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1786 if (!list_empty(&ac->tid_q) && !ac->sched) {
1788 list_add_tail(&ac->list, &txq->axq_acq);
1791 if (ac == last_ac ||
1792 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1804 * Insert a chain of ath_buf (descriptors) on a txq and
1805 * assume the descriptors are already chained together by caller.
1807 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1808 struct list_head *head, bool internal)
1810 struct ath_hw *ah = sc->sc_ah;
1811 struct ath_common *common = ath9k_hw_common(ah);
1812 struct ath_buf *bf, *bf_last;
1813 bool puttxbuf = false;
1817 * Insert the frame on the outbound list and
1818 * pass it on to the hardware.
1821 if (list_empty(head))
1824 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1825 bf = list_first_entry(head, struct ath_buf, list);
1826 bf_last = list_entry(head->prev, struct ath_buf, list);
1828 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1829 txq->axq_qnum, txq->axq_depth);
1831 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1832 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1833 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1836 list_splice_tail_init(head, &txq->axq_q);
1838 if (txq->axq_link) {
1839 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1840 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1841 txq->axq_qnum, txq->axq_link,
1842 ito64(bf->bf_daddr), bf->bf_desc);
1846 txq->axq_link = bf_last->bf_desc;
1850 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1851 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1852 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1853 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1857 TX_STAT_INC(txq->axq_qnum, txstart);
1858 ath9k_hw_txstart(ah, txq->axq_qnum);
1864 if (bf_is_ampdu_not_probing(bf))
1865 txq->axq_ampdu_depth++;
1867 bf = bf->bf_lastbf->bf_next;
1872 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_txq *txq,
1873 struct ath_atx_tid *tid, struct sk_buff *skb,
1874 struct ath_tx_control *txctl)
1876 struct ath_frame_info *fi = get_frame_info(skb);
1877 struct list_head bf_head;
1881 * Do not queue to h/w when any of the following conditions is true:
1882 * - there are pending frames in software queue
1883 * - the TID is currently paused for ADDBA/BAR request
1884 * - seqno is not within block-ack window
1885 * - h/w queue depth exceeds low water mark
1887 if ((ath_tid_has_buffered(tid) || tid->paused ||
1888 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1889 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) &&
1890 txq != sc->tx.uapsdq) {
1892 * Add this frame to software queue for scheduling later
1895 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
1896 __skb_queue_tail(&tid->buf_q, skb);
1897 if (!txctl->an || !txctl->an->sleeping)
1898 ath_tx_queue_tid(txq, tid);
1902 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
1904 ath_txq_skb_done(sc, txq, skb);
1905 ieee80211_free_txskb(sc->hw, skb);
1909 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1910 bf->bf_state.bf_type = BUF_AMPDU;
1911 INIT_LIST_HEAD(&bf_head);
1912 list_add(&bf->list, &bf_head);
1914 /* Add sub-frame to BAW */
1915 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1917 /* Queue to h/w without aggregation */
1918 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1920 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1921 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1924 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1925 struct ath_atx_tid *tid, struct sk_buff *skb)
1927 struct ath_frame_info *fi = get_frame_info(skb);
1928 struct list_head bf_head;
1933 INIT_LIST_HEAD(&bf_head);
1934 list_add_tail(&bf->list, &bf_head);
1935 bf->bf_state.bf_type = 0;
1939 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1940 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1941 TX_STAT_INC(txq->axq_qnum, queued);
1944 static void setup_frame_info(struct ieee80211_hw *hw,
1945 struct ieee80211_sta *sta,
1946 struct sk_buff *skb,
1949 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1950 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1951 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1952 const struct ieee80211_rate *rate;
1953 struct ath_frame_info *fi = get_frame_info(skb);
1954 struct ath_node *an = NULL;
1955 enum ath9k_key_type keytype;
1956 bool short_preamble = false;
1959 * We check if Short Preamble is needed for the CTS rate by
1960 * checking the BSS's global flag.
1961 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1963 if (tx_info->control.vif &&
1964 tx_info->control.vif->bss_conf.use_short_preamble)
1965 short_preamble = true;
1967 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
1968 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1971 an = (struct ath_node *) sta->drv_priv;
1973 memset(fi, 0, sizeof(*fi));
1975 fi->keyix = hw_key->hw_key_idx;
1976 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1977 fi->keyix = an->ps_key;
1979 fi->keyix = ATH9K_TXKEYIX_INVALID;
1980 fi->keytype = keytype;
1981 fi->framelen = framelen;
1982 fi->rtscts_rate = rate->hw_value;
1984 fi->rtscts_rate |= rate->hw_value_short;
1987 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1989 struct ath_hw *ah = sc->sc_ah;
1990 struct ath9k_channel *curchan = ah->curchan;
1992 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1993 (curchan->channelFlags & CHANNEL_5GHZ) &&
1994 (chainmask == 0x7) && (rate < 0x90))
1996 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2004 * Assign a descriptor (and sequence number if necessary,
2005 * and map buffer for DMA. Frees skb on error
2007 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2008 struct ath_txq *txq,
2009 struct ath_atx_tid *tid,
2010 struct sk_buff *skb)
2012 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2013 struct ath_frame_info *fi = get_frame_info(skb);
2014 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2019 bf = ath_tx_get_buffer(sc);
2021 ath_dbg(common, XMIT, "TX buffers are full\n");
2025 ATH_TXBUF_RESET(bf);
2028 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2029 seqno = tid->seq_next;
2030 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2033 hdr->seq_ctrl |= cpu_to_le16(fragno);
2035 if (!ieee80211_has_morefrags(hdr->frame_control))
2036 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2038 bf->bf_state.seqno = seqno;
2043 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2044 skb->len, DMA_TO_DEVICE);
2045 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2047 bf->bf_buf_addr = 0;
2048 ath_err(ath9k_hw_common(sc->sc_ah),
2049 "dma_mapping_error() on TX\n");
2050 ath_tx_return_buffer(sc, bf);
2059 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2060 struct ath_tx_control *txctl)
2062 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2063 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2064 struct ieee80211_sta *sta = txctl->sta;
2065 struct ieee80211_vif *vif = info->control.vif;
2066 struct ath_softc *sc = hw->priv;
2067 int frmlen = skb->len + FCS_LEN;
2068 int padpos, padsize;
2070 /* NOTE: sta can be NULL according to net/mac80211.h */
2072 txctl->an = (struct ath_node *)sta->drv_priv;
2074 if (info->control.hw_key)
2075 frmlen += info->control.hw_key->icv_len;
2078 * As a temporary workaround, assign seq# here; this will likely need
2079 * to be cleaned up to work better with Beacon transmission and virtual
2082 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2083 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2084 sc->tx.seq_no += 0x10;
2085 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2086 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2089 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2090 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2091 !ieee80211_is_data(hdr->frame_control))
2092 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2094 /* Add the padding after the header if this is not already done */
2095 padpos = ieee80211_hdrlen(hdr->frame_control);
2096 padsize = padpos & 3;
2097 if (padsize && skb->len > padpos) {
2098 if (skb_headroom(skb) < padsize)
2101 skb_push(skb, padsize);
2102 memmove(skb->data, skb->data + padsize, padpos);
2105 setup_frame_info(hw, sta, skb, frmlen);
2110 /* Upon failure caller should free skb */
2111 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2112 struct ath_tx_control *txctl)
2114 struct ieee80211_hdr *hdr;
2115 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2116 struct ieee80211_sta *sta = txctl->sta;
2117 struct ieee80211_vif *vif = info->control.vif;
2118 struct ath_softc *sc = hw->priv;
2119 struct ath_txq *txq = txctl->txq;
2120 struct ath_atx_tid *tid = NULL;
2125 ret = ath_tx_prepare(hw, skb, txctl);
2129 hdr = (struct ieee80211_hdr *) skb->data;
2131 * At this point, the vif, hw_key and sta pointers in the tx control
2132 * info are no longer valid (overwritten by the ath_frame_info data.
2135 q = skb_get_queue_mapping(skb);
2137 ath_txq_lock(sc, txq);
2138 if (txq == sc->tx.txq_map[q] &&
2139 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2141 ieee80211_stop_queue(sc->hw, q);
2142 txq->stopped = true;
2145 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2146 ath_txq_unlock(sc, txq);
2147 txq = sc->tx.uapsdq;
2148 ath_txq_lock(sc, txq);
2151 if (txctl->an && ieee80211_is_data_qos(hdr->frame_control)) {
2152 tid = ath_get_skb_tid(sc, txctl->an, skb);
2154 WARN_ON(tid->ac->txq != txctl->txq);
2157 if ((info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
2159 * Try aggregation if it's a unicast data frame
2160 * and the destination is HT capable.
2162 ath_tx_send_ampdu(sc, txq, tid, skb, txctl);
2166 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2168 ath_txq_skb_done(sc, txq, skb);
2170 dev_kfree_skb_any(skb);
2172 ieee80211_free_txskb(sc->hw, skb);
2176 bf->bf_state.bfs_paprd = txctl->paprd;
2179 bf->bf_state.bfs_paprd_timestamp = jiffies;
2181 ath_set_rates(vif, sta, bf);
2182 ath_tx_send_normal(sc, txq, tid, skb);
2185 ath_txq_unlock(sc, txq);
2190 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2191 struct sk_buff *skb)
2193 struct ath_softc *sc = hw->priv;
2194 struct ath_tx_control txctl = {
2195 .txq = sc->beacon.cabq
2197 struct ath_tx_info info = {};
2198 struct ieee80211_hdr *hdr;
2199 struct ath_buf *bf_tail = NULL;
2206 sc->cur_beacon_conf.beacon_interval * 1000 *
2207 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2210 struct ath_frame_info *fi = get_frame_info(skb);
2212 if (ath_tx_prepare(hw, skb, &txctl))
2215 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2220 ath_set_rates(vif, NULL, bf);
2221 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2222 duration += info.rates[0].PktDuration;
2224 bf_tail->bf_next = bf;
2226 list_add_tail(&bf->list, &bf_q);
2230 if (duration > max_duration)
2233 skb = ieee80211_get_buffered_bc(hw, vif);
2237 ieee80211_free_txskb(hw, skb);
2239 if (list_empty(&bf_q))
2242 bf = list_first_entry(&bf_q, struct ath_buf, list);
2243 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2245 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2246 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2247 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2248 sizeof(*hdr), DMA_TO_DEVICE);
2251 ath_txq_lock(sc, txctl.txq);
2252 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2253 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2254 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2255 ath_txq_unlock(sc, txctl.txq);
2262 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2263 int tx_flags, struct ath_txq *txq)
2265 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2266 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2267 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2268 int padpos, padsize;
2269 unsigned long flags;
2271 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2273 if (sc->sc_ah->caldata)
2274 sc->sc_ah->caldata->paprd_packet_sent = true;
2276 if (!(tx_flags & ATH_TX_ERROR))
2277 /* Frame was ACKed */
2278 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2280 padpos = ieee80211_hdrlen(hdr->frame_control);
2281 padsize = padpos & 3;
2282 if (padsize && skb->len>padpos+padsize) {
2284 * Remove MAC header padding before giving the frame back to
2287 memmove(skb->data + padsize, skb->data, padpos);
2288 skb_pull(skb, padsize);
2291 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2292 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2293 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2295 "Going back to sleep after having received TX status (0x%lx)\n",
2296 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2298 PS_WAIT_FOR_PSPOLL_DATA |
2299 PS_WAIT_FOR_TX_ACK));
2301 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2303 __skb_queue_tail(&txq->complete_q, skb);
2304 ath_txq_skb_done(sc, txq, skb);
2307 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2308 struct ath_txq *txq, struct list_head *bf_q,
2309 struct ath_tx_status *ts, int txok)
2311 struct sk_buff *skb = bf->bf_mpdu;
2312 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2313 unsigned long flags;
2317 tx_flags |= ATH_TX_ERROR;
2319 if (ts->ts_status & ATH9K_TXERR_FILT)
2320 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2322 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2323 bf->bf_buf_addr = 0;
2325 if (bf->bf_state.bfs_paprd) {
2326 if (time_after(jiffies,
2327 bf->bf_state.bfs_paprd_timestamp +
2328 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2329 dev_kfree_skb_any(skb);
2331 complete(&sc->paprd_complete);
2333 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2334 ath_tx_complete(sc, skb, tx_flags, txq);
2336 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2337 * accidentally reference it later.
2342 * Return the list of ath_buf of this mpdu to free queue
2344 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2345 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2346 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2349 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2350 struct ath_tx_status *ts, int nframes, int nbad,
2353 struct sk_buff *skb = bf->bf_mpdu;
2354 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2355 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2356 struct ieee80211_hw *hw = sc->hw;
2357 struct ath_hw *ah = sc->sc_ah;
2361 tx_info->status.ack_signal = ts->ts_rssi;
2363 tx_rateindex = ts->ts_rateindex;
2364 WARN_ON(tx_rateindex >= hw->max_rates);
2366 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2367 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2369 BUG_ON(nbad > nframes);
2371 tx_info->status.ampdu_len = nframes;
2372 tx_info->status.ampdu_ack_len = nframes - nbad;
2374 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2375 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2377 * If an underrun error is seen assume it as an excessive
2378 * retry only if max frame trigger level has been reached
2379 * (2 KB for single stream, and 4 KB for dual stream).
2380 * Adjust the long retry as if the frame was tried
2381 * hw->max_rate_tries times to affect how rate control updates
2382 * PER for the failed rate.
2383 * In case of congestion on the bus penalizing this type of
2384 * underruns should help hardware actually transmit new frames
2385 * successfully by eventually preferring slower rates.
2386 * This itself should also alleviate congestion on the bus.
2388 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2389 ATH9K_TX_DELIM_UNDERRUN)) &&
2390 ieee80211_is_data(hdr->frame_control) &&
2391 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2392 tx_info->status.rates[tx_rateindex].count =
2396 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2397 tx_info->status.rates[i].count = 0;
2398 tx_info->status.rates[i].idx = -1;
2401 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2404 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2406 struct ath_hw *ah = sc->sc_ah;
2407 struct ath_common *common = ath9k_hw_common(ah);
2408 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2409 struct list_head bf_head;
2410 struct ath_desc *ds;
2411 struct ath_tx_status ts;
2414 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2415 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2418 ath_txq_lock(sc, txq);
2420 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2423 if (list_empty(&txq->axq_q)) {
2424 txq->axq_link = NULL;
2425 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2426 ath_txq_schedule(sc, txq);
2429 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2432 * There is a race condition that a BH gets scheduled
2433 * after sw writes TxE and before hw re-load the last
2434 * descriptor to get the newly chained one.
2435 * Software must keep the last DONE descriptor as a
2436 * holding descriptor - software does so by marking
2437 * it with the STALE flag.
2442 if (list_is_last(&bf_held->list, &txq->axq_q))
2445 bf = list_entry(bf_held->list.next, struct ath_buf,
2449 lastbf = bf->bf_lastbf;
2450 ds = lastbf->bf_desc;
2452 memset(&ts, 0, sizeof(ts));
2453 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2454 if (status == -EINPROGRESS)
2457 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2460 * Remove ath_buf's of the same transmit unit from txq,
2461 * however leave the last descriptor back as the holding
2462 * descriptor for hw.
2464 lastbf->bf_stale = true;
2465 INIT_LIST_HEAD(&bf_head);
2466 if (!list_is_singular(&lastbf->list))
2467 list_cut_position(&bf_head,
2468 &txq->axq_q, lastbf->list.prev);
2471 list_del(&bf_held->list);
2472 ath_tx_return_buffer(sc, bf_held);
2475 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2477 ath_txq_unlock_complete(sc, txq);
2480 void ath_tx_tasklet(struct ath_softc *sc)
2482 struct ath_hw *ah = sc->sc_ah;
2483 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2486 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2487 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2488 ath_tx_processq(sc, &sc->tx.txq[i]);
2492 void ath_tx_edma_tasklet(struct ath_softc *sc)
2494 struct ath_tx_status ts;
2495 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2496 struct ath_hw *ah = sc->sc_ah;
2497 struct ath_txq *txq;
2498 struct ath_buf *bf, *lastbf;
2499 struct list_head bf_head;
2500 struct list_head *fifo_list;
2504 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2507 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2508 if (status == -EINPROGRESS)
2510 if (status == -EIO) {
2511 ath_dbg(common, XMIT, "Error processing tx status\n");
2515 /* Process beacon completions separately */
2516 if (ts.qid == sc->beacon.beaconq) {
2517 sc->beacon.tx_processed = true;
2518 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2522 txq = &sc->tx.txq[ts.qid];
2524 ath_txq_lock(sc, txq);
2526 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2528 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2529 if (list_empty(fifo_list)) {
2530 ath_txq_unlock(sc, txq);
2534 bf = list_first_entry(fifo_list, struct ath_buf, list);
2536 list_del(&bf->list);
2537 ath_tx_return_buffer(sc, bf);
2538 bf = list_first_entry(fifo_list, struct ath_buf, list);
2541 lastbf = bf->bf_lastbf;
2543 INIT_LIST_HEAD(&bf_head);
2544 if (list_is_last(&lastbf->list, fifo_list)) {
2545 list_splice_tail_init(fifo_list, &bf_head);
2546 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2548 if (!list_empty(&txq->axq_q)) {
2549 struct list_head bf_q;
2551 INIT_LIST_HEAD(&bf_q);
2552 txq->axq_link = NULL;
2553 list_splice_tail_init(&txq->axq_q, &bf_q);
2554 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2557 lastbf->bf_stale = true;
2559 list_cut_position(&bf_head, fifo_list,
2563 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2564 ath_txq_unlock_complete(sc, txq);
2572 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2574 struct ath_descdma *dd = &sc->txsdma;
2575 u8 txs_len = sc->sc_ah->caps.txs_len;
2577 dd->dd_desc_len = size * txs_len;
2578 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2579 &dd->dd_desc_paddr, GFP_KERNEL);
2586 static int ath_tx_edma_init(struct ath_softc *sc)
2590 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2592 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2593 sc->txsdma.dd_desc_paddr,
2594 ATH_TXSTATUS_RING_SIZE);
2599 int ath_tx_init(struct ath_softc *sc, int nbufs)
2601 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2604 spin_lock_init(&sc->tx.txbuflock);
2606 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2610 "Failed to allocate tx descriptors: %d\n", error);
2614 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2615 "beacon", ATH_BCBUF, 1, 1);
2618 "Failed to allocate beacon descriptors: %d\n", error);
2622 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2624 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2625 error = ath_tx_edma_init(sc);
2630 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2632 struct ath_atx_tid *tid;
2633 struct ath_atx_ac *ac;
2636 for (tidno = 0, tid = &an->tid[tidno];
2637 tidno < IEEE80211_NUM_TIDS;
2641 tid->seq_start = tid->seq_next = 0;
2642 tid->baw_size = WME_MAX_BA;
2643 tid->baw_head = tid->baw_tail = 0;
2645 tid->paused = false;
2646 tid->active = false;
2647 __skb_queue_head_init(&tid->buf_q);
2648 __skb_queue_head_init(&tid->retry_q);
2649 acno = TID_TO_WME_AC(tidno);
2650 tid->ac = &an->ac[acno];
2653 for (acno = 0, ac = &an->ac[acno];
2654 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2656 ac->txq = sc->tx.txq_map[acno];
2657 INIT_LIST_HEAD(&ac->tid_q);
2661 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2663 struct ath_atx_ac *ac;
2664 struct ath_atx_tid *tid;
2665 struct ath_txq *txq;
2668 for (tidno = 0, tid = &an->tid[tidno];
2669 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2674 ath_txq_lock(sc, txq);
2677 list_del(&tid->list);
2682 list_del(&ac->list);
2683 tid->ac->sched = false;
2686 ath_tid_drain(sc, txq, tid);
2687 tid->active = false;
2689 ath_txq_unlock(sc, txq);