2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 static u16 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid,
52 struct list_head *bf_head);
53 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
54 struct ath_txq *txq, struct list_head *bf_q,
55 struct ath_tx_status *ts, int txok, int sendbar);
56 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
57 struct list_head *head, bool internal);
58 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
61 int txok, bool update_rc);
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
72 static int ath_max_4ms_framelen[4][32] = {
74 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
75 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
76 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
77 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
80 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
81 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
82 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
83 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
86 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
87 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
88 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
89 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
92 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
93 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
94 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
95 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
99 /*********************/
100 /* Aggregation logic */
101 /*********************/
103 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
105 struct ath_atx_ac *ac = tid->ac;
114 list_add_tail(&tid->list, &ac->tid_q);
120 list_add_tail(&ac->list, &txq->axq_acq);
123 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
125 struct ath_txq *txq = tid->ac->txq;
127 WARN_ON(!tid->paused);
129 spin_lock_bh(&txq->axq_lock);
132 if (list_empty(&tid->buf_q))
135 ath_tx_queue_tid(txq, tid);
136 ath_txq_schedule(sc, txq);
138 spin_unlock_bh(&txq->axq_lock);
141 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
143 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
144 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
145 sizeof(tx_info->rate_driver_data));
146 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
149 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
151 struct ath_txq *txq = tid->ac->txq;
153 struct list_head bf_head;
154 struct ath_tx_status ts;
155 struct ath_frame_info *fi;
157 INIT_LIST_HEAD(&bf_head);
159 memset(&ts, 0, sizeof(ts));
160 spin_lock_bh(&txq->axq_lock);
162 while (!list_empty(&tid->buf_q)) {
163 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
164 list_move_tail(&bf->list, &bf_head);
166 spin_unlock_bh(&txq->axq_lock);
167 fi = get_frame_info(bf->bf_mpdu);
169 ath_tx_update_baw(sc, tid, fi->seqno);
170 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
172 ath_tx_send_normal(sc, txq, NULL, &bf_head);
174 spin_lock_bh(&txq->axq_lock);
177 spin_unlock_bh(&txq->axq_lock);
180 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
185 index = ATH_BA_INDEX(tid->seq_start, seqno);
186 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
188 __clear_bit(cindex, tid->tx_buf);
190 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
191 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
192 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
196 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
201 index = ATH_BA_INDEX(tid->seq_start, seqno);
202 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
203 __set_bit(cindex, tid->tx_buf);
205 if (index >= ((tid->baw_tail - tid->baw_head) &
206 (ATH_TID_MAX_BUFS - 1))) {
207 tid->baw_tail = cindex;
208 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
213 * TODO: For frame(s) that are in the retry state, we will reuse the
214 * sequence number(s) without setting the retry bit. The
215 * alternative is to give up on these and BAR the receiver's window
218 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
219 struct ath_atx_tid *tid)
223 struct list_head bf_head;
224 struct ath_tx_status ts;
225 struct ath_frame_info *fi;
227 memset(&ts, 0, sizeof(ts));
228 INIT_LIST_HEAD(&bf_head);
231 if (list_empty(&tid->buf_q))
234 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
235 list_move_tail(&bf->list, &bf_head);
237 fi = get_frame_info(bf->bf_mpdu);
239 ath_tx_update_baw(sc, tid, fi->seqno);
241 spin_unlock(&txq->axq_lock);
242 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
243 spin_lock(&txq->axq_lock);
246 tid->seq_next = tid->seq_start;
247 tid->baw_tail = tid->baw_head;
250 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
253 struct ath_frame_info *fi = get_frame_info(skb);
254 struct ieee80211_hdr *hdr;
256 TX_STAT_INC(txq->axq_qnum, a_retries);
257 if (fi->retries++ > 0)
260 hdr = (struct ieee80211_hdr *)skb->data;
261 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
264 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
266 struct ath_buf *bf = NULL;
268 spin_lock_bh(&sc->tx.txbuflock);
270 if (unlikely(list_empty(&sc->tx.txbuf))) {
271 spin_unlock_bh(&sc->tx.txbuflock);
275 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
278 spin_unlock_bh(&sc->tx.txbuflock);
283 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
285 spin_lock_bh(&sc->tx.txbuflock);
286 list_add_tail(&bf->list, &sc->tx.txbuf);
287 spin_unlock_bh(&sc->tx.txbuflock);
290 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
294 tbf = ath_tx_get_buffer(sc);
298 ATH_TXBUF_RESET(tbf);
300 tbf->bf_mpdu = bf->bf_mpdu;
301 tbf->bf_buf_addr = bf->bf_buf_addr;
302 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
303 tbf->bf_state = bf->bf_state;
308 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
309 struct ath_tx_status *ts, int txok,
310 int *nframes, int *nbad)
312 struct ath_frame_info *fi;
314 u32 ba[WME_BA_BMP_SIZE >> 5];
321 isaggr = bf_isaggr(bf);
323 seq_st = ts->ts_seqnum;
324 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
328 fi = get_frame_info(bf->bf_mpdu);
329 ba_index = ATH_BA_INDEX(seq_st, fi->seqno);
332 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
340 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
341 struct ath_buf *bf, struct list_head *bf_q,
342 struct ath_tx_status *ts, int txok, bool retry)
344 struct ath_node *an = NULL;
346 struct ieee80211_sta *sta;
347 struct ieee80211_hw *hw = sc->hw;
348 struct ieee80211_hdr *hdr;
349 struct ieee80211_tx_info *tx_info;
350 struct ath_atx_tid *tid = NULL;
351 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
352 struct list_head bf_head, bf_pending;
353 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
354 u32 ba[WME_BA_BMP_SIZE >> 5];
355 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
356 bool rc_update = true;
357 struct ieee80211_tx_rate rates[4];
358 struct ath_frame_info *fi;
364 hdr = (struct ieee80211_hdr *)skb->data;
366 tx_info = IEEE80211_SKB_CB(skb);
368 memcpy(rates, tx_info->control.rates, sizeof(rates));
372 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
376 INIT_LIST_HEAD(&bf_head);
378 bf_next = bf->bf_next;
380 bf->bf_state.bf_type |= BUF_XRETRY;
381 if (!bf->bf_stale || bf_next != NULL)
382 list_move_tail(&bf->list, &bf_head);
384 ath_tx_rc_status(sc, bf, ts, 1, 1, 0, false);
385 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
393 an = (struct ath_node *)sta->drv_priv;
394 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
395 tid = ATH_AN_2_TID(an, tidno);
398 * The hardware occasionally sends a tx status for the wrong TID.
399 * In this case, the BA status cannot be considered valid and all
400 * subframes need to be retransmitted
402 if (tidno != ts->tid)
405 isaggr = bf_isaggr(bf);
406 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
408 if (isaggr && txok) {
409 if (ts->ts_flags & ATH9K_TX_BA) {
410 seq_st = ts->ts_seqnum;
411 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
414 * AR5416 can become deaf/mute when BA
415 * issue happens. Chip needs to be reset.
416 * But AP code may have sychronization issues
417 * when perform internal reset in this routine.
418 * Only enable reset in STA mode for now.
420 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
425 INIT_LIST_HEAD(&bf_pending);
426 INIT_LIST_HEAD(&bf_head);
428 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
430 txfail = txpending = sendbar = 0;
431 bf_next = bf->bf_next;
434 tx_info = IEEE80211_SKB_CB(skb);
435 fi = get_frame_info(skb);
437 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) {
438 /* transmit completion, subframe is
439 * acked by block ack */
441 } else if (!isaggr && txok) {
442 /* transmit completion */
445 if ((tid->state & AGGR_CLEANUP) || !retry) {
447 * cleanup in progress, just fail
448 * the un-acked sub-frames
451 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
452 if (!(ts->ts_status & ATH9K_TXERR_FILT) ||
454 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
459 bf->bf_state.bf_type |= BUF_XRETRY;
467 * Make sure the last desc is reclaimed if it
468 * not a holding desc.
470 if (!bf_last->bf_stale || bf_next != NULL)
471 list_move_tail(&bf->list, &bf_head);
473 INIT_LIST_HEAD(&bf_head);
475 if (!txpending || (tid->state & AGGR_CLEANUP)) {
477 * complete the acked-ones/xretried ones; update
480 spin_lock_bh(&txq->axq_lock);
481 ath_tx_update_baw(sc, tid, fi->seqno);
482 spin_unlock_bh(&txq->axq_lock);
484 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
485 memcpy(tx_info->control.rates, rates, sizeof(rates));
486 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, true);
489 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, false);
492 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
495 /* retry the un-acked ones */
496 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, false);
497 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
498 if (bf->bf_next == NULL && bf_last->bf_stale) {
501 tbf = ath_clone_txbuf(sc, bf_last);
503 * Update tx baw and complete the
504 * frame with failed status if we
508 spin_lock_bh(&txq->axq_lock);
509 ath_tx_update_baw(sc, tid, fi->seqno);
510 spin_unlock_bh(&txq->axq_lock);
512 bf->bf_state.bf_type |=
514 ath_tx_rc_status(sc, bf, ts, nframes,
516 ath_tx_complete_buf(sc, bf, txq,
522 ath9k_hw_cleartxdesc(sc->sc_ah,
524 list_add_tail(&tbf->list, &bf_head);
527 * Clear descriptor status words for
530 ath9k_hw_cleartxdesc(sc->sc_ah,
536 * Put this buffer to the temporary pending
537 * queue to retain ordering
539 list_splice_tail_init(&bf_head, &bf_pending);
545 /* prepend un-acked frames to the beginning of the pending frame queue */
546 if (!list_empty(&bf_pending)) {
548 ieee80211_sta_set_tim(sta);
550 spin_lock_bh(&txq->axq_lock);
552 tid->ac->clear_ps_filter = true;
553 list_splice(&bf_pending, &tid->buf_q);
554 ath_tx_queue_tid(txq, tid);
555 spin_unlock_bh(&txq->axq_lock);
558 if (tid->state & AGGR_CLEANUP) {
559 ath_tx_flush_tid(sc, tid);
561 if (tid->baw_head == tid->baw_tail) {
562 tid->state &= ~AGGR_ADDBA_COMPLETE;
563 tid->state &= ~AGGR_CLEANUP;
570 ath_reset(sc, false);
573 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
574 struct ath_atx_tid *tid)
577 struct ieee80211_tx_info *tx_info;
578 struct ieee80211_tx_rate *rates;
579 u32 max_4ms_framelen, frmlen;
580 u16 aggr_limit, legacy = 0;
584 tx_info = IEEE80211_SKB_CB(skb);
585 rates = tx_info->control.rates;
588 * Find the lowest frame length among the rate series that will have a
589 * 4ms transmit duration.
590 * TODO - TXOP limit needs to be considered.
592 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
594 for (i = 0; i < 4; i++) {
595 if (rates[i].count) {
597 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
602 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
607 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
610 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
611 max_4ms_framelen = min(max_4ms_framelen, frmlen);
616 * limit aggregate size by the minimum rate if rate selected is
617 * not a probe rate, if rate selected is a probe rate then
618 * avoid aggregation of this packet.
620 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
623 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
624 aggr_limit = min((max_4ms_framelen * 3) / 8,
625 (u32)ATH_AMPDU_LIMIT_MAX);
627 aggr_limit = min(max_4ms_framelen,
628 (u32)ATH_AMPDU_LIMIT_MAX);
631 * h/w can accept aggregates up to 16 bit lengths (65535).
632 * The IE, however can hold up to 65536, which shows up here
633 * as zero. Ignore 65536 since we are constrained by hw.
635 if (tid->an->maxampdu)
636 aggr_limit = min(aggr_limit, tid->an->maxampdu);
642 * Returns the number of delimiters to be added to
643 * meet the minimum required mpdudensity.
645 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
646 struct ath_buf *bf, u16 frmlen)
648 struct sk_buff *skb = bf->bf_mpdu;
649 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
650 u32 nsymbits, nsymbols;
653 int width, streams, half_gi, ndelim, mindelim;
654 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
656 /* Select standard number of delimiters based on frame length alone */
657 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
660 * If encryption enabled, hardware requires some more padding between
662 * TODO - this could be improved to be dependent on the rate.
663 * The hardware can keep up at lower rates, but not higher rates
665 if (fi->keyix != ATH9K_TXKEYIX_INVALID)
666 ndelim += ATH_AGGR_ENCRYPTDELIM;
669 * Convert desired mpdu density from microeconds to bytes based
670 * on highest rate in rate series (i.e. first rate) to determine
671 * required minimum length for subframe. Take into account
672 * whether high rate is 20 or 40Mhz and half or full GI.
674 * If there is no mpdu density restriction, no further calculation
678 if (tid->an->mpdudensity == 0)
681 rix = tx_info->control.rates[0].idx;
682 flags = tx_info->control.rates[0].flags;
683 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
684 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
687 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
689 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
694 streams = HT_RC_2_STREAMS(rix);
695 nsymbits = bits_per_symbol[rix % 8][width] * streams;
696 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
698 if (frmlen < minlen) {
699 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
700 ndelim = max(mindelim, ndelim);
706 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
708 struct ath_atx_tid *tid,
709 struct list_head *bf_q,
712 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
713 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
714 int rl = 0, nframes = 0, ndelim, prev_al = 0;
715 u16 aggr_limit = 0, al = 0, bpad = 0,
716 al_delta, h_baw = tid->baw_size / 2;
717 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
718 struct ieee80211_tx_info *tx_info;
719 struct ath_frame_info *fi;
721 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
724 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
725 fi = get_frame_info(bf->bf_mpdu);
727 /* do not step over block-ack window */
728 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) {
729 status = ATH_AGGR_BAW_CLOSED;
734 aggr_limit = ath_lookup_rate(sc, bf, tid);
738 /* do not exceed aggregation limit */
739 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
742 (aggr_limit < (al + bpad + al_delta + prev_al))) {
743 status = ATH_AGGR_LIMITED;
747 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
748 if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
749 !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
752 /* do not exceed subframe limit */
753 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
754 status = ATH_AGGR_LIMITED;
759 /* add padding for previous frame to aggregation length */
760 al += bpad + al_delta;
763 * Get the delimiters needed to meet the MPDU
764 * density for this node.
766 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen);
767 bpad = PADBYTES(al_delta) + (ndelim << 2);
770 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
772 /* link buffers of this frame to the aggregate */
774 ath_tx_addto_baw(sc, tid, fi->seqno);
775 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
776 list_move_tail(&bf->list, bf_q);
778 bf_prev->bf_next = bf;
779 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
784 } while (!list_empty(&tid->buf_q));
792 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
793 struct ath_atx_tid *tid)
796 enum ATH_AGGR_STATUS status;
797 struct ath_frame_info *fi;
798 struct list_head bf_q;
802 if (list_empty(&tid->buf_q))
805 INIT_LIST_HEAD(&bf_q);
807 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
810 * no frames picked up to be aggregated;
811 * block-ack window is not open.
813 if (list_empty(&bf_q))
816 bf = list_first_entry(&bf_q, struct ath_buf, list);
817 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
819 if (tid->ac->clear_ps_filter) {
820 tid->ac->clear_ps_filter = false;
821 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
824 /* if only one frame, send as non-aggregate */
825 if (bf == bf->bf_lastbf) {
826 fi = get_frame_info(bf->bf_mpdu);
828 bf->bf_state.bf_type &= ~BUF_AGGR;
829 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
830 ath_buf_set_rate(sc, bf, fi->framelen);
831 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
835 /* setup first desc of aggregate */
836 bf->bf_state.bf_type |= BUF_AGGR;
837 ath_buf_set_rate(sc, bf, aggr_len);
838 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
840 /* anchor last desc of aggregate */
841 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
843 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
844 TX_STAT_INC(txq->axq_qnum, a_aggr);
846 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
847 status != ATH_AGGR_BAW_CLOSED);
850 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
853 struct ath_atx_tid *txtid;
856 an = (struct ath_node *)sta->drv_priv;
857 txtid = ATH_AN_2_TID(an, tid);
859 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
862 txtid->state |= AGGR_ADDBA_PROGRESS;
863 txtid->paused = true;
864 *ssn = txtid->seq_start = txtid->seq_next;
866 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
867 txtid->baw_head = txtid->baw_tail = 0;
872 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
874 struct ath_node *an = (struct ath_node *)sta->drv_priv;
875 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
876 struct ath_txq *txq = txtid->ac->txq;
878 if (txtid->state & AGGR_CLEANUP)
881 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
882 txtid->state &= ~AGGR_ADDBA_PROGRESS;
886 spin_lock_bh(&txq->axq_lock);
887 txtid->paused = true;
890 * If frames are still being transmitted for this TID, they will be
891 * cleaned up during tx completion. To prevent race conditions, this
892 * TID can only be reused after all in-progress subframes have been
895 if (txtid->baw_head != txtid->baw_tail)
896 txtid->state |= AGGR_CLEANUP;
898 txtid->state &= ~AGGR_ADDBA_COMPLETE;
899 spin_unlock_bh(&txq->axq_lock);
901 ath_tx_flush_tid(sc, txtid);
904 bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an)
906 struct ath_atx_tid *tid;
907 struct ath_atx_ac *ac;
909 bool buffered = false;
912 for (tidno = 0, tid = &an->tid[tidno];
913 tidno < WME_NUM_TID; tidno++, tid++) {
921 spin_lock_bh(&txq->axq_lock);
923 if (!list_empty(&tid->buf_q))
927 list_del(&tid->list);
934 spin_unlock_bh(&txq->axq_lock);
940 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
942 struct ath_atx_tid *tid;
943 struct ath_atx_ac *ac;
947 for (tidno = 0, tid = &an->tid[tidno];
948 tidno < WME_NUM_TID; tidno++, tid++) {
953 spin_lock_bh(&txq->axq_lock);
954 ac->clear_ps_filter = true;
956 if (!list_empty(&tid->buf_q) && !tid->paused) {
957 ath_tx_queue_tid(txq, tid);
958 ath_txq_schedule(sc, txq);
961 spin_unlock_bh(&txq->axq_lock);
965 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
967 struct ath_atx_tid *txtid;
970 an = (struct ath_node *)sta->drv_priv;
972 if (sc->sc_flags & SC_OP_TXAGGR) {
973 txtid = ATH_AN_2_TID(an, tid);
975 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
976 txtid->state |= AGGR_ADDBA_COMPLETE;
977 txtid->state &= ~AGGR_ADDBA_PROGRESS;
978 ath_tx_resume_tid(sc, txtid);
982 /********************/
983 /* Queue Management */
984 /********************/
986 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
989 struct ath_atx_ac *ac, *ac_tmp;
990 struct ath_atx_tid *tid, *tid_tmp;
992 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
995 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
996 list_del(&tid->list);
998 ath_tid_drain(sc, txq, tid);
1003 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1005 struct ath_hw *ah = sc->sc_ah;
1006 struct ath_common *common = ath9k_hw_common(ah);
1007 struct ath9k_tx_queue_info qi;
1008 static const int subtype_txq_to_hwq[] = {
1009 [WME_AC_BE] = ATH_TXQ_AC_BE,
1010 [WME_AC_BK] = ATH_TXQ_AC_BK,
1011 [WME_AC_VI] = ATH_TXQ_AC_VI,
1012 [WME_AC_VO] = ATH_TXQ_AC_VO,
1016 memset(&qi, 0, sizeof(qi));
1017 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1018 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1019 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1020 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1021 qi.tqi_physCompBuf = 0;
1024 * Enable interrupts only for EOL and DESC conditions.
1025 * We mark tx descriptors to receive a DESC interrupt
1026 * when a tx queue gets deep; otherwise waiting for the
1027 * EOL to reap descriptors. Note that this is done to
1028 * reduce interrupt load and this only defers reaping
1029 * descriptors, never transmitting frames. Aside from
1030 * reducing interrupts this also permits more concurrency.
1031 * The only potential downside is if the tx queue backs
1032 * up in which case the top half of the kernel may backup
1033 * due to a lack of tx descriptors.
1035 * The UAPSD queue is an exception, since we take a desc-
1036 * based intr on the EOSP frames.
1038 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1039 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1040 TXQ_FLAG_TXERRINT_ENABLE;
1042 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1043 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1045 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1046 TXQ_FLAG_TXDESCINT_ENABLE;
1048 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1049 if (axq_qnum == -1) {
1051 * NB: don't print a message, this happens
1052 * normally on parts with too few tx queues
1056 if (axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
1057 ath_err(common, "qnum %u out of range, max %zu!\n",
1058 axq_qnum, ARRAY_SIZE(sc->tx.txq));
1059 ath9k_hw_releasetxqueue(ah, axq_qnum);
1062 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1063 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1065 txq->axq_qnum = axq_qnum;
1066 txq->mac80211_qnum = -1;
1067 txq->axq_link = NULL;
1068 INIT_LIST_HEAD(&txq->axq_q);
1069 INIT_LIST_HEAD(&txq->axq_acq);
1070 spin_lock_init(&txq->axq_lock);
1072 txq->axq_ampdu_depth = 0;
1073 txq->axq_tx_inprogress = false;
1074 sc->tx.txqsetup |= 1<<axq_qnum;
1076 txq->txq_headidx = txq->txq_tailidx = 0;
1077 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1078 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1080 return &sc->tx.txq[axq_qnum];
1083 int ath_txq_update(struct ath_softc *sc, int qnum,
1084 struct ath9k_tx_queue_info *qinfo)
1086 struct ath_hw *ah = sc->sc_ah;
1088 struct ath9k_tx_queue_info qi;
1090 if (qnum == sc->beacon.beaconq) {
1092 * XXX: for beacon queue, we just save the parameter.
1093 * It will be picked up by ath_beaconq_config when
1096 sc->beacon.beacon_qi = *qinfo;
1100 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1102 ath9k_hw_get_txq_props(ah, qnum, &qi);
1103 qi.tqi_aifs = qinfo->tqi_aifs;
1104 qi.tqi_cwmin = qinfo->tqi_cwmin;
1105 qi.tqi_cwmax = qinfo->tqi_cwmax;
1106 qi.tqi_burstTime = qinfo->tqi_burstTime;
1107 qi.tqi_readyTime = qinfo->tqi_readyTime;
1109 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1110 ath_err(ath9k_hw_common(sc->sc_ah),
1111 "Unable to update hardware queue %u!\n", qnum);
1114 ath9k_hw_resettxqueue(ah, qnum);
1120 int ath_cabq_update(struct ath_softc *sc)
1122 struct ath9k_tx_queue_info qi;
1123 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1124 int qnum = sc->beacon.cabq->axq_qnum;
1126 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1128 * Ensure the readytime % is within the bounds.
1130 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1131 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1132 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1133 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1135 qi.tqi_readyTime = (cur_conf->beacon_interval *
1136 sc->config.cabqReadytime) / 100;
1137 ath_txq_update(sc, qnum, &qi);
1142 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1144 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1145 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1148 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1149 struct list_head *list, bool retry_tx)
1151 struct ath_buf *bf, *lastbf;
1152 struct list_head bf_head;
1153 struct ath_tx_status ts;
1155 memset(&ts, 0, sizeof(ts));
1156 INIT_LIST_HEAD(&bf_head);
1158 while (!list_empty(list)) {
1159 bf = list_first_entry(list, struct ath_buf, list);
1162 list_del(&bf->list);
1164 ath_tx_return_buffer(sc, bf);
1168 lastbf = bf->bf_lastbf;
1169 list_cut_position(&bf_head, list, &lastbf->list);
1172 if (bf_is_ampdu_not_probing(bf))
1173 txq->axq_ampdu_depth--;
1175 spin_unlock_bh(&txq->axq_lock);
1177 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1180 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1181 spin_lock_bh(&txq->axq_lock);
1186 * Drain a given TX queue (could be Beacon or Data)
1188 * This assumes output has been stopped and
1189 * we do not need to block ath_tx_tasklet.
1191 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1193 spin_lock_bh(&txq->axq_lock);
1194 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1195 int idx = txq->txq_tailidx;
1197 while (!list_empty(&txq->txq_fifo[idx])) {
1198 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1201 INCR(idx, ATH_TXFIFO_DEPTH);
1203 txq->txq_tailidx = idx;
1206 txq->axq_link = NULL;
1207 txq->axq_tx_inprogress = false;
1208 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1210 /* flush any pending frames if aggregation is enabled */
1211 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1212 ath_txq_drain_pending_buffers(sc, txq);
1214 spin_unlock_bh(&txq->axq_lock);
1217 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1219 struct ath_hw *ah = sc->sc_ah;
1220 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1221 struct ath_txq *txq;
1224 if (sc->sc_flags & SC_OP_INVALID)
1227 ath9k_hw_abort_tx_dma(ah);
1229 /* Check if any queue remains active */
1230 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1231 if (!ATH_TXQ_SETUP(sc, i))
1234 npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
1238 ath_err(common, "Failed to stop TX DMA!\n");
1240 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1241 if (!ATH_TXQ_SETUP(sc, i))
1245 * The caller will resume queues with ieee80211_wake_queues.
1246 * Mark the queue as not stopped to prevent ath_tx_complete
1247 * from waking the queue too early.
1249 txq = &sc->tx.txq[i];
1250 txq->stopped = false;
1251 ath_draintxq(sc, txq, retry_tx);
1257 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1259 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1260 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1263 /* For each axq_acq entry, for each tid, try to schedule packets
1264 * for transmit until ampdu_depth has reached min Q depth.
1266 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1268 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1269 struct ath_atx_tid *tid, *last_tid;
1271 if (list_empty(&txq->axq_acq) ||
1272 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1275 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1276 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1278 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1279 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1280 list_del(&ac->list);
1283 while (!list_empty(&ac->tid_q)) {
1284 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1286 list_del(&tid->list);
1292 ath_tx_sched_aggr(sc, txq, tid);
1295 * add tid to round-robin queue if more frames
1296 * are pending for the tid
1298 if (!list_empty(&tid->buf_q))
1299 ath_tx_queue_tid(txq, tid);
1301 if (tid == last_tid ||
1302 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1306 if (!list_empty(&ac->tid_q)) {
1309 list_add_tail(&ac->list, &txq->axq_acq);
1313 if (ac == last_ac ||
1314 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1324 * Insert a chain of ath_buf (descriptors) on a txq and
1325 * assume the descriptors are already chained together by caller.
1327 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1328 struct list_head *head, bool internal)
1330 struct ath_hw *ah = sc->sc_ah;
1331 struct ath_common *common = ath9k_hw_common(ah);
1332 struct ath_buf *bf, *bf_last;
1333 bool puttxbuf = false;
1337 * Insert the frame on the outbound list and
1338 * pass it on to the hardware.
1341 if (list_empty(head))
1344 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1345 bf = list_first_entry(head, struct ath_buf, list);
1346 bf_last = list_entry(head->prev, struct ath_buf, list);
1348 ath_dbg(common, ATH_DBG_QUEUE,
1349 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1351 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1352 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1353 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1356 list_splice_tail_init(head, &txq->axq_q);
1358 if (txq->axq_link) {
1359 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1360 ath_dbg(common, ATH_DBG_XMIT,
1361 "link[%u] (%p)=%llx (%p)\n",
1362 txq->axq_qnum, txq->axq_link,
1363 ito64(bf->bf_daddr), bf->bf_desc);
1367 txq->axq_link = bf_last->bf_desc;
1371 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1372 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1373 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1374 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1378 TX_STAT_INC(txq->axq_qnum, txstart);
1379 ath9k_hw_txstart(ah, txq->axq_qnum);
1384 if (bf_is_ampdu_not_probing(bf))
1385 txq->axq_ampdu_depth++;
1389 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1390 struct ath_buf *bf, struct ath_tx_control *txctl)
1392 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1393 struct list_head bf_head;
1395 bf->bf_state.bf_type |= BUF_AMPDU;
1398 * Do not queue to h/w when any of the following conditions is true:
1399 * - there are pending frames in software queue
1400 * - the TID is currently paused for ADDBA/BAR request
1401 * - seqno is not within block-ack window
1402 * - h/w queue depth exceeds low water mark
1404 if (!list_empty(&tid->buf_q) || tid->paused ||
1405 !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
1406 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1408 * Add this frame to software queue for scheduling later
1411 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1412 list_add_tail(&bf->list, &tid->buf_q);
1413 ath_tx_queue_tid(txctl->txq, tid);
1417 INIT_LIST_HEAD(&bf_head);
1418 list_add(&bf->list, &bf_head);
1420 /* Add sub-frame to BAW */
1422 ath_tx_addto_baw(sc, tid, fi->seqno);
1424 /* Queue to h/w without aggregation */
1425 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1427 ath_buf_set_rate(sc, bf, fi->framelen);
1428 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1431 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1432 struct ath_atx_tid *tid,
1433 struct list_head *bf_head)
1435 struct ath_frame_info *fi;
1438 bf = list_first_entry(bf_head, struct ath_buf, list);
1439 bf->bf_state.bf_type &= ~BUF_AMPDU;
1441 /* update starting sequence number for subsequent ADDBA request */
1443 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1446 fi = get_frame_info(bf->bf_mpdu);
1447 ath_buf_set_rate(sc, bf, fi->framelen);
1448 ath_tx_txqaddbuf(sc, txq, bf_head, false);
1449 TX_STAT_INC(txq->axq_qnum, queued);
1452 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1454 struct ieee80211_hdr *hdr;
1455 enum ath9k_pkt_type htype;
1458 hdr = (struct ieee80211_hdr *)skb->data;
1459 fc = hdr->frame_control;
1461 if (ieee80211_is_beacon(fc))
1462 htype = ATH9K_PKT_TYPE_BEACON;
1463 else if (ieee80211_is_probe_resp(fc))
1464 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1465 else if (ieee80211_is_atim(fc))
1466 htype = ATH9K_PKT_TYPE_ATIM;
1467 else if (ieee80211_is_pspoll(fc))
1468 htype = ATH9K_PKT_TYPE_PSPOLL;
1470 htype = ATH9K_PKT_TYPE_NORMAL;
1475 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1478 struct ath_softc *sc = hw->priv;
1479 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1480 struct ieee80211_sta *sta = tx_info->control.sta;
1481 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1482 struct ieee80211_hdr *hdr;
1483 struct ath_frame_info *fi = get_frame_info(skb);
1484 struct ath_node *an = NULL;
1485 struct ath_atx_tid *tid;
1486 enum ath9k_key_type keytype;
1490 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1493 an = (struct ath_node *) sta->drv_priv;
1495 hdr = (struct ieee80211_hdr *)skb->data;
1496 if (an && ieee80211_is_data_qos(hdr->frame_control) &&
1497 conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) {
1499 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
1502 * Override seqno set by upper layer with the one
1503 * in tx aggregation state.
1505 tid = ATH_AN_2_TID(an, tidno);
1506 seqno = tid->seq_next;
1507 hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
1508 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1511 memset(fi, 0, sizeof(*fi));
1513 fi->keyix = hw_key->hw_key_idx;
1514 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1515 fi->keyix = an->ps_key;
1517 fi->keyix = ATH9K_TXKEYIX_INVALID;
1518 fi->keytype = keytype;
1519 fi->framelen = framelen;
1523 static int setup_tx_flags(struct sk_buff *skb)
1525 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1528 flags |= ATH9K_TXDESC_INTREQ;
1530 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1531 flags |= ATH9K_TXDESC_NOACK;
1533 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1534 flags |= ATH9K_TXDESC_LDPC;
1541 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1542 * width - 0 for 20 MHz, 1 for 40 MHz
1543 * half_gi - to use 4us v/s 3.6 us for symbol time
1545 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1546 int width, int half_gi, bool shortPreamble)
1548 u32 nbits, nsymbits, duration, nsymbols;
1551 /* find number of symbols: PLCP + data */
1552 streams = HT_RC_2_STREAMS(rix);
1553 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1554 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1555 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1558 duration = SYMBOL_TIME(nsymbols);
1560 duration = SYMBOL_TIME_HALFGI(nsymbols);
1562 /* addup duration for legacy/ht training and signal fields */
1563 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1568 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1570 struct ath_hw *ah = sc->sc_ah;
1571 struct ath9k_channel *curchan = ah->curchan;
1572 if ((sc->sc_flags & SC_OP_ENABLE_APM) &&
1573 (curchan->channelFlags & CHANNEL_5GHZ) &&
1574 (chainmask == 0x7) && (rate < 0x90))
1580 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
1582 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1583 struct ath9k_11n_rate_series series[4];
1584 struct sk_buff *skb;
1585 struct ieee80211_tx_info *tx_info;
1586 struct ieee80211_tx_rate *rates;
1587 const struct ieee80211_rate *rate;
1588 struct ieee80211_hdr *hdr;
1590 u8 rix = 0, ctsrate = 0;
1593 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1596 tx_info = IEEE80211_SKB_CB(skb);
1597 rates = tx_info->control.rates;
1598 hdr = (struct ieee80211_hdr *)skb->data;
1599 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1602 * We check if Short Preamble is needed for the CTS rate by
1603 * checking the BSS's global flag.
1604 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1606 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1607 ctsrate = rate->hw_value;
1608 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1609 ctsrate |= rate->hw_value_short;
1611 for (i = 0; i < 4; i++) {
1612 bool is_40, is_sgi, is_sp;
1615 if (!rates[i].count || (rates[i].idx < 0))
1619 series[i].Tries = rates[i].count;
1621 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1622 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1623 flags |= ATH9K_TXDESC_RTSENA;
1624 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1625 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1626 flags |= ATH9K_TXDESC_CTSENA;
1629 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1630 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1631 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1632 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1634 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1635 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1636 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1638 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1640 series[i].Rate = rix | 0x80;
1641 series[i].ChSel = ath_txchainmask_reduction(sc,
1642 common->tx_chainmask, series[i].Rate);
1643 series[i].PktDuration = ath_pkt_duration(sc, rix, len,
1644 is_40, is_sgi, is_sp);
1645 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1646 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1651 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1652 !(rate->flags & IEEE80211_RATE_ERP_G))
1653 phy = WLAN_RC_PHY_CCK;
1655 phy = WLAN_RC_PHY_OFDM;
1657 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1658 series[i].Rate = rate->hw_value;
1659 if (rate->hw_value_short) {
1660 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1661 series[i].Rate |= rate->hw_value_short;
1666 if (bf->bf_state.bfs_paprd)
1667 series[i].ChSel = common->tx_chainmask;
1669 series[i].ChSel = ath_txchainmask_reduction(sc,
1670 common->tx_chainmask, series[i].Rate);
1672 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1673 phy, rate->bitrate * 100, len, rix, is_sp);
1676 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1677 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1678 flags &= ~ATH9K_TXDESC_RTSENA;
1680 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1681 if (flags & ATH9K_TXDESC_RTSENA)
1682 flags &= ~ATH9K_TXDESC_CTSENA;
1684 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1685 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1686 bf->bf_lastbf->bf_desc,
1687 !is_pspoll, ctsrate,
1688 0, series, 4, flags);
1692 static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
1693 struct ath_txq *txq,
1694 struct sk_buff *skb)
1696 struct ath_softc *sc = hw->priv;
1697 struct ath_hw *ah = sc->sc_ah;
1698 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1699 struct ath_frame_info *fi = get_frame_info(skb);
1701 struct ath_desc *ds;
1704 bf = ath_tx_get_buffer(sc);
1706 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1710 ATH_TXBUF_RESET(bf);
1712 bf->bf_flags = setup_tx_flags(skb);
1715 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1716 skb->len, DMA_TO_DEVICE);
1717 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1719 bf->bf_buf_addr = 0;
1720 ath_err(ath9k_hw_common(sc->sc_ah),
1721 "dma_mapping_error() on TX\n");
1722 ath_tx_return_buffer(sc, bf);
1726 frm_type = get_hw_packet_type(skb);
1729 ath9k_hw_set_desc_link(ah, ds, 0);
1731 ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
1732 fi->keyix, fi->keytype, bf->bf_flags);
1734 ath9k_hw_filltxdesc(ah, ds,
1735 skb->len, /* segment length */
1736 true, /* first segment */
1737 true, /* last segment */
1738 ds, /* first descriptor */
1746 /* FIXME: tx power */
1747 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1748 struct ath_tx_control *txctl)
1750 struct sk_buff *skb = bf->bf_mpdu;
1751 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1752 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1753 struct list_head bf_head;
1754 struct ath_atx_tid *tid = NULL;
1757 spin_lock_bh(&txctl->txq->axq_lock);
1758 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1759 ieee80211_is_data_qos(hdr->frame_control)) {
1760 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1761 IEEE80211_QOS_CTL_TID_MASK;
1762 tid = ATH_AN_2_TID(txctl->an, tidno);
1764 WARN_ON(tid->ac->txq != txctl->txq);
1767 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1769 * Try aggregation if it's a unicast data frame
1770 * and the destination is HT capable.
1772 ath_tx_send_ampdu(sc, tid, bf, txctl);
1774 INIT_LIST_HEAD(&bf_head);
1775 list_add_tail(&bf->list, &bf_head);
1777 bf->bf_state.bfs_ftype = txctl->frame_type;
1778 bf->bf_state.bfs_paprd = txctl->paprd;
1780 if (bf->bf_state.bfs_paprd)
1781 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1782 bf->bf_state.bfs_paprd);
1785 bf->bf_state.bfs_paprd_timestamp = jiffies;
1787 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1788 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
1790 ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
1793 spin_unlock_bh(&txctl->txq->axq_lock);
1796 /* Upon failure caller should free skb */
1797 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1798 struct ath_tx_control *txctl)
1800 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1801 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1802 struct ieee80211_sta *sta = info->control.sta;
1803 struct ieee80211_vif *vif = info->control.vif;
1804 struct ath_softc *sc = hw->priv;
1805 struct ath_txq *txq = txctl->txq;
1807 int padpos, padsize;
1808 int frmlen = skb->len + FCS_LEN;
1811 /* NOTE: sta can be NULL according to net/mac80211.h */
1813 txctl->an = (struct ath_node *)sta->drv_priv;
1815 if (info->control.hw_key)
1816 frmlen += info->control.hw_key->icv_len;
1819 * As a temporary workaround, assign seq# here; this will likely need
1820 * to be cleaned up to work better with Beacon transmission and virtual
1823 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1824 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1825 sc->tx.seq_no += 0x10;
1826 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1827 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1830 /* Add the padding after the header if this is not already done */
1831 padpos = ath9k_cmn_padpos(hdr->frame_control);
1832 padsize = padpos & 3;
1833 if (padsize && skb->len > padpos) {
1834 if (skb_headroom(skb) < padsize)
1837 skb_push(skb, padsize);
1838 memmove(skb->data, skb->data + padsize, padpos);
1841 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1842 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1843 !ieee80211_is_data(hdr->frame_control))
1844 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1846 setup_frame_info(hw, skb, frmlen);
1849 * At this point, the vif, hw_key and sta pointers in the tx control
1850 * info are no longer valid (overwritten by the ath_frame_info data.
1853 bf = ath_tx_setup_buffer(hw, txctl->txq, skb);
1857 q = skb_get_queue_mapping(skb);
1858 spin_lock_bh(&txq->axq_lock);
1859 if (txq == sc->tx.txq_map[q] &&
1860 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1861 ieee80211_stop_queue(sc->hw, q);
1864 spin_unlock_bh(&txq->axq_lock);
1866 ath_tx_start_dma(sc, bf, txctl);
1875 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1876 int tx_flags, int ftype, struct ath_txq *txq)
1878 struct ieee80211_hw *hw = sc->hw;
1879 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1880 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1881 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1882 int q, padpos, padsize;
1884 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1886 if (tx_flags & ATH_TX_BAR)
1887 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1889 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1890 /* Frame was ACKed */
1891 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1894 padpos = ath9k_cmn_padpos(hdr->frame_control);
1895 padsize = padpos & 3;
1896 if (padsize && skb->len>padpos+padsize) {
1898 * Remove MAC header padding before giving the frame back to
1901 memmove(skb->data + padsize, skb->data, padpos);
1902 skb_pull(skb, padsize);
1905 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1906 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1907 ath_dbg(common, ATH_DBG_PS,
1908 "Going back to sleep after having received TX status (0x%lx)\n",
1909 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1911 PS_WAIT_FOR_PSPOLL_DATA |
1912 PS_WAIT_FOR_TX_ACK));
1915 q = skb_get_queue_mapping(skb);
1916 if (txq == sc->tx.txq_map[q]) {
1917 spin_lock_bh(&txq->axq_lock);
1918 if (WARN_ON(--txq->pending_frames < 0))
1919 txq->pending_frames = 0;
1921 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1922 ieee80211_wake_queue(sc->hw, q);
1925 spin_unlock_bh(&txq->axq_lock);
1928 ieee80211_tx_status(hw, skb);
1931 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1932 struct ath_txq *txq, struct list_head *bf_q,
1933 struct ath_tx_status *ts, int txok, int sendbar)
1935 struct sk_buff *skb = bf->bf_mpdu;
1936 unsigned long flags;
1940 tx_flags = ATH_TX_BAR;
1943 tx_flags |= ATH_TX_ERROR;
1945 if (bf_isxretried(bf))
1946 tx_flags |= ATH_TX_XRETRY;
1949 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
1950 bf->bf_buf_addr = 0;
1952 if (bf->bf_state.bfs_paprd) {
1953 if (time_after(jiffies,
1954 bf->bf_state.bfs_paprd_timestamp +
1955 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
1956 dev_kfree_skb_any(skb);
1958 complete(&sc->paprd_complete);
1960 ath_debug_stat_tx(sc, bf, ts, txq);
1961 ath_tx_complete(sc, skb, tx_flags,
1962 bf->bf_state.bfs_ftype, txq);
1964 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
1965 * accidentally reference it later.
1970 * Return the list of ath_buf of this mpdu to free queue
1972 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1973 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1974 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1977 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
1978 struct ath_tx_status *ts, int nframes, int nbad,
1979 int txok, bool update_rc)
1981 struct sk_buff *skb = bf->bf_mpdu;
1982 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1983 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1984 struct ieee80211_hw *hw = sc->hw;
1985 struct ath_hw *ah = sc->sc_ah;
1989 tx_info->status.ack_signal = ts->ts_rssi;
1991 tx_rateindex = ts->ts_rateindex;
1992 WARN_ON(tx_rateindex >= hw->max_rates);
1994 if (ts->ts_status & ATH9K_TXERR_FILT)
1995 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1996 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
1997 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
1999 BUG_ON(nbad > nframes);
2001 tx_info->status.ampdu_len = nframes;
2002 tx_info->status.ampdu_ack_len = nframes - nbad;
2005 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2006 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
2008 * If an underrun error is seen assume it as an excessive
2009 * retry only if max frame trigger level has been reached
2010 * (2 KB for single stream, and 4 KB for dual stream).
2011 * Adjust the long retry as if the frame was tried
2012 * hw->max_rate_tries times to affect how rate control updates
2013 * PER for the failed rate.
2014 * In case of congestion on the bus penalizing this type of
2015 * underruns should help hardware actually transmit new frames
2016 * successfully by eventually preferring slower rates.
2017 * This itself should also alleviate congestion on the bus.
2019 if (ieee80211_is_data(hdr->frame_control) &&
2020 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2021 ATH9K_TX_DELIM_UNDERRUN)) &&
2022 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2023 tx_info->status.rates[tx_rateindex].count =
2027 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2028 tx_info->status.rates[i].count = 0;
2029 tx_info->status.rates[i].idx = -1;
2032 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2035 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2036 struct ath_tx_status *ts, struct ath_buf *bf,
2037 struct list_head *bf_head)
2042 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2043 txq->axq_tx_inprogress = false;
2044 if (bf_is_ampdu_not_probing(bf))
2045 txq->axq_ampdu_depth--;
2047 spin_unlock_bh(&txq->axq_lock);
2049 if (!bf_isampdu(bf)) {
2051 * This frame is sent out as a single frame.
2052 * Use hardware retry status for this frame.
2054 if (ts->ts_status & ATH9K_TXERR_XRETRY)
2055 bf->bf_state.bf_type |= BUF_XRETRY;
2056 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok, true);
2057 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2059 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2061 spin_lock_bh(&txq->axq_lock);
2063 if (sc->sc_flags & SC_OP_TXAGGR)
2064 ath_txq_schedule(sc, txq);
2067 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2069 struct ath_hw *ah = sc->sc_ah;
2070 struct ath_common *common = ath9k_hw_common(ah);
2071 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2072 struct list_head bf_head;
2073 struct ath_desc *ds;
2074 struct ath_tx_status ts;
2077 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2078 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2081 spin_lock_bh(&txq->axq_lock);
2083 if (list_empty(&txq->axq_q)) {
2084 txq->axq_link = NULL;
2085 if (sc->sc_flags & SC_OP_TXAGGR)
2086 ath_txq_schedule(sc, txq);
2089 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2092 * There is a race condition that a BH gets scheduled
2093 * after sw writes TxE and before hw re-load the last
2094 * descriptor to get the newly chained one.
2095 * Software must keep the last DONE descriptor as a
2096 * holding descriptor - software does so by marking
2097 * it with the STALE flag.
2102 if (list_is_last(&bf_held->list, &txq->axq_q))
2105 bf = list_entry(bf_held->list.next, struct ath_buf,
2109 lastbf = bf->bf_lastbf;
2110 ds = lastbf->bf_desc;
2112 memset(&ts, 0, sizeof(ts));
2113 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2114 if (status == -EINPROGRESS)
2117 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2120 * Remove ath_buf's of the same transmit unit from txq,
2121 * however leave the last descriptor back as the holding
2122 * descriptor for hw.
2124 lastbf->bf_stale = true;
2125 INIT_LIST_HEAD(&bf_head);
2126 if (!list_is_singular(&lastbf->list))
2127 list_cut_position(&bf_head,
2128 &txq->axq_q, lastbf->list.prev);
2131 list_del(&bf_held->list);
2132 ath_tx_return_buffer(sc, bf_held);
2135 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2137 spin_unlock_bh(&txq->axq_lock);
2140 static void ath_tx_complete_poll_work(struct work_struct *work)
2142 struct ath_softc *sc = container_of(work, struct ath_softc,
2143 tx_complete_work.work);
2144 struct ath_txq *txq;
2146 bool needreset = false;
2147 #ifdef CONFIG_ATH9K_DEBUGFS
2148 sc->tx_complete_poll_work_seen++;
2151 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2152 if (ATH_TXQ_SETUP(sc, i)) {
2153 txq = &sc->tx.txq[i];
2154 spin_lock_bh(&txq->axq_lock);
2155 if (txq->axq_depth) {
2156 if (txq->axq_tx_inprogress) {
2158 spin_unlock_bh(&txq->axq_lock);
2161 txq->axq_tx_inprogress = true;
2164 spin_unlock_bh(&txq->axq_lock);
2168 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2169 "tx hung, resetting the chip\n");
2170 spin_lock_bh(&sc->sc_pcu_lock);
2171 ath_reset(sc, true);
2172 spin_unlock_bh(&sc->sc_pcu_lock);
2175 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2176 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2181 void ath_tx_tasklet(struct ath_softc *sc)
2184 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2186 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2188 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2189 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2190 ath_tx_processq(sc, &sc->tx.txq[i]);
2194 void ath_tx_edma_tasklet(struct ath_softc *sc)
2196 struct ath_tx_status ts;
2197 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2198 struct ath_hw *ah = sc->sc_ah;
2199 struct ath_txq *txq;
2200 struct ath_buf *bf, *lastbf;
2201 struct list_head bf_head;
2205 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2206 if (status == -EINPROGRESS)
2208 if (status == -EIO) {
2209 ath_dbg(common, ATH_DBG_XMIT,
2210 "Error processing tx status\n");
2214 /* Skip beacon completions */
2215 if (ts.qid == sc->beacon.beaconq)
2218 txq = &sc->tx.txq[ts.qid];
2220 spin_lock_bh(&txq->axq_lock);
2222 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2223 spin_unlock_bh(&txq->axq_lock);
2227 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2228 struct ath_buf, list);
2229 lastbf = bf->bf_lastbf;
2231 INIT_LIST_HEAD(&bf_head);
2232 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2235 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2236 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2238 if (!list_empty(&txq->axq_q)) {
2239 struct list_head bf_q;
2241 INIT_LIST_HEAD(&bf_q);
2242 txq->axq_link = NULL;
2243 list_splice_tail_init(&txq->axq_q, &bf_q);
2244 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2248 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2249 spin_unlock_bh(&txq->axq_lock);
2257 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2259 struct ath_descdma *dd = &sc->txsdma;
2260 u8 txs_len = sc->sc_ah->caps.txs_len;
2262 dd->dd_desc_len = size * txs_len;
2263 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2264 &dd->dd_desc_paddr, GFP_KERNEL);
2271 static int ath_tx_edma_init(struct ath_softc *sc)
2275 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2277 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2278 sc->txsdma.dd_desc_paddr,
2279 ATH_TXSTATUS_RING_SIZE);
2284 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2286 struct ath_descdma *dd = &sc->txsdma;
2288 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2292 int ath_tx_init(struct ath_softc *sc, int nbufs)
2294 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2297 spin_lock_init(&sc->tx.txbuflock);
2299 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2303 "Failed to allocate tx descriptors: %d\n", error);
2307 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2308 "beacon", ATH_BCBUF, 1, 1);
2311 "Failed to allocate beacon descriptors: %d\n", error);
2315 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2317 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2318 error = ath_tx_edma_init(sc);
2330 void ath_tx_cleanup(struct ath_softc *sc)
2332 if (sc->beacon.bdma.dd_desc_len != 0)
2333 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2335 if (sc->tx.txdma.dd_desc_len != 0)
2336 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2338 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2339 ath_tx_edma_cleanup(sc);
2342 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2344 struct ath_atx_tid *tid;
2345 struct ath_atx_ac *ac;
2348 for (tidno = 0, tid = &an->tid[tidno];
2349 tidno < WME_NUM_TID;
2353 tid->seq_start = tid->seq_next = 0;
2354 tid->baw_size = WME_MAX_BA;
2355 tid->baw_head = tid->baw_tail = 0;
2357 tid->paused = false;
2358 tid->state &= ~AGGR_CLEANUP;
2359 INIT_LIST_HEAD(&tid->buf_q);
2360 acno = TID_TO_WME_AC(tidno);
2361 tid->ac = &an->ac[acno];
2362 tid->state &= ~AGGR_ADDBA_COMPLETE;
2363 tid->state &= ~AGGR_ADDBA_PROGRESS;
2366 for (acno = 0, ac = &an->ac[acno];
2367 acno < WME_NUM_AC; acno++, ac++) {
2369 ac->txq = sc->tx.txq_map[acno];
2370 INIT_LIST_HEAD(&ac->tid_q);
2374 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2376 struct ath_atx_ac *ac;
2377 struct ath_atx_tid *tid;
2378 struct ath_txq *txq;
2381 for (tidno = 0, tid = &an->tid[tidno];
2382 tidno < WME_NUM_TID; tidno++, tid++) {
2387 spin_lock_bh(&txq->axq_lock);
2390 list_del(&tid->list);
2395 list_del(&ac->list);
2396 tid->ac->sched = false;
2399 ath_tid_drain(sc, txq, tid);
2400 tid->state &= ~AGGR_ADDBA_COMPLETE;
2401 tid->state &= ~AGGR_CLEANUP;
2403 spin_unlock_bh(&txq->axq_lock);