2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
18 #include <linux/relay.h>
20 #include "ar9003_mac.h"
22 #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
24 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
26 return sc->ps_enabled &&
27 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
31 * Setup and link descriptors.
33 * 11N: we can no longer afford to self link the last descriptor.
34 * MAC acknowledges BA status as long as it copies frames to host
35 * buffer (or rx fifo). This can incorrectly acknowledge packets
36 * to a sender if last desc is self-linked.
38 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
40 struct ath_hw *ah = sc->sc_ah;
41 struct ath_common *common = ath9k_hw_common(ah);
46 ds->ds_link = 0; /* link to null */
47 ds->ds_data = bf->bf_buf_addr;
49 /* virtual addr of the beginning of the buffer. */
52 ds->ds_vdata = skb->data;
55 * setup rx descriptors. The rx_bufsize here tells the hardware
56 * how much data it can DMA to us and that we are prepared
59 ath9k_hw_setuprxdesc(ah, ds,
63 if (sc->rx.rxlink == NULL)
64 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
66 *sc->rx.rxlink = bf->bf_daddr;
68 sc->rx.rxlink = &ds->ds_link;
71 static void ath_rx_buf_relink(struct ath_softc *sc, struct ath_buf *bf)
74 ath_rx_buf_link(sc, sc->rx.buf_hold);
79 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
81 /* XXX block beacon interrupts */
82 ath9k_hw_setantenna(sc->sc_ah, antenna);
83 sc->rx.defant = antenna;
84 sc->rx.rxotherant = 0;
87 static void ath_opmode_init(struct ath_softc *sc)
89 struct ath_hw *ah = sc->sc_ah;
90 struct ath_common *common = ath9k_hw_common(ah);
94 /* configure rx filter */
95 rfilt = ath_calcrxfilter(sc);
96 ath9k_hw_setrxfilter(ah, rfilt);
98 /* configure bssid mask */
99 ath_hw_setbssidmask(common);
101 /* configure operational mode */
102 ath9k_hw_setopmode(ah);
104 /* calculate and install multicast filter */
105 mfilt[0] = mfilt[1] = ~0;
106 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
109 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
110 enum ath9k_rx_qtype qtype)
112 struct ath_hw *ah = sc->sc_ah;
113 struct ath_rx_edma *rx_edma;
117 rx_edma = &sc->rx.rx_edma[qtype];
118 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
121 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
122 list_del_init(&bf->list);
126 memset(skb->data, 0, ah->caps.rx_status_len);
127 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
128 ah->caps.rx_status_len, DMA_TO_DEVICE);
130 SKB_CB_ATHBUF(skb) = bf;
131 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
132 __skb_queue_tail(&rx_edma->rx_fifo, skb);
137 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
138 enum ath9k_rx_qtype qtype)
140 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
141 struct ath_buf *bf, *tbf;
143 if (list_empty(&sc->rx.rxbuf)) {
144 ath_dbg(common, QUEUE, "No free rx buf available\n");
148 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list)
149 if (!ath_rx_edma_buf_link(sc, qtype))
154 static void ath_rx_remove_buffer(struct ath_softc *sc,
155 enum ath9k_rx_qtype qtype)
158 struct ath_rx_edma *rx_edma;
161 rx_edma = &sc->rx.rx_edma[qtype];
163 while ((skb = __skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
164 bf = SKB_CB_ATHBUF(skb);
166 list_add_tail(&bf->list, &sc->rx.rxbuf);
170 static void ath_rx_edma_cleanup(struct ath_softc *sc)
172 struct ath_hw *ah = sc->sc_ah;
173 struct ath_common *common = ath9k_hw_common(ah);
176 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
177 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
179 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
181 dma_unmap_single(sc->dev, bf->bf_buf_addr,
184 dev_kfree_skb_any(bf->bf_mpdu);
191 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
193 skb_queue_head_init(&rx_edma->rx_fifo);
194 rx_edma->rx_fifo_hwsize = size;
197 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
199 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
200 struct ath_hw *ah = sc->sc_ah;
206 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
207 ah->caps.rx_status_len);
209 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
210 ah->caps.rx_lp_qdepth);
211 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
212 ah->caps.rx_hp_qdepth);
214 size = sizeof(struct ath_buf) * nbufs;
215 bf = devm_kzalloc(sc->dev, size, GFP_KERNEL);
219 INIT_LIST_HEAD(&sc->rx.rxbuf);
221 for (i = 0; i < nbufs; i++, bf++) {
222 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
228 memset(skb->data, 0, common->rx_bufsize);
231 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
234 if (unlikely(dma_mapping_error(sc->dev,
236 dev_kfree_skb_any(skb);
240 "dma_mapping_error() on RX init\n");
245 list_add_tail(&bf->list, &sc->rx.rxbuf);
251 ath_rx_edma_cleanup(sc);
255 static void ath_edma_start_recv(struct ath_softc *sc)
257 ath9k_hw_rxena(sc->sc_ah);
258 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP);
259 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP);
261 ath9k_hw_startpcureceive(sc->sc_ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL));
264 static void ath_edma_stop_recv(struct ath_softc *sc)
266 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
267 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
270 int ath_rx_init(struct ath_softc *sc, int nbufs)
272 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
277 spin_lock_init(&sc->sc_pcu_lock);
279 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
280 sc->sc_ah->caps.rx_status_len;
282 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
283 return ath_rx_edma_init(sc, nbufs);
285 ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n",
286 common->cachelsz, common->rx_bufsize);
288 /* Initialize rx descriptors */
290 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
294 "failed to allocate rx descriptors: %d\n",
299 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
300 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
308 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
311 if (unlikely(dma_mapping_error(sc->dev,
313 dev_kfree_skb_any(skb);
317 "dma_mapping_error() on RX init\n");
322 sc->rx.rxlink = NULL;
330 void ath_rx_cleanup(struct ath_softc *sc)
332 struct ath_hw *ah = sc->sc_ah;
333 struct ath_common *common = ath9k_hw_common(ah);
337 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
338 ath_rx_edma_cleanup(sc);
342 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
345 dma_unmap_single(sc->dev, bf->bf_buf_addr,
356 * Calculate the receive filter according to the
357 * operating mode and state:
359 * o always accept unicast, broadcast, and multicast traffic
360 * o maintain current state of phy error reception (the hal
361 * may enable phy error frames for noise immunity work)
362 * o probe request frames are accepted only when operating in
363 * hostap, adhoc, or monitor modes
364 * o enable promiscuous mode according to the interface state
366 * - when operating in adhoc mode so the 802.11 layer creates
367 * node table entries for peers,
368 * - when operating in station mode for collecting rssi data when
369 * the station is otherwise quiet, or
370 * - when operating as a repeater so we see repeater-sta beacons
374 u32 ath_calcrxfilter(struct ath_softc *sc)
378 rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
379 | ATH9K_RX_FILTER_MCAST;
381 /* if operating on a DFS channel, enable radar pulse detection */
382 if (sc->hw->conf.radar_enabled)
383 rfilt |= ATH9K_RX_FILTER_PHYRADAR | ATH9K_RX_FILTER_PHYERR;
385 if (sc->rx.rxfilter & FIF_PROBE_REQ)
386 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
389 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
390 * mode interface or when in monitor mode. AP mode does not need this
391 * since it receives all in-BSS frames anyway.
393 if (sc->sc_ah->is_monitoring)
394 rfilt |= ATH9K_RX_FILTER_PROM;
396 if (sc->rx.rxfilter & FIF_CONTROL)
397 rfilt |= ATH9K_RX_FILTER_CONTROL;
399 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
401 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
402 rfilt |= ATH9K_RX_FILTER_MYBEACON;
404 rfilt |= ATH9K_RX_FILTER_BEACON;
406 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
407 (sc->rx.rxfilter & FIF_PSPOLL))
408 rfilt |= ATH9K_RX_FILTER_PSPOLL;
410 if (conf_is_ht(&sc->hw->conf))
411 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
413 if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
414 /* This is needed for older chips */
415 if (sc->sc_ah->hw_version.macVersion <= AR_SREV_VERSION_9160)
416 rfilt |= ATH9K_RX_FILTER_PROM;
417 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
420 if (AR_SREV_9550(sc->sc_ah))
421 rfilt |= ATH9K_RX_FILTER_4ADDRESS;
427 int ath_startrecv(struct ath_softc *sc)
429 struct ath_hw *ah = sc->sc_ah;
430 struct ath_buf *bf, *tbf;
432 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
433 ath_edma_start_recv(sc);
437 if (list_empty(&sc->rx.rxbuf))
440 sc->rx.buf_hold = NULL;
441 sc->rx.rxlink = NULL;
442 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
443 ath_rx_buf_link(sc, bf);
446 /* We could have deleted elements so the list may be empty now */
447 if (list_empty(&sc->rx.rxbuf))
450 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
451 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
456 ath9k_hw_startpcureceive(ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL));
461 static void ath_flushrecv(struct ath_softc *sc)
463 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
464 ath_rx_tasklet(sc, 1, true);
465 ath_rx_tasklet(sc, 1, false);
468 bool ath_stoprecv(struct ath_softc *sc)
470 struct ath_hw *ah = sc->sc_ah;
471 bool stopped, reset = false;
473 ath9k_hw_abortpcurecv(ah);
474 ath9k_hw_setrxfilter(ah, 0);
475 stopped = ath9k_hw_stopdmarecv(ah, &reset);
479 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
480 ath_edma_stop_recv(sc);
482 sc->rx.rxlink = NULL;
484 if (!(ah->ah_flags & AH_UNPLUGGED) &&
485 unlikely(!stopped)) {
486 ath_err(ath9k_hw_common(sc->sc_ah),
487 "Could not stop RX, we could be "
488 "confusing the DMA engine when we start RX up\n");
489 ATH_DBG_WARN_ON_ONCE(!stopped);
491 return stopped && !reset;
494 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
496 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
497 struct ieee80211_mgmt *mgmt;
498 u8 *pos, *end, id, elen;
499 struct ieee80211_tim_ie *tim;
501 mgmt = (struct ieee80211_mgmt *)skb->data;
502 pos = mgmt->u.beacon.variable;
503 end = skb->data + skb->len;
505 while (pos + 2 < end) {
508 if (pos + elen > end)
511 if (id == WLAN_EID_TIM) {
512 if (elen < sizeof(*tim))
514 tim = (struct ieee80211_tim_ie *) pos;
515 if (tim->dtim_count != 0)
517 return tim->bitmap_ctrl & 0x01;
526 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
528 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
530 if (skb->len < 24 + 8 + 2 + 2)
533 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
535 if (sc->ps_flags & PS_BEACON_SYNC) {
536 sc->ps_flags &= ~PS_BEACON_SYNC;
538 "Reconfigure beacon timers based on synchronized timestamp\n");
539 ath9k_set_beacon(sc);
542 if (ath_beacon_dtim_pending_cab(skb)) {
544 * Remain awake waiting for buffered broadcast/multicast
545 * frames. If the last broadcast/multicast frame is not
546 * received properly, the next beacon frame will work as
547 * a backup trigger for returning into NETWORK SLEEP state,
548 * so we are waiting for it as well.
551 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
552 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
556 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
558 * This can happen if a broadcast frame is dropped or the AP
559 * fails to send a frame indicating that all CAB frames have
562 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
563 ath_dbg(common, PS, "PS wait for CAB frames timed out\n");
567 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon)
569 struct ieee80211_hdr *hdr;
570 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
572 hdr = (struct ieee80211_hdr *)skb->data;
574 /* Process Beacon and CAB receive in PS state */
575 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
577 ath_rx_ps_beacon(sc, skb);
578 } else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
579 (ieee80211_is_data(hdr->frame_control) ||
580 ieee80211_is_action(hdr->frame_control)) &&
581 is_multicast_ether_addr(hdr->addr1) &&
582 !ieee80211_has_moredata(hdr->frame_control)) {
584 * No more broadcast/multicast frames to be received at this
587 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
589 "All PS CAB frames received, back to sleep\n");
590 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
591 !is_multicast_ether_addr(hdr->addr1) &&
592 !ieee80211_has_morefrags(hdr->frame_control)) {
593 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
595 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
596 sc->ps_flags & (PS_WAIT_FOR_BEACON |
598 PS_WAIT_FOR_PSPOLL_DATA |
599 PS_WAIT_FOR_TX_ACK));
603 static bool ath_edma_get_buffers(struct ath_softc *sc,
604 enum ath9k_rx_qtype qtype,
605 struct ath_rx_status *rs,
606 struct ath_buf **dest)
608 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
609 struct ath_hw *ah = sc->sc_ah;
610 struct ath_common *common = ath9k_hw_common(ah);
615 skb = skb_peek(&rx_edma->rx_fifo);
619 bf = SKB_CB_ATHBUF(skb);
622 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
623 common->rx_bufsize, DMA_FROM_DEVICE);
625 ret = ath9k_hw_process_rxdesc_edma(ah, rs, skb->data);
626 if (ret == -EINPROGRESS) {
627 /*let device gain the buffer again*/
628 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
629 common->rx_bufsize, DMA_FROM_DEVICE);
633 __skb_unlink(skb, &rx_edma->rx_fifo);
634 if (ret == -EINVAL) {
635 /* corrupt descriptor, skip this one and the following one */
636 list_add_tail(&bf->list, &sc->rx.rxbuf);
637 ath_rx_edma_buf_link(sc, qtype);
639 skb = skb_peek(&rx_edma->rx_fifo);
641 bf = SKB_CB_ATHBUF(skb);
644 __skb_unlink(skb, &rx_edma->rx_fifo);
645 list_add_tail(&bf->list, &sc->rx.rxbuf);
646 ath_rx_edma_buf_link(sc, qtype);
656 static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
657 struct ath_rx_status *rs,
658 enum ath9k_rx_qtype qtype)
660 struct ath_buf *bf = NULL;
662 while (ath_edma_get_buffers(sc, qtype, rs, &bf)) {
671 static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
672 struct ath_rx_status *rs)
674 struct ath_hw *ah = sc->sc_ah;
675 struct ath_common *common = ath9k_hw_common(ah);
680 if (list_empty(&sc->rx.rxbuf)) {
681 sc->rx.rxlink = NULL;
685 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
686 if (bf == sc->rx.buf_hold)
692 * Must provide the virtual address of the current
693 * descriptor, the physical address, and the virtual
694 * address of the next descriptor in the h/w chain.
695 * This allows the HAL to look ahead to see if the
696 * hardware is done with a descriptor by checking the
697 * done bit in the following descriptor and the address
698 * of the current descriptor the DMA engine is working
699 * on. All this is necessary because of our use of
700 * a self-linked list to avoid rx overruns.
702 ret = ath9k_hw_rxprocdesc(ah, ds, rs);
703 if (ret == -EINPROGRESS) {
704 struct ath_rx_status trs;
706 struct ath_desc *tds;
708 memset(&trs, 0, sizeof(trs));
709 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
710 sc->rx.rxlink = NULL;
714 tbf = list_entry(bf->list.next, struct ath_buf, list);
717 * On some hardware the descriptor status words could
718 * get corrupted, including the done bit. Because of
719 * this, check if the next descriptor's done bit is
722 * If the next descriptor's done bit is set, the current
723 * descriptor has been corrupted. Force s/w to discard
724 * this descriptor and continue...
728 ret = ath9k_hw_rxprocdesc(ah, tds, &trs);
729 if (ret == -EINPROGRESS)
733 * mark descriptor as zero-length and set the 'more'
734 * flag to ensure that both buffers get discarded
745 * Synchronize the DMA transfer with CPU before
746 * 1. accessing the frame
747 * 2. requeueing the same buffer to h/w
749 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
756 /* Assumes you've already done the endian to CPU conversion */
757 static bool ath9k_rx_accept(struct ath_common *common,
758 struct ieee80211_hdr *hdr,
759 struct ieee80211_rx_status *rxs,
760 struct ath_rx_status *rx_stats,
763 struct ath_softc *sc = (struct ath_softc *) common->priv;
764 bool is_mc, is_valid_tkip, strip_mic, mic_error;
765 struct ath_hw *ah = common->ah;
767 u8 rx_status_len = ah->caps.rx_status_len;
769 fc = hdr->frame_control;
771 is_mc = !!is_multicast_ether_addr(hdr->addr1);
772 is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID &&
773 test_bit(rx_stats->rs_keyix, common->tkip_keymap);
774 strip_mic = is_valid_tkip && ieee80211_is_data(fc) &&
775 ieee80211_has_protected(fc) &&
776 !(rx_stats->rs_status &
777 (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC |
778 ATH9K_RXERR_KEYMISS));
781 * Key miss events are only relevant for pairwise keys where the
782 * descriptor does contain a valid key index. This has been observed
783 * mostly with CCMP encryption.
785 if (rx_stats->rs_keyix == ATH9K_RXKEYIX_INVALID ||
786 !test_bit(rx_stats->rs_keyix, common->ccmp_keymap))
787 rx_stats->rs_status &= ~ATH9K_RXERR_KEYMISS;
789 if (!rx_stats->rs_datalen) {
790 RX_STAT_INC(rx_len_err);
795 * rs_status follows rs_datalen so if rs_datalen is too large
796 * we can take a hint that hardware corrupted it, so ignore
799 if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len)) {
800 RX_STAT_INC(rx_len_err);
804 /* Only use error bits from the last fragment */
805 if (rx_stats->rs_more)
808 mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) &&
809 !ieee80211_has_morefrags(fc) &&
810 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
811 (rx_stats->rs_status & ATH9K_RXERR_MIC);
814 * The rx_stats->rs_status will not be set until the end of the
815 * chained descriptors so it can be ignored if rs_more is set. The
816 * rs_more will be false at the last element of the chained
819 if (rx_stats->rs_status != 0) {
822 if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
823 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
826 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
829 if ((rx_stats->rs_status & ATH9K_RXERR_DECRYPT) ||
830 (!is_mc && (rx_stats->rs_status & ATH9K_RXERR_KEYMISS))) {
831 *decrypt_error = true;
836 * Reject error frames with the exception of
837 * decryption and MIC failures. For monitor mode,
838 * we also ignore the CRC error.
840 status_mask = ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
843 if (ah->is_monitoring && (sc->rx.rxfilter & FIF_FCSFAIL))
844 status_mask |= ATH9K_RXERR_CRC;
846 if (rx_stats->rs_status & ~status_mask)
851 * For unicast frames the MIC error bit can have false positives,
852 * so all MIC error reports need to be validated in software.
853 * False negatives are not common, so skip software verification
854 * if the hardware considers the MIC valid.
857 rxs->flag |= RX_FLAG_MMIC_STRIPPED;
858 else if (is_mc && mic_error)
859 rxs->flag |= RX_FLAG_MMIC_ERROR;
864 static int ath9k_process_rate(struct ath_common *common,
865 struct ieee80211_hw *hw,
866 struct ath_rx_status *rx_stats,
867 struct ieee80211_rx_status *rxs)
869 struct ieee80211_supported_band *sband;
870 enum ieee80211_band band;
872 struct ath_softc __maybe_unused *sc = common->priv;
874 band = hw->conf.chandef.chan->band;
875 sband = hw->wiphy->bands[band];
877 if (rx_stats->rs_rate & 0x80) {
879 rxs->flag |= RX_FLAG_HT;
880 if (rx_stats->rs_flags & ATH9K_RX_2040)
881 rxs->flag |= RX_FLAG_40MHZ;
882 if (rx_stats->rs_flags & ATH9K_RX_GI)
883 rxs->flag |= RX_FLAG_SHORT_GI;
884 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
888 for (i = 0; i < sband->n_bitrates; i++) {
889 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
893 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
894 rxs->flag |= RX_FLAG_SHORTPRE;
901 * No valid hardware bitrate found -- we should not get here
902 * because hardware has already validated this frame as OK.
905 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
907 RX_STAT_INC(rx_rate_err);
911 static void ath9k_process_rssi(struct ath_common *common,
912 struct ieee80211_hw *hw,
913 struct ieee80211_hdr *hdr,
914 struct ath_rx_status *rx_stats)
916 struct ath_softc *sc = hw->priv;
917 struct ath_hw *ah = common->ah;
919 int rssi = rx_stats->rs_rssi;
921 if (!rx_stats->is_mybeacon ||
922 ((ah->opmode != NL80211_IFTYPE_STATION) &&
923 (ah->opmode != NL80211_IFTYPE_ADHOC)))
926 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
927 ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
929 last_rssi = sc->last_rssi;
930 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
931 rssi = ATH_EP_RND(last_rssi, ATH_RSSI_EP_MULTIPLIER);
935 /* Update Beacon RSSI, this is used by ANI. */
936 ah->stats.avgbrssi = rssi;
940 * For Decrypt or Demic errors, we only mark packet status here and always push
941 * up the frame up to let mac80211 handle the actual error case, be it no
942 * decryption key or real decryption error. This let us keep statistics there.
944 static int ath9k_rx_skb_preprocess(struct ath_softc *sc,
945 struct ieee80211_hdr *hdr,
946 struct ath_rx_status *rx_stats,
947 struct ieee80211_rx_status *rx_status,
950 struct ieee80211_hw *hw = sc->hw;
951 struct ath_hw *ah = sc->sc_ah;
952 struct ath_common *common = ath9k_hw_common(ah);
953 bool discard_current = sc->rx.discard_next;
955 sc->rx.discard_next = rx_stats->rs_more;
960 * everything but the rate is checked here, the rate check is done
961 * separately to avoid doing two lookups for a rate for each frame.
963 if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
966 /* Only use status info from the last fragment */
967 if (rx_stats->rs_more)
970 ath9k_process_rssi(common, hw, hdr, rx_stats);
972 if (ath9k_process_rate(common, hw, rx_stats, rx_status))
975 rx_status->band = hw->conf.chandef.chan->band;
976 rx_status->freq = hw->conf.chandef.chan->center_freq;
977 rx_status->signal = ah->noise + rx_stats->rs_rssi;
978 rx_status->antenna = rx_stats->rs_antenna;
979 rx_status->flag |= RX_FLAG_MACTIME_END;
980 if (rx_stats->rs_moreaggr)
981 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
983 sc->rx.discard_next = false;
987 static void ath9k_rx_skb_postprocess(struct ath_common *common,
989 struct ath_rx_status *rx_stats,
990 struct ieee80211_rx_status *rxs,
993 struct ath_hw *ah = common->ah;
994 struct ieee80211_hdr *hdr;
995 int hdrlen, padpos, padsize;
999 /* see if any padding is done by the hw and remove it */
1000 hdr = (struct ieee80211_hdr *) skb->data;
1001 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1002 fc = hdr->frame_control;
1003 padpos = ieee80211_hdrlen(fc);
1005 /* The MAC header is padded to have 32-bit boundary if the
1006 * packet payload is non-zero. The general calculation for
1007 * padsize would take into account odd header lengths:
1008 * padsize = (4 - padpos % 4) % 4; However, since only
1009 * even-length headers are used, padding can only be 0 or 2
1010 * bytes and we can optimize this a bit. In addition, we must
1011 * not try to remove padding from short control frames that do
1012 * not have payload. */
1013 padsize = padpos & 3;
1014 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1015 memmove(skb->data + padsize, skb->data, padpos);
1016 skb_pull(skb, padsize);
1019 keyix = rx_stats->rs_keyix;
1021 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1022 ieee80211_has_protected(fc)) {
1023 rxs->flag |= RX_FLAG_DECRYPTED;
1024 } else if (ieee80211_has_protected(fc)
1025 && !decrypt_error && skb->len >= hdrlen + 4) {
1026 keyix = skb->data[hdrlen + 3] >> 6;
1028 if (test_bit(keyix, common->keymap))
1029 rxs->flag |= RX_FLAG_DECRYPTED;
1031 if (ah->sw_mgmt_crypto &&
1032 (rxs->flag & RX_FLAG_DECRYPTED) &&
1033 ieee80211_is_mgmt(fc))
1034 /* Use software decrypt for management frames. */
1035 rxs->flag &= ~RX_FLAG_DECRYPTED;
1038 #ifdef CONFIG_ATH9K_DEBUGFS
1039 static s8 fix_rssi_inv_only(u8 rssi_val)
1041 if (rssi_val == 128)
1043 return (s8) rssi_val;
1047 /* returns 1 if this was a spectral frame, even if not handled. */
1048 static int ath_process_fft(struct ath_softc *sc, struct ieee80211_hdr *hdr,
1049 struct ath_rx_status *rs, u64 tsf)
1051 #ifdef CONFIG_ATH9K_DEBUGFS
1052 struct ath_hw *ah = sc->sc_ah;
1053 u8 bins[SPECTRAL_HT20_NUM_BINS];
1054 u8 *vdata = (u8 *)hdr;
1055 struct fft_sample_ht20 fft_sample;
1056 struct ath_radar_info *radar_info;
1057 struct ath_ht20_mag_info *mag_info;
1058 int len = rs->rs_datalen;
1060 u16 length, max_magnitude;
1062 /* AR9280 and before report via ATH9K_PHYERR_RADAR, AR93xx and newer
1063 * via ATH9K_PHYERR_SPECTRAL. Haven't seen ATH9K_PHYERR_FALSE_RADAR_EXT
1064 * yet, but this is supposed to be possible as well.
1066 if (rs->rs_phyerr != ATH9K_PHYERR_RADAR &&
1067 rs->rs_phyerr != ATH9K_PHYERR_FALSE_RADAR_EXT &&
1068 rs->rs_phyerr != ATH9K_PHYERR_SPECTRAL)
1071 /* check if spectral scan bit is set. This does not have to be checked
1072 * if received through a SPECTRAL phy error, but shouldn't hurt.
1074 radar_info = ((struct ath_radar_info *)&vdata[len]) - 1;
1075 if (!(radar_info->pulse_bw_info & SPECTRAL_SCAN_BITMASK))
1078 /* Variation in the data length is possible and will be fixed later.
1079 * Note that we only support HT20 for now.
1081 * TODO: add HT20_40 support as well.
1083 if ((len > SPECTRAL_HT20_TOTAL_DATA_LEN + 2) ||
1084 (len < SPECTRAL_HT20_TOTAL_DATA_LEN - 1))
1087 fft_sample.tlv.type = ATH_FFT_SAMPLE_HT20;
1088 length = sizeof(fft_sample) - sizeof(fft_sample.tlv);
1089 fft_sample.tlv.length = __cpu_to_be16(length);
1091 fft_sample.freq = __cpu_to_be16(ah->curchan->chan->center_freq);
1092 fft_sample.rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
1093 fft_sample.noise = ah->noise;
1095 switch (len - SPECTRAL_HT20_TOTAL_DATA_LEN) {
1097 /* length correct, nothing to do. */
1098 memcpy(bins, vdata, SPECTRAL_HT20_NUM_BINS);
1101 /* first byte missing, duplicate it. */
1102 memcpy(&bins[1], vdata, SPECTRAL_HT20_NUM_BINS - 1);
1106 /* MAC added 2 extra bytes at bin 30 and 32, remove them. */
1107 memcpy(bins, vdata, 30);
1108 bins[30] = vdata[31];
1109 memcpy(&bins[31], &vdata[33], SPECTRAL_HT20_NUM_BINS - 31);
1112 /* MAC added 2 extra bytes AND first byte is missing. */
1114 memcpy(&bins[0], vdata, 30);
1115 bins[31] = vdata[31];
1116 memcpy(&bins[32], &vdata[33], SPECTRAL_HT20_NUM_BINS - 32);
1122 /* DC value (value in the middle) is the blind spot of the spectral
1123 * sample and invalid, interpolate it.
1125 dc_pos = SPECTRAL_HT20_NUM_BINS / 2;
1126 bins[dc_pos] = (bins[dc_pos + 1] + bins[dc_pos - 1]) / 2;
1128 /* mag data is at the end of the frame, in front of radar_info */
1129 mag_info = ((struct ath_ht20_mag_info *)radar_info) - 1;
1131 /* copy raw bins without scaling them */
1132 memcpy(fft_sample.data, bins, SPECTRAL_HT20_NUM_BINS);
1133 fft_sample.max_exp = mag_info->max_exp & 0xf;
1135 max_magnitude = spectral_max_magnitude(mag_info->all_bins);
1136 fft_sample.max_magnitude = __cpu_to_be16(max_magnitude);
1137 fft_sample.max_index = spectral_max_index(mag_info->all_bins);
1138 fft_sample.bitmap_weight = spectral_bitmap_weight(mag_info->all_bins);
1139 fft_sample.tsf = __cpu_to_be64(tsf);
1141 ath_debug_send_fft_sample(sc, &fft_sample.tlv);
1148 static void ath9k_apply_ampdu_details(struct ath_softc *sc,
1149 struct ath_rx_status *rs, struct ieee80211_rx_status *rxs)
1151 if (rs->rs_isaggr) {
1152 rxs->flag |= RX_FLAG_AMPDU_DETAILS | RX_FLAG_AMPDU_LAST_KNOWN;
1154 rxs->ampdu_reference = sc->rx.ampdu_ref;
1156 if (!rs->rs_moreaggr) {
1157 rxs->flag |= RX_FLAG_AMPDU_IS_LAST;
1161 if (rs->rs_flags & ATH9K_RX_DELIM_CRC_PRE)
1162 rxs->flag |= RX_FLAG_AMPDU_DELIM_CRC_ERROR;
1166 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1169 struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
1170 struct ieee80211_rx_status *rxs;
1171 struct ath_hw *ah = sc->sc_ah;
1172 struct ath_common *common = ath9k_hw_common(ah);
1173 struct ieee80211_hw *hw = sc->hw;
1174 struct ieee80211_hdr *hdr;
1176 struct ath_rx_status rs;
1177 enum ath9k_rx_qtype qtype;
1178 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1180 u8 rx_status_len = ah->caps.rx_status_len;
1183 unsigned long flags;
1184 dma_addr_t new_buf_addr;
1187 dma_type = DMA_BIDIRECTIONAL;
1189 dma_type = DMA_FROM_DEVICE;
1191 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
1193 tsf = ath9k_hw_gettsf64(ah);
1194 tsf_lower = tsf & 0xffffffff;
1197 bool decrypt_error = false;
1199 memset(&rs, 0, sizeof(rs));
1201 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1203 bf = ath_get_next_rx_buf(sc, &rs);
1213 * Take frame header from the first fragment and RX status from
1217 hdr_skb = sc->rx.frag;
1221 hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
1222 rxs = IEEE80211_SKB_RXCB(hdr_skb);
1223 if (ieee80211_is_beacon(hdr->frame_control)) {
1224 RX_STAT_INC(rx_beacons);
1225 if (!is_zero_ether_addr(common->curbssid) &&
1226 ether_addr_equal(hdr->addr3, common->curbssid))
1227 rs.is_mybeacon = true;
1229 rs.is_mybeacon = false;
1232 rs.is_mybeacon = false;
1234 if (ieee80211_is_data_present(hdr->frame_control) &&
1235 !ieee80211_is_qos_nullfunc(hdr->frame_control))
1238 ath_debug_stat_rx(sc, &rs);
1240 memset(rxs, 0, sizeof(struct ieee80211_rx_status));
1242 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1243 if (rs.rs_tstamp > tsf_lower &&
1244 unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1245 rxs->mactime -= 0x100000000ULL;
1247 if (rs.rs_tstamp < tsf_lower &&
1248 unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1249 rxs->mactime += 0x100000000ULL;
1251 if (rs.rs_phyerr == ATH9K_PHYERR_RADAR)
1252 ath9k_dfs_process_phyerr(sc, hdr, &rs, rxs->mactime);
1254 if (rs.rs_status & ATH9K_RXERR_PHY) {
1255 if (ath_process_fft(sc, hdr, &rs, rxs->mactime)) {
1256 RX_STAT_INC(rx_spectral);
1257 goto requeue_drop_frag;
1261 retval = ath9k_rx_skb_preprocess(sc, hdr, &rs, rxs,
1264 goto requeue_drop_frag;
1266 if (rs.is_mybeacon) {
1267 sc->hw_busy_count = 0;
1268 ath_start_rx_poll(sc, 3);
1270 /* Ensure we always have an skb to requeue once we are done
1271 * processing the current buffer's skb */
1272 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1274 /* If there is no memory we ignore the current RX'd frame,
1275 * tell hardware it can give us a new frame using the old
1276 * skb and put it at the tail of the sc->rx.rxbuf list for
1279 RX_STAT_INC(rx_oom_err);
1280 goto requeue_drop_frag;
1283 /* We will now give hardware our shiny new allocated skb */
1284 new_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1285 common->rx_bufsize, dma_type);
1286 if (unlikely(dma_mapping_error(sc->dev, new_buf_addr))) {
1287 dev_kfree_skb_any(requeue_skb);
1288 goto requeue_drop_frag;
1291 /* Unmap the frame */
1292 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1293 common->rx_bufsize, dma_type);
1295 bf->bf_mpdu = requeue_skb;
1296 bf->bf_buf_addr = new_buf_addr;
1298 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1299 if (ah->caps.rx_status_len)
1300 skb_pull(skb, ah->caps.rx_status_len);
1303 ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
1304 rxs, decrypt_error);
1307 RX_STAT_INC(rx_frags);
1309 * rs_more indicates chained descriptors which can be
1310 * used to link buffers together for a sort of
1311 * scatter-gather operation.
1314 /* too many fragments - cannot handle frame */
1315 dev_kfree_skb_any(sc->rx.frag);
1316 dev_kfree_skb_any(skb);
1317 RX_STAT_INC(rx_too_many_frags_err);
1323 if (rs.rs_status & ATH9K_RXERR_CORRUPT_DESC)
1324 goto requeue_drop_frag;
1327 int space = skb->len - skb_tailroom(hdr_skb);
1329 if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
1331 RX_STAT_INC(rx_oom_err);
1332 goto requeue_drop_frag;
1337 skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
1339 dev_kfree_skb_any(skb);
1344 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1347 * change the default rx antenna if rx diversity
1348 * chooses the other antenna 3 times in a row.
1350 if (sc->rx.defant != rs.rs_antenna) {
1351 if (++sc->rx.rxotherant >= 3)
1352 ath_setdefantenna(sc, rs.rs_antenna);
1354 sc->rx.rxotherant = 0;
1359 if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
1360 skb_trim(skb, skb->len - 8);
1362 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1363 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
1365 PS_WAIT_FOR_PSPOLL_DATA)) ||
1366 ath9k_check_auto_sleep(sc))
1367 ath_rx_ps(sc, skb, rs.is_mybeacon);
1368 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1370 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx == 3)
1371 ath_ant_comb_scan(sc, &rs);
1373 ath9k_apply_ampdu_details(sc, &rs, rxs);
1375 ieee80211_rx(hw, skb);
1379 dev_kfree_skb_any(sc->rx.frag);
1383 list_add_tail(&bf->list, &sc->rx.rxbuf);
1388 ath_rx_edma_buf_link(sc, qtype);
1390 ath_rx_buf_relink(sc, bf);
1395 if (!(ah->imask & ATH9K_INT_RXEOL)) {
1396 ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
1397 ath9k_hw_set_interrupts(ah);