2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
18 #include <linux/slab.h>
19 #include <linux/ath9k_platform.h>
23 static char *dev_info = "ath9k";
25 MODULE_AUTHOR("Atheros Communications");
26 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
27 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
28 MODULE_LICENSE("Dual BSD/GPL");
30 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
31 module_param_named(debug, ath9k_debug, uint, 0);
32 MODULE_PARM_DESC(debug, "Debugging mask");
34 int ath9k_modparam_nohwcrypt;
35 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
36 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
39 module_param_named(blink, led_blink, int, 0444);
40 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
42 static int ath9k_btcoex_enable;
43 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
44 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
46 bool is_ath9k_unloaded;
47 /* We use the hw_value as an index into our private channel structure */
49 #define CHAN2G(_freq, _idx) { \
50 .band = IEEE80211_BAND_2GHZ, \
51 .center_freq = (_freq), \
56 #define CHAN5G(_freq, _idx) { \
57 .band = IEEE80211_BAND_5GHZ, \
58 .center_freq = (_freq), \
63 /* Some 2 GHz radios are actually tunable on 2312-2732
64 * on 5 MHz steps, we support the channels which we know
65 * we have calibration data for all cards though to make
67 static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
68 CHAN2G(2412, 0), /* Channel 1 */
69 CHAN2G(2417, 1), /* Channel 2 */
70 CHAN2G(2422, 2), /* Channel 3 */
71 CHAN2G(2427, 3), /* Channel 4 */
72 CHAN2G(2432, 4), /* Channel 5 */
73 CHAN2G(2437, 5), /* Channel 6 */
74 CHAN2G(2442, 6), /* Channel 7 */
75 CHAN2G(2447, 7), /* Channel 8 */
76 CHAN2G(2452, 8), /* Channel 9 */
77 CHAN2G(2457, 9), /* Channel 10 */
78 CHAN2G(2462, 10), /* Channel 11 */
79 CHAN2G(2467, 11), /* Channel 12 */
80 CHAN2G(2472, 12), /* Channel 13 */
81 CHAN2G(2484, 13), /* Channel 14 */
84 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
85 * on 5 MHz steps, we support the channels which we know
86 * we have calibration data for all cards though to make
88 static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
89 /* _We_ call this UNII 1 */
90 CHAN5G(5180, 14), /* Channel 36 */
91 CHAN5G(5200, 15), /* Channel 40 */
92 CHAN5G(5220, 16), /* Channel 44 */
93 CHAN5G(5240, 17), /* Channel 48 */
94 /* _We_ call this UNII 2 */
95 CHAN5G(5260, 18), /* Channel 52 */
96 CHAN5G(5280, 19), /* Channel 56 */
97 CHAN5G(5300, 20), /* Channel 60 */
98 CHAN5G(5320, 21), /* Channel 64 */
99 /* _We_ call this "Middle band" */
100 CHAN5G(5500, 22), /* Channel 100 */
101 CHAN5G(5520, 23), /* Channel 104 */
102 CHAN5G(5540, 24), /* Channel 108 */
103 CHAN5G(5560, 25), /* Channel 112 */
104 CHAN5G(5580, 26), /* Channel 116 */
105 CHAN5G(5600, 27), /* Channel 120 */
106 CHAN5G(5620, 28), /* Channel 124 */
107 CHAN5G(5640, 29), /* Channel 128 */
108 CHAN5G(5660, 30), /* Channel 132 */
109 CHAN5G(5680, 31), /* Channel 136 */
110 CHAN5G(5700, 32), /* Channel 140 */
111 /* _We_ call this UNII 3 */
112 CHAN5G(5745, 33), /* Channel 149 */
113 CHAN5G(5765, 34), /* Channel 153 */
114 CHAN5G(5785, 35), /* Channel 157 */
115 CHAN5G(5805, 36), /* Channel 161 */
116 CHAN5G(5825, 37), /* Channel 165 */
119 /* Atheros hardware rate code addition for short premble */
120 #define SHPCHECK(__hw_rate, __flags) \
121 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
123 #define RATE(_bitrate, _hw_rate, _flags) { \
124 .bitrate = (_bitrate), \
126 .hw_value = (_hw_rate), \
127 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
130 static struct ieee80211_rate ath9k_legacy_rates[] = {
132 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
133 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
134 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
145 #ifdef CONFIG_MAC80211_LEDS
146 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
147 { .throughput = 0 * 1024, .blink_time = 334 },
148 { .throughput = 1 * 1024, .blink_time = 260 },
149 { .throughput = 5 * 1024, .blink_time = 220 },
150 { .throughput = 10 * 1024, .blink_time = 190 },
151 { .throughput = 20 * 1024, .blink_time = 170 },
152 { .throughput = 50 * 1024, .blink_time = 150 },
153 { .throughput = 70 * 1024, .blink_time = 130 },
154 { .throughput = 100 * 1024, .blink_time = 110 },
155 { .throughput = 200 * 1024, .blink_time = 80 },
156 { .throughput = 300 * 1024, .blink_time = 50 },
160 static void ath9k_deinit_softc(struct ath_softc *sc);
163 * Read and write, they both share the same lock. We do this to serialize
164 * reads and writes on Atheros 802.11n PCI devices only. This is required
165 * as the FIFO on these devices can only accept sanely 2 requests.
168 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
170 struct ath_hw *ah = (struct ath_hw *) hw_priv;
171 struct ath_common *common = ath9k_hw_common(ah);
172 struct ath_softc *sc = (struct ath_softc *) common->priv;
174 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
176 spin_lock_irqsave(&sc->sc_serial_rw, flags);
177 iowrite32(val, sc->mem + reg_offset);
178 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
180 iowrite32(val, sc->mem + reg_offset);
183 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
185 struct ath_hw *ah = (struct ath_hw *) hw_priv;
186 struct ath_common *common = ath9k_hw_common(ah);
187 struct ath_softc *sc = (struct ath_softc *) common->priv;
190 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
192 spin_lock_irqsave(&sc->sc_serial_rw, flags);
193 val = ioread32(sc->mem + reg_offset);
194 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
196 val = ioread32(sc->mem + reg_offset);
200 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
202 struct ath_hw *ah = (struct ath_hw *) hw_priv;
203 struct ath_common *common = ath9k_hw_common(ah);
204 struct ath_softc *sc = (struct ath_softc *) common->priv;
205 unsigned long uninitialized_var(flags);
208 if (ah->config.serialize_regmode == SER_REG_MODE_ON)
209 spin_lock_irqsave(&sc->sc_serial_rw, flags);
211 val = ioread32(sc->mem + reg_offset);
214 iowrite32(val, sc->mem + reg_offset);
216 if (ah->config.serialize_regmode == SER_REG_MODE_ON)
217 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
222 /**************************/
224 /**************************/
226 static void setup_ht_cap(struct ath_softc *sc,
227 struct ieee80211_sta_ht_cap *ht_info)
229 struct ath_hw *ah = sc->sc_ah;
230 struct ath_common *common = ath9k_hw_common(ah);
231 u8 tx_streams, rx_streams;
234 ht_info->ht_supported = true;
235 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
236 IEEE80211_HT_CAP_SM_PS |
237 IEEE80211_HT_CAP_SGI_40 |
238 IEEE80211_HT_CAP_DSSSCCK40;
240 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
241 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
243 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
244 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
246 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
247 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
249 if (AR_SREV_9330(ah) || AR_SREV_9485(ah))
251 else if (AR_SREV_9300_20_OR_LATER(ah))
256 if (AR_SREV_9280_20_OR_LATER(ah)) {
257 if (max_streams >= 2)
258 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
259 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
262 /* set up supported mcs set */
263 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
264 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams);
265 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams);
267 ath_dbg(common, ATH_DBG_CONFIG,
268 "TX streams %d, RX streams: %d\n",
269 tx_streams, rx_streams);
271 if (tx_streams != rx_streams) {
272 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
273 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
274 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
277 for (i = 0; i < rx_streams; i++)
278 ht_info->mcs.rx_mask[i] = 0xff;
280 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
283 static int ath9k_reg_notifier(struct wiphy *wiphy,
284 struct regulatory_request *request)
286 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
287 struct ath_softc *sc = hw->priv;
288 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
290 return ath_reg_notifier_apply(wiphy, request, reg);
294 * This function will allocate both the DMA descriptor structure, and the
295 * buffers it contains. These are used to contain the descriptors used
298 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
299 struct list_head *head, const char *name,
300 int nbuf, int ndesc, bool is_tx)
302 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
305 int i, bsize, error, desc_len;
307 ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
310 INIT_LIST_HEAD(head);
313 desc_len = sc->sc_ah->caps.tx_desc_len;
315 desc_len = sizeof(struct ath_desc);
317 /* ath_desc must be a multiple of DWORDs */
318 if ((desc_len % 4) != 0) {
319 ath_err(common, "ath_desc not DWORD aligned\n");
320 BUG_ON((desc_len % 4) != 0);
325 dd->dd_desc_len = desc_len * nbuf * ndesc;
328 * Need additional DMA memory because we can't use
329 * descriptors that cross the 4K page boundary. Assume
330 * one skipped descriptor per 4K page.
332 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
334 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
337 while (ndesc_skipped) {
338 dma_len = ndesc_skipped * desc_len;
339 dd->dd_desc_len += dma_len;
341 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
345 /* allocate descriptors */
346 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
347 &dd->dd_desc_paddr, GFP_KERNEL);
348 if (dd->dd_desc == NULL) {
352 ds = (u8 *) dd->dd_desc;
353 ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
354 name, ds, (u32) dd->dd_desc_len,
355 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
357 /* allocate buffers */
358 bsize = sizeof(struct ath_buf) * nbuf;
359 bf = kzalloc(bsize, GFP_KERNEL);
366 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
368 bf->bf_daddr = DS2PHYS(dd, ds);
370 if (!(sc->sc_ah->caps.hw_caps &
371 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
373 * Skip descriptor addresses which can cause 4KB
374 * boundary crossing (addr + length) with a 32 dword
377 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
378 BUG_ON((caddr_t) bf->bf_desc >=
379 ((caddr_t) dd->dd_desc +
382 ds += (desc_len * ndesc);
384 bf->bf_daddr = DS2PHYS(dd, ds);
387 list_add_tail(&bf->list, head);
391 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
394 memset(dd, 0, sizeof(*dd));
398 void ath9k_init_crypto(struct ath_softc *sc)
400 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
403 /* Get the hardware key cache size. */
404 common->keymax = AR_KEYTABLE_SIZE;
407 * Reset the key cache since some parts do not
408 * reset the contents on initial power up.
410 for (i = 0; i < common->keymax; i++)
411 ath_hw_keyreset(common, (u16) i);
414 * Check whether the separate key cache entries
415 * are required to handle both tx+rx MIC keys.
416 * With split mic keys the number of stations is limited
417 * to 27 otherwise 59.
419 if (sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
420 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
423 static int ath9k_init_btcoex(struct ath_softc *sc)
428 switch (sc->sc_ah->btcoex_hw.scheme) {
429 case ATH_BTCOEX_CFG_NONE:
431 case ATH_BTCOEX_CFG_2WIRE:
432 ath9k_hw_btcoex_init_2wire(sc->sc_ah);
434 case ATH_BTCOEX_CFG_3WIRE:
435 ath9k_hw_btcoex_init_3wire(sc->sc_ah);
436 r = ath_init_btcoex_timer(sc);
439 txq = sc->tx.txq_map[WME_AC_BE];
440 ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
441 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
451 static int ath9k_init_queues(struct ath_softc *sc)
455 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
456 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
458 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
461 for (i = 0; i < WME_NUM_AC; i++) {
462 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
463 sc->tx.txq_map[i]->mac80211_qnum = i;
468 static int ath9k_init_channels_rates(struct ath_softc *sc)
472 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
473 ARRAY_SIZE(ath9k_5ghz_chantable) !=
476 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
477 channels = kmemdup(ath9k_2ghz_chantable,
478 sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
482 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
483 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
484 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
485 ARRAY_SIZE(ath9k_2ghz_chantable);
486 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
487 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
488 ARRAY_SIZE(ath9k_legacy_rates);
491 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
492 channels = kmemdup(ath9k_5ghz_chantable,
493 sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
495 if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
496 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
500 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
501 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
502 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
503 ARRAY_SIZE(ath9k_5ghz_chantable);
504 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
505 ath9k_legacy_rates + 4;
506 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
507 ARRAY_SIZE(ath9k_legacy_rates) - 4;
512 static void ath9k_init_misc(struct ath_softc *sc)
514 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
516 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
518 sc->config.txpowlimit = ATH_TXPOWER_MAX;
520 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
521 sc->sc_flags |= SC_OP_TXAGGR;
522 sc->sc_flags |= SC_OP_RXAGGR;
525 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
526 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
528 ath9k_hw_set_diversity(sc->sc_ah, true);
529 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
531 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
533 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
535 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
536 sc->beacon.bslot[i] = NULL;
538 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
539 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
542 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
543 const struct ath_bus_ops *bus_ops)
545 struct ath9k_platform_data *pdata = sc->dev->platform_data;
546 struct ath_hw *ah = NULL;
547 struct ath_common *common;
551 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
556 ah->hw_version.devid = devid;
557 ah->hw_version.subsysid = subsysid;
558 ah->reg_ops.read = ath9k_ioread32;
559 ah->reg_ops.write = ath9k_iowrite32;
560 ah->reg_ops.rmw = ath9k_reg_rmw;
564 ah->ah_flags |= AH_USE_EEPROM;
565 sc->sc_ah->led_pin = -1;
567 sc->sc_ah->gpio_mask = pdata->gpio_mask;
568 sc->sc_ah->gpio_val = pdata->gpio_val;
569 sc->sc_ah->led_pin = pdata->led_pin;
570 ah->is_clk_25mhz = pdata->is_clk_25mhz;
571 ah->get_mac_revision = pdata->get_mac_revision;
572 ah->external_reset = pdata->external_reset;
575 common = ath9k_hw_common(ah);
576 common->ops = &ah->reg_ops;
577 common->bus_ops = bus_ops;
581 common->debug_mask = ath9k_debug;
582 common->btcoex_enabled = ath9k_btcoex_enable == 1;
583 common->disable_ani = false;
584 spin_lock_init(&common->cc_lock);
586 spin_lock_init(&sc->sc_serial_rw);
587 spin_lock_init(&sc->sc_pm_lock);
588 mutex_init(&sc->mutex);
589 #ifdef CONFIG_ATH9K_DEBUGFS
590 spin_lock_init(&sc->nodes_lock);
591 INIT_LIST_HEAD(&sc->nodes);
593 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
594 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
598 * Cache line size is used to size and align various
599 * structures used to communicate with the hardware.
601 ath_read_cachesize(common, &csz);
602 common->cachelsz = csz << 2; /* convert to bytes */
604 /* Initializes the hardware for all supported chipsets */
605 ret = ath9k_hw_init(ah);
609 if (pdata && pdata->macaddr)
610 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
612 ret = ath9k_init_queues(sc);
616 ret = ath9k_init_btcoex(sc);
620 ret = ath9k_init_channels_rates(sc);
624 ath9k_init_crypto(sc);
630 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
631 if (ATH_TXQ_SETUP(sc, i))
632 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
643 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
645 struct ieee80211_supported_band *sband;
646 struct ieee80211_channel *chan;
647 struct ath_hw *ah = sc->sc_ah;
648 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
651 sband = &sc->sbands[band];
652 for (i = 0; i < sband->n_channels; i++) {
653 chan = &sband->channels[i];
654 ah->curchan = &ah->channels[chan->hw_value];
655 ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
656 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
657 chan->max_power = reg->max_power_level / 2;
661 static void ath9k_init_txpower_limits(struct ath_softc *sc)
663 struct ath_hw *ah = sc->sc_ah;
664 struct ath9k_channel *curchan = ah->curchan;
666 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
667 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
668 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
669 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
671 ah->curchan = curchan;
674 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
676 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
678 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
679 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
680 IEEE80211_HW_SIGNAL_DBM |
681 IEEE80211_HW_SUPPORTS_PS |
682 IEEE80211_HW_PS_NULLFUNC_STACK |
683 IEEE80211_HW_SPECTRUM_MGMT |
684 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
686 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
687 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
689 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
690 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
692 hw->wiphy->interface_modes =
693 BIT(NL80211_IFTYPE_P2P_GO) |
694 BIT(NL80211_IFTYPE_P2P_CLIENT) |
695 BIT(NL80211_IFTYPE_AP) |
696 BIT(NL80211_IFTYPE_WDS) |
697 BIT(NL80211_IFTYPE_STATION) |
698 BIT(NL80211_IFTYPE_ADHOC) |
699 BIT(NL80211_IFTYPE_MESH_POINT);
701 if (AR_SREV_5416(sc->sc_ah))
702 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
704 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
708 hw->channel_change_time = 5000;
709 hw->max_listen_interval = 10;
710 hw->max_rate_tries = 10;
711 hw->sta_data_size = sizeof(struct ath_node);
712 hw->vif_data_size = sizeof(struct ath_vif);
714 #ifdef CONFIG_ATH9K_RATE_CONTROL
715 hw->rate_control_algorithm = "ath9k_rate_control";
718 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
719 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
720 &sc->sbands[IEEE80211_BAND_2GHZ];
721 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
722 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
723 &sc->sbands[IEEE80211_BAND_5GHZ];
725 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
726 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
727 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
728 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
729 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
732 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
735 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
736 const struct ath_bus_ops *bus_ops)
738 struct ieee80211_hw *hw = sc->hw;
739 struct ath_common *common;
742 struct ath_regulatory *reg;
744 /* Bring up device */
745 error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
750 common = ath9k_hw_common(ah);
751 ath9k_set_hw_capab(sc, hw);
753 /* Initialize regulatory */
754 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
759 reg = &common->regulatory;
762 error = ath_tx_init(sc, ATH_TXBUF);
767 error = ath_rx_init(sc, ATH_RXBUF);
771 ath9k_init_txpower_limits(sc);
773 #ifdef CONFIG_MAC80211_LEDS
774 /* must be initialized before ieee80211_register_hw */
775 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
776 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
777 ARRAY_SIZE(ath9k_tpt_blink));
780 /* Register with mac80211 */
781 error = ieee80211_register_hw(hw);
785 error = ath9k_init_debug(ah);
787 ath_err(common, "Unable to create debugfs files\n");
791 /* Handle world regulatory */
792 if (!ath_is_world_regd(reg)) {
793 error = regulatory_hint(hw->wiphy, reg->alpha2);
798 INIT_WORK(&sc->hw_check_work, ath_hw_check);
799 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
800 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
801 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
804 ath_start_rfkill_poll(sc);
809 ieee80211_unregister_hw(hw);
817 ath9k_deinit_softc(sc);
822 /*****************************/
823 /* De-Initialization */
824 /*****************************/
826 static void ath9k_deinit_softc(struct ath_softc *sc)
830 if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
831 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
833 if (sc->sbands[IEEE80211_BAND_5GHZ].channels)
834 kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels);
836 if ((sc->btcoex.no_stomp_timer) &&
837 sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
838 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
840 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
841 if (ATH_TXQ_SETUP(sc, i))
842 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
844 ath9k_hw_deinit(sc->sc_ah);
850 void ath9k_deinit_device(struct ath_softc *sc)
852 struct ieee80211_hw *hw = sc->hw;
856 wiphy_rfkill_stop_polling(sc->hw->wiphy);
859 ath9k_ps_restore(sc);
861 ieee80211_unregister_hw(hw);
864 ath9k_deinit_softc(sc);
867 void ath_descdma_cleanup(struct ath_softc *sc,
868 struct ath_descdma *dd,
869 struct list_head *head)
871 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
874 INIT_LIST_HEAD(head);
875 kfree(dd->dd_bufptr);
876 memset(dd, 0, sizeof(*dd));
879 /************************/
881 /************************/
883 static int __init ath9k_init(void)
887 /* Register rate control algorithm */
888 error = ath_rate_control_register();
891 "ath9k: Unable to register rate control "
897 error = ath_pci_init();
900 "ath9k: No PCI devices found, driver not installed.\n");
902 goto err_rate_unregister;
905 error = ath_ahb_init();
917 ath_rate_control_unregister();
921 module_init(ath9k_init);
923 static void __exit ath9k_exit(void)
925 is_ath9k_unloaded = true;
928 ath_rate_control_unregister();
929 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
931 module_exit(ath9k_exit);