drivers/net/wireless/ath/ath9k/eeprom_def.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9002_phy.h"
  19
  20 static void ath9k_get_txgain_index(struct ath_hw *ah,
  21                 struct ath9k_channel *chan,
  22                 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
  23                 u8 *calChans,  u16 availPiers, u8 *pwr, u8 *pcdacIdx)
  24 {
  25         u8 pcdac, i = 0;
  26         u16 idxL = 0, idxR = 0, numPiers;
  27         bool match;
  28         struct chan_centers centers;
  29
  30         ath9k_hw_get_channel_centers(ah, chan, &centers);
  31
  32         for (numPiers = 0; numPiers < availPiers; numPiers++)
  33                 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
  34                         break;
  35
  36         match = ath9k_hw_get_lower_upper_index(
  37                         (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
  38                         calChans, numPiers, &idxL, &idxR);
  39         if (match) {
  40                 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
  41                 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
  42         } else {
  43                 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
  44                 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
  45                                 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
  46         }
  47
  48         while (pcdac > ah->originalGain[i] &&
  49                         i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
  50                 i++;
  51
  52         *pcdacIdx = i;
  53 }
  54
  55 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
  56                                 u32 initTxGain,
  57                                 int txPower,
  58                                 u8 *pPDADCValues)
  59 {
  60         u32 i;
  61         u32 offset;
  62
  63         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
  64                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
  65         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
  66                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
  67
  68         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
  69                         AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
  70
  71         offset = txPower;
  72         for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
  73                 if (i < offset)
  74                         pPDADCValues[i] = 0x0;
  75                 else
  76                         pPDADCValues[i] = 0xFF;
  77 }
  78
  79 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
  80 {
  81         return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
  82 }
  83
  84 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
  85 {
  86         return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
  87 }
  88
  89 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
  90 {
  91 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
  92         struct ath_common *common = ath9k_hw_common(ah);
  93         u16 *eep_data = (u16 *)&ah->eeprom.def;
  94         int addr, ar5416_eep_start_loc = 0x100;
  95
  96         for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
  97                 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
  98                                          eep_data)) {
  99                         ath_err(ath9k_hw_common(ah),
 100                                 "Unable to read eeprom region\n");
 101                         return false;
 102                 }
 103                 eep_data++;
 104         }
 105         return true;
 106 #undef SIZE_EEPROM_DEF
 107 }
 108
 109 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
 110 {
 111         struct ar5416_eeprom_def *eep =
 112                 (struct ar5416_eeprom_def *) &ah->eeprom.def;
 113         struct ath_common *common = ath9k_hw_common(ah);
 114         u16 *eepdata, temp, magic, magic2;
 115         u32 sum = 0, el;
 116         bool need_swap = false;
 117         int i, addr, size;
 118
 119         if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
 120                 ath_err(common, "Reading Magic # failed\n");
 121                 return false;
 122         }
 123
 124         if (!ath9k_hw_use_flash(ah)) {
 125                 ath_dbg(common, ATH_DBG_EEPROM,
 126                         "Read Magic = 0x%04X\n", magic);
 127
 128                 if (magic != AR5416_EEPROM_MAGIC) {
 129                         magic2 = swab16(magic);
 130
 131                         if (magic2 == AR5416_EEPROM_MAGIC) {
 132                                 size = sizeof(struct ar5416_eeprom_def);
 133                                 need_swap = true;
 134                                 eepdata = (u16 *) (&ah->eeprom);
 135
 136                                 for (addr = 0; addr < size / sizeof(u16); addr++) {
 137                                         temp = swab16(*eepdata);
 138                                         *eepdata = temp;
 139                                         eepdata++;
 140                                 }
 141                         } else {
 142                                 ath_err(common,
 143                                         "Invalid EEPROM Magic. Endianness mismatch.\n");
 144                                 return -EINVAL;
 145                         }
 146                 }
 147         }
 148
 149         ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
 150                 need_swap ? "True" : "False");
 151
 152         if (need_swap)
 153                 el = swab16(ah->eeprom.def.baseEepHeader.length);
 154         else
 155                 el = ah->eeprom.def.baseEepHeader.length;
 156
 157         if (el > sizeof(struct ar5416_eeprom_def))
 158                 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
 159         else
 160                 el = el / sizeof(u16);
 161
 162         eepdata = (u16 *)(&ah->eeprom);
 163
 164         for (i = 0; i < el; i++)
 165                 sum ^= *eepdata++;
 166
 167         if (need_swap) {
 168                 u32 integer, j;
 169                 u16 word;
 170
 171                 ath_dbg(common, ATH_DBG_EEPROM,
 172                         "EEPROM Endianness is not native.. Changing.\n");
 173
 174                 word = swab16(eep->baseEepHeader.length);
 175                 eep->baseEepHeader.length = word;
 176
 177                 word = swab16(eep->baseEepHeader.checksum);
 178                 eep->baseEepHeader.checksum = word;
 179
 180                 word = swab16(eep->baseEepHeader.version);
 181                 eep->baseEepHeader.version = word;
 182
 183                 word = swab16(eep->baseEepHeader.regDmn[0]);
 184                 eep->baseEepHeader.regDmn[0] = word;
 185
 186                 word = swab16(eep->baseEepHeader.regDmn[1]);
 187                 eep->baseEepHeader.regDmn[1] = word;
 188
 189                 word = swab16(eep->baseEepHeader.rfSilent);
 190                 eep->baseEepHeader.rfSilent = word;
 191
 192                 word = swab16(eep->baseEepHeader.blueToothOptions);
 193                 eep->baseEepHeader.blueToothOptions = word;
 194
 195                 word = swab16(eep->baseEepHeader.deviceCap);
 196                 eep->baseEepHeader.deviceCap = word;
 197
 198                 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
 199                         struct modal_eep_header *pModal =
 200                                 &eep->modalHeader[j];
 201                         integer = swab32(pModal->antCtrlCommon);
 202                         pModal->antCtrlCommon = integer;
 203
 204                         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 205                                 integer = swab32(pModal->antCtrlChain[i]);
 206                                 pModal->antCtrlChain[i] = integer;
 207                         }
 208
 209                         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 210                                 word = swab16(pModal->spurChans[i].spurChan);
 211                                 pModal->spurChans[i].spurChan = word;
 212                         }
 213                 }
 214         }
 215
 216         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
 217             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
 218                 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 219                         sum, ah->eep_ops->get_eeprom_ver(ah));
 220                 return -EINVAL;
 221         }
 222
 223         /* Enable fixup for AR_AN_TOP2 if necessary */
 224         if (AR_SREV_9280_20_OR_LATER(ah) &&
 225             (eep->baseEepHeader.version & 0xff) > 0x0a &&
 226             eep->baseEepHeader.pwdclkind == 0)
 227                 ah->need_an_top2_fixup = 1;
 228
 229         return 0;
 230 }
 231
 232 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
 233                                    enum eeprom_param param)
 234 {
 235         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 236         struct modal_eep_header *pModal = eep->modalHeader;
 237         struct base_eep_header *pBase = &eep->baseEepHeader;
 238
 239         switch (param) {
 240         case EEP_NFTHRESH_5:
 241                 return pModal[0].noiseFloorThreshCh[0];
 242         case EEP_NFTHRESH_2:
 243                 return pModal[1].noiseFloorThreshCh[0];
 244         case EEP_MAC_LSW:
 245                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
 246         case EEP_MAC_MID:
 247                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
 248         case EEP_MAC_MSW:
 249                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
 250         case EEP_REG_0:
 251                 return pBase->regDmn[0];
 252         case EEP_REG_1:
 253                 return pBase->regDmn[1];
 254         case EEP_OP_CAP:
 255                 return pBase->deviceCap;
 256         case EEP_OP_MODE:
 257                 return pBase->opCapFlags;
 258         case EEP_RF_SILENT:
 259                 return pBase->rfSilent;
 260         case EEP_OB_5:
 261                 return pModal[0].ob;
 262         case EEP_DB_5:
 263                 return pModal[0].db;
 264         case EEP_OB_2:
 265                 return pModal[1].ob;
 266         case EEP_DB_2:
 267                 return pModal[1].db;
 268         case EEP_MINOR_REV:
 269                 return AR5416_VER_MASK;
 270         case EEP_TX_MASK:
 271                 return pBase->txMask;
 272         case EEP_RX_MASK:
 273                 return pBase->rxMask;
 274         case EEP_FSTCLK_5G:
 275                 return pBase->fastClk5g;
 276         case EEP_RXGAIN_TYPE:
 277                 return pBase->rxGainType;
 278         case EEP_TXGAIN_TYPE:
 279                 return pBase->txGainType;
 280         case EEP_OL_PWRCTRL:
 281                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 282                         return pBase->openLoopPwrCntl ? true : false;
 283                 else
 284                         return false;
 285         case EEP_RC_CHAIN_MASK:
 286                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 287                         return pBase->rcChainMask;
 288                 else
 289                         return 0;
 290         case EEP_DAC_HPWR_5G:
 291                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
 292                         return pBase->dacHiPwrMode_5G;
 293                 else
 294                         return 0;
 295         case EEP_FRAC_N_5G:
 296                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
 297                         return pBase->frac_n_5g;
 298                 else
 299                         return 0;
 300         case EEP_PWR_TABLE_OFFSET:
 301                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
 302                         return pBase->pwr_table_offset;
 303                 else
 304                         return AR5416_PWR_TABLE_OFFSET_DB;
 305         default:
 306                 return 0;
 307         }
 308 }
 309
 310 static void ath9k_hw_def_set_gain(struct ath_hw *ah,
 311                                   struct modal_eep_header *pModal,
 312                                   struct ar5416_eeprom_def *eep,
 313                                   u8 txRxAttenLocal, int regChainOffset, int i)
 314 {
 315         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
 316                 txRxAttenLocal = pModal->txRxAttenCh[i];
 317
 318                 if (AR_SREV_9280_20_OR_LATER(ah)) {
 319                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 320                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 321                               pModal->bswMargin[i]);
 322                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 323                               AR_PHY_GAIN_2GHZ_XATTEN1_DB,
 324                               pModal->bswAtten[i]);
 325                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 326                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 327                               pModal->xatten2Margin[i]);
 328                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 329                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 330                               pModal->xatten2Db[i]);
 331                 } else {
 332                         REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 333                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
 334                            ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
 335                           | SM(pModal-> bswMargin[i],
 336                                AR_PHY_GAIN_2GHZ_BSW_MARGIN));
 337                         REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 338                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
 339                            ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
 340                           | SM(pModal->bswAtten[i],
 341                                AR_PHY_GAIN_2GHZ_BSW_ATTEN));
 342                 }
 343         }
 344
 345         if (AR_SREV_9280_20_OR_LATER(ah)) {
 346                 REG_RMW_FIELD(ah,
 347                       AR_PHY_RXGAIN + regChainOffset,
 348                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 349                 REG_RMW_FIELD(ah,
 350                       AR_PHY_RXGAIN + regChainOffset,
 351                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
 352         } else {
 353                 REG_WRITE(ah,
 354                           AR_PHY_RXGAIN + regChainOffset,
 355                           (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
 356                            ~AR_PHY_RXGAIN_TXRX_ATTEN)
 357                           | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
 358                 REG_WRITE(ah,
 359                           AR_PHY_GAIN_2GHZ + regChainOffset,
 360                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
 361                            ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
 362                           SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
 363         }
 364 }
 365
 366 static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
 367                                           struct ath9k_channel *chan)
 368 {
 369         struct modal_eep_header *pModal;
 370         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 371         int i, regChainOffset;
 372         u8 txRxAttenLocal;
 373
 374         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 375         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
 376
 377         REG_WRITE(ah, AR_PHY_SWITCH_COM,
 378                   ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
 379
 380         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 381                 if (AR_SREV_9280(ah)) {
 382                         if (i >= 2)
 383                                 break;
 384                 }
 385
 386                 if (AR_SREV_5416_20_OR_LATER(ah) &&
 387                     (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
 388                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 389                 else
 390                         regChainOffset = i * 0x1000;
 391
 392                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
 393                           pModal->antCtrlChain[i]);
 394
 395                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
 396                           (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
 397                            ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 398                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 399                           SM(pModal->iqCalICh[i],
 400                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 401                           SM(pModal->iqCalQCh[i],
 402                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 403
 404                 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
 405                         ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
 406                                               regChainOffset, i);
 407         }
 408
 409         if (AR_SREV_9280_20_OR_LATER(ah)) {
 410                 if (IS_CHAN_2GHZ(chan)) {
 411                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 412                                                   AR_AN_RF2G1_CH0_OB,
 413                                                   AR_AN_RF2G1_CH0_OB_S,
 414                                                   pModal->ob);
 415                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 416                                                   AR_AN_RF2G1_CH0_DB,
 417                                                   AR_AN_RF2G1_CH0_DB_S,
 418                                                   pModal->db);
 419                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 420                                                   AR_AN_RF2G1_CH1_OB,
 421                                                   AR_AN_RF2G1_CH1_OB_S,
 422                                                   pModal->ob_ch1);
 423                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 424                                                   AR_AN_RF2G1_CH1_DB,
 425                                                   AR_AN_RF2G1_CH1_DB_S,
 426                                                   pModal->db_ch1);
 427                 } else {
 428                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 429                                                   AR_AN_RF5G1_CH0_OB5,
 430                                                   AR_AN_RF5G1_CH0_OB5_S,
 431                                                   pModal->ob);
 432                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 433                                                   AR_AN_RF5G1_CH0_DB5,
 434                                                   AR_AN_RF5G1_CH0_DB5_S,
 435                                                   pModal->db);
 436                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 437                                                   AR_AN_RF5G1_CH1_OB5,
 438                                                   AR_AN_RF5G1_CH1_OB5_S,
 439                                                   pModal->ob_ch1);
 440                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 441                                                   AR_AN_RF5G1_CH1_DB5,
 442                                                   AR_AN_RF5G1_CH1_DB5_S,
 443                                                   pModal->db_ch1);
 444                 }
 445                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 446                                           AR_AN_TOP2_XPABIAS_LVL,
 447                                           AR_AN_TOP2_XPABIAS_LVL_S,
 448                                           pModal->xpaBiasLvl);
 449                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 450                                           AR_AN_TOP2_LOCALBIAS,
 451                                           AR_AN_TOP2_LOCALBIAS_S,
 452                                           !!(pModal->lna_ctl &
 453                                              LNA_CTL_LOCAL_BIAS));
 454                 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
 455                               !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
 456         }
 457
 458         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
 459                       pModal->switchSettling);
 460         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
 461                       pModal->adcDesiredSize);
 462
 463         if (!AR_SREV_9280_20_OR_LATER(ah))
 464                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
 465                               AR_PHY_DESIRED_SZ_PGA,
 466                               pModal->pgaDesiredSize);
 467
 468         REG_WRITE(ah, AR_PHY_RF_CTL4,
 469                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
 470                   | SM(pModal->txEndToXpaOff,
 471                        AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
 472                   | SM(pModal->txFrameToXpaOn,
 473                        AR_PHY_RF_CTL4_FRAME_XPAA_ON)
 474                   | SM(pModal->txFrameToXpaOn,
 475                        AR_PHY_RF_CTL4_FRAME_XPAB_ON));
 476
 477         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
 478                       pModal->txEndToRxOn);
 479
 480         if (AR_SREV_9280_20_OR_LATER(ah)) {
 481                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
 482                               pModal->thresh62);
 483                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
 484                               AR_PHY_EXT_CCA0_THRESH62,
 485                               pModal->thresh62);
 486         } else {
 487                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
 488                               pModal->thresh62);
 489                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
 490                               AR_PHY_EXT_CCA_THRESH62,
 491                               pModal->thresh62);
 492         }
 493
 494         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
 495                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
 496                               AR_PHY_TX_END_DATA_START,
 497                               pModal->txFrameToDataStart);
 498                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
 499                               pModal->txFrameToPaOn);
 500         }
 501
 502         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
 503                 if (IS_CHAN_HT40(chan))
 504                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
 505                                       AR_PHY_SETTLING_SWITCH,
 506                                       pModal->swSettleHt40);
 507         }
 508
 509         if (AR_SREV_9280_20_OR_LATER(ah) &&
 510             AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 511                 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
 512                               AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
 513                               pModal->miscBits);
 514
 515
 516         if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
 517                 if (IS_CHAN_2GHZ(chan))
 518                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
 519                                         eep->baseEepHeader.dacLpMode);
 520                 else if (eep->baseEepHeader.dacHiPwrMode_5G)
 521                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
 522                 else
 523                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
 524                                       eep->baseEepHeader.dacLpMode);
 525
 526                 udelay(100);
 527
 528                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
 529                               pModal->miscBits >> 2);
 530
 531                 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
 532                               AR_PHY_TX_DESIRED_SCALE_CCK,
 533                               eep->baseEepHeader.desiredScaleCCK);
 534         }
 535 }
 536
 537 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
 538                                    struct ath9k_channel *chan)
 539 {
 540 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
 541         struct modal_eep_header *pModal;
 542         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 543         u8 biaslevel;
 544
 545         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
 546                 return;
 547
 548         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
 549                 return;
 550
 551         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 552
 553         if (pModal->xpaBiasLvl != 0xff) {
 554                 biaslevel = pModal->xpaBiasLvl;
 555         } else {
 556                 u16 resetFreqBin, freqBin, freqCount = 0;
 557                 struct chan_centers centers;
 558
 559                 ath9k_hw_get_channel_centers(ah, chan, &centers);
 560
 561                 resetFreqBin = FREQ2FBIN(centers.synth_center,
 562                                          IS_CHAN_2GHZ(chan));
 563                 freqBin = XPA_LVL_FREQ(0) & 0xff;
 564                 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
 565
 566                 freqCount++;
 567
 568                 while (freqCount < 3) {
 569                         if (XPA_LVL_FREQ(freqCount) == 0x0)
 570                                 break;
 571
 572                         freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
 573                         if (resetFreqBin >= freqBin)
 574                                 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
 575                         else
 576                                 break;
 577                         freqCount++;
 578                 }
 579         }
 580
 581         if (IS_CHAN_2GHZ(chan)) {
 582                 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
 583                                         7, 1) & (~0x18)) | biaslevel << 3;
 584         } else {
 585                 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
 586                                         6, 1) & (~0xc0)) | biaslevel << 6;
 587         }
 588 #undef XPA_LVL_FREQ
 589 }
 590
 591 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
 592                                 u16 *gb,
 593                                 u16 numXpdGain,
 594                                 u16 pdGainOverlap_t2,
 595                                 int8_t pwr_table_offset,
 596                                 int16_t *diff)
 597
 598 {
 599         u16 k;
 600
 601         /* Prior to writing the boundaries or the pdadc vs. power table
 602          * into the chip registers the default starting point on the pdadc
 603          * vs. power table needs to be checked and the curve boundaries
 604          * adjusted accordingly
 605          */
 606         if (AR_SREV_9280_20_OR_LATER(ah)) {
 607                 u16 gb_limit;
 608
 609                 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
 610                         /* get the difference in dB */
 611                         *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
 612                         /* get the number of half dB steps */
 613                         *diff *= 2;
 614                         /* change the original gain boundary settings
 615                          * by the number of half dB steps
 616                          */
 617                         for (k = 0; k < numXpdGain; k++)
 618                                 gb[k] = (u16)(gb[k] - *diff);
 619                 }
 620                 /* Because of a hardware limitation, ensure the gain boundary
 621                  * is not larger than (63 - overlap)
 622                  */
 623                 gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2);
 624
 625                 for (k = 0; k < numXpdGain; k++)
 626                         gb[k] = (u16)min(gb_limit, gb[k]);
 627         }
 628
 629         return *diff;
 630 }
 631
 632 static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
 633                                       int8_t pwr_table_offset,
 634                                       int16_t diff,
 635                                       u8 *pdadcValues)
 636 {
 637 #define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
 638         u16 k;
 639
 640         /* If this is a board that has a pwrTableOffset that differs from
 641          * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
 642          * pdadc vs pwr table needs to be adjusted prior to writing to the
 643          * chip.
 644          */
 645         if (AR_SREV_9280_20_OR_LATER(ah)) {
 646                 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
 647                         /* shift the table to start at the new offset */
 648                         for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
 649                                 pdadcValues[k] = pdadcValues[k + diff];
 650                         }
 651
 652                         /* fill the back of the table */
 653                         for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
 654                                 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
 655                         }
 656                 }
 657         }
 658 #undef NUM_PDADC
 659 }
 660
 661 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
 662                                   struct ath9k_channel *chan,
 663                                   int16_t *pTxPowerIndexOffset)
 664 {
 665 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
 666 #define SM_PDGAIN_B(x, y) \
 667                 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
 668         struct ath_common *common = ath9k_hw_common(ah);
 669         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
 670         struct cal_data_per_freq *pRawDataset;
 671         u8 *pCalBChans = NULL;
 672         u16 pdGainOverlap_t2;
 673         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 674         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
 675         u16 numPiers, i, j;
 676         int16_t diff = 0;
 677         u16 numXpdGain, xpdMask;
 678         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
 679         u32 reg32, regOffset, regChainOffset;
 680         int16_t modalIdx;
 681         int8_t pwr_table_offset;
 682
 683         modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
 684         xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
 685
 686         pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
 687
 688         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 689             AR5416_EEP_MINOR_VER_2) {
 690                 pdGainOverlap_t2 =
 691                         pEepData->modalHeader[modalIdx].pdGainOverlap;
 692         } else {
 693                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 694                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 695         }
 696
 697         if (IS_CHAN_2GHZ(chan)) {
 698                 pCalBChans = pEepData->calFreqPier2G;
 699                 numPiers = AR5416_NUM_2G_CAL_PIERS;
 700         } else {
 701                 pCalBChans = pEepData->calFreqPier5G;
 702                 numPiers = AR5416_NUM_5G_CAL_PIERS;
 703         }
 704
 705         if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
 706                 pRawDataset = pEepData->calPierData2G[0];
 707                 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
 708                                  pRawDataset)->vpdPdg[0][0];
 709         }
 710
 711         numXpdGain = 0;
 712
 713         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
 714                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
 715                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
 716                                 break;
 717                         xpdGainValues[numXpdGain] =
 718                                 (u16)(AR5416_PD_GAINS_IN_MASK - i);
 719                         numXpdGain++;
 720                 }
 721         }
 722
 723         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 724                       (numXpdGain - 1) & 0x3);
 725         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 726                       xpdGainValues[0]);
 727         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 728                       xpdGainValues[1]);
 729         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
 730                       xpdGainValues[2]);
 731
 732         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 733                 if (AR_SREV_5416_20_OR_LATER(ah) &&
 734                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
 735                     (i != 0)) {
 736                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 737                 } else
 738                         regChainOffset = i * 0x1000;
 739
 740                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 741                         if (IS_CHAN_2GHZ(chan))
 742                                 pRawDataset = pEepData->calPierData2G[i];
 743                         else
 744                                 pRawDataset = pEepData->calPierData5G[i];
 745
 746
 747                         if (OLC_FOR_AR9280_20_LATER) {
 748                                 u8 pcdacIdx;
 749                                 u8 txPower;
 750
 751                                 ath9k_get_txgain_index(ah, chan,
 752                                 (struct calDataPerFreqOpLoop *)pRawDataset,
 753                                 pCalBChans, numPiers, &txPower, &pcdacIdx);
 754                                 ath9k_olc_get_pdadcs(ah, pcdacIdx,
 755                                                      txPower/2, pdadcValues);
 756                         } else {
 757                                 ath9k_hw_get_gain_boundaries_pdadcs(ah,
 758                                                         chan, pRawDataset,
 759                                                         pCalBChans, numPiers,
 760                                                         pdGainOverlap_t2,
 761                                                         gainBoundaries,
 762                                                         pdadcValues,
 763                                                         numXpdGain);
 764                         }
 765
 766                         diff = ath9k_change_gain_boundary_setting(ah,
 767                                                            gainBoundaries,
 768                                                            numXpdGain,
 769                                                            pdGainOverlap_t2,
 770                                                            pwr_table_offset,
 771                                                            &diff);
 772
 773                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
 774                                 if (OLC_FOR_AR9280_20_LATER) {
 775                                         REG_WRITE(ah,
 776                                                 AR_PHY_TPCRG5 + regChainOffset,
 777                                                 SM(0x6,
 778                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
 779                                                 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
 780                                                 SM_PD_GAIN(3) | SM_PD_GAIN(4));
 781                                 } else {
 782                                         REG_WRITE(ah,
 783                                                 AR_PHY_TPCRG5 + regChainOffset,
 784                                                 SM(pdGainOverlap_t2,
 785                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
 786                                                 SM_PDGAIN_B(0, 1) |
 787                                                 SM_PDGAIN_B(1, 2) |
 788                                                 SM_PDGAIN_B(2, 3) |
 789                                                 SM_PDGAIN_B(3, 4));
 790                                 }
 791                         }
 792
 793
 794                         ath9k_adjust_pdadc_values(ah, pwr_table_offset,
 795                                                   diff, pdadcValues);
 796
 797                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
 798                         for (j = 0; j < 32; j++) {
 799                                 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
 800                                         ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
 801                                         ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
 802                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
 803                                 REG_WRITE(ah, regOffset, reg32);
 804
 805                                 ath_dbg(common, ATH_DBG_EEPROM,
 806                                         "PDADC (%d,%4x): %4.4x %8.8x\n",
 807                                         i, regChainOffset, regOffset,
 808                                         reg32);
 809                                 ath_dbg(common, ATH_DBG_EEPROM,
 810                                         "PDADC: Chain %d | PDADC %3d "
 811                                         "Value %3d | PDADC %3d Value %3d | "
 812                                         "PDADC %3d Value %3d | PDADC %3d "
 813                                         "Value %3d |\n",
 814                                         i, 4 * j, pdadcValues[4 * j],
 815                                         4 * j + 1, pdadcValues[4 * j + 1],
 816                                         4 * j + 2, pdadcValues[4 * j + 2],
 817                                         4 * j + 3, pdadcValues[4 * j + 3]);
 818
 819                                 regOffset += 4;
 820                         }
 821                 }
 822         }
 823
 824         *pTxPowerIndexOffset = 0;
 825 #undef SM_PD_GAIN
 826 #undef SM_PDGAIN_B
 827 }
 828
 829 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
 830                                                   struct ath9k_channel *chan,
 831                                                   int16_t *ratesArray,
 832                                                   u16 cfgCtl,
 833                                                   u16 AntennaReduction,
 834                                                   u16 twiceMaxRegulatoryPower,
 835                                                   u16 powerLimit)
 836 {
 837 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
 838 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9 /* 10*log10(3)*2 */
 839
 840         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 841         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
 842         u16 twiceMaxEdgePower = MAX_RATE_POWER;
 843         static const u16 tpScaleReductionTable[5] =
 844                 { 0, 3, 6, 9, MAX_RATE_POWER };
 845
 846         int i;
 847         int16_t twiceLargestAntenna;
 848         struct cal_ctl_data *rep;
 849         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
 850                 0, { 0, 0, 0, 0}
 851         };
 852         struct cal_target_power_leg targetPowerOfdmExt = {
 853                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
 854                 0, { 0, 0, 0, 0 }
 855         };
 856         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
 857                 0, {0, 0, 0, 0}
 858         };
 859         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
 860         static const u16 ctlModesFor11a[] = {
 861                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
 862         };
 863         static const u16 ctlModesFor11g[] = {
 864                 CTL_11B, CTL_11G, CTL_2GHT20,
 865                 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
 866         };
 867         u16 numCtlModes;
 868         const u16 *pCtlMode;
 869         u16 ctlMode, freq;
 870         struct chan_centers centers;
 871         int tx_chainmask;
 872         u16 twiceMinEdgePower;
 873
 874         tx_chainmask = ah->txchainmask;
 875
 876         ath9k_hw_get_channel_centers(ah, chan, &centers);
 877
 878         twiceLargestAntenna = max(
 879                 pEepData->modalHeader
 880                         [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
 881                 pEepData->modalHeader
 882                         [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
 883
 884         twiceLargestAntenna = max((u8)twiceLargestAntenna,
 885                                   pEepData->modalHeader
 886                                   [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
 887
 888         twiceLargestAntenna = (int16_t)min(AntennaReduction -
 889                                            twiceLargestAntenna, 0);
 890
 891         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
 892
 893         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
 894                 maxRegAllowedPower -=
 895                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
 896         }
 897
 898         scaledPower = min(powerLimit, maxRegAllowedPower);
 899
 900         switch (ar5416_get_ntxchains(tx_chainmask)) {
 901         case 1:
 902                 break;
 903         case 2:
 904                 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
 905                         scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
 906                 else
 907                         scaledPower = 0;
 908                 break;
 909         case 3:
 910                 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
 911                         scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
 912                 else
 913                         scaledPower = 0;
 914                 break;
 915         }
 916
 917         if (IS_CHAN_2GHZ(chan)) {
 918                 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
 919                         SUB_NUM_CTL_MODES_AT_2G_40;
 920                 pCtlMode = ctlModesFor11g;
 921
 922                 ath9k_hw_get_legacy_target_powers(ah, chan,
 923                         pEepData->calTargetPowerCck,
 924                         AR5416_NUM_2G_CCK_TARGET_POWERS,
 925                         &targetPowerCck, 4, false);
 926                 ath9k_hw_get_legacy_target_powers(ah, chan,
 927                         pEepData->calTargetPower2G,
 928                         AR5416_NUM_2G_20_TARGET_POWERS,
 929                         &targetPowerOfdm, 4, false);
 930                 ath9k_hw_get_target_powers(ah, chan,
 931                         pEepData->calTargetPower2GHT20,
 932                         AR5416_NUM_2G_20_TARGET_POWERS,
 933                         &targetPowerHt20, 8, false);
 934
 935                 if (IS_CHAN_HT40(chan)) {
 936                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
 937                         ath9k_hw_get_target_powers(ah, chan,
 938                                 pEepData->calTargetPower2GHT40,
 939                                 AR5416_NUM_2G_40_TARGET_POWERS,
 940                                 &targetPowerHt40, 8, true);
 941                         ath9k_hw_get_legacy_target_powers(ah, chan,
 942                                 pEepData->calTargetPowerCck,
 943                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
 944                                 &targetPowerCckExt, 4, true);
 945                         ath9k_hw_get_legacy_target_powers(ah, chan,
 946                                 pEepData->calTargetPower2G,
 947                                 AR5416_NUM_2G_20_TARGET_POWERS,
 948                                 &targetPowerOfdmExt, 4, true);
 949                 }
 950         } else {
 951                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
 952                         SUB_NUM_CTL_MODES_AT_5G_40;
 953                 pCtlMode = ctlModesFor11a;
 954
 955                 ath9k_hw_get_legacy_target_powers(ah, chan,
 956                         pEepData->calTargetPower5G,
 957                         AR5416_NUM_5G_20_TARGET_POWERS,
 958                         &targetPowerOfdm, 4, false);
 959                 ath9k_hw_get_target_powers(ah, chan,
 960                         pEepData->calTargetPower5GHT20,
 961                         AR5416_NUM_5G_20_TARGET_POWERS,
 962                         &targetPowerHt20, 8, false);
 963
 964                 if (IS_CHAN_HT40(chan)) {
 965                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
 966                         ath9k_hw_get_target_powers(ah, chan,
 967                                 pEepData->calTargetPower5GHT40,
 968                                 AR5416_NUM_5G_40_TARGET_POWERS,
 969                                 &targetPowerHt40, 8, true);
 970                         ath9k_hw_get_legacy_target_powers(ah, chan,
 971                                 pEepData->calTargetPower5G,
 972                                 AR5416_NUM_5G_20_TARGET_POWERS,
 973                                 &targetPowerOfdmExt, 4, true);
 974                 }
 975         }
 976
 977         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
 978                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
 979                         (pCtlMode[ctlMode] == CTL_2GHT40);
 980                 if (isHt40CtlMode)
 981                         freq = centers.synth_center;
 982                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
 983                         freq = centers.ext_center;
 984                 else
 985                         freq = centers.ctl_center;
 986
 987                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
 988                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
 989                         twiceMaxEdgePower = MAX_RATE_POWER;
 990
 991                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
 992                         if ((((cfgCtl & ~CTL_MODE_M) |
 993                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
 994                              pEepData->ctlIndex[i]) ||
 995                             (((cfgCtl & ~CTL_MODE_M) |
 996                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
 997                              ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
 998                                 rep = &(pEepData->ctlData[i]);
 999
1000                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1001                                 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1002                                 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1003
1004                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1005                                         twiceMaxEdgePower = min(twiceMaxEdgePower,
1006                                                                 twiceMinEdgePower);
1007                                 } else {
1008                                         twiceMaxEdgePower = twiceMinEdgePower;
1009                                         break;
1010                                 }
1011                         }
1012                 }
1013
1014                 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1015
1016                 switch (pCtlMode[ctlMode]) {
1017                 case CTL_11B:
1018                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1019                                 targetPowerCck.tPow2x[i] =
1020                                         min((u16)targetPowerCck.tPow2x[i],
1021                                             minCtlPower);
1022                         }
1023                         break;
1024                 case CTL_11A:
1025                 case CTL_11G:
1026                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1027                                 targetPowerOfdm.tPow2x[i] =
1028                                         min((u16)targetPowerOfdm.tPow2x[i],
1029                                             minCtlPower);
1030                         }
1031                         break;
1032                 case CTL_5GHT20:
1033                 case CTL_2GHT20:
1034                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1035                                 targetPowerHt20.tPow2x[i] =
1036                                         min((u16)targetPowerHt20.tPow2x[i],
1037                                             minCtlPower);
1038                         }
1039                         break;
1040                 case CTL_11B_EXT:
1041                         targetPowerCckExt.tPow2x[0] = min((u16)
1042                                         targetPowerCckExt.tPow2x[0],
1043                                         minCtlPower);
1044                         break;
1045                 case CTL_11A_EXT:
1046                 case CTL_11G_EXT:
1047                         targetPowerOfdmExt.tPow2x[0] = min((u16)
1048                                         targetPowerOfdmExt.tPow2x[0],
1049                                         minCtlPower);
1050                         break;
1051                 case CTL_5GHT40:
1052                 case CTL_2GHT40:
1053                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1054                                 targetPowerHt40.tPow2x[i] =
1055                                         min((u16)targetPowerHt40.tPow2x[i],
1056                                             minCtlPower);
1057                         }
1058                         break;
1059                 default:
1060                         break;
1061                 }
1062         }
1063
1064         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1065                 ratesArray[rate18mb] = ratesArray[rate24mb] =
1066                 targetPowerOfdm.tPow2x[0];
1067         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1068         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1069         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1070         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1071
1072         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1073                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1074
1075         if (IS_CHAN_2GHZ(chan)) {
1076                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1077                 ratesArray[rate2s] = ratesArray[rate2l] =
1078                         targetPowerCck.tPow2x[1];
1079                 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1080                         targetPowerCck.tPow2x[2];
1081                 ratesArray[rate11s] = ratesArray[rate11l] =
1082                         targetPowerCck.tPow2x[3];
1083         }
1084         if (IS_CHAN_HT40(chan)) {
1085                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1086                         ratesArray[rateHt40_0 + i] =
1087                                 targetPowerHt40.tPow2x[i];
1088                 }
1089                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1090                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1091                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1092                 if (IS_CHAN_2GHZ(chan)) {
1093                         ratesArray[rateExtCck] =
1094                                 targetPowerCckExt.tPow2x[0];
1095                 }
1096         }
1097 }
1098
1099 static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1100                                     struct ath9k_channel *chan,
1101                                     u16 cfgCtl,
1102                                     u8 twiceAntennaReduction,
1103                                     u8 twiceMaxRegulatoryPower,
1104                                     u8 powerLimit, bool test)
1105 {
1106 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1107         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1108         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1109         struct modal_eep_header *pModal =
1110                 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1111         int16_t ratesArray[Ar5416RateSize];
1112         int16_t txPowerIndexOffset = 0;
1113         u8 ht40PowerIncForPdadc = 2;
1114         int i, cck_ofdm_delta = 0;
1115
1116         memset(ratesArray, 0, sizeof(ratesArray));
1117
1118         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1119             AR5416_EEP_MINOR_VER_2) {
1120                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1121         }
1122
1123         ath9k_hw_set_def_power_per_rate_table(ah, chan,
1124                                                &ratesArray[0], cfgCtl,
1125                                                twiceAntennaReduction,
1126                                                twiceMaxRegulatoryPower,
1127                                                powerLimit);
1128
1129         ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
1130
1131         regulatory->max_power_level = 0;
1132         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1133                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1134                 if (ratesArray[i] > MAX_RATE_POWER)
1135                         ratesArray[i] = MAX_RATE_POWER;
1136                 if (ratesArray[i] > regulatory->max_power_level)
1137                         regulatory->max_power_level = ratesArray[i];
1138         }
1139
1140         if (!test) {
1141                 i = rate6mb;
1142
1143                 if (IS_CHAN_HT40(chan))
1144                         i = rateHt40_0;
1145                 else if (IS_CHAN_HT20(chan))
1146                         i = rateHt20_0;
1147
1148                 regulatory->max_power_level = ratesArray[i];
1149         }
1150
1151         switch(ar5416_get_ntxchains(ah->txchainmask)) {
1152         case 1:
1153                 break;
1154         case 2:
1155                 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
1156                 break;
1157         case 3:
1158                 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1159                 break;
1160         default:
1161                 ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1162                         "Invalid chainmask configuration\n");
1163                 break;
1164         }
1165
1166         if (test)
1167                 return;
1168
1169         if (AR_SREV_9280_20_OR_LATER(ah)) {
1170                 for (i = 0; i < Ar5416RateSize; i++) {
1171                         int8_t pwr_table_offset;
1172
1173                         pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1174                                                         EEP_PWR_TABLE_OFFSET);
1175                         ratesArray[i] -= pwr_table_offset * 2;
1176                 }
1177         }
1178
1179         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1180                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
1181                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1182                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1183                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1184         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1185                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
1186                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1187                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1188                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1189
1190         if (IS_CHAN_2GHZ(chan)) {
1191                 if (OLC_FOR_AR9280_20_LATER) {
1192                         cck_ofdm_delta = 2;
1193                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1194                                 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1195                                 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1196                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1197                                 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1198                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1199                                 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1200                                 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1201                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1202                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1203                 } else {
1204                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1205                                 ATH9K_POW_SM(ratesArray[rate2s], 24)
1206                                 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1207                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1208                                 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1209                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1210                                 ATH9K_POW_SM(ratesArray[rate11s], 24)
1211                                 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1212                                 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1213                                 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1214                 }
1215         }
1216
1217         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1218                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1219                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1220                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1221                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1222         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1223                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1224                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1225                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1226                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1227
1228         if (IS_CHAN_HT40(chan)) {
1229                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1230                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
1231                                        ht40PowerIncForPdadc, 24)
1232                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1233                                          ht40PowerIncForPdadc, 16)
1234                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1235                                          ht40PowerIncForPdadc, 8)
1236                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1237                                          ht40PowerIncForPdadc, 0));
1238                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1239                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
1240                                        ht40PowerIncForPdadc, 24)
1241                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1242                                          ht40PowerIncForPdadc, 16)
1243                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1244                                          ht40PowerIncForPdadc, 8)
1245                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1246                                          ht40PowerIncForPdadc, 0));
1247                 if (OLC_FOR_AR9280_20_LATER) {
1248                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1249                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1250                                 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1251                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1252                                 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1253                 } else {
1254                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1255                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1256                                 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1257                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1258                                 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1259                 }
1260         }
1261
1262         REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1263                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1264                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1265 }
1266
1267 static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
1268                                           enum ath9k_hal_freq_band freq_band)
1269 {
1270         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1271         struct modal_eep_header *pModal =
1272                 &(eep->modalHeader[freq_band]);
1273         struct base_eep_header *pBase = &eep->baseEepHeader;
1274         u8 num_ant_config;
1275
1276         num_ant_config = 1;
1277
1278         if (pBase->version >= 0x0E0D &&
1279             (pModal->lna_ctl & LNA_CTL_USE_ANT1))
1280                 num_ant_config += 1;
1281
1282         return num_ant_config;
1283 }
1284
1285 static u32 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
1286                                                struct ath9k_channel *chan)
1287 {
1288         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1289         struct modal_eep_header *pModal =
1290                 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1291
1292         return pModal->antCtrlCommon;
1293 }
1294
1295 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1296 {
1297 #define EEP_DEF_SPURCHAN \
1298         (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1299         struct ath_common *common = ath9k_hw_common(ah);
1300
1301         u16 spur_val = AR_NO_SPUR;
1302
1303         ath_dbg(common, ATH_DBG_ANI,
1304                 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1305                 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1306
1307         switch (ah->config.spurmode) {
1308         case SPUR_DISABLE:
1309                 break;
1310         case SPUR_ENABLE_IOCTL:
1311                 spur_val = ah->config.spurchans[i][is2GHz];
1312                 ath_dbg(common, ATH_DBG_ANI,
1313                         "Getting spur val from new loc. %d\n", spur_val);
1314                 break;
1315         case SPUR_ENABLE_EEPROM:
1316                 spur_val = EEP_DEF_SPURCHAN;
1317                 break;
1318         }
1319
1320         return spur_val;
1321
1322 #undef EEP_DEF_SPURCHAN
1323 }
1324
1325 const struct eeprom_ops eep_def_ops = {
1326         .check_eeprom           = ath9k_hw_def_check_eeprom,
1327         .get_eeprom             = ath9k_hw_def_get_eeprom,
1328         .fill_eeprom            = ath9k_hw_def_fill_eeprom,
1329         .get_eeprom_ver         = ath9k_hw_def_get_eeprom_ver,
1330         .get_eeprom_rev         = ath9k_hw_def_get_eeprom_rev,
1331         .get_num_ant_config     = ath9k_hw_def_get_num_ant_config,
1332         .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
1333         .set_board_values       = ath9k_hw_def_set_board_values,
1334         .set_addac              = ath9k_hw_def_set_addac,
1335         .set_txpower            = ath9k_hw_def_set_txpower,
1336         .get_spur_channel       = ath9k_hw_def_get_spur_channel
1337 };