drivers/net/wireless/ath/ath9k/eeprom_9287.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9002_phy.h"
  19
  20 #define NUM_EEP_WORDS (sizeof(struct ar9287_eeprom) / sizeof(u16))
  21
  22 static int ath9k_hw_ar9287_get_eeprom_ver(struct ath_hw *ah)
  23 {
  24         return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
  25 }
  26
  27 static int ath9k_hw_ar9287_get_eeprom_rev(struct ath_hw *ah)
  28 {
  29         return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF;
  30 }
  31
  32 static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
  33 {
  34         struct ar9287_eeprom *eep = &ah->eeprom.map9287;
  35         struct ath_common *common = ath9k_hw_common(ah);
  36         u16 *eep_data;
  37         int addr, eep_start_loc;
  38         eep_data = (u16 *)eep;
  39
  40         if (common->bus_ops->ath_bus_type == ATH_USB)
  41                 eep_start_loc = AR9287_HTC_EEP_START_LOC;
  42         else
  43                 eep_start_loc = AR9287_EEP_START_LOC;
  44
  45         if (!ath9k_hw_use_flash(ah)) {
  46                 ath_dbg(common, ATH_DBG_EEPROM,
  47                         "Reading from EEPROM, not flash\n");
  48         }
  49
  50         for (addr = 0; addr < NUM_EEP_WORDS; addr++) {
  51                 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc,
  52                                          eep_data)) {
  53                         ath_dbg(common, ATH_DBG_EEPROM,
  54                                 "Unable to read eeprom region\n");
  55                         return false;
  56                 }
  57                 eep_data++;
  58         }
  59
  60         return true;
  61 }
  62
  63 static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
  64 {
  65         u32 sum = 0, el, integer;
  66         u16 temp, word, magic, magic2, *eepdata;
  67         int i, addr;
  68         bool need_swap = false;
  69         struct ar9287_eeprom *eep = &ah->eeprom.map9287;
  70         struct ath_common *common = ath9k_hw_common(ah);
  71
  72         if (!ath9k_hw_use_flash(ah)) {
  73                 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
  74                                          &magic)) {
  75                         ath_err(common, "Reading Magic # failed\n");
  76                         return false;
  77                 }
  78
  79                 ath_dbg(common, ATH_DBG_EEPROM,
  80                         "Read Magic = 0x%04X\n", magic);
  81
  82                 if (magic != AR5416_EEPROM_MAGIC) {
  83                         magic2 = swab16(magic);
  84
  85                         if (magic2 == AR5416_EEPROM_MAGIC) {
  86                                 need_swap = true;
  87                                 eepdata = (u16 *)(&ah->eeprom);
  88
  89                                 for (addr = 0; addr < NUM_EEP_WORDS; addr++) {
  90                                         temp = swab16(*eepdata);
  91                                         *eepdata = temp;
  92                                         eepdata++;
  93                                 }
  94                         } else {
  95                                 ath_err(common,
  96                                         "Invalid EEPROM Magic. Endianness mismatch.\n");
  97                                 return -EINVAL;
  98                         }
  99                 }
 100         }
 101
 102         ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
 103                 need_swap ? "True" : "False");
 104
 105         if (need_swap)
 106                 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
 107         else
 108                 el = ah->eeprom.map9287.baseEepHeader.length;
 109
 110         if (el > sizeof(struct ar9287_eeprom))
 111                 el = sizeof(struct ar9287_eeprom) / sizeof(u16);
 112         else
 113                 el = el / sizeof(u16);
 114
 115         eepdata = (u16 *)(&ah->eeprom);
 116
 117         for (i = 0; i < el; i++)
 118                 sum ^= *eepdata++;
 119
 120         if (need_swap) {
 121                 word = swab16(eep->baseEepHeader.length);
 122                 eep->baseEepHeader.length = word;
 123
 124                 word = swab16(eep->baseEepHeader.checksum);
 125                 eep->baseEepHeader.checksum = word;
 126
 127                 word = swab16(eep->baseEepHeader.version);
 128                 eep->baseEepHeader.version = word;
 129
 130                 word = swab16(eep->baseEepHeader.regDmn[0]);
 131                 eep->baseEepHeader.regDmn[0] = word;
 132
 133                 word = swab16(eep->baseEepHeader.regDmn[1]);
 134                 eep->baseEepHeader.regDmn[1] = word;
 135
 136                 word = swab16(eep->baseEepHeader.rfSilent);
 137                 eep->baseEepHeader.rfSilent = word;
 138
 139                 word = swab16(eep->baseEepHeader.blueToothOptions);
 140                 eep->baseEepHeader.blueToothOptions = word;
 141
 142                 word = swab16(eep->baseEepHeader.deviceCap);
 143                 eep->baseEepHeader.deviceCap = word;
 144
 145                 integer = swab32(eep->modalHeader.antCtrlCommon);
 146                 eep->modalHeader.antCtrlCommon = integer;
 147
 148                 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
 149                         integer = swab32(eep->modalHeader.antCtrlChain[i]);
 150                         eep->modalHeader.antCtrlChain[i] = integer;
 151                 }
 152
 153                 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 154                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
 155                         eep->modalHeader.spurChans[i].spurChan = word;
 156                 }
 157         }
 158
 159         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
 160             || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
 161                 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 162                         sum, ah->eep_ops->get_eeprom_ver(ah));
 163                 return -EINVAL;
 164         }
 165
 166         return 0;
 167 }
 168
 169 static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
 170                                       enum eeprom_param param)
 171 {
 172         struct ar9287_eeprom *eep = &ah->eeprom.map9287;
 173         struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
 174         struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
 175         u16 ver_minor;
 176
 177         ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK;
 178
 179         switch (param) {
 180         case EEP_NFTHRESH_2:
 181                 return pModal->noiseFloorThreshCh[0];
 182         case EEP_MAC_LSW:
 183                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
 184         case EEP_MAC_MID:
 185                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
 186         case EEP_MAC_MSW:
 187                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
 188         case EEP_REG_0:
 189                 return pBase->regDmn[0];
 190         case EEP_REG_1:
 191                 return pBase->regDmn[1];
 192         case EEP_OP_CAP:
 193                 return pBase->deviceCap;
 194         case EEP_OP_MODE:
 195                 return pBase->opCapFlags;
 196         case EEP_RF_SILENT:
 197                 return pBase->rfSilent;
 198         case EEP_MINOR_REV:
 199                 return ver_minor;
 200         case EEP_TX_MASK:
 201                 return pBase->txMask;
 202         case EEP_RX_MASK:
 203                 return pBase->rxMask;
 204         case EEP_DEV_TYPE:
 205                 return pBase->deviceType;
 206         case EEP_OL_PWRCTRL:
 207                 return pBase->openLoopPwrCntl;
 208         case EEP_TEMPSENSE_SLOPE:
 209                 if (ver_minor >= AR9287_EEP_MINOR_VER_2)
 210                         return pBase->tempSensSlope;
 211                 else
 212                         return 0;
 213         case EEP_TEMPSENSE_SLOPE_PAL_ON:
 214                 if (ver_minor >= AR9287_EEP_MINOR_VER_3)
 215                         return pBase->tempSensSlopePalOn;
 216                 else
 217                         return 0;
 218         default:
 219                 return 0;
 220         }
 221 }
 222
 223 static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah,
 224                                struct ath9k_channel *chan,
 225                                struct cal_data_per_freq_ar9287 *pRawDataSet,
 226                                u8 *bChans, u16 availPiers,
 227                                u16 tPdGainOverlap,
 228                                u16 *pPdGainBoundaries,
 229                                u8 *pPDADCValues,
 230                                u16 numXpdGains)
 231 {
 232 #define TMP_VAL_VPD_TABLE                                               \
 233         ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
 234
 235         int i, j, k;
 236         int16_t ss;
 237         u16 idxL = 0, idxR = 0, numPiers;
 238         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
 239         u8 minPwrT4[AR5416_NUM_PD_GAINS];
 240         u8 maxPwrT4[AR5416_NUM_PD_GAINS];
 241         int16_t vpdStep;
 242         int16_t tmpVal;
 243         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
 244         bool match;
 245         int16_t minDelta = 0;
 246         struct chan_centers centers;
 247         static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
 248                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 249         static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
 250                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 251         static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
 252                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 253
 254         memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
 255         ath9k_hw_get_channel_centers(ah, chan, &centers);
 256
 257         for (numPiers = 0; numPiers < availPiers; numPiers++) {
 258                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
 259                         break;
 260         }
 261
 262         match = ath9k_hw_get_lower_upper_index(
 263                 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
 264                 bChans, numPiers, &idxL, &idxR);
 265
 266         if (match) {
 267                 for (i = 0; i < numXpdGains; i++) {
 268                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
 269                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
 270                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 271                                                 pRawDataSet[idxL].pwrPdg[i],
 272                                                 pRawDataSet[idxL].vpdPdg[i],
 273                                                 AR9287_PD_GAIN_ICEPTS,
 274                                                 vpdTableI[i]);
 275                 }
 276         } else {
 277                 for (i = 0; i < numXpdGains; i++) {
 278                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
 279                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
 280                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
 281                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
 282
 283                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
 284
 285                         maxPwrT4[i] = min(pPwrL[AR9287_PD_GAIN_ICEPTS - 1],
 286                                           pPwrR[AR9287_PD_GAIN_ICEPTS - 1]);
 287
 288                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 289                                                 pPwrL, pVpdL,
 290                                                 AR9287_PD_GAIN_ICEPTS,
 291                                                 vpdTableL[i]);
 292                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 293                                                 pPwrR, pVpdR,
 294                                                 AR9287_PD_GAIN_ICEPTS,
 295                                                 vpdTableR[i]);
 296
 297                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
 298                                 vpdTableI[i][j] = (u8)(ath9k_hw_interpolate(
 299                                        (u16)FREQ2FBIN(centers. synth_center,
 300                                                       IS_CHAN_2GHZ(chan)),
 301                                        bChans[idxL], bChans[idxR],
 302                                        vpdTableL[i][j], vpdTableR[i][j]));
 303                         }
 304                 }
 305         }
 306
 307         k = 0;
 308
 309         for (i = 0; i < numXpdGains; i++) {
 310                 if (i == (numXpdGains - 1))
 311                         pPdGainBoundaries[i] =
 312                                 (u16)(maxPwrT4[i] / 2);
 313                 else
 314                         pPdGainBoundaries[i] =
 315                                 (u16)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
 316
 317                 pPdGainBoundaries[i] = min((u16)MAX_RATE_POWER,
 318                                            pPdGainBoundaries[i]);
 319
 320
 321                 minDelta = 0;
 322
 323                 if (i == 0) {
 324                         if (AR_SREV_9280_20_OR_LATER(ah))
 325                                 ss = (int16_t)(0 - (minPwrT4[i] / 2));
 326                         else
 327                                 ss = 0;
 328                 } else {
 329                         ss = (int16_t)((pPdGainBoundaries[i-1] -
 330                                         (minPwrT4[i] / 2)) -
 331                                        tPdGainOverlap + 1 + minDelta);
 332                 }
 333
 334                 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
 335                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 336
 337                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 338                         tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
 339                         pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
 340                         ss++;
 341                 }
 342
 343                 sizeCurrVpdTable = (u8)((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
 344                 tgtIndex = (u8)(pPdGainBoundaries[i] +
 345                                 tPdGainOverlap - (minPwrT4[i] / 2));
 346                 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
 347                             tgtIndex : sizeCurrVpdTable;
 348
 349                 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
 350                         pPDADCValues[k++] = vpdTableI[i][ss++];
 351
 352                 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
 353                                     vpdTableI[i][sizeCurrVpdTable - 2]);
 354                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 355
 356                 if (tgtIndex > maxIndex) {
 357                         while ((ss <= tgtIndex) &&
 358                                 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 359                                 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
 360                                 pPDADCValues[k++] =
 361                                         (u8)((tmpVal > 255) ? 255 : tmpVal);
 362                                 ss++;
 363                         }
 364                 }
 365         }
 366
 367         while (i < AR5416_PD_GAINS_IN_MASK) {
 368                 pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
 369                 i++;
 370         }
 371
 372         while (k < AR5416_NUM_PDADC_VALUES) {
 373                 pPDADCValues[k] = pPDADCValues[k-1];
 374                 k++;
 375         }
 376
 377 #undef TMP_VAL_VPD_TABLE
 378 }
 379
 380 static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
 381                             struct ath9k_channel *chan,
 382                             struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
 383                             u8 *pCalChans,  u16 availPiers, int8_t *pPwr)
 384 {
 385         u16 idxL = 0, idxR = 0, numPiers;
 386         bool match;
 387         struct chan_centers centers;
 388
 389         ath9k_hw_get_channel_centers(ah, chan, &centers);
 390
 391         for (numPiers = 0; numPiers < availPiers; numPiers++) {
 392                 if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)
 393                         break;
 394         }
 395
 396         match = ath9k_hw_get_lower_upper_index(
 397                 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
 398                 pCalChans, numPiers, &idxL, &idxR);
 399
 400         if (match) {
 401                 *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0];
 402         } else {
 403                 *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] +
 404                          (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
 405         }
 406
 407 }
 408
 409 static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
 410                                           int32_t txPower, u16 chain)
 411 {
 412         u32 tmpVal;
 413         u32 a;
 414
 415         /* Enable OLPC for chain 0 */
 416
 417         tmpVal = REG_READ(ah, 0xa270);
 418         tmpVal = tmpVal & 0xFCFFFFFF;
 419         tmpVal = tmpVal | (0x3 << 24);
 420         REG_WRITE(ah, 0xa270, tmpVal);
 421
 422         /* Enable OLPC for chain 1 */
 423
 424         tmpVal = REG_READ(ah, 0xb270);
 425         tmpVal = tmpVal & 0xFCFFFFFF;
 426         tmpVal = tmpVal | (0x3 << 24);
 427         REG_WRITE(ah, 0xb270, tmpVal);
 428
 429         /* Write the OLPC ref power for chain 0 */
 430
 431         if (chain == 0) {
 432                 tmpVal = REG_READ(ah, 0xa398);
 433                 tmpVal = tmpVal & 0xff00ffff;
 434                 a = (txPower)&0xff;
 435                 tmpVal = tmpVal | (a << 16);
 436                 REG_WRITE(ah, 0xa398, tmpVal);
 437         }
 438
 439         /* Write the OLPC ref power for chain 1 */
 440
 441         if (chain == 1) {
 442                 tmpVal = REG_READ(ah, 0xb398);
 443                 tmpVal = tmpVal & 0xff00ffff;
 444                 a = (txPower)&0xff;
 445                 tmpVal = tmpVal | (a << 16);
 446                 REG_WRITE(ah, 0xb398, tmpVal);
 447         }
 448 }
 449
 450 static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
 451                                                 struct ath9k_channel *chan,
 452                                                 int16_t *pTxPowerIndexOffset)
 453 {
 454         struct cal_data_per_freq_ar9287 *pRawDataset;
 455         struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
 456         u8 *pCalBChans = NULL;
 457         u16 pdGainOverlap_t2;
 458         u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 459         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
 460         u16 numPiers = 0, i, j;
 461         u16 numXpdGain, xpdMask;
 462         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
 463         u32 reg32, regOffset, regChainOffset, regval;
 464         int16_t modalIdx, diff = 0;
 465         struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
 466
 467         modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
 468         xpdMask = pEepData->modalHeader.xpdGain;
 469
 470         if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
 471             AR9287_EEP_MINOR_VER_2)
 472                 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
 473         else
 474                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 475                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 476
 477         if (IS_CHAN_2GHZ(chan)) {
 478                 pCalBChans = pEepData->calFreqPier2G;
 479                 numPiers = AR9287_NUM_2G_CAL_PIERS;
 480                 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
 481                         pRawDatasetOpenLoop =
 482                         (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[0];
 483                         ah->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
 484                 }
 485         }
 486
 487         numXpdGain = 0;
 488
 489         /* Calculate the value of xpdgains from the xpdGain Mask */
 490         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
 491                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
 492                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
 493                                 break;
 494                         xpdGainValues[numXpdGain] =
 495                                 (u16)(AR5416_PD_GAINS_IN_MASK-i);
 496                         numXpdGain++;
 497                 }
 498         }
 499
 500         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 501                       (numXpdGain - 1) & 0x3);
 502         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 503                       xpdGainValues[0]);
 504         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 505                       xpdGainValues[1]);
 506         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
 507                       xpdGainValues[2]);
 508
 509         for (i = 0; i < AR9287_MAX_CHAINS; i++) {
 510                 regChainOffset = i * 0x1000;
 511
 512                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 513                         pRawDatasetOpenLoop =
 514                         (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[i];
 515
 516                         if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
 517                                 int8_t txPower;
 518                                 ar9287_eeprom_get_tx_gain_index(ah, chan,
 519                                                         pRawDatasetOpenLoop,
 520                                                         pCalBChans, numPiers,
 521                                                         &txPower);
 522                                 ar9287_eeprom_olpc_set_pdadcs(ah, txPower, i);
 523                         } else {
 524                                 pRawDataset =
 525                                         (struct cal_data_per_freq_ar9287 *)
 526                                         pEepData->calPierData2G[i];
 527
 528                                 ath9k_hw_get_ar9287_gain_boundaries_pdadcs(ah, chan,
 529                                                            pRawDataset,
 530                                                            pCalBChans, numPiers,
 531                                                            pdGainOverlap_t2,
 532                                                            gainBoundaries,
 533                                                            pdadcValues,
 534                                                            numXpdGain);
 535                         }
 536
 537                         if (i == 0) {
 538                                 if (!ath9k_hw_ar9287_get_eeprom(ah,
 539                                                         EEP_OL_PWRCTRL)) {
 540
 541                                         regval = SM(pdGainOverlap_t2,
 542                                                     AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
 543                                                 | SM(gainBoundaries[0],
 544                                                      AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
 545                                                 | SM(gainBoundaries[1],
 546                                                      AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
 547                                                 | SM(gainBoundaries[2],
 548                                                      AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
 549                                                 | SM(gainBoundaries[3],
 550                                                      AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4);
 551
 552                                         REG_WRITE(ah,
 553                                                   AR_PHY_TPCRG5 + regChainOffset,
 554                                                   regval);
 555                                 }
 556                         }
 557
 558                         if ((int32_t)AR9287_PWR_TABLE_OFFSET_DB !=
 559                             pEepData->baseEepHeader.pwrTableOffset) {
 560                                 diff = (u16)(pEepData->baseEepHeader.pwrTableOffset -
 561                                              (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
 562                                 diff *= 2;
 563
 564                                 for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++)
 565                                         pdadcValues[j] = pdadcValues[j+diff];
 566
 567                                 for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff);
 568                                      j < AR5416_NUM_PDADC_VALUES; j++)
 569                                         pdadcValues[j] =
 570                                           pdadcValues[AR5416_NUM_PDADC_VALUES-diff];
 571                         }
 572
 573                         if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
 574                                 regOffset = AR_PHY_BASE +
 575                                         (672 << 2) + regChainOffset;
 576
 577                                 for (j = 0; j < 32; j++) {
 578                                         reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0)
 579                                                 | ((pdadcValues[4*j + 1] & 0xFF) << 8)
 580                                                 | ((pdadcValues[4*j + 2] & 0xFF) << 16)
 581                                                 | ((pdadcValues[4*j + 3] & 0xFF) << 24);
 582
 583                                         REG_WRITE(ah, regOffset, reg32);
 584                                         regOffset += 4;
 585                                 }
 586                         }
 587                 }
 588         }
 589
 590         *pTxPowerIndexOffset = 0;
 591 }
 592
 593 static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
 594                                                      struct ath9k_channel *chan,
 595                                                      int16_t *ratesArray,
 596                                                      u16 cfgCtl,
 597                                                      u16 AntennaReduction,
 598                                                      u16 twiceMaxRegulatoryPower,
 599                                                      u16 powerLimit)
 600 {
 601 #define CMP_CTL \
 602         (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
 603          pEepData->ctlIndex[i])
 604
 605 #define CMP_NO_CTL \
 606         (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
 607          ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
 608
 609 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6
 610 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   10
 611
 612         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 613         u16 twiceMaxEdgePower = MAX_RATE_POWER;
 614         static const u16 tpScaleReductionTable[5] =
 615                 { 0, 3, 6, 9, MAX_RATE_POWER };
 616         int i;
 617         int16_t twiceLargestAntenna;
 618         struct cal_ctl_data_ar9287 *rep;
 619         struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
 620                                     targetPowerCck = {0, {0, 0, 0, 0} };
 621         struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} },
 622                                     targetPowerCckExt = {0, {0, 0, 0, 0} };
 623         struct cal_target_power_ht targetPowerHt20,
 624                                     targetPowerHt40 = {0, {0, 0, 0, 0} };
 625         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
 626         static const u16 ctlModesFor11g[] = {
 627                 CTL_11B, CTL_11G, CTL_2GHT20,
 628                 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
 629         };
 630         u16 numCtlModes = 0;
 631         const u16 *pCtlMode = NULL;
 632         u16 ctlMode, freq;
 633         struct chan_centers centers;
 634         int tx_chainmask;
 635         u16 twiceMinEdgePower;
 636         struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
 637         tx_chainmask = ah->txchainmask;
 638
 639         ath9k_hw_get_channel_centers(ah, chan, &centers);
 640
 641         /* Compute TxPower reduction due to Antenna Gain */
 642         twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0],
 643                                   pEepData->modalHeader.antennaGainCh[1]);
 644         twiceLargestAntenna = (int16_t)min((AntennaReduction) -
 645                                            twiceLargestAntenna, 0);
 646
 647         /*
 648          * scaledPower is the minimum of the user input power level
 649          * and the regulatory allowed power level.
 650          */
 651         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
 652
 653         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX)
 654                 maxRegAllowedPower -=
 655                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
 656
 657         scaledPower = min(powerLimit, maxRegAllowedPower);
 658
 659         /*
 660          * Reduce scaled Power by number of chains active
 661          * to get the per chain tx power level.
 662          */
 663         switch (ar5416_get_ntxchains(tx_chainmask)) {
 664         case 1:
 665                 break;
 666         case 2:
 667                 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
 668                 break;
 669         case 3:
 670                 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
 671                 break;
 672         }
 673         scaledPower = max((u16)0, scaledPower);
 674
 675         /*
 676          * Get TX power from EEPROM.
 677          */
 678         if (IS_CHAN_2GHZ(chan)) {
 679                 /* CTL_11B, CTL_11G, CTL_2GHT20 */
 680                 numCtlModes =
 681                         ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
 682
 683                 pCtlMode = ctlModesFor11g;
 684
 685                 ath9k_hw_get_legacy_target_powers(ah, chan,
 686                                                   pEepData->calTargetPowerCck,
 687                                                   AR9287_NUM_2G_CCK_TARGET_POWERS,
 688                                                   &targetPowerCck, 4, false);
 689                 ath9k_hw_get_legacy_target_powers(ah, chan,
 690                                                   pEepData->calTargetPower2G,
 691                                                   AR9287_NUM_2G_20_TARGET_POWERS,
 692                                                   &targetPowerOfdm, 4, false);
 693                 ath9k_hw_get_target_powers(ah, chan,
 694                                            pEepData->calTargetPower2GHT20,
 695                                            AR9287_NUM_2G_20_TARGET_POWERS,
 696                                            &targetPowerHt20, 8, false);
 697
 698                 if (IS_CHAN_HT40(chan)) {
 699                         /* All 2G CTLs */
 700                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
 701                         ath9k_hw_get_target_powers(ah, chan,
 702                                                    pEepData->calTargetPower2GHT40,
 703                                                    AR9287_NUM_2G_40_TARGET_POWERS,
 704                                                    &targetPowerHt40, 8, true);
 705                         ath9k_hw_get_legacy_target_powers(ah, chan,
 706                                                   pEepData->calTargetPowerCck,
 707                                                   AR9287_NUM_2G_CCK_TARGET_POWERS,
 708                                                   &targetPowerCckExt, 4, true);
 709                         ath9k_hw_get_legacy_target_powers(ah, chan,
 710                                                   pEepData->calTargetPower2G,
 711                                                   AR9287_NUM_2G_20_TARGET_POWERS,
 712                                                   &targetPowerOfdmExt, 4, true);
 713                 }
 714         }
 715
 716         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
 717                 bool isHt40CtlMode =
 718                         (pCtlMode[ctlMode] == CTL_2GHT40) ? true : false;
 719
 720                 if (isHt40CtlMode)
 721                         freq = centers.synth_center;
 722                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
 723                         freq = centers.ext_center;
 724                 else
 725                         freq = centers.ctl_center;
 726
 727                 /* Walk through the CTL indices stored in EEPROM */
 728                 for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
 729                         struct cal_ctl_edges *pRdEdgesPower;
 730
 731                         /*
 732                          * Compare test group from regulatory channel list
 733                          * with test mode from pCtlMode list
 734                          */
 735                         if (CMP_CTL || CMP_NO_CTL) {
 736                                 rep = &(pEepData->ctlData[i]);
 737                                 pRdEdgesPower =
 738                                 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1];
 739
 740                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
 741                                                                 pRdEdgesPower,
 742                                                                 IS_CHAN_2GHZ(chan),
 743                                                                 AR5416_NUM_BAND_EDGES);
 744
 745                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
 746                                         twiceMaxEdgePower = min(twiceMaxEdgePower,
 747                                                                 twiceMinEdgePower);
 748                                 } else {
 749                                         twiceMaxEdgePower = twiceMinEdgePower;
 750                                         break;
 751                                 }
 752                         }
 753                 }
 754
 755                 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
 756
 757                 /* Apply ctl mode to correct target power set */
 758                 switch (pCtlMode[ctlMode]) {
 759                 case CTL_11B:
 760                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
 761                                 targetPowerCck.tPow2x[i] =
 762                                         (u8)min((u16)targetPowerCck.tPow2x[i],
 763                                                 minCtlPower);
 764                         }
 765                         break;
 766                 case CTL_11A:
 767                 case CTL_11G:
 768                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
 769                                 targetPowerOfdm.tPow2x[i] =
 770                                         (u8)min((u16)targetPowerOfdm.tPow2x[i],
 771                                                 minCtlPower);
 772                         }
 773                         break;
 774                 case CTL_5GHT20:
 775                 case CTL_2GHT20:
 776                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
 777                                 targetPowerHt20.tPow2x[i] =
 778                                         (u8)min((u16)targetPowerHt20.tPow2x[i],
 779                                                 minCtlPower);
 780                         }
 781                         break;
 782                 case CTL_11B_EXT:
 783                         targetPowerCckExt.tPow2x[0] =
 784                                 (u8)min((u16)targetPowerCckExt.tPow2x[0],
 785                                         minCtlPower);
 786                         break;
 787                 case CTL_11A_EXT:
 788                 case CTL_11G_EXT:
 789                         targetPowerOfdmExt.tPow2x[0] =
 790                                 (u8)min((u16)targetPowerOfdmExt.tPow2x[0],
 791                                         minCtlPower);
 792                         break;
 793                 case CTL_5GHT40:
 794                 case CTL_2GHT40:
 795                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
 796                                 targetPowerHt40.tPow2x[i] =
 797                                         (u8)min((u16)targetPowerHt40.tPow2x[i],
 798                                                 minCtlPower);
 799                         }
 800                         break;
 801                 default:
 802                         break;
 803                 }
 804         }
 805
 806         /* Now set the rates array */
 807
 808         ratesArray[rate6mb] =
 809         ratesArray[rate9mb] =
 810         ratesArray[rate12mb] =
 811         ratesArray[rate18mb] =
 812         ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
 813
 814         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
 815         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
 816         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
 817         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
 818
 819         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
 820                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
 821
 822         if (IS_CHAN_2GHZ(chan)) {
 823                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
 824                 ratesArray[rate2s] =
 825                 ratesArray[rate2l] = targetPowerCck.tPow2x[1];
 826                 ratesArray[rate5_5s] =
 827                 ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
 828                 ratesArray[rate11s] =
 829                 ratesArray[rate11l] = targetPowerCck.tPow2x[3];
 830         }
 831         if (IS_CHAN_HT40(chan)) {
 832                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++)
 833                         ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
 834
 835                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
 836                 ratesArray[rateDupCck]  = targetPowerHt40.tPow2x[0];
 837                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
 838
 839                 if (IS_CHAN_2GHZ(chan))
 840                         ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
 841         }
 842
 843 #undef CMP_CTL
 844 #undef CMP_NO_CTL
 845 #undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
 846 #undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
 847 }
 848
 849 static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
 850                                         struct ath9k_channel *chan, u16 cfgCtl,
 851                                         u8 twiceAntennaReduction,
 852                                         u8 twiceMaxRegulatoryPower,
 853                                         u8 powerLimit, bool test)
 854 {
 855         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 856         struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
 857         struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
 858         int16_t ratesArray[Ar5416RateSize];
 859         int16_t txPowerIndexOffset = 0;
 860         u8 ht40PowerIncForPdadc = 2;
 861         int i;
 862
 863         memset(ratesArray, 0, sizeof(ratesArray));
 864
 865         if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
 866             AR9287_EEP_MINOR_VER_2)
 867                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
 868
 869         ath9k_hw_set_ar9287_power_per_rate_table(ah, chan,
 870                                                  &ratesArray[0], cfgCtl,
 871                                                  twiceAntennaReduction,
 872                                                  twiceMaxRegulatoryPower,
 873                                                  powerLimit);
 874
 875         ath9k_hw_set_ar9287_power_cal_table(ah, chan, &txPowerIndexOffset);
 876
 877         regulatory->max_power_level = 0;
 878         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
 879                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
 880                 if (ratesArray[i] > MAX_RATE_POWER)
 881                         ratesArray[i] = MAX_RATE_POWER;
 882
 883                 if (ratesArray[i] > regulatory->max_power_level)
 884                         regulatory->max_power_level = ratesArray[i];
 885         }
 886
 887         if (test)
 888                 return;
 889
 890         if (IS_CHAN_2GHZ(chan))
 891                 i = rate1l;
 892         else
 893                 i = rate6mb;
 894
 895         regulatory->max_power_level = ratesArray[i];
 896
 897         if (AR_SREV_9280_20_OR_LATER(ah)) {
 898                 for (i = 0; i < Ar5416RateSize; i++)
 899                         ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
 900         }
 901
 902         /* OFDM power per rate */
 903         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
 904                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
 905                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
 906                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
 907                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
 908
 909         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
 910                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
 911                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
 912                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
 913                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
 914
 915         /* CCK power per rate */
 916         if (IS_CHAN_2GHZ(chan)) {
 917                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
 918                           ATH9K_POW_SM(ratesArray[rate2s], 24)
 919                           | ATH9K_POW_SM(ratesArray[rate2l], 16)
 920                           | ATH9K_POW_SM(ratesArray[rateXr], 8)
 921                           | ATH9K_POW_SM(ratesArray[rate1l], 0));
 922                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
 923                           ATH9K_POW_SM(ratesArray[rate11s], 24)
 924                           | ATH9K_POW_SM(ratesArray[rate11l], 16)
 925                           | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
 926                           | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
 927         }
 928
 929         /* HT20 power per rate */
 930         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
 931                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
 932                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
 933                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
 934                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
 935
 936         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
 937                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
 938                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
 939                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
 940                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
 941
 942         /* HT40 power per rate */
 943         if (IS_CHAN_HT40(chan)) {
 944                 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
 945                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
 946                                   ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
 947                                   | ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
 948                                   | ATH9K_POW_SM(ratesArray[rateHt40_1], 8)
 949                                   | ATH9K_POW_SM(ratesArray[rateHt40_0], 0));
 950
 951                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
 952                                   ATH9K_POW_SM(ratesArray[rateHt40_7], 24)
 953                                   | ATH9K_POW_SM(ratesArray[rateHt40_6], 16)
 954                                   | ATH9K_POW_SM(ratesArray[rateHt40_5], 8)
 955                                   | ATH9K_POW_SM(ratesArray[rateHt40_4], 0));
 956                 } else {
 957                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
 958                                   ATH9K_POW_SM(ratesArray[rateHt40_3] +
 959                                                ht40PowerIncForPdadc, 24)
 960                                   | ATH9K_POW_SM(ratesArray[rateHt40_2] +
 961                                                  ht40PowerIncForPdadc, 16)
 962                                   | ATH9K_POW_SM(ratesArray[rateHt40_1] +
 963                                                  ht40PowerIncForPdadc, 8)
 964                                   | ATH9K_POW_SM(ratesArray[rateHt40_0] +
 965                                                  ht40PowerIncForPdadc, 0));
 966
 967                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
 968                                   ATH9K_POW_SM(ratesArray[rateHt40_7] +
 969                                                ht40PowerIncForPdadc, 24)
 970                                   | ATH9K_POW_SM(ratesArray[rateHt40_6] +
 971                                                  ht40PowerIncForPdadc, 16)
 972                                   | ATH9K_POW_SM(ratesArray[rateHt40_5] +
 973                                                  ht40PowerIncForPdadc, 8)
 974                                   | ATH9K_POW_SM(ratesArray[rateHt40_4] +
 975                                                  ht40PowerIncForPdadc, 0));
 976                 }
 977
 978                 /* Dup/Ext power per rate */
 979                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
 980                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
 981                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
 982                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
 983                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
 984         }
 985 }
 986
 987 static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah,
 988                                       struct ath9k_channel *chan)
 989 {
 990 }
 991
 992 static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
 993                                              struct ath9k_channel *chan)
 994 {
 995         struct ar9287_eeprom *eep = &ah->eeprom.map9287;
 996         struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
 997         u16 antWrites[AR9287_ANT_16S];
 998         u32 regChainOffset, regval;
 999         u8 txRxAttenLocal;
1000         int i, j, offset_num;
1001
1002         pModal = &eep->modalHeader;
1003
1004         antWrites[0] = (u16)((pModal->antCtrlCommon >> 28) & 0xF);
1005         antWrites[1] = (u16)((pModal->antCtrlCommon >> 24) & 0xF);
1006         antWrites[2] = (u16)((pModal->antCtrlCommon >> 20) & 0xF);
1007         antWrites[3] = (u16)((pModal->antCtrlCommon >> 16) & 0xF);
1008         antWrites[4] = (u16)((pModal->antCtrlCommon >> 12) & 0xF);
1009         antWrites[5] = (u16)((pModal->antCtrlCommon >> 8) & 0xF);
1010         antWrites[6] = (u16)((pModal->antCtrlCommon >> 4)  & 0xF);
1011         antWrites[7] = (u16)(pModal->antCtrlCommon & 0xF);
1012
1013         offset_num = 8;
1014
1015         for (i = 0, j = offset_num; i < AR9287_MAX_CHAINS; i++) {
1016                 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 28) & 0xf);
1017                 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 10) & 0x3);
1018                 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 8) & 0x3);
1019                 antWrites[j++] = 0;
1020                 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 6) & 0x3);
1021                 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 4) & 0x3);
1022                 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 2) & 0x3);
1023                 antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3);
1024         }
1025
1026         REG_WRITE(ah, AR_PHY_SWITCH_COM,
1027                   ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1028
1029         for (i = 0; i < AR9287_MAX_CHAINS; i++) {
1030                 regChainOffset = i * 0x1000;
1031
1032                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1033                           pModal->antCtrlChain[i]);
1034
1035                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1036                           (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)
1037                            & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1038                                AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1039                           SM(pModal->iqCalICh[i],
1040                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1041                           SM(pModal->iqCalQCh[i],
1042                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1043
1044                 txRxAttenLocal = pModal->txRxAttenCh[i];
1045
1046                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1047                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1048                               pModal->bswMargin[i]);
1049                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1050                               AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1051                               pModal->bswAtten[i]);
1052                 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1053                               AR9280_PHY_RXGAIN_TXRX_ATTEN,
1054                               txRxAttenLocal);
1055                 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1056                               AR9280_PHY_RXGAIN_TXRX_MARGIN,
1057                               pModal->rxTxMarginCh[i]);
1058         }
1059
1060
1061         if (IS_CHAN_HT40(chan))
1062                 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1063                               AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
1064         else
1065                 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1066                               AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
1067
1068         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1069                       AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
1070
1071         REG_WRITE(ah, AR_PHY_RF_CTL4,
1072                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1073                   | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1074                   | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1075                   | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1076
1077         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3,
1078                       AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
1079
1080         REG_RMW_FIELD(ah, AR_PHY_CCA,
1081                       AR9280_PHY_CCA_THRESH62, pModal->thresh62);
1082         REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
1083                       AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62);
1084
1085         regval = REG_READ(ah, AR9287_AN_RF2G3_CH0);
1086         regval &= ~(AR9287_AN_RF2G3_DB1 |
1087                     AR9287_AN_RF2G3_DB2 |
1088                     AR9287_AN_RF2G3_OB_CCK |
1089                     AR9287_AN_RF2G3_OB_PSK |
1090                     AR9287_AN_RF2G3_OB_QAM |
1091                     AR9287_AN_RF2G3_OB_PAL_OFF);
1092         regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
1093                    SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
1094                    SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
1095                    SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
1096                    SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
1097                    SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
1098
1099         ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH0, regval);
1100
1101         regval = REG_READ(ah, AR9287_AN_RF2G3_CH1);
1102         regval &= ~(AR9287_AN_RF2G3_DB1 |
1103                     AR9287_AN_RF2G3_DB2 |
1104                     AR9287_AN_RF2G3_OB_CCK |
1105                     AR9287_AN_RF2G3_OB_PSK |
1106                     AR9287_AN_RF2G3_OB_QAM |
1107                     AR9287_AN_RF2G3_OB_PAL_OFF);
1108         regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
1109                    SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
1110                    SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
1111                    SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
1112                    SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
1113                    SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
1114
1115         ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH1, regval);
1116
1117         REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1118                       AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart);
1119         REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1120                       AR_PHY_TX_END_PA_ON, pModal->txFrameToPaOn);
1121
1122         ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TOP2,
1123                                   AR9287_AN_TOP2_XPABIAS_LVL,
1124                                   AR9287_AN_TOP2_XPABIAS_LVL_S,
1125                                   pModal->xpaBiasLvl);
1126 }
1127
1128 static u8 ath9k_hw_ar9287_get_num_ant_config(struct ath_hw *ah,
1129                                              enum ath9k_hal_freq_band freq_band)
1130 {
1131         return 1;
1132 }
1133
1134 static u32 ath9k_hw_ar9287_get_eeprom_antenna_cfg(struct ath_hw *ah,
1135                                                   struct ath9k_channel *chan)
1136 {
1137         struct ar9287_eeprom *eep = &ah->eeprom.map9287;
1138         struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
1139
1140         return pModal->antCtrlCommon;
1141 }
1142
1143 static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
1144                                             u16 i, bool is2GHz)
1145 {
1146 #define EEP_MAP9287_SPURCHAN \
1147         (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
1148
1149         struct ath_common *common = ath9k_hw_common(ah);
1150         u16 spur_val = AR_NO_SPUR;
1151
1152         ath_dbg(common, ATH_DBG_ANI,
1153                 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1154                 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1155
1156         switch (ah->config.spurmode) {
1157         case SPUR_DISABLE:
1158                 break;
1159         case SPUR_ENABLE_IOCTL:
1160                 spur_val = ah->config.spurchans[i][is2GHz];
1161                 ath_dbg(common, ATH_DBG_ANI,
1162                         "Getting spur val from new loc. %d\n", spur_val);
1163                 break;
1164         case SPUR_ENABLE_EEPROM:
1165                 spur_val = EEP_MAP9287_SPURCHAN;
1166                 break;
1167         }
1168
1169         return spur_val;
1170
1171 #undef EEP_MAP9287_SPURCHAN
1172 }
1173
1174 const struct eeprom_ops eep_ar9287_ops = {
1175         .check_eeprom           = ath9k_hw_ar9287_check_eeprom,
1176         .get_eeprom             = ath9k_hw_ar9287_get_eeprom,
1177         .fill_eeprom            = ath9k_hw_ar9287_fill_eeprom,
1178         .get_eeprom_ver         = ath9k_hw_ar9287_get_eeprom_ver,
1179         .get_eeprom_rev         = ath9k_hw_ar9287_get_eeprom_rev,
1180         .get_num_ant_config     = ath9k_hw_ar9287_get_num_ant_config,
1181         .get_eeprom_antenna_cfg = ath9k_hw_ar9287_get_eeprom_antenna_cfg,
1182         .set_board_values       = ath9k_hw_ar9287_set_board_values,
1183         .set_addac              = ath9k_hw_ar9287_set_addac,
1184         .set_txpower            = ath9k_hw_ar9287_set_txpower,
1185         .get_spur_channel       = ath9k_hw_ar9287_get_spur_channel
1186 };