2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9002_phy.h"
20 #define NUM_EEP_WORDS (sizeof(struct ar9287_eeprom) / sizeof(u16))
22 static int ath9k_hw_ar9287_get_eeprom_ver(struct ath_hw *ah)
24 return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
27 static int ath9k_hw_ar9287_get_eeprom_rev(struct ath_hw *ah)
29 return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF;
32 static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
34 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
35 struct ath_common *common = ath9k_hw_common(ah);
37 int addr, eep_start_loc = AR9287_EEP_START_LOC;
38 eep_data = (u16 *)eep;
40 if (!ath9k_hw_use_flash(ah)) {
41 ath_print(common, ATH_DBG_EEPROM,
42 "Reading from EEPROM, not flash\n");
45 for (addr = 0; addr < NUM_EEP_WORDS; addr++) {
46 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc,
48 ath_print(common, ATH_DBG_EEPROM,
49 "Unable to read eeprom region\n");
58 static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
60 u32 sum = 0, el, integer;
61 u16 temp, word, magic, magic2, *eepdata;
63 bool need_swap = false;
64 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
65 struct ath_common *common = ath9k_hw_common(ah);
67 if (!ath9k_hw_use_flash(ah)) {
68 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
70 ath_print(common, ATH_DBG_FATAL,
71 "Reading Magic # failed\n");
75 ath_print(common, ATH_DBG_EEPROM,
76 "Read Magic = 0x%04X\n", magic);
78 if (magic != AR5416_EEPROM_MAGIC) {
79 magic2 = swab16(magic);
81 if (magic2 == AR5416_EEPROM_MAGIC) {
83 eepdata = (u16 *)(&ah->eeprom);
85 for (addr = 0; addr < NUM_EEP_WORDS; addr++) {
86 temp = swab16(*eepdata);
91 ath_print(common, ATH_DBG_FATAL,
92 "Invalid EEPROM Magic. "
93 "Endianness mismatch.\n");
99 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
100 need_swap ? "True" : "False");
103 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
105 el = ah->eeprom.map9287.baseEepHeader.length;
107 if (el > sizeof(struct ar9287_eeprom))
108 el = sizeof(struct ar9287_eeprom) / sizeof(u16);
110 el = el / sizeof(u16);
112 eepdata = (u16 *)(&ah->eeprom);
114 for (i = 0; i < el; i++)
118 word = swab16(eep->baseEepHeader.length);
119 eep->baseEepHeader.length = word;
121 word = swab16(eep->baseEepHeader.checksum);
122 eep->baseEepHeader.checksum = word;
124 word = swab16(eep->baseEepHeader.version);
125 eep->baseEepHeader.version = word;
127 word = swab16(eep->baseEepHeader.regDmn[0]);
128 eep->baseEepHeader.regDmn[0] = word;
130 word = swab16(eep->baseEepHeader.regDmn[1]);
131 eep->baseEepHeader.regDmn[1] = word;
133 word = swab16(eep->baseEepHeader.rfSilent);
134 eep->baseEepHeader.rfSilent = word;
136 word = swab16(eep->baseEepHeader.blueToothOptions);
137 eep->baseEepHeader.blueToothOptions = word;
139 word = swab16(eep->baseEepHeader.deviceCap);
140 eep->baseEepHeader.deviceCap = word;
142 integer = swab32(eep->modalHeader.antCtrlCommon);
143 eep->modalHeader.antCtrlCommon = integer;
145 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
146 integer = swab32(eep->modalHeader.antCtrlChain[i]);
147 eep->modalHeader.antCtrlChain[i] = integer;
150 for (i = 0; i < AR9287_EEPROM_MODAL_SPURS; i++) {
151 word = swab16(eep->modalHeader.spurChans[i].spurChan);
152 eep->modalHeader.spurChans[i].spurChan = word;
156 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
157 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
158 ath_print(common, ATH_DBG_FATAL,
159 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
160 sum, ah->eep_ops->get_eeprom_ver(ah));
167 static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
168 enum eeprom_param param)
170 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
171 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
172 struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
175 ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK;
179 return pModal->noiseFloorThreshCh[0];
181 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
183 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
185 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
187 return pBase->regDmn[0];
189 return pBase->regDmn[1];
191 return pBase->deviceCap;
193 return pBase->opCapFlags;
195 return pBase->rfSilent;
199 return pBase->txMask;
201 return pBase->rxMask;
203 return pBase->deviceType;
205 return pBase->openLoopPwrCntl;
206 case EEP_TEMPSENSE_SLOPE:
207 if (ver_minor >= AR9287_EEP_MINOR_VER_2)
208 return pBase->tempSensSlope;
211 case EEP_TEMPSENSE_SLOPE_PAL_ON:
212 if (ver_minor >= AR9287_EEP_MINOR_VER_3)
213 return pBase->tempSensSlopePalOn;
221 static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah,
222 struct ath9k_channel *chan,
223 struct cal_data_per_freq_ar9287 *pRawDataSet,
224 u8 *bChans, u16 availPiers,
226 u16 *pPdGainBoundaries,
230 #define TMP_VAL_VPD_TABLE \
231 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
235 u16 idxL = 0, idxR = 0, numPiers;
236 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
237 u8 minPwrT4[AR9287_NUM_PD_GAINS];
238 u8 maxPwrT4[AR9287_NUM_PD_GAINS];
241 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
243 int16_t minDelta = 0;
244 struct chan_centers centers;
245 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
246 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
247 static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
248 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
249 static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
250 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
252 memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
253 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
255 for (numPiers = 0; numPiers < availPiers; numPiers++) {
256 if (bChans[numPiers] == AR9287_BCHAN_UNUSED)
260 match = ath9k_hw_get_lower_upper_index(
261 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
262 bChans, numPiers, &idxL, &idxR);
265 for (i = 0; i < numXpdGains; i++) {
266 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
267 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
268 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
269 pRawDataSet[idxL].pwrPdg[i],
270 pRawDataSet[idxL].vpdPdg[i],
271 AR9287_PD_GAIN_ICEPTS,
275 for (i = 0; i < numXpdGains; i++) {
276 pVpdL = pRawDataSet[idxL].vpdPdg[i];
277 pPwrL = pRawDataSet[idxL].pwrPdg[i];
278 pVpdR = pRawDataSet[idxR].vpdPdg[i];
279 pPwrR = pRawDataSet[idxR].pwrPdg[i];
281 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
283 maxPwrT4[i] = min(pPwrL[AR9287_PD_GAIN_ICEPTS - 1],
284 pPwrR[AR9287_PD_GAIN_ICEPTS - 1]);
286 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
288 AR9287_PD_GAIN_ICEPTS,
290 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
292 AR9287_PD_GAIN_ICEPTS,
295 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
296 vpdTableI[i][j] = (u8)(ath9k_hw_interpolate(
297 (u16)FREQ2FBIN(centers. synth_center,
299 bChans[idxL], bChans[idxR],
300 vpdTableL[i][j], vpdTableR[i][j]));
307 for (i = 0; i < numXpdGains; i++) {
308 if (i == (numXpdGains - 1))
309 pPdGainBoundaries[i] =
310 (u16)(maxPwrT4[i] / 2);
312 pPdGainBoundaries[i] =
313 (u16)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
315 pPdGainBoundaries[i] = min((u16)AR5416_MAX_RATE_POWER,
316 pPdGainBoundaries[i]);
322 if (AR_SREV_9280_10_OR_LATER(ah))
323 ss = (int16_t)(0 - (minPwrT4[i] / 2));
327 ss = (int16_t)((pPdGainBoundaries[i-1] -
329 tPdGainOverlap + 1 + minDelta);
332 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
333 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
335 while ((ss < 0) && (k < (AR9287_NUM_PDADC_VALUES - 1))) {
336 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
337 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
341 sizeCurrVpdTable = (u8)((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
342 tgtIndex = (u8)(pPdGainBoundaries[i] +
343 tPdGainOverlap - (minPwrT4[i] / 2));
344 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
345 tgtIndex : sizeCurrVpdTable;
347 while ((ss < maxIndex) && (k < (AR9287_NUM_PDADC_VALUES - 1)))
348 pPDADCValues[k++] = vpdTableI[i][ss++];
350 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
351 vpdTableI[i][sizeCurrVpdTable - 2]);
352 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
354 if (tgtIndex > maxIndex) {
355 while ((ss <= tgtIndex) &&
356 (k < (AR9287_NUM_PDADC_VALUES - 1))) {
357 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
359 (u8)((tmpVal > 255) ? 255 : tmpVal);
365 while (i < AR9287_PD_GAINS_IN_MASK) {
366 pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
370 while (k < AR9287_NUM_PDADC_VALUES) {
371 pPDADCValues[k] = pPDADCValues[k-1];
375 #undef TMP_VAL_VPD_TABLE
378 static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
379 struct ath9k_channel *chan,
380 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
381 u8 *pCalChans, u16 availPiers, int8_t *pPwr)
383 u16 idxL = 0, idxR = 0, numPiers;
385 struct chan_centers centers;
387 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
389 for (numPiers = 0; numPiers < availPiers; numPiers++) {
390 if (pCalChans[numPiers] == AR9287_BCHAN_UNUSED)
394 match = ath9k_hw_get_lower_upper_index(
395 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
396 pCalChans, numPiers, &idxL, &idxR);
399 *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0];
401 *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] +
402 (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
407 static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
408 int32_t txPower, u16 chain)
413 /* Enable OLPC for chain 0 */
415 tmpVal = REG_READ(ah, 0xa270);
416 tmpVal = tmpVal & 0xFCFFFFFF;
417 tmpVal = tmpVal | (0x3 << 24);
418 REG_WRITE(ah, 0xa270, tmpVal);
420 /* Enable OLPC for chain 1 */
422 tmpVal = REG_READ(ah, 0xb270);
423 tmpVal = tmpVal & 0xFCFFFFFF;
424 tmpVal = tmpVal | (0x3 << 24);
425 REG_WRITE(ah, 0xb270, tmpVal);
427 /* Write the OLPC ref power for chain 0 */
430 tmpVal = REG_READ(ah, 0xa398);
431 tmpVal = tmpVal & 0xff00ffff;
433 tmpVal = tmpVal | (a << 16);
434 REG_WRITE(ah, 0xa398, tmpVal);
437 /* Write the OLPC ref power for chain 1 */
440 tmpVal = REG_READ(ah, 0xb398);
441 tmpVal = tmpVal & 0xff00ffff;
443 tmpVal = tmpVal | (a << 16);
444 REG_WRITE(ah, 0xb398, tmpVal);
448 static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
449 struct ath9k_channel *chan,
450 int16_t *pTxPowerIndexOffset)
452 struct cal_data_per_freq_ar9287 *pRawDataset;
453 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
454 u8 *pCalBChans = NULL;
455 u16 pdGainOverlap_t2;
456 u8 pdadcValues[AR9287_NUM_PDADC_VALUES];
457 u16 gainBoundaries[AR9287_PD_GAINS_IN_MASK];
458 u16 numPiers = 0, i, j;
459 u16 numXpdGain, xpdMask;
460 u16 xpdGainValues[AR9287_NUM_PD_GAINS] = {0, 0, 0, 0};
461 u32 reg32, regOffset, regChainOffset, regval;
462 int16_t modalIdx, diff = 0;
463 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
465 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
466 xpdMask = pEepData->modalHeader.xpdGain;
468 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
469 AR9287_EEP_MINOR_VER_2)
470 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
472 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
473 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
475 if (IS_CHAN_2GHZ(chan)) {
476 pCalBChans = pEepData->calFreqPier2G;
477 numPiers = AR9287_NUM_2G_CAL_PIERS;
478 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
479 pRawDatasetOpenLoop =
480 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[0];
481 ah->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
487 /* Calculate the value of xpdgains from the xpdGain Mask */
488 for (i = 1; i <= AR9287_PD_GAINS_IN_MASK; i++) {
489 if ((xpdMask >> (AR9287_PD_GAINS_IN_MASK - i)) & 1) {
490 if (numXpdGain >= AR9287_NUM_PD_GAINS)
492 xpdGainValues[numXpdGain] =
493 (u16)(AR9287_PD_GAINS_IN_MASK-i);
498 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
499 (numXpdGain - 1) & 0x3);
500 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
502 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
504 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
507 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
508 regChainOffset = i * 0x1000;
510 if (pEepData->baseEepHeader.txMask & (1 << i)) {
511 pRawDatasetOpenLoop =
512 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[i];
514 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
516 ar9287_eeprom_get_tx_gain_index(ah, chan,
518 pCalBChans, numPiers,
520 ar9287_eeprom_olpc_set_pdadcs(ah, txPower, i);
523 (struct cal_data_per_freq_ar9287 *)
524 pEepData->calPierData2G[i];
526 ath9k_hw_get_ar9287_gain_boundaries_pdadcs(ah, chan,
528 pCalBChans, numPiers,
536 if (!ath9k_hw_ar9287_get_eeprom(ah,
539 regval = SM(pdGainOverlap_t2,
540 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
541 | SM(gainBoundaries[0],
542 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
543 | SM(gainBoundaries[1],
544 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
545 | SM(gainBoundaries[2],
546 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
547 | SM(gainBoundaries[3],
548 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4);
551 AR_PHY_TPCRG5 + regChainOffset,
556 if ((int32_t)AR9287_PWR_TABLE_OFFSET_DB !=
557 pEepData->baseEepHeader.pwrTableOffset) {
558 diff = (u16)(pEepData->baseEepHeader.pwrTableOffset -
559 (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
562 for (j = 0; j < ((u16)AR9287_NUM_PDADC_VALUES-diff); j++)
563 pdadcValues[j] = pdadcValues[j+diff];
565 for (j = (u16)(AR9287_NUM_PDADC_VALUES-diff);
566 j < AR9287_NUM_PDADC_VALUES; j++)
568 pdadcValues[AR9287_NUM_PDADC_VALUES-diff];
571 if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
572 regOffset = AR_PHY_BASE +
573 (672 << 2) + regChainOffset;
575 for (j = 0; j < 32; j++) {
576 reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0)
577 | ((pdadcValues[4*j + 1] & 0xFF) << 8)
578 | ((pdadcValues[4*j + 2] & 0xFF) << 16)
579 | ((pdadcValues[4*j + 3] & 0xFF) << 24);
581 REG_WRITE(ah, regOffset, reg32);
588 *pTxPowerIndexOffset = 0;
591 static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
592 struct ath9k_channel *chan,
595 u16 AntennaReduction,
596 u16 twiceMaxRegulatoryPower,
600 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
601 pEepData->ctlIndex[i])
604 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
605 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
607 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6
608 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
610 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
611 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
612 static const u16 tpScaleReductionTable[5] =
613 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
615 int16_t twiceLargestAntenna;
616 struct cal_ctl_data_ar9287 *rep;
617 struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
618 targetPowerCck = {0, {0, 0, 0, 0} };
619 struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} },
620 targetPowerCckExt = {0, {0, 0, 0, 0} };
621 struct cal_target_power_ht targetPowerHt20,
622 targetPowerHt40 = {0, {0, 0, 0, 0} };
623 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
624 u16 ctlModesFor11g[] = {CTL_11B,
630 u16 numCtlModes = 0, *pCtlMode = NULL, ctlMode, freq;
631 struct chan_centers centers;
633 u16 twiceMinEdgePower;
634 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
635 tx_chainmask = ah->txchainmask;
637 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
639 /* Compute TxPower reduction due to Antenna Gain */
640 twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0],
641 pEepData->modalHeader.antennaGainCh[1]);
642 twiceLargestAntenna = (int16_t)min((AntennaReduction) -
643 twiceLargestAntenna, 0);
646 * scaledPower is the minimum of the user input power level
647 * and the regulatory allowed power level.
649 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
651 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX)
652 maxRegAllowedPower -=
653 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
655 scaledPower = min(powerLimit, maxRegAllowedPower);
658 * Reduce scaled Power by number of chains active
659 * to get the per chain tx power level.
661 switch (ar5416_get_ntxchains(tx_chainmask)) {
665 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
668 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
671 scaledPower = max((u16)0, scaledPower);
674 * Get TX power from EEPROM.
676 if (IS_CHAN_2GHZ(chan)) {
677 /* CTL_11B, CTL_11G, CTL_2GHT20 */
679 ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
681 pCtlMode = ctlModesFor11g;
683 ath9k_hw_get_legacy_target_powers(ah, chan,
684 pEepData->calTargetPowerCck,
685 AR9287_NUM_2G_CCK_TARGET_POWERS,
686 &targetPowerCck, 4, false);
687 ath9k_hw_get_legacy_target_powers(ah, chan,
688 pEepData->calTargetPower2G,
689 AR9287_NUM_2G_20_TARGET_POWERS,
690 &targetPowerOfdm, 4, false);
691 ath9k_hw_get_target_powers(ah, chan,
692 pEepData->calTargetPower2GHT20,
693 AR9287_NUM_2G_20_TARGET_POWERS,
694 &targetPowerHt20, 8, false);
696 if (IS_CHAN_HT40(chan)) {
698 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
699 ath9k_hw_get_target_powers(ah, chan,
700 pEepData->calTargetPower2GHT40,
701 AR9287_NUM_2G_40_TARGET_POWERS,
702 &targetPowerHt40, 8, true);
703 ath9k_hw_get_legacy_target_powers(ah, chan,
704 pEepData->calTargetPowerCck,
705 AR9287_NUM_2G_CCK_TARGET_POWERS,
706 &targetPowerCckExt, 4, true);
707 ath9k_hw_get_legacy_target_powers(ah, chan,
708 pEepData->calTargetPower2G,
709 AR9287_NUM_2G_20_TARGET_POWERS,
710 &targetPowerOfdmExt, 4, true);
714 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
716 (pCtlMode[ctlMode] == CTL_2GHT40) ? true : false;
719 freq = centers.synth_center;
720 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
721 freq = centers.ext_center;
723 freq = centers.ctl_center;
725 /* Walk through the CTL indices stored in EEPROM */
726 for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
727 struct cal_ctl_edges *pRdEdgesPower;
730 * Compare test group from regulatory channel list
731 * with test mode from pCtlMode list
733 if (CMP_CTL || CMP_NO_CTL) {
734 rep = &(pEepData->ctlData[i]);
736 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1];
738 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
741 AR5416_NUM_BAND_EDGES);
743 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
744 twiceMaxEdgePower = min(twiceMaxEdgePower,
747 twiceMaxEdgePower = twiceMinEdgePower;
753 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
755 /* Apply ctl mode to correct target power set */
756 switch (pCtlMode[ctlMode]) {
758 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
759 targetPowerCck.tPow2x[i] =
760 (u8)min((u16)targetPowerCck.tPow2x[i],
766 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
767 targetPowerOfdm.tPow2x[i] =
768 (u8)min((u16)targetPowerOfdm.tPow2x[i],
774 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
775 targetPowerHt20.tPow2x[i] =
776 (u8)min((u16)targetPowerHt20.tPow2x[i],
781 targetPowerCckExt.tPow2x[0] =
782 (u8)min((u16)targetPowerCckExt.tPow2x[0],
787 targetPowerOfdmExt.tPow2x[0] =
788 (u8)min((u16)targetPowerOfdmExt.tPow2x[0],
793 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
794 targetPowerHt40.tPow2x[i] =
795 (u8)min((u16)targetPowerHt40.tPow2x[i],
804 /* Now set the rates array */
806 ratesArray[rate6mb] =
807 ratesArray[rate9mb] =
808 ratesArray[rate12mb] =
809 ratesArray[rate18mb] =
810 ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
812 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
813 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
814 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
815 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
817 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
818 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
820 if (IS_CHAN_2GHZ(chan)) {
821 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
823 ratesArray[rate2l] = targetPowerCck.tPow2x[1];
824 ratesArray[rate5_5s] =
825 ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
826 ratesArray[rate11s] =
827 ratesArray[rate11l] = targetPowerCck.tPow2x[3];
829 if (IS_CHAN_HT40(chan)) {
830 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++)
831 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
833 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
834 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
835 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
837 if (IS_CHAN_2GHZ(chan))
838 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
843 #undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
844 #undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
847 static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
848 struct ath9k_channel *chan, u16 cfgCtl,
849 u8 twiceAntennaReduction,
850 u8 twiceMaxRegulatoryPower,
853 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
854 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
855 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
856 int16_t ratesArray[Ar5416RateSize];
857 int16_t txPowerIndexOffset = 0;
858 u8 ht40PowerIncForPdadc = 2;
861 memset(ratesArray, 0, sizeof(ratesArray));
863 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
864 AR9287_EEP_MINOR_VER_2)
865 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
867 ath9k_hw_set_ar9287_power_per_rate_table(ah, chan,
868 &ratesArray[0], cfgCtl,
869 twiceAntennaReduction,
870 twiceMaxRegulatoryPower,
873 ath9k_hw_set_ar9287_power_cal_table(ah, chan, &txPowerIndexOffset);
875 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
876 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
877 if (ratesArray[i] > AR9287_MAX_RATE_POWER)
878 ratesArray[i] = AR9287_MAX_RATE_POWER;
881 if (AR_SREV_9280_10_OR_LATER(ah)) {
882 for (i = 0; i < Ar5416RateSize; i++)
883 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
886 /* OFDM power per rate */
887 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
888 ATH9K_POW_SM(ratesArray[rate18mb], 24)
889 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
890 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
891 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
893 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
894 ATH9K_POW_SM(ratesArray[rate54mb], 24)
895 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
896 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
897 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
899 /* CCK power per rate */
900 if (IS_CHAN_2GHZ(chan)) {
901 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
902 ATH9K_POW_SM(ratesArray[rate2s], 24)
903 | ATH9K_POW_SM(ratesArray[rate2l], 16)
904 | ATH9K_POW_SM(ratesArray[rateXr], 8)
905 | ATH9K_POW_SM(ratesArray[rate1l], 0));
906 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
907 ATH9K_POW_SM(ratesArray[rate11s], 24)
908 | ATH9K_POW_SM(ratesArray[rate11l], 16)
909 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
910 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
913 /* HT20 power per rate */
914 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
915 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
916 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
917 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
918 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
920 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
921 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
922 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
923 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
924 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
926 /* HT40 power per rate */
927 if (IS_CHAN_HT40(chan)) {
928 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
929 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
930 ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
931 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
932 | ATH9K_POW_SM(ratesArray[rateHt40_1], 8)
933 | ATH9K_POW_SM(ratesArray[rateHt40_0], 0));
935 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
936 ATH9K_POW_SM(ratesArray[rateHt40_7], 24)
937 | ATH9K_POW_SM(ratesArray[rateHt40_6], 16)
938 | ATH9K_POW_SM(ratesArray[rateHt40_5], 8)
939 | ATH9K_POW_SM(ratesArray[rateHt40_4], 0));
941 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
942 ATH9K_POW_SM(ratesArray[rateHt40_3] +
943 ht40PowerIncForPdadc, 24)
944 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
945 ht40PowerIncForPdadc, 16)
946 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
947 ht40PowerIncForPdadc, 8)
948 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
949 ht40PowerIncForPdadc, 0));
951 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
952 ATH9K_POW_SM(ratesArray[rateHt40_7] +
953 ht40PowerIncForPdadc, 24)
954 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
955 ht40PowerIncForPdadc, 16)
956 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
957 ht40PowerIncForPdadc, 8)
958 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
959 ht40PowerIncForPdadc, 0));
962 /* Dup/Ext power per rate */
963 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
964 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
965 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
966 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
967 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
970 if (IS_CHAN_2GHZ(chan))
975 if (AR_SREV_9280_10_OR_LATER(ah))
976 regulatory->max_power_level =
977 ratesArray[i] + AR9287_PWR_TABLE_OFFSET_DB * 2;
979 regulatory->max_power_level = ratesArray[i];
982 static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah,
983 struct ath9k_channel *chan)
987 static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
988 struct ath9k_channel *chan)
990 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
991 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
992 u16 antWrites[AR9287_ANT_16S];
993 u32 regChainOffset, regval;
995 int i, j, offset_num;
997 pModal = &eep->modalHeader;
999 antWrites[0] = (u16)((pModal->antCtrlCommon >> 28) & 0xF);
1000 antWrites[1] = (u16)((pModal->antCtrlCommon >> 24) & 0xF);
1001 antWrites[2] = (u16)((pModal->antCtrlCommon >> 20) & 0xF);
1002 antWrites[3] = (u16)((pModal->antCtrlCommon >> 16) & 0xF);
1003 antWrites[4] = (u16)((pModal->antCtrlCommon >> 12) & 0xF);
1004 antWrites[5] = (u16)((pModal->antCtrlCommon >> 8) & 0xF);
1005 antWrites[6] = (u16)((pModal->antCtrlCommon >> 4) & 0xF);
1006 antWrites[7] = (u16)(pModal->antCtrlCommon & 0xF);
1010 for (i = 0, j = offset_num; i < AR9287_MAX_CHAINS; i++) {
1011 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 28) & 0xf);
1012 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 10) & 0x3);
1013 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 8) & 0x3);
1015 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 6) & 0x3);
1016 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 4) & 0x3);
1017 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 2) & 0x3);
1018 antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3);
1021 REG_WRITE(ah, AR_PHY_SWITCH_COM,
1022 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1024 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
1025 regChainOffset = i * 0x1000;
1027 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1028 pModal->antCtrlChain[i]);
1030 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1031 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)
1032 & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1033 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1034 SM(pModal->iqCalICh[i],
1035 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1036 SM(pModal->iqCalQCh[i],
1037 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1039 txRxAttenLocal = pModal->txRxAttenCh[i];
1041 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1042 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1043 pModal->bswMargin[i]);
1044 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1045 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1046 pModal->bswAtten[i]);
1047 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1048 AR9280_PHY_RXGAIN_TXRX_ATTEN,
1050 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1051 AR9280_PHY_RXGAIN_TXRX_MARGIN,
1052 pModal->rxTxMarginCh[i]);
1056 if (IS_CHAN_HT40(chan))
1057 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1058 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
1060 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1061 AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
1063 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1064 AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
1066 REG_WRITE(ah, AR_PHY_RF_CTL4,
1067 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1068 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1069 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1070 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1072 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3,
1073 AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
1075 REG_RMW_FIELD(ah, AR_PHY_CCA,
1076 AR9280_PHY_CCA_THRESH62, pModal->thresh62);
1077 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
1078 AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62);
1080 regval = REG_READ(ah, AR9287_AN_RF2G3_CH0);
1081 regval &= ~(AR9287_AN_RF2G3_DB1 |
1082 AR9287_AN_RF2G3_DB2 |
1083 AR9287_AN_RF2G3_OB_CCK |
1084 AR9287_AN_RF2G3_OB_PSK |
1085 AR9287_AN_RF2G3_OB_QAM |
1086 AR9287_AN_RF2G3_OB_PAL_OFF);
1087 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
1088 SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
1089 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
1090 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
1091 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
1092 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
1094 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH0, regval);
1096 regval = REG_READ(ah, AR9287_AN_RF2G3_CH1);
1097 regval &= ~(AR9287_AN_RF2G3_DB1 |
1098 AR9287_AN_RF2G3_DB2 |
1099 AR9287_AN_RF2G3_OB_CCK |
1100 AR9287_AN_RF2G3_OB_PSK |
1101 AR9287_AN_RF2G3_OB_QAM |
1102 AR9287_AN_RF2G3_OB_PAL_OFF);
1103 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
1104 SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
1105 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
1106 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
1107 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
1108 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
1110 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH1, regval);
1112 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1113 AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart);
1114 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1115 AR_PHY_TX_END_PA_ON, pModal->txFrameToPaOn);
1117 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TOP2,
1118 AR9287_AN_TOP2_XPABIAS_LVL,
1119 AR9287_AN_TOP2_XPABIAS_LVL_S,
1120 pModal->xpaBiasLvl);
1123 static u8 ath9k_hw_ar9287_get_num_ant_config(struct ath_hw *ah,
1124 enum ieee80211_band freq_band)
1129 static u32 ath9k_hw_ar9287_get_eeprom_antenna_cfg(struct ath_hw *ah,
1130 struct ath9k_channel *chan)
1132 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
1133 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
1135 return pModal->antCtrlCommon;
1138 static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
1141 #define EEP_MAP9287_SPURCHAN \
1142 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
1144 struct ath_common *common = ath9k_hw_common(ah);
1145 u16 spur_val = AR_NO_SPUR;
1147 ath_print(common, ATH_DBG_ANI,
1148 "Getting spur idx %d is2Ghz. %d val %x\n",
1149 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1151 switch (ah->config.spurmode) {
1154 case SPUR_ENABLE_IOCTL:
1155 spur_val = ah->config.spurchans[i][is2GHz];
1156 ath_print(common, ATH_DBG_ANI,
1157 "Getting spur val from new loc. %d\n", spur_val);
1159 case SPUR_ENABLE_EEPROM:
1160 spur_val = EEP_MAP9287_SPURCHAN;
1166 #undef EEP_MAP9287_SPURCHAN
1169 const struct eeprom_ops eep_ar9287_ops = {
1170 .check_eeprom = ath9k_hw_ar9287_check_eeprom,
1171 .get_eeprom = ath9k_hw_ar9287_get_eeprom,
1172 .fill_eeprom = ath9k_hw_ar9287_fill_eeprom,
1173 .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver,
1174 .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev,
1175 .get_num_ant_config = ath9k_hw_ar9287_get_num_ant_config,
1176 .get_eeprom_antenna_cfg = ath9k_hw_ar9287_get_eeprom_antenna_cfg,
1177 .set_board_values = ath9k_hw_ar9287_set_board_values,
1178 .set_addac = ath9k_hw_ar9287_set_addac,
1179 .set_txpower = ath9k_hw_ar9287_set_txpower,
1180 .get_spur_channel = ath9k_hw_ar9287_get_spur_channel